repo2/common/components/usbhostslave/trunk/RTL/serialInterfaceEngine/updateCRC5.v
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//// ////
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//// updateCRC5.v ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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module updateCRC5 (rstCRC, CRCResult, CRCEn, CRC5_8BitIn, dataIn, ready, clk, rst);
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input rstCRC;
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input CRCEn;
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input CRC5_8BitIn;
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input [7:0] dataIn;
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input clk;
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input rst;
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output [4:0] CRCResult;
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output ready;
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wire rstCRC;
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wire CRCEn;
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wire CRC5_8BitIn;
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wire [7:0] dataIn;
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wire clk;
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wire rst;
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reg [4:0] CRCResult;
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reg ready;
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reg doUpdateCRC;
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reg [7:0] data;
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reg [3:0] loopEnd;
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reg [3:0] i;
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always @(posedge clk)
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begin
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if (rst == 1'b1 || rstCRC == 1'b1) begin
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doUpdateCRC <= 1'b0;
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i <= 4'h0;
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CRCResult <= 5'h1f;
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ready <= 1'b1;
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end
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else
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begin
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if (doUpdateCRC == 1'b0) begin
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if (CRCEn == 1'b1) begin
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ready <= 1'b0;
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doUpdateCRC <= 1'b1;
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data <= dataIn;
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if (CRC5_8BitIn == 1'b1) begin
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loopEnd <= 4'h7;
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end
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else begin
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loopEnd <= 4'h2;
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end
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end
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end
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else begin
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i <= i + 1'b1;
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if ( (CRCResult[0] ^ data[0]) == 1'b1) begin
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CRCResult <= {1'b0, CRCResult[4:1]} ^ 5'h14;
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end
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else begin
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CRCResult <= {1'b0, CRCResult[4:1]};
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end
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data <= {1'b0, data[7:1]};
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if (i == loopEnd) begin
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doUpdateCRC <= 1'b0;
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i <= 4'h0;
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ready <= 1'b1;
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end
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end
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end
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end
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endmodule
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