repo2/common/components/usbhostslave/trunk/RTL/hostSlaveMux/hostSlaveMuxBI.v
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//// ////
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//// hostSlaveMuxBI.v ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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`include "usbHostSlave_h.v"
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module hostSlaveMuxBI (dataIn, dataOut, address, writeEn, strobe_i, busClk, usbClk,
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hostMode, hostSlaveMuxSel, rstFromWire, rstSyncToBusClkOut, rstSyncToUsbClkOut);
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input [7:0] dataIn;
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input address;
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input writeEn;
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input strobe_i;
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input busClk;
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input usbClk;
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output [7:0] dataOut;
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input hostSlaveMuxSel;
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output hostMode;
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input rstFromWire;
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output rstSyncToBusClkOut;
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output rstSyncToUsbClkOut;
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wire [7:0] dataIn;
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wire address;
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wire writeEn;
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wire strobe_i;
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wire busClk;
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wire usbClk;
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reg [7:0] dataOut;
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wire hostSlaveMuxSel;
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reg hostMode;
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wire rstFromWire;
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reg rstSyncToBusClkOut;
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reg rstSyncToUsbClkOut;
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//internal wire and regs
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reg [5:0] rstShift;
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reg rstFromBus;
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reg rstSyncToUsbClkFirst;
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//sync write demux
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always @(posedge busClk)
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begin
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if (rstSyncToBusClkOut == 1'b1)
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hostMode <= 1'b0;
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else begin
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if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG )
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hostMode <= dataIn[0];
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end
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if (writeEn == 1'b1 && hostSlaveMuxSel == 1'b1 && strobe_i == 1'b1 && address == `HOST_SLAVE_CONTROL_REG && dataIn[1] == 1'b1 )
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rstFromBus <= 1'b1;
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else
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rstFromBus <= 1'b0;
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end
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// async read mux
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always @(address or hostMode)
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begin
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case (address)
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`HOST_SLAVE_CONTROL_REG: dataOut <= {7'h0, hostMode};
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`HOST_SLAVE_VERSION_REG: dataOut <= `USBHOSTSLAVE_VERSION_NUM;
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endcase
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end
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// reset control
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//generate 'rstSyncToBusClk'
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//assuming that 'busClk' < 5 * 'usbClk'. ie 'busClk' < 240MHz
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always @(posedge busClk) begin
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if (rstFromWire == 1'b1 || rstFromBus == 1'b1)
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rstShift <= 6'b111111;
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else
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rstShift <= {1'b0, rstShift[5:1]};
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end
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always @(rstShift)
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rstSyncToBusClkOut <= rstShift[0];
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// double sync across clock domains to generate 'forceEmptySyncToWrClk'
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always @(posedge usbClk) begin
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rstSyncToUsbClkFirst <= rstSyncToBusClkOut;
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rstSyncToUsbClkOut <= rstSyncToUsbClkFirst;
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end
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endmodule
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