repo2/common/components/usbhostslave/trunk/RTL/busInterface/wishBoneBI.v
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//// ////
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//// wishBoneBI.v ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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`include "wishBoneBus_h.v"
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module wishBoneBI (
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address, dataIn, dataOut, writeEn,
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strobe_i,
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ack_o,
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clk, rst,
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hostControlSel,
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hostRxFifoSel, hostTxFifoSel,
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slaveControlSel,
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slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel,
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slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel,
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hostSlaveMuxSel,
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dataFromHostControl,
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dataFromHostRxFifo,
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dataFromHostTxFifo,
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dataFromSlaveControl,
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dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo,
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dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo,
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dataFromHostSlaveMux
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);
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input clk;
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input rst;
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input [7:0] address;
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input [7:0] dataIn;
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output [7:0] dataOut;
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input strobe_i;
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output ack_o;
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input writeEn;
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output hostControlSel;
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output hostRxFifoSel;
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output hostTxFifoSel;
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output slaveControlSel;
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output slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel;
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output slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel;
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output hostSlaveMuxSel;
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input [7:0] dataFromHostControl;
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input [7:0] dataFromHostRxFifo;
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input [7:0] dataFromHostTxFifo;
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input [7:0] dataFromSlaveControl;
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input [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
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input [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
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input [7:0] dataFromHostSlaveMux;
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wire clk;
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wire rst;
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wire [7:0] address;
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wire [7:0] dataIn;
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reg [7:0] dataOut;
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wire writeEn;
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wire strobe_i;
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reg ack_o;
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reg hostControlSel;
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reg hostRxFifoSel;
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reg hostTxFifoSel;
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reg slaveControlSel;
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reg slaveEP0RxFifoSel, slaveEP1RxFifoSel, slaveEP2RxFifoSel, slaveEP3RxFifoSel;
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reg slaveEP0TxFifoSel, slaveEP1TxFifoSel, slaveEP2TxFifoSel, slaveEP3TxFifoSel;
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reg hostSlaveMuxSel;
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wire [7:0] dataFromHostControl;
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wire [7:0] dataFromHostRxFifo;
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wire [7:0] dataFromHostTxFifo;
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wire [7:0] dataFromSlaveControl;
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wire [7:0] dataFromEP0RxFifo, dataFromEP1RxFifo, dataFromEP2RxFifo, dataFromEP3RxFifo;
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wire [7:0] dataFromEP0TxFifo, dataFromEP1TxFifo, dataFromEP2TxFifo, dataFromEP3TxFifo;
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wire [7:0] dataFromHostSlaveMux;
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//internal wires and regs
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reg ack_delayed;
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reg ack_immediate;
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//address decode and data mux
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always @(address or
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dataFromHostControl or
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dataFromHostRxFifo or
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dataFromHostTxFifo or
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dataFromSlaveControl or
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dataFromEP0RxFifo or
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dataFromEP1RxFifo or
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dataFromEP2RxFifo or
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dataFromEP3RxFifo or
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dataFromHostSlaveMux or
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dataFromEP0TxFifo or
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dataFromEP1TxFifo or
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dataFromEP2TxFifo or
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dataFromEP3TxFifo)
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begin
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hostControlSel <= 1'b0;
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hostRxFifoSel <= 1'b0;
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hostTxFifoSel <= 1'b0;
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slaveControlSel <= 1'b0;
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slaveEP0RxFifoSel <= 1'b0;
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slaveEP0TxFifoSel <= 1'b0;
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slaveEP1RxFifoSel <= 1'b0;
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slaveEP1TxFifoSel <= 1'b0;
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slaveEP2RxFifoSel <= 1'b0;
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slaveEP2TxFifoSel <= 1'b0;
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slaveEP3RxFifoSel <= 1'b0;
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slaveEP3TxFifoSel <= 1'b0;
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hostSlaveMuxSel <= 1'b0;
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case (address & `ADDRESS_DECODE_MASK)
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`HCREG_BASE : begin
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hostControlSel <= 1'b1;
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dataOut <= dataFromHostControl;
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end
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`HCREG_BASE_PLUS_0X10 : begin
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hostControlSel <= 1'b1;
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dataOut <= dataFromHostControl;
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end
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`HOST_RX_FIFO_BASE : begin
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hostRxFifoSel <= 1'b1;
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dataOut <= dataFromHostRxFifo;
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end
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`HOST_TX_FIFO_BASE : begin
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hostTxFifoSel <= 1'b1;
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dataOut <= dataFromHostTxFifo;
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end
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`SCREG_BASE : begin
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slaveControlSel <= 1'b1;
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dataOut <= dataFromSlaveControl;
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end
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`SCREG_BASE_PLUS_0X10 : begin
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slaveControlSel <= 1'b1;
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dataOut <= dataFromSlaveControl;
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end
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`EP0_RX_FIFO_BASE : begin
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slaveEP0RxFifoSel <= 1'b1;
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dataOut <= dataFromEP0RxFifo;
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end
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`EP0_TX_FIFO_BASE : begin
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slaveEP0TxFifoSel <= 1'b1;
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dataOut <= dataFromEP0TxFifo;
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end
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`EP1_RX_FIFO_BASE : begin
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slaveEP1RxFifoSel <= 1'b1;
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dataOut <= dataFromEP1RxFifo;
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end
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`EP1_TX_FIFO_BASE : begin
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slaveEP1TxFifoSel <= 1'b1;
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dataOut <= dataFromEP1TxFifo;
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end
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`EP2_RX_FIFO_BASE : begin
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slaveEP2RxFifoSel <= 1'b1;
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dataOut <= dataFromEP2RxFifo;
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end
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`EP2_TX_FIFO_BASE : begin
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slaveEP2TxFifoSel <= 1'b1;
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dataOut <= dataFromEP2TxFifo;
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end
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`EP3_RX_FIFO_BASE : begin
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slaveEP3RxFifoSel <= 1'b1;
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dataOut <= dataFromEP3RxFifo;
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end
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`EP3_TX_FIFO_BASE : begin
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slaveEP3TxFifoSel <= 1'b1;
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dataOut <= dataFromEP3TxFifo;
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end
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`HOST_SLAVE_CONTROL_BASE : begin
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hostSlaveMuxSel <= 1'b1;
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dataOut <= dataFromHostSlaveMux;
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end
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default:
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dataOut <= 8'h00;
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endcase
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end
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//delayed ack
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always @(posedge clk) begin
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ack_delayed <= strobe_i;
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end
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//immediate ack
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always @(strobe_i) begin
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ack_immediate <= strobe_i;
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end
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//select between immediate and delayed ack
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always @(writeEn or address or ack_delayed or ack_immediate) begin
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if (writeEn == 1'b0 &&
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(address == `HOST_RX_FIFO_BASE + `FIFO_DATA_REG ||
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address == `HOST_TX_FIFO_BASE + `FIFO_DATA_REG ||
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address == `EP0_RX_FIFO_BASE + `FIFO_DATA_REG ||
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address == `EP0_TX_FIFO_BASE + `FIFO_DATA_REG ||
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address == `EP1_RX_FIFO_BASE + `FIFO_DATA_REG ||
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address == `EP1_TX_FIFO_BASE + `FIFO_DATA_REG ||
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address == `EP2_RX_FIFO_BASE + `FIFO_DATA_REG ||
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address == `EP2_TX_FIFO_BASE + `FIFO_DATA_REG ||
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address == `EP3_RX_FIFO_BASE + `FIFO_DATA_REG ||
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address == `EP3_TX_FIFO_BASE + `FIFO_DATA_REG) )
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begin
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ack_o <= ack_delayed & ack_immediate;
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end
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else
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begin
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ack_o <= ack_immediate;
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end
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end
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endmodule
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