repo2/common/components/usbhostslave/trunk/RTL/buffers/fifoRTL.v
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//// ////
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//// fifoRTL.v ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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//// parameterized dual clock domain fifo.
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//// fifo depth is restricted to 2^ADDR_WIDTH
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//// No protection against over runs and under runs.
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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module fifoRTL(wrClk, rdClk, rstSyncToWrClk, rstSyncToRdClk, dataIn,
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dataOut, fifoWEn, fifoREn, fifoFull, fifoEmpty,
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forceEmptySyncToWrClk, forceEmptySyncToRdClk, numElementsInFifo);
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//FIFO_DEPTH = ADDR_WIDTH^2. Min = 2, Max = 66536
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parameter FIFO_WIDTH = 8;
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parameter FIFO_DEPTH = 64;
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parameter ADDR_WIDTH = 6;
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// Two clock domains within this module
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// These ports are within 'wrClk' domain
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input wrClk;
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input rstSyncToWrClk;
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input [FIFO_WIDTH-1:0] dataIn;
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input fifoWEn;
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input forceEmptySyncToWrClk;
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output fifoFull;
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// These ports are within 'rdClk' domain
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input rdClk;
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input rstSyncToRdClk;
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output [FIFO_WIDTH-1:0] dataOut;
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input fifoREn;
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input forceEmptySyncToRdClk;
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output fifoEmpty;
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output [15:0]numElementsInFifo; //note that this implies a max fifo depth of 65536
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wire wrClk;
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wire rdClk;
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wire rstSyncToWrClk;
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wire rstSyncToRdClk;
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wire [FIFO_WIDTH-1:0] dataIn;
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reg [FIFO_WIDTH-1:0] dataOut;
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wire fifoWEn;
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wire fifoREn;
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reg fifoFull;
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reg fifoEmpty;
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wire forceEmpty;
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reg [15:0]numElementsInFifo;
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// local registers
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reg [ADDR_WIDTH:0]bufferInIndex;
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reg [ADDR_WIDTH:0]bufferInIndexSyncToRdClk;
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reg [ADDR_WIDTH:0]bufferOutIndex;
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reg [ADDR_WIDTH:0]bufferOutIndexSyncToWrClk;
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reg [ADDR_WIDTH-1:0]bufferInIndexToMem;
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reg [ADDR_WIDTH-1:0]bufferOutIndexToMem;
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reg [ADDR_WIDTH:0]bufferCnt;
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reg fifoREnDelayed;
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wire [FIFO_WIDTH-1:0] dataFromMem;
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always @(posedge wrClk)
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begin
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bufferOutIndexSyncToWrClk <= bufferOutIndex;
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if (rstSyncToWrClk == 1'b1 || forceEmptySyncToWrClk == 1'b1)
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begin
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fifoFull <= 1'b0;
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bufferInIndex <= 0;
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end
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else
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begin
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if (fifoWEn == 1'b1) begin
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bufferInIndex <= bufferInIndex + 1'b1;
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end
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if ((bufferOutIndexSyncToWrClk[ADDR_WIDTH-1:0] == bufferInIndex[ADDR_WIDTH-1:0]) &&
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(bufferOutIndexSyncToWrClk[ADDR_WIDTH] != bufferInIndex[ADDR_WIDTH]) )
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fifoFull <= 1'b1;
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else
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fifoFull <= 1'b0;
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end
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end
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always @(bufferInIndexSyncToRdClk or bufferOutIndex)
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bufferCnt <= bufferInIndexSyncToRdClk - bufferOutIndex;
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always @(posedge rdClk)
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begin
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numElementsInFifo <= { {16-ADDR_WIDTH+1{1'b0}}, bufferCnt }; //pad bufferCnt with leading zeroes
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bufferInIndexSyncToRdClk <= bufferInIndex;
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if (rstSyncToRdClk == 1'b1 || forceEmptySyncToRdClk == 1'b1)
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begin
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fifoEmpty <= 1'b1;
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bufferOutIndex <= 0;
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fifoREnDelayed <= 1'b0;
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end
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else
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begin
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fifoREnDelayed <= fifoREn;
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if (fifoREn == 1'b1 && fifoREnDelayed == 1'b0) begin
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dataOut <= dataFromMem;
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bufferOutIndex <= bufferOutIndex + 1'b1;
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end
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if (bufferInIndexSyncToRdClk == bufferOutIndex)
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fifoEmpty <= 1'b1;
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else
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fifoEmpty <= 1'b0;
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end
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end
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always @(bufferInIndex or bufferOutIndex) begin
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bufferInIndexToMem <= bufferInIndex[ADDR_WIDTH-1:0];
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bufferOutIndexToMem <= bufferOutIndex[ADDR_WIDTH-1:0];
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end
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dpMem_dc #(FIFO_WIDTH, FIFO_DEPTH, ADDR_WIDTH) u_dpMem_dc (
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.addrIn(bufferInIndexToMem),
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.addrOut(bufferOutIndexToMem),
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.wrClk(wrClk),
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.rdClk(rdClk),
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.dataIn(dataIn),
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.writeEn(fifoWEn),
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.readEn(fifoREn),
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.dataOut(dataFromMem));
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endmodule
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