repo2/common/components/usbhostslave/trunk/RTL/buffers/RxFifo.v
| 264 | markw | //////////////////////////////////////////////////////////////////////
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//// ////
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//// RxFifo.v ////
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//// ////
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//// This file is part of the usbhostslave opencores effort.
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//// <http://www.opencores.org/cores//> ////
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//// ////
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//// Module Description: ////
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//// parameterized RxFifo wrapper. Min depth = 2, Max depth = 65536
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//// fifo read access via bus interface, fifo write access is direct
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////
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//// ////
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//// To Do: ////
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////
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//// ////
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//// Author(s): ////
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//// - Steve Fielding, sfielding@base2designs.com ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from <http://www.opencores.org/lgpl.shtml> ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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`include "timescale.v"
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module RxFifo(
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busClk,
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usbClk,
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rstSyncToBusClk,
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rstSyncToUsbClk,
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fifoWEn,
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fifoFull,
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busAddress,
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busWriteEn,
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busStrobe_i,
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busFifoSelect,
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busDataIn,
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busDataOut,
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fifoDataIn );
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//FIFO_DEPTH = ADDR_WIDTH^2
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parameter FIFO_DEPTH = 64;
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parameter ADDR_WIDTH = 6;
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input busClk;
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input usbClk;
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input rstSyncToBusClk;
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input rstSyncToUsbClk;
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input fifoWEn;
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output fifoFull;
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input [2:0] busAddress;
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input busWriteEn;
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input busStrobe_i;
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input busFifoSelect;
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input [7:0] busDataIn;
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output [7:0] busDataOut;
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input [7:0] fifoDataIn;
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wire busClk;
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wire usbClk;
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wire rstSyncToBusClk;
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wire rstSyncToUsbClk;
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wire fifoWEn;
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wire fifoFull;
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wire [2:0] busAddress;
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wire busWriteEn;
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wire busStrobe_i;
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wire busFifoSelect;
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wire [7:0] busDataIn;
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wire [7:0] busDataOut;
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wire [7:0] fifoDataIn;
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//internal wires and regs
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wire [7:0] dataFromFifoToBus;
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wire fifoREn;
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wire forceEmptySyncToBusClk;
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wire forceEmptySyncToUsbClk;
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wire [15:0] numElementsInFifo;
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wire fifoEmpty; //not used
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fifoRTL #(8, FIFO_DEPTH, ADDR_WIDTH) u_fifo(
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.wrClk(usbClk),
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.rdClk(busClk),
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.rstSyncToWrClk(rstSyncToUsbClk),
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.rstSyncToRdClk(rstSyncToBusClk),
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.dataIn(fifoDataIn),
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.dataOut(dataFromFifoToBus),
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.fifoWEn(fifoWEn),
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.fifoREn(fifoREn),
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.fifoFull(fifoFull),
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.fifoEmpty(fifoEmpty),
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.forceEmptySyncToWrClk(forceEmptySyncToUsbClk),
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.forceEmptySyncToRdClk(forceEmptySyncToBusClk),
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.numElementsInFifo(numElementsInFifo) );
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RxfifoBI u_RxfifoBI(
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.address(busAddress),
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.writeEn(busWriteEn),
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.strobe_i(busStrobe_i),
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.busClk(busClk),
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.usbClk(usbClk),
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.rstSyncToBusClk(rstSyncToBusClk),
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.fifoSelect(busFifoSelect),
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.fifoDataIn(dataFromFifoToBus),
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.busDataIn(busDataIn),
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.busDataOut(busDataOut),
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.fifoREn(fifoREn),
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.forceEmptySyncToBusClk(forceEmptySyncToBusClk),
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.forceEmptySyncToUsbClk(forceEmptySyncToUsbClk),
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.numElementsInFifo(numElementsInFifo)
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);
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endmodule
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