repo2/common/a8core/sid8580/sid8580.v
| 960 | markw | ||
module sid8580
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(
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input reset,
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input clk,
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input ce_1m,
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input we,
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input [4:0] addr,
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input [7:0] data_in,
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output [ 7:0] data_out,
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input [7:0] pot_x,
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input [7:0] pot_y,
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input extfilter_en,
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output [17:0] audio_data
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);
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// Internal Signals
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reg [7:0] Voice_1_Freq_lo;
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reg [7:0] Voice_1_Freq_hi;
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reg [7:0] Voice_1_Pw_lo;
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reg [3:0] Voice_1_Pw_hi;
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reg [7:0] Voice_1_Control;
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reg [7:0] Voice_1_Att_dec;
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reg [7:0] Voice_1_Sus_Rel;
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reg [7:0] Voice_2_Freq_lo;
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reg [7:0] Voice_2_Freq_hi;
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reg [7:0] Voice_2_Pw_lo;
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reg [3:0] Voice_2_Pw_hi;
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reg [7:0] Voice_2_Control;
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reg [7:0] Voice_2_Att_dec;
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reg [7:0] Voice_2_Sus_Rel;
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reg [7:0] Voice_3_Freq_lo;
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reg [7:0] Voice_3_Freq_hi;
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reg [7:0] Voice_3_Pw_lo;
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reg [3:0] Voice_3_Pw_hi;
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reg [7:0] Voice_3_Control;
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reg [7:0] Voice_3_Att_dec;
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reg [7:0] Voice_3_Sus_Rel;
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reg [7:0] Filter_Fc_lo;
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reg [7:0] Filter_Fc_hi;
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reg [7:0] Filter_Res_Filt;
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reg [7:0] Filter_Mode_Vol;
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wire [7:0] Misc_Osc3_Random;
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wire [7:0] Misc_Env3;
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reg [7:0] do_buf;
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reg [7:0] sidrandom;
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wire [11:0] voice_1;
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wire [11:0] voice_2;
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wire [11:0] voice_3;
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wire [17:0] voice_mixed;
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reg [17:0] voice_volume;
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wire voice_1_PA_MSB;
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wire voice_2_PA_MSB;
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wire voice_3_PA_MSB;
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wire [18:0] filtered_audio;
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wire [17:0] unsigned_audio;
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wire [18:0] unsigned_filt;
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localparam DC_offset = 14'b00111111111111;
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reg [7:0] _st_out[3];
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reg [7:0] p_t_out[3];
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reg [7:0] ps__out[3];
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reg [7:0] pst_out[3];
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wire [11:0] sawtooth[3];
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wire [11:0] triangle[3];
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// Voice 1 Instantiation
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sid_voice v1
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(
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.clock(clk),
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.ce_1m(ce_1m),
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.reset(reset),
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.freq_lo(Voice_1_Freq_lo),
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.freq_hi(Voice_1_Freq_hi),
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.pw_lo(Voice_1_Pw_lo),
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.pw_hi(Voice_1_Pw_hi),
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.control(Voice_1_Control),
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.att_dec(Voice_1_Att_dec),
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.sus_rel(Voice_1_Sus_Rel),
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.osc_msb_in(voice_3_PA_MSB),
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.osc_msb_out(voice_1_PA_MSB),
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.signal_out(voice_1),
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._st_out(_st_out[0]),
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.p_t_out(p_t_out[0]),
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.ps__out(ps__out[0]),
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.pst_out(pst_out[0]),
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.sawtooth(sawtooth[0]),
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.triangle(triangle[0])
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);
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// Voice 2 Instantiation
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sid_voice v2
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(
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.clock(clk),
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.ce_1m(ce_1m),
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.reset(reset),
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.freq_lo(Voice_2_Freq_lo),
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.freq_hi(Voice_2_Freq_hi),
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.pw_lo(Voice_2_Pw_lo),
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.pw_hi(Voice_2_Pw_hi),
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.control(Voice_2_Control),
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.att_dec(Voice_2_Att_dec),
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.sus_rel(Voice_2_Sus_Rel),
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.osc_msb_in(voice_1_PA_MSB),
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.osc_msb_out(voice_2_PA_MSB),
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.signal_out(voice_2),
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._st_out(_st_out[1]),
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.p_t_out(p_t_out[1]),
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.ps__out(ps__out[1]),
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.pst_out(pst_out[1]),
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.sawtooth(sawtooth[1]),
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.triangle(triangle[1])
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);
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// Voice 3 Instantiation
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sid_voice v3
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(
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.clock(clk),
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.ce_1m(ce_1m),
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.reset(reset),
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.freq_lo(Voice_3_Freq_lo),
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.freq_hi(Voice_3_Freq_hi),
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.pw_lo(Voice_3_Pw_lo),
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.pw_hi(Voice_3_Pw_hi),
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.control(Voice_3_Control),
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.att_dec(Voice_3_Att_dec),
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.sus_rel(Voice_3_Sus_Rel),
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.osc_msb_in(voice_2_PA_MSB),
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.osc_msb_out(voice_3_PA_MSB),
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.signal_out(voice_3),
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.osc_out(Misc_Osc3_Random),
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.env_out(Misc_Env3),
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._st_out(_st_out[2]),
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.p_t_out(p_t_out[2]),
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.ps__out(ps__out[2]),
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.pst_out(pst_out[2]),
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.sawtooth(sawtooth[2]),
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.triangle(triangle[2])
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);
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// Filter Instantiation
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sid_filters filters
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(
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.clk(clk),
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.rst(reset),
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.Fc_lo(Filter_Fc_lo),
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.Fc_hi(Filter_Fc_hi),
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.Res_Filt(Filter_Res_Filt),
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.Mode_Vol(Filter_Mode_Vol),
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.voice1(voice_1),
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.voice2(voice_2),
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.voice3(voice_3),
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.input_valid(ce_1m),
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.ext_in(12'hfff),
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.sound(audio_data),
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.extfilter_en(extfilter_en)
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);
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sid_tables sid_tables
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(
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.clock(clk),
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.sawtooth(f_sawtooth),
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.triangle(f_triangle),
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._st_out(f__st_out),
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.p_t_out(f_p_t_out),
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.ps__out(f_ps__out),
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.pst_out(f_pst_out)
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);
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wire [7:0] f__st_out;
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wire [7:0] f_p_t_out;
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wire [7:0] f_ps__out;
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wire [7:0] f_pst_out;
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reg [11:0] f_sawtooth;
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reg [11:0] f_triangle;
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always @(posedge clk) begin
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reg [3:0] state;
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if(~&state) state <= state + 1'd1;;
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if(ce_1m) state <= 0;
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case(state)
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1,5,9: begin
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f_sawtooth <= sawtooth[state[3:2]];
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f_triangle <= triangle[state[3:2]];
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end
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endcase
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case(state)
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3,7,11: begin
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_st_out[state[3:2]] <= f__st_out;
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p_t_out[state[3:2]] <= f_p_t_out;
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ps__out[state[3:2]] <= f_ps__out;
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pst_out[state[3:2]] <= f_pst_out;
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end
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endcase
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end
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assign data_out = do_buf;
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reg [7:0] last_wr;
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always @(*) begin
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case (addr)
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5'h19: do_buf = pot_x;
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5'h1a: do_buf = pot_y;
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5'h1b: do_buf = Misc_Osc3_Random;
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5'h1c: do_buf = Misc_Env3;
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default: do_buf = last_wr;
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endcase
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end
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// Register Decoding
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always @(posedge clk) begin
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if (reset) begin
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Voice_1_Freq_lo <= 0;
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Voice_1_Freq_hi <= 0;
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Voice_1_Pw_lo <= 0;
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Voice_1_Pw_hi <= 0;
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Voice_1_Control <= 0;
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Voice_1_Att_dec <= 0;
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Voice_1_Sus_Rel <= 0;
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Voice_2_Freq_lo <= 0;
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Voice_2_Freq_hi <= 0;
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Voice_2_Pw_lo <= 0;
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Voice_2_Pw_hi <= 0;
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Voice_2_Control <= 0;
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Voice_2_Att_dec <= 0;
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Voice_2_Sus_Rel <= 0;
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Voice_3_Freq_lo <= 0;
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Voice_3_Freq_hi <= 0;
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Voice_3_Pw_lo <= 0;
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Voice_3_Pw_hi <= 0;
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Voice_3_Control <= 0;
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Voice_3_Att_dec <= 0;
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Voice_3_Sus_Rel <= 0;
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Filter_Fc_lo <= 0;
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Filter_Fc_hi <= 0;
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Filter_Res_Filt <= 0;
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Filter_Mode_Vol <= 0;
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end
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else begin
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if (we) begin
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last_wr <= data_in;
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case (addr)
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5'h00: Voice_1_Freq_lo <= data_in;
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5'h01: Voice_1_Freq_hi <= data_in;
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5'h02: Voice_1_Pw_lo <= data_in;
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5'h03: Voice_1_Pw_hi <= data_in[3:0];
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5'h04: Voice_1_Control <= data_in;
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5'h05: Voice_1_Att_dec <= data_in;
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5'h06: Voice_1_Sus_Rel <= data_in;
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5'h07: Voice_2_Freq_lo <= data_in;
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5'h08: Voice_2_Freq_hi <= data_in;
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5'h09: Voice_2_Pw_lo <= data_in;
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5'h0a: Voice_2_Pw_hi <= data_in[3:0];
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5'h0b: Voice_2_Control <= data_in;
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5'h0c: Voice_2_Att_dec <= data_in;
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5'h0d: Voice_2_Sus_Rel <= data_in;
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5'h0e: Voice_3_Freq_lo <= data_in;
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5'h0f: Voice_3_Freq_hi <= data_in;
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5'h10: Voice_3_Pw_lo <= data_in;
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5'h11: Voice_3_Pw_hi <= data_in[3:0];
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5'h12: Voice_3_Control <= data_in;
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5'h13: Voice_3_Att_dec <= data_in;
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5'h14: Voice_3_Sus_Rel <= data_in;
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5'h15: Filter_Fc_lo <= data_in;
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5'h16: Filter_Fc_hi <= data_in;
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5'h17: Filter_Res_Filt <= data_in;
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5'h18: Filter_Mode_Vol <= data_in;
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endcase
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end
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end
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end
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endmodule
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