repo2/chameleon2/chameleon_phi_clock_e.vhd
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--
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-- VGA-64
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--
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-- Multi purpose FPGA expansion for the Commodore 64 computer
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--
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-- -----------------------------------------------------------------------
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-- Copyright 2005-2018 by Peter Wendrich (pwsoft@syntiac.com)
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-- http://www.syntiac.com/chameleon.html
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--
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-- This source file is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU Lesser General Public License as published
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-- by the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This source file is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- -----------------------------------------------------------------------
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--
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-- C64 Phi2-clock regeneration and divider
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--
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-- -----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.all;
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-- -----------------------------------------------------------------------
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entity chameleon_phi_clock is
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generic (
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phase_shift : integer := 8
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);
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port (
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clk : in std_logic;
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phi2_n : in std_logic;
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-- Standalone mode, 0=PAL and 1=NTSC
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mode : in std_logic := '0';
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-- Buffered and inverted phi_n (delayed)
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phiLength : out unsigned(7 downto 0);
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-- no_clock is high when there are no phiIn changes detected.
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-- This signal allows switching between real I/O and internal emulation.
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no_clock : out std_logic;
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-- docking_station is high when there are no phiIn changes (no_clock) and
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-- the phi signal is low. Without docking station phi is pulled up.
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docking_station : out std_logic;
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-- Resynthesised Phi2 clock
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phiLocal : out std_logic;
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-- Cycle counter
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phiCnt : out unsigned(7 downto 0);
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-- Control pulses
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phiPreHalf : out std_logic;
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phiHalf : out std_logic;
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phiPreEnd : out std_logic;
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phiEnd : out std_logic;
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-- First cycle where phiLocal is changed.
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phiPost1 : out std_logic;
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-- Second cycle after phiLocal change.
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phiPost2 : out std_logic;
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-- Third cycle after phiLocal change.
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phiPost3 : out std_logic;
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-- Forth cycle after phiLocal change.
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phiPost4 : out std_logic
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);
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end entity;
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