repo2/atari_chips/tb_gtiamax/pll.vhd
| 817 | markw | LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY pll IS
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PORT
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(
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inclk0 : IN STD_LOGIC;
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c0 : OUT STD_LOGIC;
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locked : OUT STD_LOGIC
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);
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END pll;
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ARCHITECTURE vhdl OF pll IS
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constant CLK0_PERIOD : time := 1 us / (1.79*32);
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begin
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p_clk_gen_a : process
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begin
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if inclk0/= '1' then
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wait until (inclk0='1');
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end if;
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c0 <= '1';
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wait for clk0_period/2;
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c0 <= '0';
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wait for clk0_period - (clk0_period/2 );
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c0 <= '1';
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wait for CLK0_PERIOD/2;
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c0 <= '0';
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wait for CLK0_PERIOD - (CLK0_PERIOD/2 );
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c0 <= '1';
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wait for clk0_period/2;
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c0 <= '0';
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wait for clk0_period - (clk0_period/2 );
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c0 <= '1';
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wait for CLK0_PERIOD/2;
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c0 <= '0';
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wait for CLK0_PERIOD - (CLK0_PERIOD/2 );
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c0 <= '1';
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wait for clk0_period/2;
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c0 <= '0';
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wait for clk0_period - (clk0_period/2 );
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c0 <= '1';
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wait for CLK0_PERIOD/2;
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c0 <= '0';
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wait for CLK0_PERIOD - (CLK0_PERIOD/2 );
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c0 <= '1';
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wait for clk0_period/2;
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c0 <= '0';
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wait for clk0_period - (clk0_period/2 );
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c0 <= '1';
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wait for CLK0_PERIOD/2;
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c0 <= '0';
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wait for CLK0_PERIOD - (CLK0_PERIOD/2 );
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c0 <= '1';
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wait for clk0_period/2;
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c0 <= '0';
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wait for clk0_period - (clk0_period/2 );
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c0 <= '1';
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wait for CLK0_PERIOD/2;
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c0 <= '0';
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wait for CLK0_PERIOD - (CLK0_PERIOD/2 );
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c0 <= '1';
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wait for clk0_period/2;
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c0 <= '0';
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wait for clk0_period - (clk0_period/2 );
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c0 <= '1';
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wait for CLK0_PERIOD/2;
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c0 <= '0';
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wait for CLK0_PERIOD - (CLK0_PERIOD/2 );
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c0 <= '1';
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wait for clk0_period/2;
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c0 <= '0';
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wait for clk0_period - (clk0_period/2 );
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c0 <= '1';
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wait for CLK0_PERIOD/2;
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c0 <= '0';
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wait for CLK0_PERIOD - (CLK0_PERIOD/2 );
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c0 <= '1';
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wait for clk0_period/2;
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c0 <= '0';
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wait for clk0_period - (clk0_period/2 );
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c0 <= '1';
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wait for CLK0_PERIOD/2;
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c0 <= '0';
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wait for CLK0_PERIOD - (CLK0_PERIOD/2 );
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c0 <= '1';
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wait for clk0_period/2;
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c0 <= '0';
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wait for clk0_period - (clk0_period/2 );
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c0 <= '1';
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wait for CLK0_PERIOD/2;
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c0 <= '0';
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wait for CLK0_PERIOD - (CLK0_PERIOD/2 );
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c0 <= '1';
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wait for clk0_period/2;
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c0 <= '0';
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wait for clk0_period - (clk0_period/2 );
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c0 <= '1';
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wait for CLK0_PERIOD/2;
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c0 <= '0';
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wait for CLK0_PERIOD - (CLK0_PERIOD/2 );
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c0 <= '1';
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wait for clk0_period/2;
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c0 <= '0';
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wait for clk0_period - (clk0_period/2 );
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c0 <= '1';
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wait for CLK0_PERIOD/2;
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c0 <= '0';
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wait for CLK0_PERIOD - (CLK0_PERIOD/2 );
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c0 <= '1';
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wait for clk0_period/2;
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c0 <= '0';
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wait for clk0_period - (clk0_period/2 );
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c0 <= '1';
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wait for CLK0_PERIOD/2;
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c0 <= '0';
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wait for CLK0_PERIOD - (CLK0_PERIOD/2 );
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c0 <= '1';
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wait for clk0_period/2;
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c0 <= '0';
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wait for clk0_period - (clk0_period/2 );
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c0 <= '1';
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wait for CLK0_PERIOD/2;
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c0 <= '0';
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wait for CLK0_PERIOD - (CLK0_PERIOD/2 );
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c0 <= '1';
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wait for clk0_period/2;
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c0 <= '0';
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wait for clk0_period - (clk0_period/2 );
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c0 <= '1';
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wait for CLK0_PERIOD/2;
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c0 <= '0';
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wait for CLK0_PERIOD - (CLK0_PERIOD/2 );
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c0 <= '1';
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wait for clk0_period/2;
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c0 <= '0';
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wait for clk0_period - (clk0_period/2 );
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c0 <= '1';
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wait for CLK0_PERIOD/2;
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c0 <= '0';
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wait for CLK0_PERIOD - (CLK0_PERIOD/2 );
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c0 <= '1';
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wait for clk0_period/2;
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c0 <= '0';
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wait for CLK0_PERIOD - (CLK0_PERIOD/2 );
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c0 <= '1';
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wait for clk0_period/2;
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c0 <= '0';
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end process;
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locked <= '0', '1' after 2000ns;
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end vhdl;
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