repo2/atari_chips/sally/sallymax.vhd
| 701 | markw | ---------------------------------------------------------------------------
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-- (c) 2018 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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USE IEEE.STD_LOGIC_UNSIGNED.ALL;
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LIBRARY work;
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| 793 | markw | ENTITY sallymax IS
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| 701 | markw | PORT
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(
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| 809 | markw | PHI0 : IN STD_LOGIC; -- need to sync to this! TODO
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RST_N : IN STD_LOGIC; -- connect me TODO
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| 793 | markw | ||
| 701 | markw | CLK_OUT : OUT STD_LOGIC; -- Use PHI2 and internal oscillator to create a clock, feed out here
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CLK_SLOW : IN STD_LOGIC; -- ... and back in here, then to pll!
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D : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
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| 793 | markw | A : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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W_N : OUT STD_LOGIC;
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| 714 | markw | ||
| 793 | markw | RDY : IN STD_LOGIC;
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| 812 | markw | HALT_N : IN STD_LOGIC; -- TODO, wire this up!
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| 793 | markw | NMI_N : IN STD_LOGIC;
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IRQ_N : IN STD_LOGIC;
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S0 : IN STD_LOGIC; -- not implemented yet!
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SYNC : OUT STD_LOGIC;
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PHI1 : OUT STD_LOGIC;
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| 809 | markw | PHI2 : OUT STD_LOGIC;
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NC : INOUT STD_LOGIC_VECTOR(8 downto 0)
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| 701 | markw | );
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| 793 | markw | END sallymax;
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| 701 | markw | ||
| 793 | markw | ARCHITECTURE vhdl OF sallymax IS
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| 701 | markw | component int_osc is
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port (
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clkout : out std_logic; -- clkout.clk
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oscena : in std_logic := '0' -- oscena.oscena
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);
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end component;
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| 714 | markw | ||
component pll
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port (
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inclk0 : in std_logic := '0';
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c0 : out std_logic;
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locked : out std_logic
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);
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end component;
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signal OSC_CLK : std_logic;
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signal PHI2_6X : std_logic;
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signal CLK : std_logic;
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signal RESET_N : std_logic;
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| 793 | markw | signal CPU_REQUEST : std_logic;
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signal CPU_REQUEST_COMPLETE : std_logic;
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signal CPU_ADDR : std_logic_vector(15 downto 0);
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signal CPU_WRITE_DATA : std_logic_vector(7 downto 0);
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signal CPU_READ_DATA : std_logic_vector(7 downto 0);
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signal CPU_WRITE_N : std_logic;
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| 714 | markw | ||
| 812 | markw | signal CPU_NMI_N : std_logic;
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signal CPU_IRQ_N : std_logic;
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| 1406 | markw | signal CPU_RDY : std_logic;
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| 793 | markw | signal BUS_ADDR : std_logic_vector(15 downto 0);
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signal BUS_ADDR_OE : std_logic;
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| 716 | markw | signal BUS_DATA : std_logic_vector(7 downto 0);
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| 793 | markw | signal BUS_DATA_OE : std_logic;
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| 809 | markw | signal BUS_WRITE_N : std_logic;
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| 810 | markw | signal BUS_WRITE_OE : std_logic;
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| 809 | markw | ||
signal PLLRESET_N : std_logic;
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| 701 | markw | BEGIN
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| 809 | markw | NC <= (others=>'Z');
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| 701 | markw | oscillator : int_osc
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port map
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(
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| 714 | markw | clkout => OSC_CLK,
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| 701 | markw | oscena => '1'
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);
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| 714 | markw | ||
| 730 | markw | --phi_multiplier : entity work.phi_mult
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--port map
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--(
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-- clkin => OSC_CLK,
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-- phi2 => PHI2,
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-- clkout => PHI2_6X -- 6x phi2, aligned!
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--);
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PHI2_6X <= OSC_CLK;
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| 714 | markw | ||
pll_inst : pll
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PORT MAP(inclk0 => CLK_SLOW,
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c0 => CLK, -- 27MHz
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| 809 | markw | locked => PLLRESET_N);
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RESET_N <= PLLRESET_N and RST_N;
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| 714 | markw | ||
| 793 | markw | bus_adapt : entity work.timing6502
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| 716 | markw | PORT MAP
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(
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CLK => CLK,
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RESET_N => RESET_N,
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| 809 | markw | ||
PHI0 => PHI0,
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HALT_N => HALT_N,
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| 812 | markw | NMI_N => NMI_N,
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IRQ_N => IRQ_N,
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| 716 | markw | ||
| 793 | markw | -- FGPA side
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ADDR_IN => CPU_ADDR,
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DATA_IN => CPU_WRITE_DATA,
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WRITE_IN => not(CPU_WRITE_N),
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| 717 | markw | ||
| 793 | markw | DATA_OUT => CPU_READ_DATA,
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| 809 | markw | ||
CPU_REQUEST => CPU_REQUEST,
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CPU_REQUEST_COMPLETE => CPU_REQUEST_COMPLETE,
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| 812 | markw | CPU_NMI_N => CPU_NMI_N,
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CPU_IRQ_N => CPU_IRQ_N,
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| 1406 | markw | CPU_RDY => CPU_RDY,
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| 714 | markw | ||
| 793 | markw | -- bus side
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| 809 | markw | BUS_DATA_IN => D,
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| 793 | markw | BUS_PHI1 => PHI1,
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BUS_PHI2 => PHI2,
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BUS_SUBCYCLE => open,
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BUS_ADDR_OUT => BUS_ADDR,
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BUS_ADDR_OE => BUS_ADDR_OE,
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BUS_DATA_OUT => BUS_DATA,
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BUS_DATA_OE => BUS_DATA_OE,
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| 809 | markw | BUS_WRITE_N => BUS_WRITE_N,
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| 1406 | markw | BUS_WRITE_OE => BUS_WRITE_OE,
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BUS_RDY => RDY
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| 809 | markw | );
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| 793 | markw | cpu6502 : entity work.cpu
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PORT MAP(CLK => CLK,
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RESET => NOT(RESET_N),
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ENABLE => RESET_N,
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| 812 | markw | IRQ_n => CPU_IRQ_N,
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NMI_n => CPU_NMI_N,
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| 793 | markw | MEMORY_READY => CPU_REQUEST_COMPLETE,
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| 809 | markw | THROTTLE => CPU_REQUEST,
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| 1406 | markw | RDY => CPU_RDY,
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| 793 | markw | DI => CPU_READ_DATA,
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R_W_n => CPU_WRITE_N,
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| 809 | markw | CPU_FETCH => open,
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| 793 | markw | A => CPU_ADDR,
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DO => CPU_WRITE_DATA);
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| 725 | markw | ||
| 714 | markw | -- Wire up pins
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CLK_OUT <= PHI2_6X;
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| 810 | markw | D <= BUS_DATA when (BUS_DATA_OE='1') else (others=>'Z');
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A <= BUS_ADDR when (BUS_ADDR_OE='1') else (others=>'Z');
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W_N <= BUS_WRITE_N when (BUS_WRITE_OE='1') else 'Z';
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| 714 | markw | ||
| 793 | markw | SYNC <= 'Z'; -- Not implemented yet
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| 714 | markw | ||
| 701 | markw | END vhdl;
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