repo2/atari_chips/sally/phi_mult.vhdl
| 714 | markw | ---------------------------------------------------------------------------
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-- (c) 2018 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY phi_mult IS
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PORT
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(
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clkin : IN STD_LOGIC; -- 55 to 116MHz
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phi2 : IN STD_LOGIC; -- about 1.8MHz
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clkout : OUT STD_LOGIC -- about 6x phi2, in sync with phi2!
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);
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END phi_mult;
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ARCHITECTURE vhdl OF phi_mult IS
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signal measure_next : std_logic_vector(5 downto 0); -- we do not know osc frequency, measure how many cycles in 1 cycle
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signal measure_reg : std_logic_vector(5 downto 0);
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signal target_next : std_logic_vector(3 downto 0); -- this is 1/6 of the cycle length, flip our output every time
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signal target_reg : std_logic_vector(3 downto 0);
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signal counter_next : std_logic_vector(3 downto 0);
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signal counter_reg : std_logic_vector(3 downto 0);
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signal output_next : std_logic;
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signal output_reg : std_logic;
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signal phi2_next : std_logic;
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signal phi2_reg : std_logic;
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signal phi2_sync : std_logic;
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| 716 | markw | ||
signal flip : std_logic;
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| 714 | markw | begin
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phi2_next <= phi2_sync;
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process(clkin)
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begin
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if (clkin'event and clkin='1') then
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phi2_reg <= phi2_next;
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measure_reg <= measure_next;
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target_reg <= target_next;
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counter_reg <= counter_next;
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output_reg <= output_next;
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end if;
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end process;
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sync_clk : entity work.synchronizer
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port map
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(
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CLK => clkin,
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RAW => phi2,
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SYNC => phi2_sync
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);
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| 716 | markw | process(phi2_reg, phi2_sync,measure_reg,target_reg,counter_reg)
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| 714 | markw | variable sum : std_logic_vector(10 downto 0);
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begin
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measure_next <= std_logic_vector(unsigned(measure_reg) + 1);
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target_next <= target_reg;
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counter_next <= std_logic_vector(unsigned(counter_reg) +1);
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| 716 | markw | flip <= '0';
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| 714 | markw | ||
if (phi2_sync = '1' and phi2_reg = '0') then
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measure_next <= "000000";
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-- *21/128 to get 1/6
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| 716 | markw | -- 10101 is 20...
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| 714 | markw | sum := std_logic_vector(unsigned("00000"&measure_reg)+unsigned("000"&measure_reg&"00")+unsigned("0"&measure_reg&"0000"));
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target_next <= sum(10 downto 7);
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counter_next <= "0011";
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end if;
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| 716 | markw | ||
if (counter_reg=target_reg) then
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counter_next <= (others=>'0');
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flip <= '1';
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end if;
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| 714 | markw | end process;
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| 716 | markw | process(phi2_reg, phi2_sync, flip, output_reg)
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| 714 | markw | begin
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output_next <= output_reg;
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if (phi2_sync = '1' and phi2_reg = '0') then
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output_next <= '1'; -- put in sync (should already be one...)
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end if;
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| 716 | markw | if (flip='1') then
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| 714 | markw | output_next <= not(output_reg); -- next!
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end if;
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end process;
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CLKOUT <= output_reg;
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end vhdl;
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