EclaireXL

/*

WARNING: Do NOT edit the input and output ports in this file in a text

editor if you plan to continue editing the block that represents it in

the Block Editor! File corruption is VERY likely to occur.

*/

/*

and other software and tools, and any partner logic

functions, and any output files from any of the foregoing

(including device programming or simulation files), and any

associated documentation or information are expressly subject

to the terms and conditions of the Intel Program License

Subscription Agreement, the Intel Quartus Prime License Agreement,

the Intel FPGA IP License Agreement, or other applicable license

agreement, including, without limitation, that your use is for

the sole purpose of programming logic devices manufactured by

Intel and sold by Intel or its authorized distributors. Please

refer to the applicable agreement for further details, at

https://fpgasoftware.intel.com/eula.

*/

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(input)

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(text "clock" (rect 4 61 34 72)(font "Arial" (font_size 8)))

(port

(pt 0 112)

(input)

(text "avmm_csr_addr" (rect 0 0 69 12)(font "Arial" (font_size 8)))

(text "avmm_csr_addr" (rect 4 101 82 112)(font "Arial" (font_size 8)))

(port

(pt 0 128)

(input)

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(text "avmm_csr_read" (rect 4 117 82 128)(font "Arial" (font_size 8)))

(port

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(input)

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(text "avmm_csr_writedata[31..0]" (rect 4 133 154 144)(font "Arial" (font_size 8)))

(port

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(text "avmm_csr_write" (rect 4 149 88 160)(font "Arial" (font_size 8)))

(port

(pt 0 216)

(input)

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(port

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(text "avmm_data_write" (rect 4 253 94 264)(font "Arial" (font_size 8)))

(port

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(port

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(output)

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(text "avmm_data_waitrequest" (rect 4 285 130 296)(font "Arial" (font_size 8)))

(port

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(output)

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(text "avmm_data_readdatavalid" (rect 4 301 142 312)(font "Arial" (font_size 8)))

(drawing

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(text "readdata" (rect 149 275 346 560)(font "Arial" (color 0 0 0)))

(text "waitrequest" (rect 149 291 364 592)(font "Arial" (color 0 0 0)))

(text "readdatavalid" (rect 149 307 376 624)(font "Arial" (color 0 0 0)))

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)

)