repo2/atari_chips/pokeyv2/fir_buffer.cmp
| 1454 | markw | --Copyright (C) 2024 Intel Corporation. All rights reserved.
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--Your use of Intel Corporation's design tools, logic functions
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--and other software and tools, and any partner logic
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--functions, and any output files from any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Intel Program License
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--Subscription Agreement, the Intel Quartus Prime License Agreement,
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--the Intel FPGA IP License Agreement, or other applicable license
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--agreement, including, without limitation, that your use is for
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--the sole purpose of programming logic devices manufactured by
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--Intel and sold by Intel or its authorized distributors. Please
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--refer to the applicable agreement for further details, at
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--https://fpgasoftware.intel.com/eula.
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component fir_buffer
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PORT
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(
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data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
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rdaddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
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rdclock : IN STD_LOGIC ;
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wraddress : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
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wrclock : IN STD_LOGIC := '1';
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wren : IN STD_LOGIC := '0';
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q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
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);
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end component;
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