repo2/atari_chips/pokey/pokey_poly_17_9.vhdl
| 714 | markw | ---------------------------------------------------------------------------
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY pokey_poly_17_9 IS
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PORT
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(
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CLK : IN STD_LOGIC;
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RESET_N : IN STD_LOGIC;
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ENABLE : IN STD_LOGIC;
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SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low
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INIT : IN STD_LOGIC;
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BIT_OUT : OUT STD_LOGIC;
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RAND_OUT : OUT std_logic_vector(7 downto 0)
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);
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END pokey_poly_17_9;
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ARCHITECTURE vhdl OF pokey_poly_17_9 IS
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signal shift_reg: std_logic_vector(16 downto 0);
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signal shift_next: std_logic_vector(16 downto 0);
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signal cycle_delay_reg : std_logic;
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signal cycle_delay_next : std_logic;
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| 795 | markw | ||
signal select_9_17_del_reg : std_logic;
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signal select_9_17_del_next : std_logic;
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| 714 | markw | ||
signal feedback : std_logic;
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BEGIN
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-- register
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process(clk,reset_n)
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begin
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if (reset_n = '0') then
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shift_reg <= "01010101010101010";
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cycle_delay_reg <= '0';
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| 795 | markw | select_9_17_del_reg <= '0';
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| 714 | markw | elsif (clk'event and clk='1') then
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shift_reg <= shift_next;
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cycle_delay_reg <= cycle_delay_next;
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| 795 | markw | select_9_17_del_reg <= select_9_17_del_next;
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| 714 | markw | end if;
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end process;
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-- next state (as pokey decap)
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feedback <= shift_reg(13) xnor shift_reg(8);
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| 795 | markw | process(enable,shift_reg,feedback,select_9_17,select_9_17_del_reg,init,cycle_delay_reg)
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| 714 | markw | begin
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shift_next <= shift_reg;
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cycle_delay_next <= cycle_delay_reg;
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| 795 | markw | select_9_17_del_next <= select_9_17_del_reg;
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| 714 | markw | ||
if (enable = '1') then
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| 795 | markw | select_9_17_del_next <= select_9_17;
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| 714 | markw | shift_next(15 downto 8) <= shift_reg(16 downto 9);
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shift_next(7) <= feedback;
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shift_next(6 downto 0) <= shift_reg(7 downto 1);
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| 795 | markw | shift_next(16) <= ((feedback and select_9_17_del_reg) or (shift_reg(0) and not(select_9_17))) and not(init);
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| 714 | markw | ||
cycle_delay_next <= shift_reg(9);
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end if;
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end process;
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-- output
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bit_out <= cycle_delay_reg; -- from pokey schematics
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RAND_OUT(7 downto 0) <= not(shift_reg(15 downto 8));
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END vhdl;
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