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<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
<file
path="osc_in_sim/altera_gpio_lite/altera_gpio_lite.sv"
type="SYSTEM_VERILOG"
library="osc_in" />
<file
path="osc_in_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv"
type="SYSTEM_VERILOG_ENCRYPT"
library="osc_in"
simulator="modelsim" />
<file path="osc_in_sim/osc_in.vhd" type="VHDL" />
<topLevel name="osc_in" />
<deviceFamily name="max10" />
</simPackage>