repo2/atari_chips/antic/complete_address_decoder.vhdl
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-- (c) 2013 mark watson
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-- I am happy for anyone to use this for non-commercial use.
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-- If my vhdl files are used commercially or otherwise sold,
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-- please contact me for explicit permission at scrameta (gmail).
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-- This applies for source and binary form and derived works.
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---------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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ENTITY complete_address_decoder IS
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generic (width : natural := 1);
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PORT
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(
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addr_in : in std_logic_vector(width-1 downto 0);
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addr_decoded : out std_logic_vector((2**width)-1 downto 0)
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);
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END complete_address_decoder;
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--ARCHITECTURE vhdl OF complete_address_decoder IS
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--BEGIN
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-- comp_gen:
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-- for i in 0 to ((2**width)-1) generate
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-- addr_decoded(i) <= '1' when i=to_integer(unsigned(addr_in)) else '0';
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-- end generate;
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--end vhdl;
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architecture tree of complete_address_decoder is
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constant STAGE : natural:=width;
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type std_logic_2d is array (natural range <>,natural range <>) of std_logic;
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signal p: std_logic_2d(stage downto 0,2**stage-1 downto 0);
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signal a: std_logic_vector(width-1 downto 0) ;
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begin
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a<=addr_in;
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process(a,p)
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begin
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p(stage,0) <= '1';
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for s in stage downto 1 loop
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for r in 0 to (2**(stage-s)-1) loop
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p(s-1,2*r) <= (not a(s-1)) and p(s,r);
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p(s-1,2*r+1) <= a(s-1) and p(s,r);
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end loop;
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end loop;
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for i in 0 to (2**stage-1) loop
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addr_decoded(i) <= p(0,i);
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end loop;
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end process;
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end tree;
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