Activity
From 04/30/2017 to 05/29/2017
05/28/2017
- SA 10:15 PM Feature #2: PBI support
- foft wrote:
> Interesting the acid test now fails with this core, which explains the blips I got when running real cartridges before. So probably some antic timings are wrong when the active cycle is in the 2nd colour clock of the cycle... - FO 10:05 PM Feature #2: PBI support
- Interesting the acid test now fails with this core, which explains the blips I got when running real cartridges before. So probably some antic timings are wrong when the active cycle is in the 2nd colour clock of the cycle.
- FO 09:59 PM Feature #2: PBI support
- PBI lives!!
Still some debugging to do but so far...
Cartridges are working again, which is a good sign (these are now via the PBI component)
Turbo freezer works - sort of! Sometimes is seems inactive and the memory expansion doesn'...
05/27/2017
- FO 10:49 PM Feature #2: PBI support
- Still no luck with signaltap, so got the real logic analyzer on the GPIOs to debug. Squashed one sync bug but still no dice. But now confident I can get the values I need out where I can see them at least.
- FO 10:28 AM Feature #2: PBI support
- I started to bisect to find the problem - and found the core stops working when connecting RAS and CAS! Which are largely just for show, I doubt anyone will really use a 1064... Anyway I checked the pin assignments and found a bunch of d...
- FO 11:20 AM Arriving!
- The first board has arrived, the rest should be there shortly.
Please post in the forum when you board arrives and tell us what you think.
Its worth putting on the v8.sof firmware on arrival. I hope to have one with pbi support soo... - FO 10:46 AM Bug #17: NTSC crashing on some builds
- Interesting when I build on AWS I get completely screwed up builds with the registered sdram input. Seemingly every time.
05/26/2017
- FO 08:53 PM Feature #2: PBI support
- The core blows up with signaltap2 enabled! Looks great on sim, but I can't see what is going wrong on the actual hardware:-(
05/25/2017
- SA 11:29 PM Feature #2: PBI support
- foft wrote:
> Made several more fixes and the core no longer crashes with PBI enabled. However it all crashes when I plug in a cartridge! These worked without PBI support, but I replaced the cartridge logic too when I implemented this. ... - FO 11:10 PM Feature #2: PBI support
- Made several more fixes and the core no longer crashes with PBI enabled. However it all crashes when I plug in a cartridge! These worked without PBI support, but I replaced the cartridge logic too when I implemented this. Interestingly s...
05/24/2017
- SA 11:49 PM Document: Notes and a guide for spacers - v3 prototype
- SA 11:42 PM Document: First owner notice - v1 Prototype
- FO 10:09 PM Feature #2: PBI support
- Looking good on simulation now but does not run on the board. I think the issue is when pbi takes over the bus when a transaction is already in process.
This is all so complicated because I'm running the clock at 32x the original one...
05/23/2017
- FO 09:43 PM Feature #2: PBI support
- Integrated into the description and synthesising:-)
For now I took the strategy of delaying the cycle until we know if PBI wants to take over. Its enabled only in 1x speed for now.
05/22/2017
- FO 09:55 PM Feature #2: PBI support
- PBI looking good on simulation (bit itself). Based timings on the Freddie data sheet.
Made a start on wiring it up to the core. Need to remind myself how the enable strategy works and what they are all used for.
Initial idea is to ju...
05/21/2017
- FO 02:37 PM Feature #2: PBI support
- Started on a PBI component that will correctly communicate with the bus. Then this can be checked/simulated - and as a later stage I can do the core connection.
05/20/2017
- FO 10:39 PM Bug #17: NTSC crashing on some builds
- I've still had bad builds since registering the sdram input directly.
I tried to specify an externally switchable input clock for timequest as a proxy for ntsc/pal clocks. However it doesn't make it past derive_pll_clocks, so I guess ... - FO 10:36 PM Feature #8: Implement 4 channel ADC
- So I guess we should have some more passive components here. On the other hand I'm kind of attached to SIO noise down to cable interference. If we fix this too well we may lose that!
- FO 10:35 PM Feature #8: Implement 4 channel ADC
- Pretty sure this is down to floating inputs. Since there is no driver and low capacitance the input picks up the previous sample stored in the ADC. I checked this out by trying two approaches:
i) Sample a single channel and checking for...
05/18/2017
- FO 11:01 PM Feature #8: Implement 4 channel ADC
- Sigh, it definitely works but if I read say channel 1 - I still receive input from the other channels
- FO 09:00 PM Feature #8: Implement 4 channel ADC
- Debugged and now working.
PBI and SIO audio will be mixed. For now I'm not feeding MIC_L and MIC_R anywhere - these will be connected to some sampler register. I guess D500 and D501 if the 'replay cartrige mode' is enabled. - FO 06:56 AM Feature #8: Implement 4 channel ADC
- Now I have the board its clear this needs debugging.
- FO 06:58 AM Feature #1: Svideo sync line support
- Received the board and gave this a go. svideo and composite look nice and bright now. However saturation is too low, need to work out how to boost this without too much impact to brightness.
Also need to work out why its just black an...
05/16/2017
- FO 09:24 PM Feature #13: 32x speed cpu without wait states
- I enabled 32x mode in the core and sorted out single cycle writes from the block ram for now. Hardly any difference in sysinfo but good to see at least some difference.
- FO 09:22 PM Bug #17: NTSC crashing on some builds
- Ijor recommended I try registering the input directly from SDRAM. I've done this and see if it helps.
He is also kindly helping me write some correct timequest rules, really appreciated:) - FO 08:30 PM It is time!
- Panos will be in touch about shipping...
05/12/2017
- FO 09:52 PM Bug #17 (Closed): NTSC crashing on some builds
- Investigate why... On the v1 core this occurred when running the PLL at very high fVCO. However we already fixed that in v1, so not sure why.
- FO 07:48 PM Bug #16 (Closed): Audio bug report for Altirra
- One for the coders, please can you check if these bugs are present?
From post on atariage...
http://atariage.com/forums/topic/256683-altirra-280-released/page-24#entry3760704
Let me report a couple of issues with POKEY chip in Altir...
05/11/2017
- FO 09:42 PM Feature #15: Implement programmable PLL
- Attaching PLL chip datasheet
- FO 09:41 PM Feature #15 (New): Implement programmable PLL
- See if the programmable PLL works. This will allow us to support different/custom VGA modes, once we have EDID/DDC working. For now I just want to find out if its alive.
- FO 08:38 PM Feature #13: 32x speed cpu without wait states
- So thinking about options...
Double the main clock speed and pipeline a bit
or
Output next address from antic and the cpu, so I can read the memory 1 cycle earlier - antic clearly knows what it will read, does the 6502 core?
or
A... - FO 08:34 PM Feature #7: Implement I2C vga/hdmi support
- Used this controller for the ADC on v1: https://eewiki.net/pages/viewpage.action?pageId=10125324
So I guess I just need to wire this to the ZPU, then I can experiment with this in firmware.
I guess a write FIFO that captures 16 bits ... - FO 08:30 PM Feature #7: Implement I2C vga/hdmi support
- DDC looks a little funkier
- FO 08:28 PM Feature #7: Implement I2C vga/hdmi support
- EDID is apparently one of these I can access at address 0x50
- FO 08:26 PM Feature #7: Implement I2C vga/hdmi support
- Attached mux/level converter chip data sheet
- FO 08:27 PM Feature #8: Implement 4 channel ADC
- Attached ADC data sheet
- FO 08:25 PM No sign of FT232 chips
- Panos is chasing up - and if not good news he will order from somewhere quicker!
In the meantime I've added ADC support to the new core, important for SIO sounds such as tapes with speech and just plain interference from the cable!
05/08/2017
- FO 10:08 PM Feature #8 (In Progress): Implement 4 channel ADC
- Written initial support based on data sheet and simulated. Not yet built into test core or tried on real hardware.
So far all four channels sampled, but only SIO input connected to core.
05/04/2017
- FO 09:25 PM Feature #13: 32x speed cpu without wait states
- Nope, this is not going to be so simple... Massive timing violations.
05/03/2017
- FO 08:27 PM Missing parts
- Panos is waiting for the last few remaining parts to arrive. Most notably the FT232 USB chip. We're expecting they will arrive later this week.
05/02/2017
- FO 10:15 PM Feature #14: Svideo core for first prototype
- Debugged in isim to get lots of overflow/underflow/blanking/burst incorrect cases!
Added colour bars and asserts for under/overflow. Looks like we have more space than I thought to allow slightly higher luma scaling (224/256). Verifying... - FO 06:40 AM Feature #14: Svideo core for first prototype
- Scaled luma with 64 space for chroma - when in composite mode only. No point throwing away svideo brightness.
Added composite to video selection menu - since the G pin is used for both it can't be generated together.
Built for v1 a... - FO 06:38 AM Sub PCB - now populated!
- !sub-board-pop.jpg!
04/30/2017
- FO 09:06 PM Sub-board
- Here is the first picture of a sub-board, which also arrived in Greece. None completed yet but all the parts fit - and they fit in the Mhero S R case.
!sub-board.jpg!
- FO 09:01 PM Video DAC regulator patch
- Here is a picture of the patch Panos has skillfully applied to the boards.
!patch.jpg! - FO 08:58 PM Boards received
- The boards arrived in Greece. Panos is in the process of adding some final parts and trying them out.
Some good news:
FPGA is seen on JTAG
FPGA can be flashed ok
The core runs, the USB keyboard is working, SD card access is workin...