Activity

From 04/25/2017 to 05/24/2017

FO 10:09 PM Feature #2: PBI support: Looking good on simulation now but does not run on the board. I think the issue is when pbi takes over the bus when a transaction is already in process.
This is all so complicated because I'm running the clock at 32x the original one... foft

FO 09:43 PM Feature #2: PBI support: Integrated into the description and synthesising:-)
For now I took the strategy of delaying the cycle until we know if PBI wants to take over. Its enabled only in 1x speed for now. foft

FO 09:55 PM Feature #2: PBI support: PBI looking good on simulation (bit itself). Based timings on the Freddie data sheet.
Made a start on wiring it up to the core. Need to remind myself how the enable strategy works and what they are all used for.
Initial idea is to ju... foft

FO 02:37 PM Feature #2: PBI support: Started on a PBI component that will correctly communicate with the bus. Then this can be checked/simulated - and as a later stage I can do the core connection. foft

FO 10:39 PM Bug #17: NTSC crashing on some builds: I've still had bad builds since registering the sdram input directly.
I tried to specify an externally switchable input clock for timequest as a proxy for ntsc/pal clocks. However it doesn't make it past derive_pll_clocks, so I guess ... foft
FO 10:36 PM Feature #8: Implement 4 channel ADC: So I guess we should have some more passive components here. On the other hand I'm kind of attached to SIO noise down to cable interference. If we fix this too well we may lose that! foft
FO 10:35 PM Feature #8: Implement 4 channel ADC: Pretty sure this is down to floating inputs. Since there is no driver and low capacitance the input picks up the previous sample stored in the ADC. I checked this out by trying two approaches:
i) Sample a single channel and checking for... foft

FO 11:01 PM Feature #8: Implement 4 channel ADC: Sigh, it definitely works but if I read say channel 1 - I still receive input from the other channels foft
FO 09:00 PM Feature #8: Implement 4 channel ADC: Debugged and now working.
PBI and SIO audio will be mixed. For now I'm not feeding MIC_L and MIC_R anywhere - these will be connected to some sampler register. I guess D500 and D501 if the 'replay cartrige mode' is enabled. foft
FO 06:56 AM Feature #8: Implement 4 channel ADC: Now I have the board its clear this needs debugging. foft
FO 06:58 AM Feature #1: Svideo sync line support: Received the board and gave this a go. svideo and composite look nice and bright now. However saturation is too low, need to work out how to boost this without too much impact to brightness.
Also need to work out why its just black an... foft

FO 09:24 PM Feature #13: 32x speed cpu without wait states: I enabled 32x mode in the core and sorted out single cycle writes from the block ram for now. Hardly any difference in sysinfo but good to see at least some difference. foft
FO 09:22 PM Bug #17: NTSC crashing on some builds: Ijor recommended I try registering the input directly from SDRAM. I've done this and see if it helps.
He is also kindly helping me write some correct timequest rules, really appreciated:) foft

FO 09:52 PM Bug #17 (Closed): NTSC crashing on some builds: Investigate why... On the v1 core this occurred when running the PLL at very high fVCO. However we already fixed that in v1, so not sure why.
foft
FO 07:48 PM Bug #16 (Closed): Audio bug report for Altirra: One for the coders, please can you check if these bugs are present?
From post on atariage...
http://atariage.com/forums/topic/256683-altirra-280-released/page-24#entry3760704
Let me report a couple of issues with POKEY chip in Altir... foft

FO 09:42 PM Feature #15: Implement programmable PLL: Attaching PLL chip datasheet foft
FO 09:41 PM Feature #15 (New): Implement programmable PLL: See if the programmable PLL works. This will allow us to support different/custom VGA modes, once we have EDID/DDC working. For now I just want to find out if its alive. foft
FO 08:38 PM Feature #13: 32x speed cpu without wait states: So thinking about options...
Double the main clock speed and pipeline a bit
or
Output next address from antic and the cpu, so I can read the memory 1 cycle earlier - antic clearly knows what it will read, does the 6502 core?
or
A... foft
FO 08:34 PM Feature #7: Implement I2C vga/hdmi support: Used this controller for the ADC on v1: https://eewiki.net/pages/viewpage.action?pageId=10125324
So I guess I just need to wire this to the ZPU, then I can experiment with this in firmware.
I guess a write FIFO that captures 16 bits ... foft
FO 08:30 PM Feature #7: Implement I2C vga/hdmi support: DDC looks a little funkier foft
FO 08:28 PM Feature #7: Implement I2C vga/hdmi support: EDID is apparently one of these I can access at address 0x50 foft
FO 08:26 PM Feature #7: Implement I2C vga/hdmi support: Attached mux/level converter chip data sheet foft
FO 08:27 PM Feature #8: Implement 4 channel ADC: Attached ADC data sheet foft

FO 10:08 PM Feature #8 (In Progress): Implement 4 channel ADC: Written initial support based on data sheet and simulated. Not yet built into test core or tried on real hardware.
So far all four channels sampled, but only SIO input connected to core. foft

FO 09:25 PM Feature #13: 32x speed cpu without wait states: Nope, this is not going to be so simple... Massive timing violations. foft

FO 10:15 PM Feature #14: Svideo core for first prototype: Debugged in isim to get lots of overflow/underflow/blanking/burst incorrect cases!
Added colour bars and asserts for under/overflow. Looks like we have more space than I thought to allow slightly higher luma scaling (224/256). Verifying... foft
FO 06:40 AM Feature #14: Svideo core for first prototype: Scaled luma with 64 space for chroma - when in composite mode only. No point throwing away svideo brightness.
Added composite to video selection menu - since the G pin is used for both it can't be generated together.
Built for v1 a... foft

FO 08:54 PM Feature #14: Svideo core for first prototype: Setting this up in the simulator so I can understand chroma better.
The problem seems to be that I've used all the space for luma and chroma is a sine wave +-255. For some reason it only allows space of 32 though - which is odd! Anywa... foft
FO 08:51 PM Feature #13: 32x speed cpu without wait states: I have something working on the simulator - alone. Now need to plug it into the core proper to see if it works. Will probably need some clever timequest rules too, since the read/write deadlines are different now. foft

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