Activity

From 04/05/2017 to 05/04/2017

FO 09:25 PM Feature #13: 32x speed cpu without wait states: Nope, this is not going to be so simple... Massive timing violations. foft

FO 08:27 PM Missing parts: Panos is waiting for the last few remaining parts to arrive. Most notably the FT232 USB chip. We're expecting they will arrive later this week. foft

FO 10:15 PM Feature #14: Svideo core for first prototype: Debugged in isim to get lots of overflow/underflow/blanking/burst incorrect cases!
Added colour bars and asserts for under/overflow. Looks like we have more space than I thought to allow slightly higher luma scaling (224/256). Verifying... foft
FO 06:40 AM Feature #14: Svideo core for first prototype: Scaled luma with 64 space for chroma - when in composite mode only. No point throwing away svideo brightness.
Added composite to video selection menu - since the G pin is used for both it can't be generated together.
Built for v1 a... foft
FO 06:38 AM Sub PCB - now populated!: !sub-board-pop.jpg! foft

FO 09:06 PM Sub-board: Here is the first picture of a sub-board, which also arrived in Greece. None completed yet but all the parts fit - and they fit in the Mhero S R case.
!sub-board.jpg!
foft
FO 09:01 PM Video DAC regulator patch: Here is a picture of the patch Panos has skillfully applied to the boards.
!patch.jpg! foft
FO 08:58 PM Boards received: The boards arrived in Greece. Panos is in the process of adding some final parts and trying them out.
Some good news:
FPGA is seen on JTAG
FPGA can be flashed ok
The core runs, the USB keyboard is working, SD card access is workin... foft

SA 11:43 PM Document: Eclaire XL v1.0 Board Spec: Eclaire XL v1.0 Board Spec sadosp
SA 11:43 PM Eclaire XL v1.0.jpg: sadosp
SA 11:43 PM Eclaire XL v1.0 b.JPG: sadosp
SA 11:42 PM Eclaire XL v1.0 Spec.odt: sadosp
SA 11:42 PM Eclaire XL v1.0 Spec.jpg: sadosp
FO 08:54 PM Feature #14: Svideo core for first prototype: Setting this up in the simulator so I can understand chroma better.
The problem seems to be that I've used all the space for luma and chroma is a sine wave +-255. For some reason it only allows space of 32 though - which is odd! Anywa... foft
FO 08:51 PM Feature #13: 32x speed cpu without wait states: I have something working on the simulator - alone. Now need to plug it into the core proper to see if it works. Will probably need some clever timequest rules too, since the read/write deadlines are different now. foft

FO 10:14 PM Feature #14: Svideo core for first prototype: Should add that this should not be done for direct chroma output for svideo... Since that is still on a 0-0.7V DAC output. foft
FO 10:14 PM Feature #14: Svideo core for first prototype: Panos tried out a new core with composite only - on green using the sync pin. Looks brighter but just black and white - on several TVS.
I think its black and white because...
Basically I re-scaled Y to use the full DAC range. Compo... foft
FO 07:58 PM Feature #14 (Closed): Svideo core for first prototype: Waiting the Chinese sun to rising, I decide to proceed with the "video mod" of our v 1.0 board. So I desolder the "vsync" pin 12 of video dac, and solder it again using a "kynar cable" to a near via, which drive directly to F15 of FPGA.
... foft
FO 07:56 PM Pictures!: The PCB company sent us an initial picture!
!v3board_small.jpg! foft

FO 10:19 PM Delays: We received an update from the PCB company. Unfortunately it wasn't to say 'shipping' as we'd hoped.
Instead they requested some more information for their machine setup, so apparently they have not started assembly yet as promised!
... foft

FO 10:07 PM Feature #13 (In Progress): 32x speed cpu without wait states: Trying simply feeding in the clock at twice the speed to see if it passes timing! foft

SA 09:46 PM Feature #1: Svideo sync line support: admin wrote:
> Doesn't look too hard to change. In the svideo component they do this for luma:
> ...
\
In all the cases we need to connect the sync pin of dac on a I/O of fpga?
sadosp
FO 08:35 PM Feature #1 (Resolved): Svideo sync line support: Implemented in test core, probably will need some debugging... foft

FO 08:08 PM Feature #13 (New): 32x speed cpu without wait states: The whole system is clocked at 32*original clock. However the 6502 turbo is limited to 16x due to the ram speed, since a block ram access cycle takes 2 cycles. Try to clock the block ram at 64* original clock as a quick win to get 32x tu... foft

FO 09:37 PM Feature #2 (In Progress): PBI support: foft
FO 08:57 PM Feature #12 (In Progress): Set up redmine backups!: Adding svn backups too while at it.
Need to do these to the raid instead of to another local disk though really...
foft
FO 08:41 PM Feature #12: Set up redmine backups!: Added file backups
Both these are as crons under postgres_backup user foft
FO 08:23 PM Feature #12: Set up redmine backups!: Added postgres backups.
TODO: verify it runs from cron ok foft
FO 07:53 PM Bug #9 (Rejected): Fix svn repository: Decided to just disable this - its complicated enough anyway an the svn can already be checked out or browsed. foft
FO 07:45 PM Feature #10 (Closed): Set up email in redmine: Found password, set up config and tested ok. foft
FO 06:59 PM Parts arriving monday: Sent on:9:04 amFrom:Eric Wu
hi Panos
THE COMPONENTS WILL COME HERE ON MONDAY
THEN START to fabricate
about 3-4days to ship out foft

SA 05:59 AM Document: MHero S R ext JTAG installation - v1 prototype: sadosp
SA 05:57 AM JTAG External Guide.odt: MHero S R ext JTAG installation - v1 prototype sadosp
SA 05:56 AM Document: eclaire XL HW Spec - v1 prototype: sadosp
SA 05:56 AM eclaire XL HW Specifications - v1 proto.txt: eclaire XL HW Spec - v1 prototype sadosp
SA 05:52 AM Document: Atari 800 User Manual Generic: sadosp
SA 05:51 AM Atari 800 FPGA Manual.pdf: Atari 800 FPGA User Manual Generic sadosp
SA 05:49 AM eclaire XL new v1.0.sch: Main Board schema sadosp
SA 05:49 AM eclaire XL new v1.0.brd: Main Board pcb sadosp

FO 10:06 PM Feature #12 (Closed): Set up redmine backups!: Set up backups for this... foft
AD 09:46 PM Sub PCB - ready: SUB BOARD
Techonology Finished Finished Time
MI (Manufacture Instruction) 2017/3/30 23:25:07
Board Cutting 2017/3/31 6:11:23
Drill 2017/3/31 6:20:52
First Routing 2017/3/31 10:39:14
Plated Through Hole 2017/3/31 10:3... admin
FO 09:13 PM Bug #9: Fix svn repository: Removed for now foft
AD 09:12 PM Feature #10: Set up email in redmine: Need password! admin
AD 09:09 PM Main PCB - ready!: Techonology Finished Finished Time
MI (Manufacture Instruction) 2017/4/1 21:45:19
Board Cutting 2017/4/1 21:56:23
Drill 2017/4/3 0:00:18
Inner Circuit 2017/4/2 8:42:02
Inner Etching 2017/4/2 10:53:08
Inner Laminating... admin
AD 08:34 PM JTAG External Guide (1).pdf: Add JTAG to external ports admin
AD 08:34 PM Document: MHero S R installation instructions - v1 prototype: admin
AD 08:33 PM ITX CASE Assembly Guide (3).pdf: admin
FO 06:59 AM Feature #11 (New): Non-uk keyboard support (custom keyboard mapping): Only a uk keyboard with stickers is supported right now.
Make this remappable via a file. foft

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EclaireXL