EclaireXL

Will have a look after PBI support - or as part of it. I'm replacing the cartridge reading logic as part of that.

Not sure what you mean here. If I put in a cartridge and press F10 then the computer reboots and the cartridge runs. I checked with pole position, frogger and bug hunt.

do you have an XEG cart with more than 16?
try one of the carts that do Bank Switching

Nir

Bug hunt does bank switching

Ah, I see what you mean. The hard reset does not power off the system. So if the cart has state then it won't reset that. Not sure what I can do about that one since I can't power off the cartridge.

I mean the 'hard reset' just clears memory then drops the reset line.

it should also clear the D5XX to its imitate state so the bank switching cart will be set to its default state

I can't tell the init state, since its an external cartridge. The logic could set up the registers written to by D500 to any value. Its possible most default to 00, but it can't be known.

If you think writing 0 to D500 will increase compatibility happy to add.

yes i think so..

there are different banking cart schemes, some use data to change bank and other use address to change their banks
i think that writing 00 to D500 and set the Address line D5XX to D500 will cover them all

Nir

OK, I'll add that in v9

Added to svn code

Arg, of course I turned off pbi/cart in turbo mode and on zpu accesses... Better change that too I guess otherwise I can't do this from the firmware!

Bumped to v10...

This is still on the list, but not yet in place...

This is the last thing remaining for V15. In order to do it (simply) I decided to allow off PBI access from turbo mode and zpu. That seems to work now, except its failing timing. I think I need to plumb the internal freezer in differently to meet timing, thinking about how to do that.

What am I expecting to see happen with this change to write to D500? I think its enabled in my test core (though need to connect LA to check) yet I haven't spotted any difference yet!