Revision 1546
Added by markw 5 days ago
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signal ram_record_enabled_next : std_logic;
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signal ram_record_source_reg : std_logic;
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signal ram_record_source_next : std_logic;
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signal data_to_write : std_logic_vector(7 downto 0);
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signal ch0_start_addr_reg : std_logic_vector(15 downto 0);
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signal ch0_start_addr_next : std_logic_vector(15 downto 0);
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| ... | ... | |
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adpcm_data_ready_next <= '0';
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end if;
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end process;
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process(ram_record_source_reg, request, DI, AUDIO_IN0, AUDIO_IN1)
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begin
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DATA_TO_WRITE <= DI;
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if (request='0') then
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if (ram_record_source_reg='1') then
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DATA_TO_WRITE <= std_logic_vector(AUDIO_IN1(15 downto 8));
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else
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DATA_TO_WRITE <= std_logic_vector(AUDIO_IN0(15 downto 8));
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end if;
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end if;
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end process;
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process(clk,reset_n)
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begin
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| ... | ... | |
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RAM_WRITE_ENABLE <= RAM_CPU_WRITE_ENABLE OR RAM_RECORD_WRITE_ENABLE;
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RAM_WRITE_DATA <= std_logic_vector(AUDIO_IN1(15 downto 8)) when ram_record_source_reg='1' else std_logic_vector(AUDIO_IN0(15 downto 8));
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RAM_WRITE_DATA <= DATA_TO_WRITE;
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END vhdl;
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Fix the CPU writes to sample ram