Revision 1510
Added by markw 1 day ago
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DI : in std_logic_vector(7 downto 0);
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DO : out std_logic_vector(7 downto 0);
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AUDIO0 : out std_logic_vector(15 downto 0);
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AUDIO1 : out std_logic_vector(15 downto 0);
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AUDIO0 : out signed(15 downto 0);
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AUDIO1 : out signed(15 downto 0);
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IRQ : out std_logic;
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RAM_ADDR : out std_logic_vector(15 downto 0);
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| ... | ... | |
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process(addr_decoded5,CH0_REG,CH1_REG,CH2_REG,CH3_REG,
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ram_cpu_addr_reg, ram_data,
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irq_en_reg,irq_active_reg
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irq_en_reg,irq_active_reg,
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adpcm_reg,bits8_reg
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)
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begin
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DO <= (others=>'0');
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| ... | ... | |
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store_data <= (others=>'0');
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case store_source is
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when "0001"|"0011"|"0101"|"0111"|"1001"|"1011"|"1101"|"1111" =>
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store_data(12 downto 5) <= di;
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store_data(12) <= not(di(7));
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store_data(11 downto 5) <= di(6 downto 0);
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when "0110"|"1110" =>
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store_data <= adpcm_decoded(15 downto 3);
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when "1100" =>
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store_data(12) <= not(ram_data(7));
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store_data(11 downto 5) <= ram_data(6 downto 0);
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store_data(12 downto 5) <= ram_data(7 downto 0);
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when "0100" =>
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if (data_nibble='0') then
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store_data(12) <= not(ram_data(7));
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store_data(11 downto 9) <= ram_data(6 downto 4);
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store_data(12 downto 9) <= ram_data(7 downto 4);
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else
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store_data(12) <= not(ram_data(3));
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store_data(11 downto 9) <= ram_data(2 downto 0);
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store_data(12 downto 9) <= ram_data(3 downto 0);
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end if;
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when others=>
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| ... | ... | |
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process (ch0_reg,ch1_reg,ch2_reg,ch3_reg,
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ch0_volume_reg,ch1_volume_reg,ch2_volume_reg,ch3_volume_reg)
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variable l : unsigned(26 downto 0);
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variable r : unsigned(26 downto 0);
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variable l : signed(26 downto 0);
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variable r : signed(26 downto 0);
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begin
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l := resize(unsigned(CH0_REG),18)*resize(unsigned(ch0_volume_reg),9);
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l := l + resize(unsigned(CH3_REG),18)*resize(unsigned(ch3_volume_reg),9);
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r := resize(unsigned(CH1_REG),18)*resize(unsigned(ch1_volume_reg),9);
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r := r + resize(unsigned(CH2_REG),18)*resize(unsigned(ch2_volume_reg),9);
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l := resize(signed(CH0_REG),18)*resize(signed('0'&ch0_volume_reg),9);
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l := l + resize(signed(CH3_REG),18)*resize(signed('0'&ch3_volume_reg),9);
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r := resize(signed(CH1_REG),18)*resize(signed('0'&ch1_volume_reg),9);
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r := r + resize(signed(CH2_REG),18)*resize(signed('0'&ch2_volume_reg),9);
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-- TODO: probably need to register here?
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AUDIO0 <= std_logic_vector(l(19 downto 4));
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AUDIO1 <= std_logic_vector(r(19 downto 4));
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AUDIO0(15 downto 0) <= l(19 downto 4);
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AUDIO1(15 downto 0) <= r(19 downto 4);
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-- TODO: modulation?
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-- TODO: samples from rom and put in voice samples after core?
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Use natural signed/unsigned source depending on which chip. Mix with signed, with a dc blocker. Add a bit more dither to make the mid level voltage acceptable through the sigma delta, since it now sits a 2.5v for silence (internally, external is ac coupled). This fixes the sample engine clicks when playing mod files due to the sample engine volume being applied on unsigned converted samples, which gave a dc bias betwen samples. Paula samples have to end/start at signed midpoint you see.