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Revision 1481
Added by markw 13 days ago
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if (((enable_15 and not(skctl_reg(2))) or (enable_179 and skctl_reg(2))) = '1') then
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pot_counter_next <= std_logic_vector(unsigned(pot_counter_reg) + 1);
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if (pot_counter_reg = X"E4") then
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pot_reset_next <= '1'; -- turn on pot dump transistors
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allpot_next <= (others=>'0');
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end if;
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if (pot_reset_reg = '0') then
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if (pot_in(0) = '0') then -- pot now high, latch
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| ... | ... | |
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allpot_next <= allpot_reg and not(pot_in);
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end if;
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if (pot_counter_reg = X"E4") then
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pot_reset_next <= '1'; -- turn on pot dump transistors
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allpot_next <= (others=>'0');
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end if;
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end if;
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if (potgo_write = '1') then
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| ... | ... | |
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sio_clockin_oe <= not(clock_input);
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sio_clockin_out <= serin_clock_reg;
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pot_reset <= pot_reset_reg;
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pot_reset <= pot_reset_reg and not(skctl_reg(2));
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END vhdl;
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Also available in: Unified diff
Disable dump transistors in fast pot scan mode. When counter is E4 reset allpot_next (it was overwritten because pot_reset_reg is 0).