Revision 1472
Added by markw 7 months ago
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-- spdif
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signal spdif_mux : std_logic_vector(15 downto 0);
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signal spdif_right : std_logic;
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signal spdif_left : std_logic;
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signal spdif_out : std_logic;
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signal CLK6144 : std_logic; --spdif
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signal AUDIO_2_FILTERED : unsigned(15 downto 0);
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| ... | ... | |
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spdif_on : if enable_spdif=1 generate
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-- todo: clock domain crossing!
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spdif_mux <= std_logic_vector(audio_2_filtered) when spdif_right='0'
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spdif_mux <= std_logic_vector(audio_2_filtered) when spdif_left='1'
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else std_logic_vector(audio_3_filtered);
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filter_left : entity work.simple_low_pass_filter
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| ... | ... | |
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data_in(23) => not(spdif_mux(15)),
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data_in(22 downto 8) => spdif_mux(14 downto 0),
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data_in(7 downto 0) => (others=>'0'),
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address_out => spdif_right,
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address_out => spdif_left,
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spdif_out => spdif_out
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);
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Also available in: Unified diff
spdif seems to have left/right backwards