Revision 1343
Added by markw almost 4 years ago
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signal audc3_next : std_logic_vector(7 downto 0);
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signal audctl_next : std_logic_vector(7 downto 0);
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signal audf0_pulse_raw : std_logic;
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signal audf1_pulse_raw : std_logic;
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signal audf2_pulse_raw : std_logic;
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signal audf3_pulse_raw : std_logic;
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signal audf0_pulse : std_logic;
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signal audf1_pulse : std_logic;
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signal audf2_pulse : std_logic;
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-- Instantiate timers
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timer0 : pokey_countdown_timer
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generic map (UNDERFLOW_DELAY=>3)
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port map(clk=>clk,enable=>audf0_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf0_reload,data_in=>audf0_next,DATA_OUT=>audf0_pulse);
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port map(clk=>clk,enable=>audf0_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf0_reload,data_in=>audf0_next,DATA_OUT=>audf0_pulse_raw);
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timer1 : pokey_countdown_timer
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generic map (UNDERFLOW_DELAY=>3)
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port map(clk=>clk,enable=>audf1_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf1_reload,data_in=>audf1_next,DATA_OUT=>audf1_pulse);
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port map(clk=>clk,enable=>audf1_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf1_reload,data_in=>audf1_next,DATA_OUT=>audf1_pulse_raw);
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timer2 : pokey_countdown_timer
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generic map (UNDERFLOW_DELAY=>3)
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port map(clk=>clk,enable=>audf2_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf2_reload,data_in=>audf2_next,DATA_OUT=>audf2_pulse);
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port map(clk=>clk,enable=>audf2_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf2_reload,data_in=>audf2_next,DATA_OUT=>audf2_pulse_raw);
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timer3 : pokey_countdown_timer
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generic map (UNDERFLOW_DELAY=>3)
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port map(clk=>clk,enable=>audf3_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf3_reload,data_in=>audf3_next,DATA_OUT=>audf3_pulse);
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port map(clk=>clk,enable=>audf3_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf3_reload,data_in=>audf3_next,DATA_OUT=>audf3_pulse_raw);
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-- Timer reloading
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process (audctl_reg, audf0_pulse, audf1_pulse, audf2_pulse, audf3_pulse, stimer_write_delayed, async_serial_reset, twotone_reset_delayed)
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process (audctl_reg, audf0_pulse_raw, audf1_pulse_raw, audf2_pulse_raw, audf3_pulse_raw, stimer_write_delayed, async_serial_reset, twotone_reset_delayed)
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begin
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audf0_reload <= ((not(audctl_reg(4)) and audf0_pulse)) or (audctl_reg(4) and audf1_pulse) or stimer_write_delayed or twotone_reset_delayed;
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audf1_reload <= audf1_pulse or stimer_write_delayed or twotone_reset_delayed;
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audf2_reload <= ((not(audctl_reg(3)) and audf2_pulse)) or (audctl_reg(3) and audf3_pulse) or stimer_write_delayed or async_serial_reset;
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audf3_reload <= audf3_pulse or stimer_write_delayed or async_serial_reset;
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audf0_reload <= ((not(audctl_reg(4)) and audf0_pulse_raw)) or (audctl_reg(4) and audf1_pulse_raw) or stimer_write_delayed or twotone_reset_delayed;
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audf1_reload <= audf1_pulse_raw or stimer_write_delayed or twotone_reset_delayed;
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audf2_reload <= ((not(audctl_reg(3)) and audf2_pulse_raw)) or (audctl_reg(3) and audf3_pulse_raw) or stimer_write_delayed or async_serial_reset;
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audf3_reload <= audf3_pulse_raw or stimer_write_delayed or async_serial_reset;
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end process;
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audf0_pulse <= audf0_pulse_raw and not(twotone_reset_delayed);
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audf1_pulse <= audf1_pulse_raw and not(twotone_reset_delayed);
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audf2_pulse <= audf2_pulse_raw and not(async_serial_reset);
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audf3_pulse <= audf3_pulse_raw and not(async_serial_reset);
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twotone_del : latch_delay_line
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generic map (count=>2)
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port map (clk=>clk, sync_reset=>'0',data_in=>twotone_reset, enable=>enable_179, reset_n=>reset_n, data_out=>twotone_reset_delayed);
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Also available in: Unified diff
Two tone reset suppresses the pulse