Revision 1325
Added by markw almost 4 years ago
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create_clock -period 1.9MHz [get_ports PHI2]
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create_clock -period 85MHz [get_ports CLK_SLOW]
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create_clock -period 87.36MHz [get_ports CLK_SLOW]
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derive_pll_clocks
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derive_clock_uncertainty
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Also available in: Unified diff
sidmax changes. Also silent pokey interference support