Add v4 xel build: CS1 forced high. Left external pin carries right internal audio instead.
Forgot to commit a few files
Refreshed v1
Allow recording 4 selected channels at once. Gate record behind a flag. Include board version in version string instead of useless leading 1
Only instantiate DC blocker if needed
Added dc blocker to all builds
Move dc blocker to be per unsigned channel. Works better for recording and now everything is signed in priciple with no dc offset for the mixer.
Allow reading the record reg.
Sid routing is using wrong bit
Recording channels were flipped
Fix pm v1 and sidmax builds following sample changes
Fix the CPU writes to sample ram
Allow recording of a channel to the sample memory (for looping etc). Allow feeding a channel to the SID ext input, in order to use filters. This mutes the original channel so its not duplicated..
Fix for right channel detection logic
Correct a few sensitivity list issues
Fix unintentional latch
Fix channel 0 getting mixed in everywhere!
Cut a few registers
v2 actually measures better than v4. Need to investigate more since it should be better.
hq_dac needs signed input
Change area optimisation flags to be more aggressive
Get sidmax buiding again by refresing it form the pokeymax changes
Add a v4 build with 64KB sample ram. Had to drop the fir to fit it, so split the build.
Added 9k grouped to allow for more block ram for sample engine
No room for 64KB sample memory with FIR filter
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