Activity

From 08/15/2017 to 09/13/2017

AD 11:24 AM Bug #59: Game test: Crownland: Save the video settings (yeah I know that doesn't make sense!) admin
JO 06:37 AM Bug #59: Game test: Crownland: Yes, it was the memory. Maybe I pushed the reset button after I set the memory. Sorry for the false alarm.
Btw. Is there a way to store the setting I make on the F12 screen? jozsef

FO 09:24 PM Feature #55: Replace main CPU: I read up on the 'altera virtual jtag' and think I now understand how to get this connected, at least in theory.
I guess next steps that might make sense are:
i) Build a core with virtual jtag and signal tap and try to send it equiv... foft

SA 10:21 PM Feature #55: Replace main CPU: :-)
sadosp
FO 10:06 PM Feature #55: Replace main CPU: Been trying out openocd locally with the cpu running in verilator. gdb connects, code loads and runs. Pretty cool! OK I just ran some commands as documented but I'm still pleased:-)
I'm very impressed with this riscv cpu project - see... foft
JO 06:37 AM Bug #59: Game test: Crownland: I feel myself sooooo dumb, if it is the reason. I have no access to my gear till next week, but that will be the first thing to check.
Sorry! jozsef

FO 09:39 PM Bug #59: Game test: Crownland: It requires 128K, can you check what memory settings you have? I can only reproduce without extended ram. foft
FO 07:44 PM Bug #59: Game test: Crownland: I'll have to check, I thought that worked.
BTW this one is better than v14: svideo_gtia9.sof foft
JO 09:55 AM Bug #59 (Closed): Game test: Crownland: Finally my USB-Blaster arrived and I could upgrade to the latest FW:v14
The game loads fine, and I can start playing. That's where the problem is: instead of the playfield graphics, only garbage appears on the screen, and the protagonis... jozsef
FO 07:43 PM Feature #55: Replace main CPU: The author of the cpu kindly got back to me with some details.
The wishbone interface adaptor looks pretty easy.
Apparently the chip uses a non-standard debugging interface though. Which is good actually since its simpler. However ... foft

FO 09:44 PM Feature #55: Replace main CPU: I've managed to get the spinal HDL project compiled, so now have a verilog or vhdl file for the CPU. It seems to have 3 ports. Instruction master, data master and debug slave. So I will need to map them into wishbone. They are also in th... foft

FO 01:40 PM Feature #55: Replace main CPU: To Panos' comment. Yeah I'd love some help, if someone could help me define the memory map and write the firmware for the RISC V that would be an enormous help. There are also many HDL parts that need doing if anyone fancies working on t... foft
FO 01:37 PM Feature #55: Replace main CPU: There are several problems with the current setup:
* The firmware is constrained by the current ZPU setup. Its hard to debug and tricky to add more memory to it.
* I'm struggling to meet timing requirements, due to the over-complex int... foft

SA 11:00 AM Feature #55: Replace main CPU: 917k wrote:
>Sounds cool. I am wondering what this will do for the project, I mean what would this actually mean to the end user?
Βeyond the technical part that I really do not fully understand, I think is an effort of Mark to stimul... sadosp
91 09:14 AM Feature #55: Replace main CPU: Sounds cool! 917k
91 08:58 AM Feature #55: Replace main CPU: Sounds cool. I am wondering what this will do for the project, I mean what would this actually mean to the end user? 917k

SA 10:59 PM Feature #55: Replace main CPU: foft wrote:
> So I'm now thinking about ditching my address decoder rework and doing something more fundamental.
> ...
:-)
sadosp
FO 09:06 PM Feature #55: Replace main CPU: So I'm now thinking about ditching my address decoder rework and doing something more fundamental.
Using this CPU to build a complete system with a large linear address space. With SDRAM, block ram, custom chips, pbi and the 'zpu regs... foft

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