Bug #64
closedPokey pdm timing incorrect
0%
Description
So white on black is currently good, while black on white should be better. Seems related to the rise/fall times...
Updated by foft almost 6 years ago
- Subject changed from Pokey rise/fall times not correct to Pokey pdm timing incorrect
Phaeron got a scope on it:
http://atariage.com/forums/topic/244946-using-pulse-density-modulation-for-8-bit-pcm/page-7#entry4036484
Looks to be high pass filter propagation delay related.
Updated by foft almost 6 years ago
Tried a 1 cycle and a half cycle delay on the input to the xor. Neither are seeming quite right, but 1 cycle delay is closest...
Updated by foft almost 6 years ago
Been checking on the scope. The one cycle delay looks correct.
Some jitter issues due to when I activate pokey. I was doing so on the memory access completion, but this really varies too much when accessing SDRAM and block RAM. So I've changed it to activate on the final cycle, as with antic.
Updated by admin almost 6 years ago
- Status changed from New to Closed
Seems to run fine, Acid now passes again as far as I can tell.
Updated by foft almost 6 years ago
- Status changed from Closed to In Progress
Reopening, inconsistent timing in calibrate
Updated by foft almost 6 years ago
The issue was that the write to stimer was now exactly on the enable cycle. I modified the latch delay line to support this. Fundamentally though, this isn’t meant to happen, so perhaps an issue with the pbi implementation is causing the writes to be on an unexpected cycle??
Updated by foft over 5 years ago
- Status changed from In Progress to Closed
Found the issue when doing the pokeymax work - I'd lost some changes by accident.