Revision 82
Added by markw over 11 years ago
| common/antic.wcfg | ||
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</top_modules>
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</db_ref>
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</db_ref_list>
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<WVObjectSize size="34" />
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<WVObjectSize size="36" />
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<wave_markers>
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<marker time="517213670600" label="" />
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</wave_markers>
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| ... | ... | |
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<obj_property name="ObjectShortName">delay_display_shift_reg[24:0]</obj_property>
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<obj_property name="Radix">HEXRADIX</obj_property>
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</wvobject>
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<wvobject fp_name="/antic_tb/antic1/antic_ready" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">antic_ready</obj_property>
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<obj_property name="ObjectShortName">antic_ready</obj_property>
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</wvobject>
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<wvobject fp_name="/antic_tb/antic1/wsync_delay/data_in" type="logic" db_ref_id="1">
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<obj_property name="ElementShortName">data_in</obj_property>
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<obj_property name="ObjectShortName">data_in</obj_property>
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</wvobject>
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</wave_config>
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| common/tb_antic/antic_tb.vhd | ||
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wait for 1100ns;
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wait until cpu_shared_enable = '1';
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cpu_wr_en <= '1';
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cpu_addr<= x"d402";
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cpu_data_in <= x"00";
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wait for clk_a_period;
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wait until cpu_shared_enable = '0';
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cpu_wr_en <= '0';
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wait until cpu_shared_enable = '1';
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cpu_wr_en <= '1';
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cpu_addr<= x"d403";
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cpu_data_in <= x"06";
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wait for clk_a_period;
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wait until cpu_shared_enable = '0';
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cpu_wr_en <= '0';
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wait until cpu_shared_enable = '1';
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cpu_wr_en <= '1';
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cpu_addr <= x"d400";
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cpu_data_in <= x"22";
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wait for clk_a_period;
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wait until cpu_shared_enable = '0';
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cpu_wr_en <= '0';
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wait until cpu_shared_enable = '1';
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wait for clk_a_period*7;
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cpu_wr_en <= '1';
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cpu_addr <= x"d40a";
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cpu_data_in <= x"11";
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wait for clk_a_period*1;
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cpu_wr_en <= '0';
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wait for 100000000us;
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end process;
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tb tweaks