EclaireXL

// set io_rd once read_state machine starts waiting (rising edge of req_io_rd)

// and clear it once io controller uploads something (io_ack==1)

always @(posedge req_io_rd or posedge io_ack) begin

if(io_ack) io_rd <= 1'b0;

else io_rd <= 1'b1;

// 0=idle, 1=wait for io ctrl, 2=wait for byte start, 3=send token, 4=send data, 5/6=send crc[0..1]

localparam RD_STATE_IDLE = 3'd0;

localparam RD_STATE_WAIT_IO = 3'd1;

reg [2:0] read_state = RD_STATE_IDLE;

// 0=idle

reg [31:0] lba;

assign io_lba = io_sdhc?lba:{9'd0, lba[31:9]};

// the command crc is actually never evaluated

reg [7:0] crc;

// falling edge of io_ack signals that a sector to be read has been written into

// the sector bufffer by the io controller. This signal is kept set as long

// as the read state machine is in the "wait for io controller" state (state 1)

reg rd_io_ack = 1'b0 /* synthesis noprune */;

always @(negedge io_ack or negedge rd_wait_io) begin

if(!rd_wait_io) rd_io_ack <= 1'b0;

else rd_io_ack <= 1'b1;

end

wire wr_wait_io = (write_state == WR_STATE_BUSY);

reg wr_io_ack = 1'b0 /* synthesis noprune */;

always @(negedge io_ack or negedge wr_wait_io) begin

csd_wptr <= csd_wptr + 1;

end

end

always @(posedge buffer_read_latch)

cid_byte <= cid[buffer_rptr];

always @(posedge buffer_read_latch)

csd_byte <= csd[buffer_rptr];

// ----------------- spi transmitter --------------------

reg rd_io_ackD, wr_io_ackD;

core_buffer_read_strobe <= 1'b0;

// using rd_io_ack directly brings the read state machine into an

// non-existing state every now and then. For unknown reason

rd_io_ackD <= rd_io_ack;

// CMD17: READ_SINGLE_BLOCK

if(cmd == 8'h51)

read_state <= RD_STATE_WAIT_IO; // start waiting for data from io controller

end

end

end

// send data token

sd_sdo <= READ_DATA_TOKEN[~bit_cnt];

if(bit_cnt == 7)

read_state <= RD_STATE_SEND_DATA; // next: send data

end

// send data

if(cmd == 8'h51) // CMD17: READ_SINGLE_BLOCK

sd_sdo <= buffer_byte[~bit_cnt];

else if(cmd == 8'h49) // CMD9: SEND_CSD

sd_sdo <= csd_byte[~bit_cnt];

else if(cmd == 8'h4a) // CMD10: SEND_CID

sd_sdo <= cid_byte[~bit_cnt];

if(bit_cnt == 7) begin

core_buffer_read_strobe <= 1'b1;

// send 512 sector data bytes?

if((cmd == 8'h51) && (buffer_rptr == 511))

read_state <= RD_STATE_SEND_CRC0; // next: send crc

read_state <= RD_STATE_IDLE; // return to idle state

end

end

// send crc[0]

sd_sdo <= 1'b1;

if(bit_cnt == 7)

read_state <= RD_STATE_SEND_CRC1; // send second crc byte

end

// send crc[1]

sd_sdo <= 1'b1;

if(bit_cnt == 7)

read_state <= RD_STATE_IDLE; // return to idle state

end

end

end

// set io_rd once read_state machine starts waiting (rising edge of req_io_rd)

// and clear it once io controller uploads something (io_ack==1)

always @(posedge req_io_rd or posedge io_ack) begin

if(io_ack) io_rd <= 1'b0;

else io_rd <= 1'b1;

// 0=idle, 1=wait for io ctrl, 2=wait for byte start, 3=send token, 4=send data, 5/6=send crc[0..1]

localparam RD_STATE_IDLE = 3'd0;

localparam RD_STATE_WAIT_IO = 3'd1;

reg [2:0] read_state = RD_STATE_IDLE;

// 0=idle

reg [31:0] lba;

assign io_lba = io_sdhc?lba:{9'd0, lba[31:9]};

// the command crc is actually never evaluated

reg [7:0] crc;

// falling edge of io_ack signals that a sector to be read has been written into

// the sector bufffer by the io controller. This signal is kept set as long

// as the read state machine is in the "wait for io controller" state (state 1)

reg rd_io_ack = 1'b0 /* synthesis noprune */;

always @(negedge io_ack or negedge rd_wait_io) begin

if(!rd_wait_io) rd_io_ack <= 1'b0;

else rd_io_ack <= 1'b1;

end

wire wr_wait_io = (write_state == WR_STATE_BUSY);

reg wr_io_ack = 1'b0 /* synthesis noprune */;

always @(negedge io_ack or negedge wr_wait_io) begin

csd_wptr <= csd_wptr + 1;

end

end

always @(posedge buffer_read_latch)

cid_byte <= cid[buffer_rptr];

always @(posedge buffer_read_latch)

csd_byte <= csd[buffer_rptr];

// ----------------- spi transmitter --------------------

reg rd_io_ackD, wr_io_ackD;

core_buffer_read_strobe <= 1'b0;

// using rd_io_ack directly brings the read state machine into an

// non-existing state every now and then. For unknown reason

rd_io_ackD <= rd_io_ack;

// CMD17: READ_SINGLE_BLOCK

if(cmd == 8'h51)

read_state <= RD_STATE_WAIT_IO; // start waiting for data from io controller

end

end

end

// send data token

sd_sdo <= READ_DATA_TOKEN[~bit_cnt];

if(bit_cnt == 7)

read_state <= RD_STATE_SEND_DATA; // next: send data

end

// send data

if(cmd == 8'h51) // CMD17: READ_SINGLE_BLOCK

sd_sdo <= buffer_byte[~bit_cnt];

else if(cmd == 8'h49) // CMD9: SEND_CSD

sd_sdo <= csd_byte[~bit_cnt];

else if(cmd == 8'h4a) // CMD10: SEND_CID

sd_sdo <= cid_byte[~bit_cnt];

if(bit_cnt == 7) begin

core_buffer_read_strobe <= 1'b1;

// send 512 sector data bytes?

if((cmd == 8'h51) && (buffer_rptr == 511))

read_state <= RD_STATE_SEND_CRC0; // next: send crc

read_state <= RD_STATE_IDLE; // return to idle state

end

end

// send crc[0]

sd_sdo <= 1'b1;

if(bit_cnt == 7)

read_state <= RD_STATE_SEND_CRC1; // send second crc byte

end

// send crc[1]

sd_sdo <= 1'b1;

if(bit_cnt == 7)

read_state <= RD_STATE_IDLE; // return to idle state

end

end

end