Revision 214
Added by markw about 11 years ago
| common/a8core/cpu_6510.vhd | ||
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pipelineOpcode : boolean;
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pipelineAluMux : boolean;
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pipelineAluOut : boolean;
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emulate_bitfade : boolean
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emulate_bitfade : boolean;
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emulate_01_write : boolean
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);
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port (
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clk : in std_logic;
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| ... | ... | |
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d : in unsigned(7 downto 0);
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q : out unsigned(7 downto 0);
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vic_last_data : in unsigned(7 downto 0) := (others => '1');
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diIO : in unsigned(7 downto 0);
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doIO : out unsigned(7 downto 0);
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debugOpcode : out unsigned(7 downto 0);
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debugJam : out std_logic;
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debugPc : out unsigned(15 downto 0);
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debugA : out unsigned(7 downto 0);
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debugX : out unsigned(7 downto 0);
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| ... | ... | |
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signal ioDir : unsigned(7 downto 0);
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signal ioData : unsigned(7 downto 0);
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signal accessIO : std_logic;
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signal accessing_IO : boolean;
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signal ioFade : unsigned(7 downto 0) := (others => '0');
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begin
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cpuInstance: entity work.cpu_65xx
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| ... | ... | |
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we => localWe,
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debugOpcode => debugOpcode,
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debugJam => debugJam,
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debugPc => debugPc,
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debugA => debugA,
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debugX => debugX,
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| ... | ... | |
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debug_flags => debug_flags
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);
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process(localA)
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begin
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accessIO <= '0';
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if localA(15 downto 1) = 0 then
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accessIO <= '1';
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end if;
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end process;
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accessing_IO <= localA(15 downto 1) = 0;
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process(d, localA, ioDir, currentIO, accessIO)
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process(d, localA, ioDir, currentIO, accessing_IO)
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begin
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localD <= d;
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if accessIO = '1' then
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if accessing_IO then
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if localA(0) = '0' then
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localD <= ioDir;
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else
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| ... | ... | |
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process(clk)
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begin
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if rising_edge(clk) then
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if accessIO = '1' then
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if accessing_IO then
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if localWe = '1'
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and enable = '1' then
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if localA(0) = '0' then
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| ... | ... | |
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end if;
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end process;
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process(ioDir, ioData, diIO)
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process(ioDir, ioData, diIO, ioFade)
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begin
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for i in 0 to 7 loop
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if ioDir(i) = '0' then
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| ... | ... | |
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-- Cunnect zee wires
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a <= localA;
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q <= localQ;
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q <= vic_last_data when (emulate_01_write and accessing_IO) else localQ;
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we <= localWe;
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doIO <= currentIO;
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debug_io <= "00" & (ioData(5 downto 0) or (not ioDir(5 downto 0)));
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| common/a8core/cpu_65xx_a.vhd | ||
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library IEEE;
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use ieee.std_logic_1164.ALL;
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use ieee.std_logic_unsigned.ALL;
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use ieee.numeric_std.ALL;
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-- -----------------------------------------------------------------------
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| ... | ... | |
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constant opcIncrAfter : integer := 23; -- Insert extra cycle to increment PC (RTS)
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constant opcRti : integer := 24;
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constant opcIRQ : integer := 25;
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constant opcJAM : integer := 26;
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constant opcInA : integer := 26;
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constant opcInE : integer := 27;
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constant opcInX : integer := 28;
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constant opcInY : integer := 29;
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constant opcInS : integer := 30;
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constant opcInT : integer := 31;
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constant opcInH : integer := 32;
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constant opcInClear : integer := 33;
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constant aluMode1From : integer := 34;
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constant opcInA : integer := 27;
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constant opcInE : integer := 28;
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constant opcInX : integer := 29;
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constant opcInY : integer := 30;
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constant opcInS : integer := 31;
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constant opcInT : integer := 32;
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constant opcInH : integer := 33;
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constant opcInClear : integer := 34;
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constant aluMode1From : integer := 35;
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--
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constant aluMode1To : integer := 37;
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constant aluMode2From : integer := 38;
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constant aluMode1To : integer := 38;
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constant aluMode2From : integer := 39;
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--
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constant aluMode2To : integer := 40;
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constant aluMode2To : integer := 41;
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--
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constant opcInCmp : integer := 41;
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constant opcInCpx : integer := 42;
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constant opcInCpy : integer := 43;
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constant opcInCmp : integer := 42;
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constant opcInCpx : integer := 43;
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constant opcInCpy : integer := 44;
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subtype addrDef is unsigned(0 to 15);
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subtype addrDef is unsigned(0 to 16);
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--
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-- is Interrupt -----------------+
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-- instruction is RTI ----------------+|
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-- PC++ on last cycle (RTS) ---------------+||
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-- RMW --------------+|||
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-- Write -------------+||||
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-- Pop/Stack up -------------+|||||
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-- Branch ---------+ ||||||
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-- Jump ----------+| ||||||
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-- Push or Pop data -------+|| ||||||
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-- Push or Pop addr ------+||| ||||||
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-- Indirect -----+|||| ||||||
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-- ZeroPage ----+||||| ||||||
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-- Absolute ---+|||||| ||||||
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-- PC++ on cycle2 --+||||||| ||||||
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-- |AZI||JBXY|WM|||
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constant immediate : addrDef := "1000000000000000";
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constant implied : addrDef := "0000000000000000";
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-- is JAM ------------------+
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-- is Interrupt -----------------+|
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-- instruction is RTI ----------------+||
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-- PC++ on last cycle (RTS) ---------------+|||
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-- RMW --------------+||||
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-- Write -------------+|||||
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-- Pop/Stack up -------------+||||||
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-- Branch ---------+ |||||||
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-- Jump ----------+| |||||||
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-- Push or Pop data -------+|| |||||||
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-- Push or Pop addr ------+||| |||||||
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-- Indirect -----+|||| |||||||
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-- ZeroPage ----+||||| |||||||
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-- Absolute ---+|||||| |||||||
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-- PC++ on cycle2 --+||||||| |||||||
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-- |AZI||JBXY|WM||||
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constant immediate : addrDef := "10000000000000000";
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constant implied : addrDef := "00000000000000000";
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-- Zero page
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constant readZp : addrDef := "1010000000000000";
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constant writeZp : addrDef := "1010000000010000";
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constant rmwZp : addrDef := "1010000000001000";
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constant readZp : addrDef := "10100000000000000";
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constant writeZp : addrDef := "10100000000100000";
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constant rmwZp : addrDef := "10100000000010000";
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-- Zero page indexed
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constant readZpX : addrDef := "1010000010000000";
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constant writeZpX : addrDef := "1010000010010000";
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constant rmwZpX : addrDef := "1010000010001000";
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constant readZpY : addrDef := "1010000001000000";
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constant writeZpY : addrDef := "1010000001010000";
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constant rmwZpY : addrDef := "1010000001001000";
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constant readZpX : addrDef := "10100000100000000";
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constant writeZpX : addrDef := "10100000100100000";
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constant rmwZpX : addrDef := "10100000100010000";
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constant readZpY : addrDef := "10100000010000000";
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constant writeZpY : addrDef := "10100000010100000";
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constant rmwZpY : addrDef := "10100000010010000";
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-- Zero page indirect
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constant readIndX : addrDef := "1001000010000000";
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constant writeIndX : addrDef := "1001000010010000";
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constant rmwIndX : addrDef := "1001000010001000";
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constant readIndY : addrDef := "1001000001000000";
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constant writeIndY : addrDef := "1001000001010000";
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constant rmwIndY : addrDef := "1001000001001000";
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constant readIndX : addrDef := "10010000100000000";
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constant writeIndX : addrDef := "10010000100100000";
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constant rmwIndX : addrDef := "10010000100010000";
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constant readIndY : addrDef := "10010000010000000";
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constant writeIndY : addrDef := "10010000010100000";
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constant rmwIndY : addrDef := "10010000010010000";
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-- |AZI||JBXY|WM||
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-- Absolute
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constant readAbs : addrDef := "1100000000000000";
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constant writeAbs : addrDef := "1100000000010000";
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constant rmwAbs : addrDef := "1100000000001000";
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constant readAbsX : addrDef := "1100000010000000";
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constant writeAbsX : addrDef := "1100000010010000";
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constant rmwAbsX : addrDef := "1100000010001000";
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constant readAbsY : addrDef := "1100000001000000";
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constant writeAbsY : addrDef := "1100000001010000";
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constant rmwAbsY : addrDef := "1100000001001000";
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constant readAbs : addrDef := "11000000000000000";
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constant writeAbs : addrDef := "11000000000100000";
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constant rmwAbs : addrDef := "11000000000010000";
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constant readAbsX : addrDef := "11000000100000000";
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constant writeAbsX : addrDef := "11000000100100000";
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constant rmwAbsX : addrDef := "11000000100010000";
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constant readAbsY : addrDef := "11000000010000000";
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constant writeAbsY : addrDef := "11000000010100000";
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constant rmwAbsY : addrDef := "11000000010010000";
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-- PHA PHP
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constant push : addrDef := "0000010000000000";
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constant push : addrDef := "00000100000000000";
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-- PLA PLP
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constant pop : addrDef := "0000010000100000";
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constant pop : addrDef := "00000100001000000";
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-- Jumps
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constant jsr : addrDef := "1000101000000000";
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constant jumpAbs : addrDef := "1000001000000000";
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constant jumpInd : addrDef := "1100001000000000";
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constant relative : addrDef := "1000000100000000";
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constant jsr : addrDef := "10001010000000000";
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constant jumpAbs : addrDef := "10000010000000000";
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constant jumpInd : addrDef := "11000010000000000";
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constant relative : addrDef := "10000001000000000";
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-- Specials
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constant rts : addrDef := "0000101000100100";
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constant rti : addrDef := "0000111000100010";
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constant brk : addrDef := "1000111000000001";
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constant rts : addrDef := "00001010001001000";
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constant rti : addrDef := "00001110001000100";
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constant brk : addrDef := "10001110000000010";
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constant xxxxxxxx : addrDef := "0---------0---001";
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-- constant : unsigned(0 to 0) := "0";
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constant xxxxxxxx : addrDef := "----------0---00";
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-- A = accu
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-- E = Accu | 0xEE (for ANE, LXA)
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| ... | ... | |
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constant stackDec : unsigned(0 to 0) := "1";
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constant stackXXX : unsigned(0 to 0) := "-";
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subtype decodedBitsDef is unsigned(0 to 43);
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subtype decodedBitsDef is unsigned(0 to 44);
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type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
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constant opcodeInfoTable : opcodeInfoTableDef := (
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-- +------- Update register A
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| ... | ... | |
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"0000" & "000000" & writeAbsX & aluInYH & aluInp, -- 9C iSHY abs,x
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"0000" & "000000" & writeAbsX & aluInA & aluInp, -- 9D STA abs,x
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"0000" & "000000" & writeAbsY & aluInXH & aluInp, -- 9E iSHX abs,y
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"0000" & "000000" & writeAbsY & aluInAX & aluInp, -- 9F iAHX abs,y
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"0000" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9F iAHX abs,y
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-- AXYS NVDIZC addressing aluInput aluMode
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"0010" & "100010" & immediate & aluInT & aluInp, -- A0 LDY imm
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"1000" & "100010" & readIndX & aluInT & aluInp, -- A1 LDA (zp,x)
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| ... | ... | |
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"0010" & "100010" & implied & aluInA & aluInp, -- A8 TAY
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"1000" & "100010" & immediate & aluInT & aluInp, -- A9 LDA imm
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"0100" & "100010" & implied & aluInA & aluInp, -- AA TAX
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"1100" & "100010" & immediate & aluInET & aluAnd, -- AB iLXA imm - MWW:change for Atari800 CPU
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--"1100" & "100010" & immediate & aluInET & aluInp, -- AB iLXA imm
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"1100" & "100010" & immediate & aluInET & aluAnd, -- AB iLXA imm - MWW:change for Atari800 CPU
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"0010" & "100010" & readAbs & aluInT & aluInp, -- AC LDY abs
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"1000" & "100010" & readAbs & aluInT & aluInp, -- AD LDA abs
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"0100" & "100010" & readAbs & aluInT & aluInp, -- AE LDX abs
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| ... | ... | |
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-- Indexing
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signal indexOut : unsigned(8 downto 0);
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-- JAM
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signal jam_flag : std_logic := '0';
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begin
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processAluInput: process(clk, opcInfo, A, X, Y, T, S)
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variable temp : unsigned(7 downto 0);
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| ... | ... | |
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-- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA
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-- Some instructions are both RMW and accumulator so for most
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-- instructions the rmw results are routed through accu alu too.
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processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, Nreg, Vreg, Dreg, Ireg, Zreg, Creg)
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processAlu: process(clk,
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opcInfo, aluInput, aluInputReg, aluCmpInput, aluCmpInputReg, aluNineReg,
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A, T, irqActive, Nreg, Vreg, Dreg, Ireg, Zreg, Creg, aluNreg, aluVreg, aluZreg, aluCreg)
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variable lowBits: unsigned(5 downto 0);
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variable nineBits: unsigned(8 downto 0);
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variable rmwBits: unsigned(8 downto 0);
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| ... | ... | |
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begin
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if rising_edge(clk) then
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if (enable = '1') then -- and (halt = '0') then
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irqReg <= irq_n;
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nmiEdge <= nmi_n;
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if (nmiEdge = '1') and (nmi_n = '0') then
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nmiReg <= '0';
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end if;
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if theCpuCycle = cycleStack4 -- MWW
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or reset = '1' then
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nmiReg <= '1';
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end if;
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if theCpuCycle = cycleStack4
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or reset = '1' then
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nmiReg <= '1';
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end if;
|
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if halt = '0' then
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if theCpuCycle /= cycleBranchTaken then
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-- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
|
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| ... | ... | |
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nextOpcode <= myNextOpcode;
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end process;
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nextOpcInfo <= opcodeInfoTable(to_integer(to_01(nextOpcode, '0')));
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nextOpcInfo <= opcodeInfoTable(to_integer(to_01(nextOpcode,'0')));
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process(clk)
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begin
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if rising_edge(clk) then
|
||
| ... | ... | |
|
if rising_edge(clk) then
|
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if (enable = '1') and (halt = '0') then
|
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theCpuCycle <= nextCpuCycle;
|
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debugJam <= jam_flag;
|
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end if;
|
||
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if reset = '1' then
|
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theCpuCycle <= cycle2;
|
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debugJam <= '0';
|
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end if;
|
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end if;
|
||
|
end process;
|
||
| ... | ... | |
|
-- go to opcodeFetch to get the next opcode.
|
||
|
calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, Nreg, Vreg, Creg, Zreg)
|
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|
begin
|
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jam_flag <= '0';
|
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nextCpuCycle <= opcodeFetch;
|
||
|
|
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|
case theCpuCycle is
|
||
|
when opcodeFetch =>
|
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nextCpuCycle <= cycle2;
|
||
|
when cycle2 =>
|
||
|
if opcInfo(opcBranch) = '1' then
|
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|
if enable_jam and (opcInfo(opcJAM) = '1') then
|
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nextCpuCycle <= cycle2;
|
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jam_flag <= '1';
|
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|
-- Stay in cycle2
|
||
|
elsif opcInfo(opcBranch) = '1' then
|
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|
if (Nreg = theOpcode(5) and theOpcode(7 downto 6) = "00")
|
||
|
or (Vreg = theOpcode(5) and theOpcode(7 downto 6) = "01")
|
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|
or (Creg = theOpcode(5) and theOpcode(7 downto 6) = "10")
|
||
| ... | ... | |
|
Ireg <= '1';
|
||
|
end if;
|
||
|
end if;
|
||
|
|
||
|
if enable = '1' and reset = '1' then
|
||
|
Ireg <= '1';
|
||
|
end if;
|
||
|
end if;
|
||
|
end process;
|
||
|
|
||
| ... | ... | |
|
if rising_edge(clk) then
|
||
|
if (enable = '1') and (halt = '0') then
|
||
|
doReg <= aluRmwOut;
|
||
|
if opcInfo(opcInH) = '1' then
|
||
|
if opcInfo(opcInH) = '1' and (halt_dly = '0') then
|
||
|
-- For illegal opcodes SHA, SHX, SHY, SHS
|
||
|
doReg <= aluRmwOut and myAddrIncrH;
|
||
|
end if;
|
||
| common/a8core/cpu_65xx_e.vhd | ||
|---|---|---|
|
|
||
|
entity cpu_65xx is
|
||
|
generic (
|
||
|
enable_jam : boolean := true;
|
||
|
pipelineOpcode : boolean;
|
||
|
pipelineAluMux : boolean;
|
||
|
pipelineAluOut : boolean
|
||
| ... | ... | |
|
we : out std_logic;
|
||
|
|
||
|
debugOpcode : out unsigned(7 downto 0);
|
||
|
debugJam : out std_logic;
|
||
|
debugPc : out unsigned(15 downto 0);
|
||
|
debugA : out unsigned(7 downto 0);
|
||
|
debugX : out unsigned(7 downto 0);
|
||
Upgraded to latest version of Peter Wendrichs core. Thanks Peter!