Revision 167
Added by markw about 11 years ago
| common/a8core/pokey_poly_17_9.vhdl | ||
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ARCHITECTURE vhdl OF pokey_poly_17_9 IS
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signal shift_reg: std_logic_vector(16 downto 0);
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signal shift_next: std_logic_vector(16 downto 0);
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signal cycle_delay_reg : std_logic;
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signal cycle_delay_next : std_logic;
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signal feedback : std_logic;
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BEGIN
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| ... | ... | |
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begin
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if (reset_n = '0') then
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shift_reg <= "01010101010101010";
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cycle_delay_reg <= '0';
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elsif (clk'event and clk='1') then
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shift_reg <= shift_next;
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cycle_delay_reg <= cycle_delay_next;
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end if;
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end process;
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-- next state (as pokey decap)
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feedback <= shift_reg(13) xnor shift_reg(8);
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process(enable,shift_reg,feedback,select_9_17,init)
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process(enable,shift_reg,feedback,select_9_17,init,cycle_delay_reg)
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begin
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shift_next <= shift_reg;
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cycle_delay_next <= cycle_delay_reg;
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if (enable = '1') then
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shift_next(15 downto 8) <= shift_reg(16 downto 9);
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| ... | ... | |
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shift_next(6 downto 0) <= shift_reg(7 downto 1);
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shift_next(16) <= ((feedback and select_9_17) or (shift_reg(0) and not(select_9_17))) and not(init);
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cycle_delay_next <= shift_reg(9);
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end if;
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end process;
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-- output
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bit_out <= shift_reg(9);
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bit_out <= cycle_delay_reg; -- from pokey schematics
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RAND_OUT(7 downto 0) <= not(shift_reg(15 downto 8));
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END vhdl;
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| common/a8core/pokey_poly_4.vhdl | ||
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end process;
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-- output
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bit_out <= not(shift_reg(0));
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bit_out <= shift_reg(0);
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END vhdl;
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Match more closely to schematic - delay/inversion