I upgraded my server for the meltdown patch and my hard drive took the opportunity to die. So that was fun...
Not much progress on this side. I played around in WUDSN with programming the new highres modes which was quite fun. They are running pretty well. I just need to get motivated to squash the remaining alignment bugs.
No takers for helping by writing an 80-column E: driver? Or better supporting all the modes by using e.g. Gr 8+64 or Gr8+128? That would be awesome. I did some initial playing and checked out the OS++ and OS source code. I think this is a project in itself though.
Given the current state of the project, do you think we should make more boards? Or better off to hold off for another year while we squash bugs and add features?
OK this one is mostly exciting news for me... Just bought an i7-8700 box to do the builds on. This should mean I waste less time waiting for builds.
Still cracking on with high-res support. Subsequent to the updates on the issue here I was playing a bit with OS patches to make it work better.
I have high-res mode working! More debugging to do, but I've uploaded a preview for anyone who wants to play with it.
Here is a video showing graphics 0 in 80 column and 160 column mode - I should have used HD!
[[https://www.youtube.com/watch?v=I8Ox-bQicUs]]
Known issues:
i) Some acid tests are broken
ii) hscrol does not yet work on 2x and 4x colour clocks
iii) HDMI and svideo have a max res of 640 pixels wide, so gr.0 4x and gr8 4x won't look good (I've not tried yet). However they are still useful for GTIA modes. 320x200 in greyscale.
iv) Horizontal offset wrong, blank space on right.
v) Built in freezer broken (NOT related)
vi) It only works in turbo mode! PBI access requires waiting for 1/2 a cycle to know if PBI devices are going to take over the bus. This breaks the intra cycle DMA.
Still its exciting to have it working.
I've uploaded it for prototype 1 and 2 as highres5.sof. Please give it a go, try some custom display lists etc and see what you can get going. I've not tried doing much with it yet. Except poke 559,66 (2x) and poke 559,98 (4x) :-)
I found something else interesting. The source of some of the timing problems I have been having. I thought I'd reverted to before them in v16, but I as wrong. In fact they came from PBI support when fixing the turbo freezer. This logic is a problem:
if freezer enabled, disable pbi
if pbi enabled, set read/write on freezer
depending on read or write to freezer, freezer enabled
->>> combination loop!! Timing problems galore. Not sure how I missed it in the warnings. I've fixed the timing problem in this build but broke freezer again at the same time!
v15 is dead and the large structural changes are still a lot of work.
As such I've revised the v15 wip as v16 and ported it to v1 and v2 boards.
This is largely just to get the svn branch back in a state so it builds. So I can work on random little fixes independently of the large structural core changes(different cpu, debug support, linear ram etc)
A reminder:
DONE:SIO IN has zpu output on
DONE:US keyboard selection
- NO BLOCK RAM FOR ZPU LEFT!!
DONE:freeze when exiting zpu menu
DONE:debug port over gpio (v2 only)
DONE:rom in block ram (inc load from sd)
- found bad we
- removed clear
DONE:Antic refresh behaviour on pbi
DONE:svideo atari style (v2 only - also note that on v1 composite also does nothing right now, use svideo for composite and svideo)
I'm back from my holidays. I didn't find much time to work on this, a few hours here and there. The address decoder/bus master priority logic rework is taking shape and looking much neater - it was long overdue. I estimate about a days solid work still though (I have about 30 mins/day though...).
So I decided to rewrite the address decoding and priority access to fix the timing issues. Currently the 'address decoder' has a load of random stuff in it. Multiple bus masters come in (6502, dma and antic) and it chooses who has priority then maps the data output from back to the internal bus. There is not real bi-directional internal bus, its all constructed via a bunch of multiplexors. Mixed into all this we have the cartridge logic and the turbo freezer. Not to mention waiting for PBI access at original machine speed. Anyway its all pretty complicated and I'm trying to design it then write it this time! I originally spent time on the custom chip logic then wired them together as quickly as possible - in a pretty hacky way.
This is quite a beast to do so it will take a few weeks. I got off to a decent start, then... We've just had the Paléo festival here so not had much time in the last week. Next week though I have two weeks holiday - staying with the inlaws. I won't have the eclaireXL with me but I hope I'll have a day in there to get the decoder written. Its hard to know since we've got quite a lot planned.
I'm sure you've already seen Steve's great setup, but if not go and see here. Very nice work:-)
http://atariage.com/forums/topic/267845-my-eclairexl-a-salute-to-the-atari-400-my-first-atari-computer/
I'm still working away on the core. The next update is almost ready and will include:
- SIO in line pulled low by ZPU. To allow SIO debugging externally.
- ISO/ANSI keyboard selection (thanks Steve)
- Fix for crash on existing zpu menu that was introduced by PBI (this was tricky!)
- PBI access from zpu, and the groundwork for pbi access from turbo - basically we need to support a subset of addresses to make this work.
- ROM in block RAM instead of SDRAM. This is much faster.
- Antic refresh cycles on PBI
- Svideo/composite reimplemented using the Atari technique - fixed amplitude sin + brightness, phase shifted.
- 0 written to D500 on cold reboot, which Nir advises me will fix some cart reset issues.
- Debug output over GPIO, this will allow cycle by cycle capture with an 8-bit logic analyzer - and better with a 16-bit one... Which will allow us to more easily debug some of the bugs. Debugging on the FPGA usually entails capturing a very small precise section of logic, so its hard to capture things that only happen on one frame and do not repeat without significant effort. I plan to write something to capture the output and compare vs what say ... Altirra would do. Not sure how tricky that will be to wire up. Anyone want to help once I get a dump?
Anyway v15 is basically all done, except I have some timing problems - so I need to rewrite the central device select mmu logic. Its long overdue... Bear with me, this will take the rest of this week I think.
In v16 I need to start to tackle some of the bigger questions, such as ... the block rom for the ZPU is full! I was scrambling for bytes to add the ISO keyboard support. I can of course assign more rom, but I'm tempted to do a larger restructure. Perhaps a bunch of 6502s would be more in spirit? One for USB, one for drive emulation, one for... What do you think? Anyone up for porting the USB logic to 6502?
Core v10 is out for both v1 and v2/3
The turbo freezer works! Both of them!