64kib

09/10/2017

FO 09:24 PM EclaireXL Feature #55: Replace main CPU

I read up on the 'altera virtual jtag' and think I now understand how to get this connected, at least in theory.
I guess next steps that might make sense are:
i) Build a core with virtual jtag and signal tap and try to send it equiv... foft

FO 08:41 PM EclaireXL Developer: RE: Accessing new Antic modes through BASIC?

I can, but it doesn't work properly yet!
The register is 559, the shadow for DMACTL.
Normally its poke 559,0 to turn the screen off and poke 559,34 to turn it on. Which is the sum of 2 (normal width) and 32 (playfield dma on).
... foft

09/08/2017

FO 10:06 PM EclaireXL Feature #55: Replace main CPU

Been trying out openocd locally with the cpu running in verilator. gdb connects, code loads and runs. Pretty cool! OK I just ran some commands as documented but I'm still pleased:-)
I'm very impressed with this riscv cpu project - see... foft

09/07/2017

FO 09:39 PM EclaireXL Bug #59: Game test: Crownland

It requires 128K, can you check what memory settings you have? I can only reproduce without extended ram. foft

FO 07:44 PM EclaireXL Bug #59: Game test: Crownland

I'll have to check, I thought that worked.
BTW this one is better than v14: svideo_gtia9.sof foft

FO 07:43 PM EclaireXL Feature #55: Replace main CPU

The author of the cpu kindly got back to me with some details.
The wishbone interface adaptor looks pretty easy.
Apparently the chip uses a non-standard debugging interface though. Which is good actually since its simpler. However ... foft

09/06/2017

FO 09:44 PM EclaireXL Feature #55: Replace main CPU

I've managed to get the spinal HDL project compiled, so now have a verilog or vhdl file for the CPU. It seems to have 3 ports. Instruction master, data master and debug slave. So I will need to map them into wishbone. They are also in th... foft

09/03/2017

FO 01:40 PM EclaireXL Feature #55: Replace main CPU

To Panos' comment. Yeah I'd love some help, if someone could help me define the memory map and write the firmware for the RISC V that would be an enormous help. There are also many HDL parts that need doing if anyone fancies working on t... foft

FO 01:37 PM EclaireXL Feature #55: Replace main CPU

There are several problems with the current setup:
* The firmware is constrained by the current ZPU setup. Its hard to debug and tricky to add more memory to it.
* I'm struggling to meet timing requirements, due to the over-complex int... foft

09/01/2017

FO 09:06 PM EclaireXL Feature #55: Replace main CPU

So I'm now thinking about ditching my address decoder rework and doing something more fundamental.
Using this CPU to build a complete system with a large linear address space. With SDRAM, block ram, custom chips, pbi and the 'zpu regs... foft

08/28/2017

FO 09:18 AM EclaireXL Developer: RE: Curious if progress is being made on this project any longer?

Not much. Had some back issues after my holidays and generally not been very motivated with this project recently. It was always unlikely to develop at the same pace as when the new boards were made though, that was pretty unsustainable ... foft

08/13/2017

FO 09:52 PM EclaireXL Back from holidays

I'm back from my holidays. I didn't find much time to work on this, a few hours here and there. The address decoder/bus master priority logic rework is taking shape and looking much neater - it was long overdue. I estimate about a days s... foft

FO 09:46 PM EclaireXL Feature #58: Maybe consider moving CART selection closer to top in F12 menu ?

Yes I agree this makes sense. I'd like a wider review/redesign on the firmware, there is a lot of scope for improvement. I'd really like it if someone else could pick this up so I could focus on the hardware aspect, any takers? foft

FO 09:43 PM EclaireXL Bug #57: Ballblazer playfield has issues after firing in v14

Pleased its a non-issue:-) Did you try this version on a real NTSC system? foft