Index: eclaireXL_ITX/pixels.vhdl
===================================================================
--- eclaireXL_ITX/pixels.vhdl	(revision 973)
+++ eclaireXL_ITX/pixels.vhdl	(nonexistent)
@@ -1,48 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-package Pixels is
-
-type t_Pixel is record
-    red   : std_logic_vector(7 downto 0);
-    green : std_logic_vector(7 downto 0);
-    blue  : std_logic_vector(7 downto 0);
-end record t_Pixel;  
-  
-type t_Pixel2x2 is array (0 to 3) of t_Pixel;
-type t_Pixel4x4 is array (0 to (4*4-1)) of t_Pixel;
-
-function pixel_to2x2(v: t_Pixel4x4) return t_Pixel2x2;
-function pixel2x2_idx(i,j : integer) return integer;
-function pixel4x4_idx(i,j : integer) return integer;
-
-end package Pixels;
-
-package body Pixels is
-	function pixel_to2x2(v: t_Pixel4x4) return t_Pixel2x2 is
-		variable res : t_Pixel2x2;
-	begin
-		for i in 0 to 1 loop
-			for j in 0 to 1 loop
-				res(pixel2x2_idx(i,j)) := v(pixel4x4_idx(i,j));
-			end loop;
-		end loop;
-		return res;
-	end pixel_to2x2;
-	
-	function pixel2x2_idx(i,j : integer) return integer is
-		variable res : integer;
-	begin
-		res := i*2+j;
-		return res;
-	end pixel2x2_idx;
-
-	function pixel4x4_idx(i,j : integer) return integer is
-		variable res : integer;
-	begin
-		res := i*4+j;
-		return res;
-	end pixel4x4_idx;	
-	
-end Pixels;
-
Index: eclaireXL_ITX/areascale.vhd
===================================================================
--- eclaireXL_ITX/areascale.vhd	(revision 973)
+++ eclaireXL_ITX/areascale.vhd	(nonexistent)
@@ -1,467 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
---USE ieee.std_logic_arith.all;
---USE ieee.std_logic_unsigned.all;
-USE ieee.numeric_std.all;
-use work.pixels.all;
-
---TODO: scanlines!!
---out_colour(7 downto 4) <= out_colour_raw(7 downto 4);
---out_colour(3 downto 0) <= out_colour_raw(3 downto 0) when (not(out_scanlines) or vcnt(0))='1' else '0'&out_colour_raw(3 downto 1);
-
-ENTITY areascale IS
-  PORT(
-    clock   : IN     STD_LOGIC;                             --system clock
-    reset_n : IN     STD_LOGIC;                             --asynchronous reset
-
-    -- need to know:
-    -- block of 4 pixels (x,y:x+1,y:x,y+1:x+1,y+1)
-    -- relative scale ratios
-    --p1 : in std_logic_vector(23 downto 0); --RGB
-    --p2 : in std_logic_vector(23 downto 0); --RGB
-    --p3 : in std_logic_vector(23 downto 0); --RGB
-    --p4 : in std_logic_vector(23 downto 0); --RGB
-	 
-	 pixels : in t_Pixel2x2;
-
-    -- next output line
-    next_y_in : in std_logic;
-    next_frame_in : in std_logic;
-	 field2 : in std_logic;
-    
-    -- sync/blank from crtc -> need to be delayed in line with pipeline
-    hsync_in : in std_logic;
-    vsync_in : in std_logic;
-    blank_in : in std_logic; 
-	 
-    -- need to provide control signals:
-    next_x : OUT STD_LOGIC;
-	 next_x_size : out std_logic_vector(1 downto 0);
-    next_y : OUT STD_LOGIC;	 
-
-    -- need to output
-    -- current pixel
-    r : out std_logic_vector(7 downto 0);
-    g : out std_logic_vector(7 downto 0);
-    b : out std_logic_vector(7 downto 0);
-    hsync : out std_logic;
-    vsync : out std_logic;
-    blank : out std_logic;
-	 
-	 -- to set up params
- 	 sda : inout std_logic;
-	 scl : inout std_logic	 
-  );
-END areascale;
-
--- customscalex:568 customscaley:256 xdelta:640 ydelta:102 TA:65536
-ARCHITECTURE vhdl OF areascale IS
-	signal param_xthreshold_next : unsigned(10 downto 0);
-	signal param_xthreshold_reg : unsigned(10 downto 0);
-	signal param_ythreshold_next : unsigned(10 downto 0);
-	signal param_ythreshold_reg : unsigned(10 downto 0);
-	signal param_xdelta_next : unsigned(10 downto 0);
-	signal param_xdelta_reg : unsigned(10 downto 0);
-	signal param_ydelta_next : unsigned(10 downto 0);
-	signal param_ydelta_reg : unsigned(10 downto 0);
-	signal param_ydeltaeach_next : unsigned(10 downto 0);
-	signal param_ydeltaeach_reg : unsigned(10 downto 0);	
-	signal param_xaddrskip_next : unsigned(1 downto 0); -- We only support upscaling, so for some cases need to skip 2 pixels
-	signal param_xaddrskip_reg : unsigned(1 downto 0);
-	
-	-- stage 1:5 Delay syncs in line with pipeline
-	signal hsync_next : std_logic_vector(6 downto 1);
-	signal hsync_reg : std_logic_vector(6 downto 1);
-	signal vsync_next : std_logic_vector(6 downto 1);
-	signal vsync_reg : std_logic_vector(6 downto 1);
-	signal blank_next : std_logic_vector(6 downto 1);
-	signal blank_reg : std_logic_vector(6 downto 1);
-	
-	-- stage 1 : Accumulators/ data request
-	signal xacc_next : unsigned(11 downto 0);
-	signal xacc_reg : unsigned(11 downto 0);
-	signal yacc_next : unsigned(11 downto 0);
-	signal yacc_reg : unsigned(11 downto 0);
-	
-	-- stage 2 : Area calc 
-	signal dl_next : unsigned(8 downto 0);
-	signal dl_reg : unsigned(8 downto 0);
-	signal dlO_next : unsigned(8 downto 0);
-	signal dlO_reg : unsigned(8 downto 0);
-	signal dt_next : unsigned(8 downto 0);
-	signal dt_reg : unsigned(8 downto 0);
-	signal dtO_next : unsigned(8 downto 0);
-	signal dtO_reg : unsigned(8 downto 0);	
-
-	-- stage 3 : Area calc mult
-	signal A1_next : unsigned(17 downto 0);
-	signal A1_reg : unsigned(17 downto 0);
-	signal A2_next : unsigned(17 downto 0);
-	signal A2_reg : unsigned(17 downto 0);
-	signal A3_next : unsigned(17 downto 0);
-	signal A3_reg : unsigned(17 downto 0);
-	signal A4_next : unsigned(17 downto 0);
-	signal A4_reg : unsigned(17 downto 0);
-
-	signal p1_s3_reg : t_Pixel;
-	signal p2_s3_reg : t_Pixel;
-	signal p3_s3_reg : t_Pixel;
-	signal p4_s3_reg : t_Pixel;
-	signal p1_s3_next : t_Pixel;
-	signal p2_s3_next : t_Pixel;
-	signal p3_s3_next : t_Pixel;
-	signal p4_s3_next : t_Pixel;
-
-	-- stage 4: Pixel scaling
-	signal f1_r_reg : unsigned(35 downto 0);
-	signal f2_r_reg : unsigned(35 downto 0);
-	signal f3_r_reg : unsigned(35 downto 0);
-	signal f4_r_reg : unsigned(35 downto 0);
-
-	signal f1_g_reg : unsigned(35 downto 0);
-	signal f2_g_reg : unsigned(35 downto 0);
-	signal f3_g_reg : unsigned(35 downto 0);
-	signal f4_g_reg : unsigned(35 downto 0);
-
-	signal f1_b_reg : unsigned(35 downto 0);
-	signal f2_b_reg : unsigned(35 downto 0);
-	signal f3_b_reg : unsigned(35 downto 0);
-	signal f4_b_reg : unsigned(35 downto 0);
-
-	signal f1_r_next : unsigned(35 downto 0);
-	signal f2_r_next : unsigned(35 downto 0);
-	signal f3_r_next : unsigned(35 downto 0);
-	signal f4_r_next : unsigned(35 downto 0);
-
-	signal f1_g_next : unsigned(35 downto 0);
-	signal f2_g_next : unsigned(35 downto 0);
-	signal f3_g_next : unsigned(35 downto 0);
-	signal f4_g_next : unsigned(35 downto 0);
-
-	signal f1_b_next : unsigned(35 downto 0);
-	signal f2_b_next : unsigned(35 downto 0);
-	signal f3_b_next : unsigned(35 downto 0);
-	signal f4_b_next : unsigned(35 downto 0);
-
-	-- stage 5: Pixel output
-	signal r_reg : std_logic_vector(7 downto 0);
-	signal r_next : std_logic_vector(7 downto 0);
-	signal g_reg : std_logic_vector(7 downto 0);
-	signal g_next : std_logic_vector(7 downto 0);
-	signal b_reg : std_logic_vector(7 downto 0);
-	signal b_next : std_logic_vector(7 downto 0);
-
-BEGIN
-	process(clock,reset_n)
-	begin
-		if (reset_n='0') then
-			param_xthreshold_reg <= (others=>'0');
-			param_ythreshold_reg <= (others=>'0');
-			param_xdelta_reg <= (others=>'0');
-			param_ydelta_reg <= (others=>'0');
-			param_ydeltaeach_reg <= (others=>'0');
-			param_xaddrskip_reg <= "01";
-			
-			-- multi stage 1-5
-			hsync_reg <= (others=>'0');
-			vsync_reg <= (others=>'0');
-			blank_reg <= (others=>'0');
-
-			-- stage 1
-			xacc_reg <= (others=>'0');
-			yacc_reg <= (others=>'0');
-
-			-- stage 2
-			dt_reg <= (others=>'0');
-			dl_reg <= (others=>'0');
-			dtO_reg <= (others=>'0');
-			dlO_reg <= (others=>'0');
-
-			-- stage 3
-			A1_reg <= (others=>'0');
-			A2_reg <= (others=>'0');
-			A3_reg <= (others=>'0');
-			A4_reg <= (others=>'0');
-
-			p1_s3_reg <= (others=>(others=>'0'));
-			p2_s3_reg <= (others=>(others=>'0'));
-			p3_s3_reg <= (others=>(others=>'0'));
-			p4_s3_reg <= (others=>(others=>'0'));
-
-			-- stage 4
-			f1_r_reg <= (others=>'0');
-			f2_r_reg <= (others=>'0');
-			f3_r_reg <= (others=>'0');
-			f4_r_reg <= (others=>'0');
-
-			f1_g_reg <= (others=>'0');
-			f2_g_reg <= (others=>'0');
-			f3_g_reg <= (others=>'0');
-			f4_g_reg <= (others=>'0');
-
-			f1_b_reg <= (others=>'0');
-			f2_b_reg <= (others=>'0');
-			f3_b_reg <= (others=>'0');
-			f4_b_reg <= (others=>'0');
-
-			-- stage 5
-			r_reg <= (others=>'0');
-			g_reg <= (others=>'0');
-			b_reg <= (others=>'0');
-		elsif (clock'event and clock='1') then
-			param_xthreshold_reg <= param_xthreshold_next;
-			param_xdelta_reg <= param_xdelta_next;
-			param_ythreshold_reg <= param_ythreshold_next;
-			param_ydelta_reg <= param_ydelta_next;
-			param_ydeltaeach_reg <= param_ydeltaeach_next;
-			param_xaddrskip_reg <= param_xaddrskip_next;
-
-			-- multi stage 1-5
-			hsync_reg <= hsync_next;
-			vsync_reg <= vsync_next;
-			blank_reg <= blank_next;			
-			
-			-- stage 1
-			xacc_reg <= xacc_next;
-			yacc_reg <= yacc_next;
-
-			-- stage 2
-			dt_reg <= dt_next;
-			dl_reg <= dl_next;
-			dtO_reg <= dtO_next;
-			dlO_reg <= dlO_next;
-
-			-- stage 3
-			A1_reg <= A1_next;
-			A2_reg <= A2_next;
-			A3_reg <= A3_next;
-			A4_reg <= A4_next;
-
-			p1_s3_reg <= p1_s3_next;
-			p2_s3_reg <= p2_s3_next;
-			p3_s3_reg <= p3_s3_next;
-			p4_s3_reg <= p4_s3_next;
-
-			-- stage 4
-			f1_r_reg <= f1_r_next;
-			f2_r_reg <= f2_r_next;
-			f3_r_reg <= f3_r_next;
-			f4_r_reg <= f4_r_next;
-
-			f1_g_reg <= f1_g_next;
-			f2_g_reg <= f2_g_next;
-			f3_g_reg <= f3_g_next;
-			f4_g_reg <= f4_g_next;
-
-			f1_b_reg <= f1_b_next;
-			f2_b_reg <= f2_b_next;
-			f3_b_reg <= f3_b_next;
-			f4_b_reg <= f4_b_next;
-
-			-- stage 5
-			r_reg <= r_next;
-			g_reg <= g_next;
-			b_reg <= b_next;
-		end if;
-	end process;
-	
-	-- temporary params, until i2c implemented
-	-- 720p
---	param_xthreshold_next <= to_unsigned(699,10); -- these need to be inputs
---	param_xdelta_next <= to_unsigned(393,10);
---	param_ythreshold_next <= to_unsigned(400,9);
---	param_ydelta_next <= to_unsigned(166,9);
--- param_ydeltaeach_next <= to_unsigned(166,9);
---	param_xaddrskip_next <= "10";
-
-	-- 1080i
-	param_xthreshold_next <= to_unsigned(400,11); -- these need to be inputs
-	param_xdelta_next <= to_unsigned(300,11);
-	param_ythreshold_next <= to_unsigned(786,11);
-	param_ydelta_next <= to_unsigned(218,11);
-	param_ydeltaeach_next <= to_unsigned(437,11); --interlace, need to skip a line
-	param_xaddrskip_next <= "01";
-	
---  Delay sync in line with pipeline: multi stage 1-5
-   process(hsync_reg,vsync_reg,blank_reg,hsync_in,vsync_in,blank_in)
-	begin		
-		hsync_next <= hsync_reg(5 downto 1)&hsync_in;
-		vsync_next <= vsync_reg(5 downto 1)&vsync_in;
-		blank_next <= blank_reg(5 downto 1)&blank_in;
-	end process;
-
--- 	Compute accumulator - pipeline stage 1
-	process(xacc_reg,param_xdelta_reg,param_xthreshold_reg,next_y_in)
-	begin
-		next_x <= '0';
-		xacc_next <= xacc_reg+param_xdelta_reg;
-		if ((xacc_reg+param_xdelta_reg)>=param_xthreshold_reg) then
-			next_x <= '1'; -- when I ask for data, its on p1 in 2 cycles, i.e. pipeline stage 3
-			xacc_next <= xacc_reg+param_xdelta_reg-param_xthreshold_reg;
-		end if;
-
-		if (next_y_in ='1') then 
-			xacc_next <= (others=>'0');
-		end if;
-	end process;
-
-	process(yacc_reg,param_ydeltaeach_reg,param_ythreshold_reg,next_y_in,next_frame_in,field2)
-	begin
-		yacc_next <= yacc_reg;
-		next_y <= '0';
-
-		if (next_y_in='1') then
-			yacc_next <= yacc_reg+param_ydeltaeach_reg; 
-			if ((yacc_reg+param_ydeltaeach_reg)>=param_ythreshold_reg) then
-				next_y <= '1';
-				yacc_next <= yacc_reg+param_ydeltaeach_reg-param_ythreshold_reg;
-			end if;
-		end if;
-
-		if (next_frame_in='1') then
-			yacc_next <= (others=>'0');
-			if (field2='1') then --slightly lower on interlace field 2
-				yacc_next(9 downto 0) <= param_ythreshold_reg(10 downto 1);
-			end if;
-		end if;
-	end process;
-
---      Area computation - pipeline stage 2
---      dl = min(customscalex-xacc_i,xdelta);
---      dt = min(customscaley-yacc_i,ydelta);
---      
---      dlO = (xdelta-dl);
---      dtO = (ydelta-dt);
---      
---      A1 = dl*dt;   %M1
---      A2 = dlO*dt;  %M2
---      A3 = dl*dtO;  %M3
---      A4 = TA-A3-A2-A1; %Save 1!
-	process(
-		param_xthreshold_reg,xacc_reg,param_xdelta_reg,
-		param_ythreshold_reg,yacc_reg,param_ydelta_reg)
-		variable dl : unsigned(10 downto 0);
-		variable dt : unsigned(10 downto 0);
-
-		variable dlO : unsigned(10 downto 0);
-		variable dtO : unsigned(10 downto 0);
-	begin
-		dl := param_xthreshold_reg-xacc_reg(10 downto 0);
-		if (dl>param_xdelta_reg) then
-			dl := param_xdelta_reg;
-		end if;
-
-		dt := param_ythreshold_reg-yacc_reg(10 downto 0);
-		if (dt>param_ydelta_reg) then
-			dt := param_ydelta_reg;
-		end if;
-
-		dlO:= param_xdelta_reg-dl;
-		dtO:= param_ydelta_reg-dt;
-
-		dt_next <= dt(8 downto 0);
-		dl_next <= dl(8 downto 0);
-		dtO_next <= dtO(8 downto 0);
-		dlO_next <= dlO(8 downto 0);
-	end process;
-
---      Area computation - pipeline stage 3
-	process(dl_reg,dlO_reg,dt_reg,dtO_reg)
-	begin
-		-- dsp blocks 9x9 multipliers
-		-- 3 per block
-		A1_next <= dl_reg*dt_reg;
-		A2_next <= dlO_reg*dt_reg;
-		A3_next <= dl_reg*dtO_reg;
-		A4_next <= dlO_reg*dtO_reg; --can save this one (leaving for now)
-
-		--A1 <= to_unsigned(0,18);
-		--A2 <= to_unsigned(0,18);
-		--A3 <= to_unsigned(0,18);
-		--A4 <= to_unsigned(65535,18);
-	end process;
-
-	-- delay pixel data
-	process(pixels)
-	begin
-		p1_s3_next <= pixels(pixel2x2_idx(0,0));
-		p2_s3_next <= pixels(pixel2x2_idx(1,0));
-		p3_s3_next <= pixels(pixel2x2_idx(0,1));
-		p4_s3_next <= pixels(pixel2x2_idx(1,1));
-	end process;
-
---      Pixel scaling computation - pipeline stage 4
-	-- Compute output
-	-- (p1*A1 + p2*A2 + p3*A3 + p4*A4)/65536
-	process(A1_reg,A2_reg,A3_reg,A4_reg,p1_s3_reg,p2_s3_reg,p3_s3_reg,p4_s3_reg)
-	begin
-		-- dsp blocks 18x18 multipliers
-		-- 2 per block
-		f1_r_next <= unsigned("0000000000"&p1_s3_reg.red)*A1_reg;
-		f2_r_next <= unsigned("0000000000"&p2_s3_reg.red)*A2_reg;
-		f3_r_next <= unsigned("0000000000"&p3_s3_reg.red)*A3_reg;
-		f4_r_next <= unsigned("0000000000"&p4_s3_reg.red)*A4_reg;
-
-		f1_g_next <= unsigned("0000000000"&p1_s3_reg.green)*A1_reg;
-		f2_g_next <= unsigned("0000000000"&p2_s3_reg.green)*A2_reg;
-		f3_g_next <= unsigned("0000000000"&p3_s3_reg.green)*A3_reg;
-		f4_g_next <= unsigned("0000000000"&p4_s3_reg.green)*A4_reg;
-
-		f1_b_next <= unsigned("0000000000"&p1_s3_reg.blue)*A1_reg;
-		f2_b_next <= unsigned("0000000000"&p2_s3_reg.blue)*A2_reg;
-		f3_b_next <= unsigned("0000000000"&p3_s3_reg.blue)*A3_reg;
-		f4_b_next <= unsigned("0000000000"&p4_s3_reg.blue)*A4_reg;
-	end process;
-
---      Pixel scaling computation - pipeline stage 5
-	-- Compute output
-	-- (p1*A1 + p2*A2 + p3*A3 + p4*A4)/65536
-	process(
-		f1_r_reg,f2_r_reg,f3_r_reg,f4_r_reg,
-		f1_g_reg,f2_g_reg,f3_g_reg,f4_g_reg,
-		f1_b_reg,f2_b_reg,f3_b_reg,f4_b_reg)
-		variable sum_r : unsigned(9 downto 0);
-		variable sum_g : unsigned(9 downto 0);
-		variable sum_b : unsigned(9 downto 0);
-	begin
-		sum_r := (f1_r_reg(23 downto 14)+f2_r_reg(23 downto 14))+(f3_r_reg(23 downto 14)+f4_r_reg(23 downto 14));
-		sum_g := (f1_g_reg(23 downto 14)+f2_g_reg(23 downto 14))+(f3_g_reg(23 downto 14)+f4_g_reg(23 downto 14));
-		sum_b := (f1_b_reg(23 downto 14)+f2_b_reg(23 downto 14))+(f3_b_reg(23 downto 14)+f4_b_reg(23 downto 14));
-
-		r_next <= std_logic_vector(sum_r(9 downto 2));
-		g_next <= std_logic_vector(sum_g(9 downto 2));
-		b_next <= std_logic_vector(sum_b(9 downto 2));
-	end process;
-
-	-- outputnext_x_size
-	r<=r_reg;
-	g<=g_reg;
-	b<=b_reg;
-	hsync<=hsync_reg(6); -- TODO: why 6 and not 5?
-	vsync<=vsync_reg(6);
-	blank<=blank_reg(6); 
-	
-	next_x_size <= std_logic_vector(param_xaddrskip_reg);
-
-END vhdl;
-
---              h_pixels_across  <= 720 - 1;
---              h_sync_on <= 732 - 1;
---              h_sync_off <= 795 - 1;
---              h_end_count <= 864 - 1;
---              v_pixels_down <= 576 - 1;
---              v_sync_on <=  581 - 1;
---              v_sync_off <= 586 - 1;
---              v_end_count <=  625 - 1;
-
---                --PAL
---                h_pixels_across  <= 1280 - 1;
---                h_sync_on <= 1720 - 1;
---                h_sync_off <= 1760 - 1;
---                h_end_count <= 1980 - 1;
---                v_pixels_down <= 720 - 1;
---                v_sync_on <=  725 - 1;
---                v_sync_off <= 730 - 1;
---                v_end_count <=  750 - 1;
-
-
Index: eclaireXL_ITX/polyphasicscale.vhd
===================================================================
--- eclaireXL_ITX/polyphasicscale.vhd	(revision 973)
+++ eclaireXL_ITX/polyphasicscale.vhd	(nonexistent)
@@ -1,910 +0,0 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
---USE ieee.std_logic_arith.all;
---USE ieee.std_logic_unsigned.all;
-USE ieee.numeric_std.all;
-use work.pixels.all;
-
---TODO: scanlines!!
---out_colour(7 downto 4) <= out_colour_raw(7 downto 4);
---out_colour(3 downto 0) <= out_colour_raw(3 downto 0) when (not(out_scanlines) or vcnt(0))='1' else '0'&out_colour_raw(3 downto 1);
-
-ENTITY polyphasicscale IS
-  PORT(
-    clock   : IN     STD_LOGIC;                             --system clock
-    reset_n : IN     STD_LOGIC;                             --asynchronous reset
-
-    -- input pixels
-    pixels : in t_Pixel4x4;
-
-    -- next output line
-    next_y_in : in std_logic;
-    next_frame_in : in std_logic;
-    field2 : in std_logic;
-    
-    -- sync/blank from crtc -> need to be delayed in line with pipeline
-    hsync_in : in std_logic;
-    vsync_in : in std_logic;
-    blank_in : in std_logic; 
-	 
-    -- need to provide control signals:
-    next_x : OUT STD_LOGIC;
-	 next_x_size : out std_logic_vector(1 downto 0);
-    next_y : OUT STD_LOGIC;	 
-
-    -- need to output
-    -- current pixel
-    r : out std_logic_vector(7 downto 0);
-    g : out std_logic_vector(7 downto 0);
-    b : out std_logic_vector(7 downto 0);
-    hsync : out std_logic;
-    vsync : out std_logic;
-    blank : out std_logic;
-	 
-    -- to set up params
-    sda : inout std_logic;
-    scl : inout std_logic	 
-  );
-END polyphasicscale;
-
--- customscalex:568 customscaley:256 xdelta:640 ydelta:102 TA:65536
-ARCHITECTURE vhdl OF polyphasicscale IS
-	signal param_xthreshold_next : unsigned(10 downto 0);
-	signal param_xthreshold_reg : unsigned(10 downto 0);
-	signal param_ythreshold_next : unsigned(10 downto 0);
-	signal param_ythreshold_reg : unsigned(10 downto 0);
-	signal param_xdelta_next : unsigned(10 downto 0);
-	signal param_xdelta_reg : unsigned(10 downto 0);
-	signal param_ydeltaeach_next : unsigned(10 downto 0);
-	signal param_ydeltaeach_reg : unsigned(10 downto 0);	
-	signal param_xaddrskip_next : unsigned(1 downto 0); -- We only support upscaling, so for some cases need to skip 2 pixels
-	signal param_xaddrskip_reg : unsigned(1 downto 0);
-	
-	-- stage 1:5 Delay syncs in line with pipeline
-	signal hsync_next : std_logic_vector(6 downto 1);
-	signal hsync_reg : std_logic_vector(6 downto 1);
-	signal vsync_next : std_logic_vector(6 downto 1);
-	signal vsync_reg : std_logic_vector(6 downto 1);
-	signal blank_next : std_logic_vector(6 downto 1);
-	signal blank_reg : std_logic_vector(6 downto 1);
-	
-	-- stage 1 : Accumulators/ data request
-	signal xacc_next : unsigned(11 downto 0);
-	signal xacc_reg : unsigned(11 downto 0);
-	signal yacc_next : unsigned(11 downto 0);
-	signal yacc_reg : unsigned(11 downto 0);
-	signal next_x_delay1_next : std_logic;
-	signal next_x_delay1_reg : std_logic;	
-	
-	-- stage 2 : Coefs calc
-	type t_Coef is record
-		 c1  : signed(8 downto 0);
-		 c2  : signed(8 downto 0);
-		 c3  : signed(8 downto 0);
-		 c4  : signed(8 downto 0);
-	end record t_Coef;  	
-	
-	signal coefx_next: t_Coef;
-	signal coefx_reg : t_Coef;
-	signal coefx3_next: t_Coef;
-	signal coefx3_reg : t_Coef;	
-	signal coefx4_next: t_Coef;
-	signal coefx4_reg : t_Coef;		
-	signal coefy_next: t_Coef;
-	signal coefy_reg : t_Coef;
-	signal next_x_delay2_next : std_logic;
-	signal next_x_delay2_reg : std_logic;		
-
-	-- stage 3 : Y mult
-	signal ry1_next : signed(17 downto 0);
-	signal ry1_reg : signed(17 downto 0);
-	signal ry2_next : signed(17 downto 0);
-	signal ry2_reg : signed(17 downto 0);
-	signal ry3_next : signed(17 downto 0);
-	signal ry3_reg : signed(17 downto 0);
-	signal ry4_next : signed(17 downto 0);
-	signal ry4_reg : signed(17 downto 0);
-
-	signal gy1_next : signed(17 downto 0);
-	signal gy1_reg : signed(17 downto 0);
-	signal gy2_next : signed(17 downto 0);
-	signal gy2_reg : signed(17 downto 0);
-	signal gy3_next : signed(17 downto 0);
-	signal gy3_reg : signed(17 downto 0);
-	signal gy4_next : signed(17 downto 0);
-	signal gy4_reg : signed(17 downto 0);
-
-	signal by1_next : signed(17 downto 0);
-	signal by1_reg : signed(17 downto 0);
-	signal by2_next : signed(17 downto 0);
-	signal by2_reg : signed(17 downto 0);
-	signal by3_next : signed(17 downto 0);
-	signal by3_reg : signed(17 downto 0);
-	signal by4_next : signed(17 downto 0);
-	signal by4_reg : signed(17 downto 0);
-	signal next_x_delay3_next : std_logic;
-	signal next_x_delay3_reg : std_logic;	
-
-	-- stage 4: X pixels
-	signal pixel_rx1_next : signed(8 downto 0);
-	signal pixel_rx1_reg : signed(8 downto 0);
-	signal pixel_rx2_next : signed(8 downto 0);
-	signal pixel_rx2_reg : signed(8 downto 0);
-	signal pixel_rx3_next : signed(8 downto 0);
-	signal pixel_rx3_reg : signed(8 downto 0);
-	signal pixel_rx4_next : signed(8 downto 0);
-	signal pixel_rx4_reg : signed(8 downto 0);
-
-	signal pixel_gx1_next : signed(8 downto 0);
-	signal pixel_gx1_reg : signed(8 downto 0);
-	signal pixel_gx2_next : signed(8 downto 0);
-	signal pixel_gx2_reg : signed(8 downto 0);
-	signal pixel_gx3_next : signed(8 downto 0);
-	signal pixel_gx3_reg : signed(8 downto 0);
-	signal pixel_gx4_next : signed(8 downto 0);
-	signal pixel_gx4_reg : signed(8 downto 0);
-
-	signal pixel_bx1_next : signed(8 downto 0);
-	signal pixel_bx1_reg : signed(8 downto 0);
-	signal pixel_bx2_next : signed(8 downto 0);
-	signal pixel_bx2_reg : signed(8 downto 0);
-	signal pixel_bx3_next : signed(8 downto 0);
-	signal pixel_bx3_reg : signed(8 downto 0);
-	signal pixel_bx4_next : signed(8 downto 0);
-	signal pixel_bx4_reg : signed(8 downto 0);
-
-	-- stage 5: X mult
-	signal rx1_next : signed(17 downto 0);
-	signal rx1_reg : signed(17 downto 0);
-	signal rx2_next : signed(17 downto 0);
-	signal rx2_reg : signed(17 downto 0);
-	signal rx3_next : signed(17 downto 0);
-	signal rx3_reg : signed(17 downto 0);
-	signal rx4_next : signed(17 downto 0);
-	signal rx4_reg : signed(17 downto 0);
-
-	signal gx1_next : signed(17 downto 0);
-	signal gx1_reg : signed(17 downto 0);
-	signal gx2_next : signed(17 downto 0);
-	signal gx2_reg : signed(17 downto 0);
-	signal gx3_next : signed(17 downto 0);
-	signal gx3_reg : signed(17 downto 0);
-	signal gx4_next : signed(17 downto 0);
-	signal gx4_reg : signed(17 downto 0);
-
-	signal bx1_next : signed(17 downto 0);
-	signal bx1_reg : signed(17 downto 0);
-	signal bx2_next : signed(17 downto 0);
-	signal bx2_reg : signed(17 downto 0);
-	signal bx3_next : signed(17 downto 0);
-	signal bx3_reg : signed(17 downto 0);
-	signal bx4_next : signed(17 downto 0);
-	signal bx4_reg : signed(17 downto 0);
-
-	-- stage 6: Pixel output (sum)
-	signal r_reg : std_logic_vector(7 downto 0);
-	signal r_next : std_logic_vector(7 downto 0);
-	signal g_reg : std_logic_vector(7 downto 0);
-	signal g_next : std_logic_vector(7 downto 0);
-	signal b_reg : std_logic_vector(7 downto 0);
-	signal b_next : std_logic_vector(7 downto 0);
-
-BEGIN
-	process(clock,reset_n)
-	begin
-		if (reset_n='0') then
-			param_xthreshold_reg <= (others=>'0');
-			param_ythreshold_reg <= (others=>'0');
-			param_xdelta_reg <= (others=>'0');
-			param_ydeltaeach_reg <= (others=>'0');
-			param_xaddrskip_reg <= "01";
-			
-			-- multi stage 1-5
-			hsync_reg <= (others=>'0');
-			vsync_reg <= (others=>'0');
-			blank_reg <= (others=>'0');
-
-			-- stage 1
-			xacc_reg <= (others=>'0');
-			yacc_reg <= (others=>'0');
-			next_x_delay1_reg <= '0';
-
-			-- stage 2
-			coefx_reg.c1 <= (others=>'0');
-			coefx_reg.c2 <= (others=>'0');
-			coefx_reg.c3 <= (others=>'0');
-			coefx_reg.c4 <= (others=>'0');
-			coefy_reg.c1 <= (others=>'0');
-			coefy_reg.c2 <= (others=>'0');
-			coefy_reg.c3 <= (others=>'0');
-			coefy_reg.c4 <= (others=>'0');
-			next_x_delay2_reg <= '0';
-
-			-- stage 3
-			ry1_reg <= (others=>'0');
-			ry2_reg <= (others=>'0');
-			ry3_reg <= (others=>'0');
-			ry4_reg <= (others=>'0');
-
-			gy1_reg <= (others=>'0');
-			gy2_reg <= (others=>'0');
-			gy3_reg <= (others=>'0');
-			gy4_reg <= (others=>'0');
-
-			by1_reg <= (others=>'0');
-			by2_reg <= (others=>'0');
-			by3_reg <= (others=>'0');
-			by4_reg <= (others=>'0');
-			
-			coefx3_reg.c1 <= (others=>'0');
-			coefx3_reg.c2 <= (others=>'0');
-			coefx3_reg.c3 <= (others=>'0');
-			coefx3_reg.c4 <= (others=>'0');	
-			next_x_delay3_reg <= '0';
-
-			-- stage 4
-			pixel_rx1_reg <= (others=>'0');
-			pixel_gx1_reg <= (others=>'0');
-			pixel_bx1_reg <= (others=>'0');
-
-			pixel_rx2_reg <= (others=>'0');
-			pixel_gx2_reg <= (others=>'0');
-			pixel_bx2_reg <= (others=>'0');
-
-			pixel_rx3_reg <= (others=>'0');
-			pixel_gx3_reg <= (others=>'0');
-			pixel_bx3_reg <= (others=>'0');
-
-			pixel_rx4_reg <= (others=>'0');
-			pixel_gx4_reg <= (others=>'0');
-			pixel_bx4_reg <= (others=>'0');		
-	
-			coefx4_reg.c1 <= (others=>'0');
-			coefx4_reg.c2 <= (others=>'0');
-			coefx4_reg.c3 <= (others=>'0');
-			coefx4_reg.c4 <= (others=>'0');	
-
-			-- stage 5
-			rx1_reg <= (others=>'0');
-			rx2_reg <= (others=>'0');
-			rx3_reg <= (others=>'0');
-			rx4_reg <= (others=>'0');
-
-			gx1_reg <= (others=>'0');
-			gx2_reg <= (others=>'0');
-			gx3_reg <= (others=>'0');
-			gx4_reg <= (others=>'0');
-
-			bx1_reg <= (others=>'0');
-			bx2_reg <= (others=>'0');
-			bx3_reg <= (others=>'0');
-			bx4_reg <= (others=>'0');
-
-			-- stage 6
-			r_reg <= (others=>'0');
-			g_reg <= (others=>'0');
-			b_reg <= (others=>'0');
-		elsif (clock'event and clock='1') then
-			param_xthreshold_reg <= param_xthreshold_next;
-			param_xdelta_reg <= param_xdelta_next;
-			param_ythreshold_reg <= param_ythreshold_next;
-			param_ydeltaeach_reg <= param_ydeltaeach_next;
-			param_xaddrskip_reg <= param_xaddrskip_next;
-
-			-- multi stage 1-5
-			hsync_reg <= hsync_next;
-			vsync_reg <= vsync_next;
-			blank_reg <= blank_next;			
-			
-			-- stage 1
-			xacc_reg <= xacc_next;
-			yacc_reg <= yacc_next;
-			next_x_delay1_reg <= next_x_delay1_next;
-
-			-- stage 2
-			coefx_reg <= coefx_next;
-			coefy_reg <= coefy_next;
-			next_x_delay2_reg <= next_x_delay2_next;
-
-			-- stage 3
-			ry1_reg <= ry1_next;
-			ry2_reg <= ry2_next;
-			ry3_reg <= ry3_next;
-			ry4_reg <= ry4_next;
-
-			gy1_reg <= gy1_next;
-			gy2_reg <= gy2_next;
-			gy3_reg <= gy3_next;
-			gy4_reg <= gy4_next;
-
-			by1_reg <= by1_next;
-			by2_reg <= by2_next;
-			by3_reg <= by3_next;
-			by4_reg <= by4_next;
-			
-			coefx3_reg <= coefx3_next;			
-			next_x_delay3_reg <= next_x_delay3_next;
-
-			-- stage 4
-			pixel_rx1_reg <= pixel_rx1_next;
-			pixel_gx1_reg <= pixel_gx1_next;
-			pixel_bx1_reg <= pixel_bx1_next;
-
-			pixel_rx2_reg <= pixel_rx2_next;
-			pixel_gx2_reg <= pixel_gx2_next;
-			pixel_bx2_reg <= pixel_bx2_next;
-
-			pixel_rx3_reg <= pixel_rx3_next;
-			pixel_gx3_reg <= pixel_gx3_next;
-			pixel_bx3_reg <= pixel_bx3_next;
-
-			pixel_rx4_reg <= pixel_rx4_next;
-			pixel_gx4_reg <= pixel_gx4_next;
-			pixel_bx4_reg <= pixel_bx4_next;
-			
-			coefx4_reg <= coefx4_next;		
-
-			-- stage 5
-			rx1_reg <= rx1_next;
-			rx2_reg <= rx2_next;
-			rx3_reg <= rx3_next;
-			rx4_reg <= rx4_next;
-
-			gx1_reg <= gx1_next;
-			gx2_reg <= gx2_next;
-			gx3_reg <= gx3_next;
-			gx4_reg <= gx4_next;
-
-			bx1_reg <= bx1_next;
-			bx2_reg <= bx2_next;
-			bx3_reg <= bx3_next;
-			bx4_reg <= bx4_next;
-
-			-- stage 6
-			r_reg <= r_next;
-			g_reg <= g_next;
-			b_reg <= b_next;
-		end if;
-	end process;
-	
-	-- temporary params, until i2c implemented
-	-- 720p
---	param_xthreshold_next <= to_unsigned(699,10); -- these need to be inputs
---	param_xdelta_next <= to_unsigned(393,10);
---	param_ythreshold_next <= to_unsigned(400,9);
---	param_ydelta_next <= to_unsigned(166,9);
--- param_ydeltaeach_next <= to_unsigned(166,9);
---	param_xaddrskip_next <= "10";
-
-	-- 1080i
---	param_xthreshold_next <= to_unsigned(400,11); -- these need to be inputs
---	param_xdelta_next <= to_unsigned(300,11);
---	param_ythreshold_next <= to_unsigned(786,11);
---	param_ydelta_next <= to_unsigned(218,11);
---	param_ydeltaeach_next <= to_unsigned(437,11); --interlace, need to skip a line
---	param_xaddrskip_next <= "01";
-
-
-	param_xthreshold_next <= to_unsigned(1024,11); -- these need to be inputs
-	param_xdelta_next <= to_unsigned(768,11);
-	--param_xdelta_next <= to_unsigned(64,11);
-	param_ythreshold_next <= to_unsigned(1024,11);
-	--param_ydelta_next <= to_unsigned(284,11);
-	param_ydeltaeach_next <= to_unsigned(569,11); --interlace, need to skip a line
-	param_xaddrskip_next <= "01";
-	
---  Delay sync in line with pipeline: multi stage 1-5
-   process(hsync_reg,vsync_reg,blank_reg,hsync_in,vsync_in,blank_in)
-	begin		
-		hsync_next <= hsync_reg(5 downto 1)&hsync_in;
-		vsync_next <= vsync_reg(5 downto 1)&vsync_in;
-		blank_next <= blank_reg(5 downto 1)&blank_in;
-	end process;
-
--- 	Compute accumulator - pipeline stage 1
-	process(xacc_reg,param_xdelta_reg,param_xthreshold_reg,next_y_in)
-	begin
-		next_x <= '0';
-		next_x_delay1_next <= '0';
-		xacc_next <= xacc_reg+param_xdelta_reg;
-		if ((xacc_reg+param_xdelta_reg)>=param_xthreshold_reg) then
-			next_x <= '1'; -- when I ask for data, its on p1 in 2 cycles, i.e. pipeline stage 3
-			next_x_delay1_next <= '1';
-			xacc_next <= xacc_reg+param_xdelta_reg-param_xthreshold_reg;
-		end if;
-
-		if (next_y_in ='1') then 
-			xacc_next <= (others=>'0');
-		end if;
-	end process;
-
-	process(yacc_reg,param_ydeltaeach_reg,param_ythreshold_reg,next_y_in,next_frame_in,field2)
-	begin
-		yacc_next <= yacc_reg;
-		next_y <= '0';
-
-		if (next_y_in='1') then
-			yacc_next <= yacc_reg+param_ydeltaeach_reg; 
-			if ((yacc_reg+param_ydeltaeach_reg)>=param_ythreshold_reg) then
-				next_y <= '1';
-				yacc_next <= yacc_reg+param_ydeltaeach_reg-param_ythreshold_reg;
-			end if;
-		end if;
-
-		if (next_frame_in='1') then
-			yacc_next <= (others=>'0');
-			if (field2='1') then --slightly lower on interlace field 2
-				yacc_next(9 downto 0) <= param_ythreshold_reg(10 downto 1);
-			end if;
-		end if;
-	end process;
-
---      Coef computation - pipeline stage 2
-	process(
-		xacc_reg,
-		yacc_reg)
-	variable xphase : std_logic_vector(3 downto 0);
-	variable yphase : std_logic_vector(3 downto 0);
-	begin
-		coefx_next.c1 <= (others=>'0');
-		coefx_next.c2 <= (others=>'0');
-		coefx_next.c3 <= (others=>'0');
-		coefx_next.c4 <= (others=>'0');
-		coefy_next.c1 <= (others=>'0');
-		coefy_next.c2 <= (others=>'0');
-		coefy_next.c3 <= (others=>'0');
-		coefy_next.c4 <= (others=>'0');
-
-		xphase := std_logic_vector(xacc_reg(9 downto 6));
-		yphase := std_logic_vector(yacc_reg(9 downto 6));
-
---		case xphase is
---		when "0000" =>
---			coefx_next <= x"7f000000";
---		when "0001" =>
---			coefx_next <= x"7f000000";
---		when "0010" =>
---			coefx_next <= x"7f000000";
---		when "0011" =>
---			coefx_next <= x"7f000000";
---		when "0100" =>
---			coefx_next <= x"7f000000";
---		when "0101" =>
---			coefx_next <= x"7f000000";
---		when "0110" =>
---			coefx_next <= x"7f000000";
---		when "0111" =>
---			coefx_next <= x"7f000000";
---		when "1000" =>
---		        coefx_next <= x"7f000000";
---		when "1001" =>
---		        coefx_next <= x"7f000000";
---		when "1010" =>
---		        coefx_next <= x"7f000000";
---		when "1011" =>
---		        coefx_next <= x"7f000000";
---		when "1100" =>
---		        coefx_next <= x"7f000000";
---		when "1101" =>
---		        coefx_next <= x"7f000000";
---		when "1110" =>
---		        coefx_next <= x"7f000000";
---		when "1111" =>
---			coefx_next <= x"7f000000";
---		when others=>
---			coefx_next <= (others=>'0');
---		end case;
---
---		case yphase is
---		when "0000" =>
---			coefy_next <= x"7f000000";
---		when "0001" =>
---			coefy_next <= x"7f000000";
---		when "0010" =>
---			coefy_next <= x"7f000000";
---		when "0011" =>
---			coefy_next <= x"7f000000";
---		when "0100" =>
---			coefy_next <= x"7f000000";
---		when "0101" =>
---			coefy_next <= x"7f000000";
---		when "0110" =>
---			coefy_next <= x"7f000000";
---		when "0111" =>
---			coefy_next <= x"7f000000";
---		when "1000" =>
---		        coefy_next <= x"7f000000";
---		when "1001" =>
---		        coefy_next <= x"7f000000";
---		when "1010" =>
---		        coefy_next <= x"7f000000";
---		when "1011" =>
---		        coefy_next <= x"7f000000";
---		when "1100" =>
---		        coefy_next <= x"7f000000";
---		when "1101" =>
---		        coefy_next <= x"7f000000";
---		when "1110" =>
---		        coefy_next <= x"7f000000";
---		when "1111" =>
---			coefy_next <= x"7f000000";
---		when others=>
---			coefy_next <= (others=>'0');
---		end case;
-case xphase is 
-when "0000" =>
-	coefx_next.c1 <= to_signed(-8,9);
-	coefx_next.c2 <= to_signed(147,9);
-	coefx_next.c3 <= to_signed(-8,9);
-	coefx_next.c4 <= to_signed(1,9);
-when "0001" =>
-	coefx_next.c1 <= to_signed(-6,9);
-	coefx_next.c2 <= to_signed(148,9);
-	coefx_next.c3 <= to_signed(-11,9);
-	coefx_next.c4 <= to_signed(1,9);
-when "0010" =>
-	coefx_next.c1 <= to_signed(-3,9);
-	coefx_next.c2 <= to_signed(147,9);
-	coefx_next.c3 <= to_signed(-13,9);
-	coefx_next.c4 <= to_signed(1,9);
-when "0011" =>
-	coefx_next.c1 <= to_signed(-1,9);
-	coefx_next.c2 <= to_signed(145,9);
-	coefx_next.c3 <= to_signed(-13,9);
-	coefx_next.c4 <= to_signed(1,9);
-when "0100" =>
-	coefx_next.c1 <= to_signed(0,9);
-	coefx_next.c2 <= to_signed(141,9);
-	coefx_next.c3 <= to_signed(-10,9);
-	coefx_next.c4 <= to_signed(1,9);
-when "0101" =>
-	coefx_next.c1 <= to_signed(1,9);
-	coefx_next.c2 <= to_signed(133,9);
-	coefx_next.c3 <= to_signed(-3,9);
-	coefx_next.c4 <= to_signed(1,9);
-when "0110" =>
-	coefx_next.c1 <= to_signed(1,9);
-	coefx_next.c2 <= to_signed(118,9);
-	coefx_next.c3 <= to_signed(12,9);
-	coefx_next.c4 <= to_signed(1,9);
-when "0111" =>
-	coefx_next.c1 <= to_signed(1,9);
-	coefx_next.c2 <= to_signed(95,9);
-	coefx_next.c3 <= to_signed(35,9);
-	coefx_next.c4 <= to_signed(1,9);
-when "1000" =>
-	coefx_next.c1 <= to_signed(1,9);
-	coefx_next.c2 <= to_signed(65,9);
-	coefx_next.c3 <= to_signed(65,9);
-	coefx_next.c4 <= to_signed(1,9);
-when "1001" =>
-	coefx_next.c1 <= to_signed(1,9);
-	coefx_next.c2 <= to_signed(35,9);
-	coefx_next.c3 <= to_signed(95,9);
-	coefx_next.c4 <= to_signed(1,9);
-when "1010" =>
-	coefx_next.c1 <= to_signed(1,9);
-	coefx_next.c2 <= to_signed(12,9);
-	coefx_next.c3 <= to_signed(118,9);
-	coefx_next.c4 <= to_signed(1,9);
-when "1011" =>
-	coefx_next.c1 <= to_signed(1,9);
-	coefx_next.c2 <= to_signed(-3,9);
-	coefx_next.c3 <= to_signed(133,9);
-	coefx_next.c4 <= to_signed(1,9);
-when "1100" =>
-	coefx_next.c1 <= to_signed(1,9);
-	coefx_next.c2 <= to_signed(-10,9);
-	coefx_next.c3 <= to_signed(141,9);
-	coefx_next.c4 <= to_signed(0,9);
-when "1101" =>
-	coefx_next.c1 <= to_signed(1,9);
-	coefx_next.c2 <= to_signed(-13,9);
-	coefx_next.c3 <= to_signed(145,9);
-	coefx_next.c4 <= to_signed(-1,9);
-when "1110" =>
-	coefx_next.c1 <= to_signed(1,9);
-	coefx_next.c2 <= to_signed(-13,9);
-	coefx_next.c3 <= to_signed(147,9);
-	coefx_next.c4 <= to_signed(-3,9);
-when "1111" =>
-	coefx_next.c1 <= to_signed(1,9);
-	coefx_next.c2 <= to_signed(-11,9);
-	coefx_next.c3 <= to_signed(148,9);
-	coefx_next.c4 <= to_signed(-6,9);
-when others => 
-	coefx_next.c1 <= (others=>'0');
-	coefx_next.c2 <= (others=>'0');
-	coefx_next.c3 <= (others=>'0');
-	coefx_next.c4 <= (others=>'0');
-end case;
-case yphase is 
-when "0000" =>
-	coefy_next.c1 <= to_signed(-8,9);
-	coefy_next.c2 <= to_signed(147,9);
-	coefy_next.c3 <= to_signed(-8,9);
-	coefy_next.c4 <= to_signed(1,9);
-when "0001" =>
-	coefy_next.c1 <= to_signed(-6,9);
-	coefy_next.c2 <= to_signed(148,9);
-	coefy_next.c3 <= to_signed(-11,9);
-	coefy_next.c4 <= to_signed(1,9);
-when "0010" =>
-	coefy_next.c1 <= to_signed(-3,9);
-	coefy_next.c2 <= to_signed(147,9);
-	coefy_next.c3 <= to_signed(-13,9);
-	coefy_next.c4 <= to_signed(1,9);
-when "0011" =>
-	coefy_next.c1 <= to_signed(-1,9);
-	coefy_next.c2 <= to_signed(145,9);
-	coefy_next.c3 <= to_signed(-13,9);
-	coefy_next.c4 <= to_signed(1,9);
-when "0100" =>
-	coefy_next.c1 <= to_signed(0,9);
-	coefy_next.c2 <= to_signed(141,9);
-	coefy_next.c3 <= to_signed(-10,9);
-	coefy_next.c4 <= to_signed(1,9);
-when "0101" =>
-	coefy_next.c1 <= to_signed(1,9);
-	coefy_next.c2 <= to_signed(133,9);
-	coefy_next.c3 <= to_signed(-3,9);
-	coefy_next.c4 <= to_signed(1,9);
-when "0110" =>
-	coefy_next.c1 <= to_signed(1,9);
-	coefy_next.c2 <= to_signed(118,9);
-	coefy_next.c3 <= to_signed(12,9);
-	coefy_next.c4 <= to_signed(1,9);
-when "0111" =>
-	coefy_next.c1 <= to_signed(1,9);
-	coefy_next.c2 <= to_signed(95,9);
-	coefy_next.c3 <= to_signed(35,9);
-	coefy_next.c4 <= to_signed(1,9);
-when "1000" =>
-	coefy_next.c1 <= to_signed(1,9);
-	coefy_next.c2 <= to_signed(65,9);
-	coefy_next.c3 <= to_signed(65,9);
-	coefy_next.c4 <= to_signed(1,9);
-when "1001" =>
-	coefy_next.c1 <= to_signed(1,9);
-	coefy_next.c2 <= to_signed(35,9);
-	coefy_next.c3 <= to_signed(95,9);
-	coefy_next.c4 <= to_signed(1,9);
-when "1010" =>
-	coefy_next.c1 <= to_signed(1,9);
-	coefy_next.c2 <= to_signed(12,9);
-	coefy_next.c3 <= to_signed(118,9);
-	coefy_next.c4 <= to_signed(1,9);
-when "1011" =>
-	coefy_next.c1 <= to_signed(1,9);
-	coefy_next.c2 <= to_signed(-3,9);
-	coefy_next.c3 <= to_signed(133,9);
-	coefy_next.c4 <= to_signed(1,9);
-when "1100" =>
-	coefy_next.c1 <= to_signed(1,9);
-	coefy_next.c2 <= to_signed(-10,9);
-	coefy_next.c3 <= to_signed(141,9);
-	coefy_next.c4 <= to_signed(0,9);
-when "1101" =>
-	coefy_next.c1 <= to_signed(1,9);
-	coefy_next.c2 <= to_signed(-13,9);
-	coefy_next.c3 <= to_signed(145,9);
-	coefy_next.c4 <= to_signed(-1,9);
-when "1110" =>
-	coefy_next.c1 <= to_signed(1,9);
-	coefy_next.c2 <= to_signed(-13,9);
-	coefy_next.c3 <= to_signed(147,9);
-	coefy_next.c4 <= to_signed(-3,9);
-when "1111" =>
-	coefy_next.c1 <= to_signed(1,9);
-	coefy_next.c2 <= to_signed(-11,9);
-	coefy_next.c3 <= to_signed(148,9);
-	coefy_next.c4 <= to_signed(-6,9);
-when others => 
-	coefy_next.c1 <= (others=>'0');
-	coefy_next.c2 <= (others=>'0');
-	coefy_next.c3 <= (others=>'0');
-	coefy_next.c4 <= (others=>'0');
-end case;
-
-
-	end process;
-
-	next_x_delay2_next <= next_x_delay1_reg;
-	
---      YMult - pipeline stage 3
-	process(pixels, coefy_reg)
-		variable p1 : t_pixel;
-		variable p2 : t_pixel;
-		variable p3 : t_pixel;
-		variable p4 : t_pixel;
-	begin
-		p1 := pixels(pixel4x4_idx(0,0));
-		p2 := pixels(pixel4x4_idx(0,1));
-		p3 := pixels(pixel4x4_idx(0,2));
-		p4 := pixels(pixel4x4_idx(0,3));
-
-		-- dsp blocks 9x9 multipliers
-		-- 3 per block -> 4 blocks
-		ry1_next <= signed('0'&p1.red)*coefy_reg.c1;
-		ry2_next <= signed('0'&p2.red)*coefy_reg.c2;
-		ry3_next <= signed('0'&p3.red)*coefy_reg.c3;
-		ry4_next <= signed('0'&p4.red)*coefy_reg.c4;
-
-		gy1_next <= signed('0'&p1.green)*coefy_reg.c1;
-		gy2_next <= signed('0'&p2.green)*coefy_reg.c2;
-		gy3_next <= signed('0'&p3.green)*coefy_reg.c3;
-		gy4_next <= signed('0'&p4.green)*coefy_reg.c4;
-
-		by1_next <= signed('0'&p1.blue)*coefy_reg.c1;
-		by2_next <= signed('0'&p2.blue)*coefy_reg.c2;
-		by3_next <= signed('0'&p3.blue)*coefy_reg.c3;
-		by4_next <= signed('0'&p4.blue)*coefy_reg.c4;
-	end process;
-	
-	next_x_delay3_next <= next_x_delay2_reg;
-	coefx3_next <= coefx_reg;
-
---      X pixels - pipeline stage 4
-	process(
-		pixel_rx1_reg,pixel_rx2_reg,pixel_rx3_reg,pixel_rx4_reg,
-		pixel_gx1_reg,pixel_gx2_reg,pixel_gx3_reg,pixel_gx4_reg,
-		pixel_bx1_reg,pixel_bx2_reg,pixel_bx3_reg,pixel_bx4_reg,
-		ry1_reg,ry2_reg,ry3_reg,ry4_reg,
-		gy1_reg,gy2_reg,gy3_reg,gy4_reg,
-		by1_reg,by2_reg,by3_reg,by4_reg,
-		next_x_delay3_reg
-		)
-		variable ry_sum : signed (17 downto 0);
-		variable gy_sum : signed (17 downto 0);
-		variable by_sum : signed (17 downto 0);
-	begin
-		pixel_rx1_next <= pixel_rx1_reg;
-		pixel_rx2_next <= pixel_rx2_reg;
-		pixel_rx3_next <= pixel_rx3_reg;
-		pixel_rx4_next <= pixel_rx4_reg;
-
-		pixel_gx1_next <= pixel_gx1_reg;
-		pixel_gx2_next <= pixel_gx2_reg;
-		pixel_gx3_next <= pixel_gx3_reg;
-		pixel_gx4_next <= pixel_gx4_reg;
-
-		pixel_bx1_next <= pixel_bx1_reg;
-		pixel_bx2_next <= pixel_bx2_reg;
-		pixel_bx3_next <= pixel_bx3_reg;
-		pixel_bx4_next <= pixel_bx4_reg;
-
-		if (next_x_delay3_reg='1') then
---		   ry_sum := ry1_reg+ry2_reg+ry3_reg+ry4_reg;			
---			pixel_rx1_next <= ry_sum(17)&ry_sum(15 downto 8); 
---			pixel_rx2_next <= pixel_rx1_reg;
---			pixel_rx3_next <= pixel_rx2_reg;
---			pixel_rx4_next <= pixel_rx3_reg;
---
---			gy_sum := gy1_reg+gy2_reg+gy3_reg+gy4_reg;
---			pixel_gx1_next <= gy_sum(17)&gy_sum(15 downto 8);
---			pixel_gx2_next <= pixel_gx1_reg;
---			pixel_gx3_next <= pixel_gx2_reg;
---			pixel_gx4_next <= pixel_gx3_reg;
---
---			by_sum := by1_reg+by2_reg+by3_reg+by4_reg;
---			pixel_bx1_next <= by_sum(17)&by_sum(15 downto 8);
---			pixel_bx2_next <= pixel_bx1_reg;
---			pixel_bx3_next <= pixel_bx2_reg;
---			pixel_bx4_next <= pixel_bx3_reg;
-			
-		   ry_sum := ry1_reg+ry2_reg+ry3_reg+ry4_reg;			
-			pixel_rx4_next <= ry_sum(17)&ry_sum(15 downto 8); 
-			pixel_rx3_next <= pixel_rx4_reg;
-			pixel_rx2_next <= pixel_rx3_reg;
-			pixel_rx1_next <= pixel_rx2_reg;
-
-			gy_sum := gy1_reg+gy2_reg+gy3_reg+gy4_reg;
-			pixel_gx4_next <= gy_sum(17)&gy_sum(15 downto 8);
-			pixel_gx3_next <= pixel_gx4_reg;
-			pixel_gx2_next <= pixel_gx3_reg;
-			pixel_gx1_next <= pixel_gx2_reg;
-
-			by_sum := by1_reg+by2_reg+by3_reg+by4_reg;
-			pixel_bx4_next <= by_sum(17)&by_sum(15 downto 8);
-			pixel_bx3_next <= pixel_bx4_reg;
-			pixel_bx2_next <= pixel_bx3_reg;
-			pixel_bx1_next <= pixel_bx2_reg;			
-		end if;
-	end process;
-	
-	coefx4_next <= coefx3_reg;	
-
---      X mult - pipeline stage 5
-	process(
-		pixel_rx1_reg,pixel_rx2_reg,pixel_rx3_reg,pixel_rx4_reg,
-		pixel_gx1_reg,pixel_gx2_reg,pixel_gx3_reg,pixel_gx4_reg,
-		pixel_bx1_reg,pixel_bx2_reg,pixel_bx3_reg,pixel_bx4_reg,
-	       	coefx4_reg)
-	begin
-		-- dsp blocks 9x9 multipliers
-		-- 3 per block -> 4 blocks
-		rx1_next <= pixel_rx1_reg*coefx4_reg.c1;
-		rx2_next <= pixel_rx2_reg*coefx4_reg.c2;
-		rx3_next <= pixel_rx3_reg*coefx4_reg.c3;
-		rx4_next <= pixel_rx4_reg*coefx4_reg.c4;
-
-		gx1_next <= pixel_gx1_reg*coefx4_reg.c1;
-		gx2_next <= pixel_gx2_reg*coefx4_reg.c2;
-		gx3_next <= pixel_gx3_reg*coefx4_reg.c3;
-		gx4_next <= pixel_gx4_reg*coefx4_reg.c4;
-
-		bx1_next <= pixel_bx1_reg*coefx4_reg.c1;
-		bx2_next <= pixel_bx2_reg*coefx4_reg.c2;
-		bx3_next <= pixel_bx3_reg*coefx4_reg.c3;
-		bx4_next <= pixel_bx4_reg*coefx4_reg.c4;
-	end process;
-
-
---      Pixel scaling computation - pipeline stage 6
-	-- Compute output
-	-- (p1*A1 + p2*A2 + p3*A3 + p4*A4)/65536
-	process(
-		rx1_reg,rx2_reg,rx3_reg,rx4_reg,
-		gx1_reg,gx2_reg,gx3_reg,gx4_reg,
-		bx1_reg,bx2_reg,bx3_reg,bx4_reg)
-		variable sum_r : signed(17 downto 0);
-		variable sum_g : signed(17 downto 0);
-		variable sum_b : signed(17 downto 0);
-	begin
-		sum_r := (rx1_reg+rx2_reg)+(rx3_reg+rx4_reg);
-		sum_g := (gx1_reg+gx2_reg)+(gx3_reg+gx4_reg);
-		sum_b := (bx1_reg+bx2_reg)+(bx3_reg+bx4_reg);
-
-		if (sum_r(17)='1') then
-			sum_r := (others=>'0');
-		elsif (sum_r(15) or sum_r(14))='1' then
-			sum_r := to_signed(16383,18);
-		end if;
-		if (sum_g(17)='1') then
-			sum_g := (others=>'0');
-		elsif (sum_g(15) or sum_g(14))='1' then
-			sum_g := to_signed(16383,18);
-		end if;
-		if (sum_b(17)='1') then
-			sum_b := (others=>'0');
-		elsif (sum_b(15) or sum_b(14))='1' then
-			sum_b := to_signed(16383,18);
-		end if;
-		r_next <= std_logic_vector(sum_r(13 downto 6));
-		g_next <= std_logic_vector(sum_g(13 downto 6));
-		b_next <= std_logic_vector(sum_b(13 downto 6));
-	end process;
-
-	-- outputnext_x_size
-	r<=r_reg;
-	g<=g_reg;
-	b<=b_reg;
-	hsync<=hsync_reg(6); -- TODO: why 6 and not 5?
-	vsync<=vsync_reg(6);
-	blank<=blank_reg(6); 
-	
-	next_x_size <= std_logic_vector(param_xaddrskip_reg);
-
-END vhdl;
-
---              h_pixels_across  <= 720 - 1;
---              h_sync_on <= 732 - 1;
---              h_sync_off <= 795 - 1;
---              h_end_count <= 864 - 1;
---              v_pixels_down <= 576 - 1;
---              v_sync_on <=  581 - 1;
---              v_sync_off <= 586 - 1;
---              v_end_count <=  625 - 1;
-
---                --PAL
---                h_pixels_across  <= 1280 - 1;
---                h_sync_on <= 1720 - 1;
---                h_sync_off <= 1760 - 1;
---                h_end_count <= 1980 - 1;
---                v_pixels_down <= 720 - 1;
---                v_sync_on <=  725 - 1;
---                v_sync_off <= 730 - 1;
---                v_end_count <=  750 - 1;
-
-
-
Index: eclaireXL_ITX/pll_hdmi.cmp
===================================================================
--- eclaireXL_ITX/pll_hdmi.cmp	(revision 973)
+++ eclaireXL_ITX/pll_hdmi.cmp	(revision 974)
@@ -3,7 +3,6 @@
 			refclk   : in  std_logic := 'X'; -- clk
 			rst      : in  std_logic := 'X'; -- reset
 			outclk_0 : out std_logic;        -- clk
-			outclk_1 : out std_logic;        -- clk
 			locked   : out std_logic         -- export
 		);
 	end component pll_hdmi;
Index: eclaireXL_ITX/pll_hdmi.qip
===================================================================
--- eclaireXL_ITX/pll_hdmi.qip	(revision 973)
+++ eclaireXL_ITX/pll_hdmi.qip	(revision 974)
@@ -1,5 +1,5 @@
 set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
-set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "16.1"
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_VERSION "18.0"
 set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"
 set_global_assignment -library "pll_hdmi" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi.cmp"]
 set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
@@ -7,26 +7,26 @@
 set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_QSYS_MODE "UNKNOWN"
 set_global_assignment -name SYNTHESIS_ONLY_QIP ON
 set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_NAME "cGxsX2hkbWk="
-set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
 set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
-set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTYuMQ=="
-set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTguMA=="
+set_global_assignment -entity "pll_hdmi" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_NAME "cGxsX2hkbWlfMDAwMg=="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTYuMQ=="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_VERSION "MTguMA=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTQuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTQuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
@@ -35,17 +35,17 @@
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw=="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MjcuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTQ4LjU=::RGVzaXJlZCBGcmVxdWVuY3k="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::NTQ=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MzM=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTAw::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTI=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
@@ -55,9 +55,9 @@
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTM1LjA=::RGVzaXJlZCBGcmVxdWVuY3k="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::NTQ=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::NTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MjA=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MjI=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
@@ -65,11 +65,11 @@
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::NzQuMjU=::RGVzaXJlZCBGcmVxdWVuY3k="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::NTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::NDA=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
@@ -77,11 +77,11 @@
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MzcxLjI1::RGVzaXJlZCBGcmVxdWVuY3k="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::NTU=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::OA==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
@@ -256,10 +256,10 @@
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MjcuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTQ4LjUwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTM1LjAwMDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
@@ -310,7 +310,7 @@
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T2Zm::UExMIEF1dG8gUmVzZXQ="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
@@ -317,8 +317,8 @@
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MjcsMjcsMywyLGZhbHNlLGZhbHNlLGZhbHNlLHRydWUsMTAsMTAsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMiwyLDEsMCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDIsMjAsMTAwMDAsNTQwLjAgTUh6LDEsZ2NsayxnbGIsZmJfMSxwaF9tdXhfY2xrLGZhbHNl::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MTcsMTYsMiwyLGZhbHNlLGZhbHNlLHRydWUsZmFsc2UsMiwxLDEsMCxwaF9tdXhfY2xrLGZhbHNlLHRydWUsMiwyMCw2MDAwLDQ0NS41IE1IeiwxLGdjbGssZ2xiLGZiXzEscGhfbXV4X2Nsayx0cnVl::UGFyYW1ldGVyIFZhbHVlcw=="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
@@ -333,5 +333,5 @@
 set_global_assignment -library "pll_hdmi" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi/pll_hdmi_0002.qip"]
 
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_NAME "altera_pll"
-set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "16.1"
+set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_VERSION "18.0"
 set_global_assignment -entity "pll_hdmi_0002" -library "pll_hdmi" -name IP_TOOL_ENV "mwpim"
Index: eclaireXL_ITX/pll_hdmi.vhd
===================================================================
--- eclaireXL_ITX/pll_hdmi.vhd	(revision 973)
+++ eclaireXL_ITX/pll_hdmi.vhd	(revision 974)
@@ -1,8 +1,8 @@
--- megafunction wizard: %Altera PLL v16.1%
+-- megafunction wizard: %PLL Intel FPGA IP v18.0%
 -- GENERATION: XML
 -- pll_hdmi.vhd
 
--- Generated using ACDS version 16.1 196
+-- Generated using ACDS version 18.0 614
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -13,7 +13,6 @@
 		refclk   : in  std_logic := '0'; --  refclk.clk
 		rst      : in  std_logic := '0'; --   reset.reset
 		outclk_0 : out std_logic;        -- outclk0.clk
-		outclk_1 : out std_logic;        -- outclk1.clk
 		locked   : out std_logic         --  locked.export
 	);
 end entity pll_hdmi;
@@ -24,7 +23,6 @@
 			refclk   : in  std_logic := 'X'; -- clk
 			rst      : in  std_logic := 'X'; -- reset
 			outclk_0 : out std_logic;        -- clk
-			outclk_1 : out std_logic;        -- clk
 			locked   : out std_logic         -- export
 		);
 	end component pll_hdmi_0002;
@@ -36,7 +34,6 @@
 			refclk   => refclk,   --  refclk.clk
 			rst      => rst,      --   reset.reset
 			outclk_0 => outclk_0, -- outclk0.clk
-			outclk_1 => outclk_1, -- outclk1.clk
 			locked   => locked    --  locked.export
 		);
 
@@ -47,7 +44,7 @@
 --	************************************************************
 --	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --	************************************************************
---	Copyright (C) 1991-2016 Altera Corporation
+--	Copyright (C) 1991-2020 Altera Corporation
 --	Any megafunction design, and related net list (encrypted or decrypted),
 --	support information, device programming or simulation file, and any other
 --	associated documentation or information provided by Altera or a partner
@@ -67,7 +64,7 @@
 --	their respective licensors.  No other licenses, including any licenses
 --	needed under any third party's intellectual property, are provided herein.
 ---->
--- Retrieval info: <instance entity-name="altera_pll" version="16.1" >
+-- Retrieval info: <instance entity-name="altera_pll" version="18.0" >
 -- Retrieval info: 	<generic name="debug_print_output" value="false" />
 -- Retrieval info: 	<generic name="debug_use_rbc_taf_method" value="false" />
 -- Retrieval info: 	<generic name="device_family" value="Cyclone V" />
@@ -74,7 +71,7 @@
 -- Retrieval info: 	<generic name="device" value="5CEBA2F17A7" />
 -- Retrieval info: 	<generic name="gui_device_speed_grade" value="2" />
 -- Retrieval info: 	<generic name="gui_pll_mode" value="Integer-N PLL" />
--- Retrieval info: 	<generic name="gui_reference_clock_frequency" value="50.0" />
+-- Retrieval info: 	<generic name="gui_reference_clock_frequency" value="54.0" />
 -- Retrieval info: 	<generic name="gui_channel_spacing" value="0.0" />
 -- Retrieval info: 	<generic name="gui_operation_mode" value="normal" />
 -- Retrieval info: 	<generic name="gui_feedback_clock" value="Global Clock" />
@@ -82,12 +79,12 @@
 -- Retrieval info: 	<generic name="gui_dsm_out_sel" value="1st_order" />
 -- Retrieval info: 	<generic name="gui_use_locked" value="true" />
 -- Retrieval info: 	<generic name="gui_en_adv_params" value="false" />
--- Retrieval info: 	<generic name="gui_number_of_clocks" value="2" />
+-- Retrieval info: 	<generic name="gui_number_of_clocks" value="1" />
 -- Retrieval info: 	<generic name="gui_multiply_factor" value="1" />
 -- Retrieval info: 	<generic name="gui_frac_multiply_factor" value="1" />
 -- Retrieval info: 	<generic name="gui_divide_factor_n" value="1" />
 -- Retrieval info: 	<generic name="gui_cascade_counter0" value="false" />
--- Retrieval info: 	<generic name="gui_output_clock_frequency0" value="27.0" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency0" value="148.5" />
 -- Retrieval info: 	<generic name="gui_divide_factor_c0" value="1" />
 -- Retrieval info: 	<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
 -- Retrieval info: 	<generic name="gui_ps_units0" value="ps" />
@@ -105,7 +102,7 @@
 -- Retrieval info: 	<generic name="gui_actual_phase_shift1" value="0" />
 -- Retrieval info: 	<generic name="gui_duty_cycle1" value="50" />
 -- Retrieval info: 	<generic name="gui_cascade_counter2" value="false" />
--- Retrieval info: 	<generic name="gui_output_clock_frequency2" value="100.0" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency2" value="74.25" />
 -- Retrieval info: 	<generic name="gui_divide_factor_c2" value="1" />
 -- Retrieval info: 	<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
 -- Retrieval info: 	<generic name="gui_ps_units2" value="ps" />
@@ -114,7 +111,7 @@
 -- Retrieval info: 	<generic name="gui_actual_phase_shift2" value="0" />
 -- Retrieval info: 	<generic name="gui_duty_cycle2" value="50" />
 -- Retrieval info: 	<generic name="gui_cascade_counter3" value="false" />
--- Retrieval info: 	<generic name="gui_output_clock_frequency3" value="100.0" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency3" value="371.25" />
 -- Retrieval info: 	<generic name="gui_divide_factor_c3" value="1" />
 -- Retrieval info: 	<generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
 -- Retrieval info: 	<generic name="gui_ps_units3" value="ps" />
@@ -248,7 +245,7 @@
 -- Retrieval info: 	<generic name="gui_phase_shift_deg17" value="0.0" />
 -- Retrieval info: 	<generic name="gui_actual_phase_shift17" value="0" />
 -- Retrieval info: 	<generic name="gui_duty_cycle17" value="50" />
--- Retrieval info: 	<generic name="gui_pll_auto_reset" value="Off" />
+-- Retrieval info: 	<generic name="gui_pll_auto_reset" value="On" />
 -- Retrieval info: 	<generic name="gui_pll_bandwidth_preset" value="Auto" />
 -- Retrieval info: 	<generic name="gui_en_reconf" value="false" />
 -- Retrieval info: 	<generic name="gui_en_dps_ports" value="false" />
@@ -260,8 +257,8 @@
 -- Retrieval info: 	<generic name="gui_dps_num" value="1" />
 -- Retrieval info: 	<generic name="gui_dps_dir" value="Positive" />
 -- Retrieval info: 	<generic name="gui_refclk_switch" value="false" />
--- Retrieval info: 	<generic name="gui_refclk1_frequency" value="100.0" />
--- Retrieval info: 	<generic name="gui_switchover_mode" value="Automatic Switchover" />
+-- Retrieval info: 	<generic name="gui_refclk1_frequency" value="74.25" />
+-- Retrieval info: 	<generic name="gui_switchover_mode" value="Manual Switchover" />
 -- Retrieval info: 	<generic name="gui_switchover_delay" value="0" />
 -- Retrieval info: 	<generic name="gui_active_clk" value="false" />
 -- Retrieval info: 	<generic name="gui_clk_bad" value="false" />
Index: eclaireXL_ITX/pll_hdmi2/pll_hdmi2_0002.v
===================================================================
--- eclaireXL_ITX/pll_hdmi2/pll_hdmi2_0002.v	(nonexistent)
+++ eclaireXL_ITX/pll_hdmi2/pll_hdmi2_0002.v	(revision 974)
@@ -0,0 +1,90 @@
+`timescale 1ns/10ps
+module  pll_hdmi2_0002(
+
+	// interface 'refclk'
+	input wire refclk,
+
+	// interface 'reset'
+	input wire rst,
+
+	// interface 'outclk0'
+	output wire outclk_0,
+
+	// interface 'outclk1'
+	output wire outclk_1,
+
+	// interface 'locked'
+	output wire locked
+);
+
+	altera_pll #(
+		.fractional_vco_multiplier("false"),
+		.reference_clock_frequency("148.5 MHz"),
+		.operation_mode("direct"),
+		.number_of_clocks(2),
+		.output_clock_frequency0("74.250000 MHz"),
+		.phase_shift0("0 ps"),
+		.duty_cycle0(50),
+		.output_clock_frequency1("371.250000 MHz"),
+		.phase_shift1("0 ps"),
+		.duty_cycle1(50),
+		.output_clock_frequency2("0 MHz"),
+		.phase_shift2("0 ps"),
+		.duty_cycle2(50),
+		.output_clock_frequency3("0 MHz"),
+		.phase_shift3("0 ps"),
+		.duty_cycle3(50),
+		.output_clock_frequency4("0 MHz"),
+		.phase_shift4("0 ps"),
+		.duty_cycle4(50),
+		.output_clock_frequency5("0 MHz"),
+		.phase_shift5("0 ps"),
+		.duty_cycle5(50),
+		.output_clock_frequency6("0 MHz"),
+		.phase_shift6("0 ps"),
+		.duty_cycle6(50),
+		.output_clock_frequency7("0 MHz"),
+		.phase_shift7("0 ps"),
+		.duty_cycle7(50),
+		.output_clock_frequency8("0 MHz"),
+		.phase_shift8("0 ps"),
+		.duty_cycle8(50),
+		.output_clock_frequency9("0 MHz"),
+		.phase_shift9("0 ps"),
+		.duty_cycle9(50),
+		.output_clock_frequency10("0 MHz"),
+		.phase_shift10("0 ps"),
+		.duty_cycle10(50),
+		.output_clock_frequency11("0 MHz"),
+		.phase_shift11("0 ps"),
+		.duty_cycle11(50),
+		.output_clock_frequency12("0 MHz"),
+		.phase_shift12("0 ps"),
+		.duty_cycle12(50),
+		.output_clock_frequency13("0 MHz"),
+		.phase_shift13("0 ps"),
+		.duty_cycle13(50),
+		.output_clock_frequency14("0 MHz"),
+		.phase_shift14("0 ps"),
+		.duty_cycle14(50),
+		.output_clock_frequency15("0 MHz"),
+		.phase_shift15("0 ps"),
+		.duty_cycle15(50),
+		.output_clock_frequency16("0 MHz"),
+		.phase_shift16("0 ps"),
+		.duty_cycle16(50),
+		.output_clock_frequency17("0 MHz"),
+		.phase_shift17("0 ps"),
+		.duty_cycle17(50),
+		.pll_type("General"),
+		.pll_subtype("General")
+	) altera_pll_i (
+		.rst	(rst),
+		.outclk	({outclk_1, outclk_0}),
+		.locked	(locked),
+		.fboutclk	( ),
+		.fbclk	(1'b0),
+		.refclk	(refclk)
+	);
+endmodule
+
Index: eclaireXL_ITX/pll_hdmi2.cmp
===================================================================
--- eclaireXL_ITX/pll_hdmi2.cmp	(nonexistent)
+++ eclaireXL_ITX/pll_hdmi2.cmp	(revision 974)
@@ -0,0 +1,10 @@
+	component pll_hdmi2 is
+		port (
+			refclk   : in  std_logic := 'X'; -- clk
+			rst      : in  std_logic := 'X'; -- reset
+			outclk_0 : out std_logic;        -- clk
+			outclk_1 : out std_logic;        -- clk
+			locked   : out std_logic         -- export
+		);
+	end component pll_hdmi2;
+
Index: eclaireXL_ITX/pll_hdmi2.sip
===================================================================
--- eclaireXL_ITX/pll_hdmi2.sip	(nonexistent)
+++ eclaireXL_ITX/pll_hdmi2.sip	(revision 974)
@@ -0,0 +1,6 @@
+set_global_assignment -entity "pll_hdmi2" -library "lib_pll_hdmi2" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_hdmi2" -library "lib_pll_hdmi2" -name IP_TOOL_VERSION "18.0"
+set_global_assignment -entity "pll_hdmi2" -library "lib_pll_hdmi2" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "lib_pll_hdmi2" -name SPD_FILE [file join $::quartus(sip_path) "pll_hdmi2.spd"]
+
+set_global_assignment -library "lib_pll_hdmi2" -name MISC_FILE [file join $::quartus(sip_path) "pll_hdmi2_sim/pll_hdmi2.vho"]
Index: eclaireXL_ITX/pll_hdmi2_sim/aldec/rivierapro_setup.tcl
===================================================================
--- eclaireXL_ITX/pll_hdmi2_sim/aldec/rivierapro_setup.tcl	(nonexistent)
+++ eclaireXL_ITX/pll_hdmi2_sim/aldec/rivierapro_setup.tcl	(revision 974)
@@ -0,0 +1,279 @@
+
+# (C) 2001-2020 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 18.0 614 linux 2020.02.02.21:28:40
+# ----------------------------------------
+# Auto-generated simulation script rivierapro_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     pll_hdmi2
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "aldec.do", and modify the text as directed.
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog -sv2k5 <your compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If pll_hdmi2 is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] { 
+  set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
+  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] { 
+  set TOP_LEVEL_NAME "pll_hdmi2"
+}
+
+if ![info exists QSYS_SIMDIR] { 
+  set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] { 
+  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/18.0/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
+  set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
+  set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+set Aldec "Riviera"
+if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
+  set Aldec "Active"
+}
+
+if { [ string match "Active" $Aldec ] } {
+  scripterconf -tcl
+  createdesign "$TOP_LEVEL_NAME"  "."
+  opendesign "$TOP_LEVEL_NAME"
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+  echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib      ./libraries     
+ensure_lib      ./libraries/work
+vmap       work ./libraries/work
+ensure_lib              ./libraries/altera      
+vmap       altera       ./libraries/altera      
+ensure_lib              ./libraries/lpm         
+vmap       lpm          ./libraries/lpm         
+ensure_lib              ./libraries/sgate       
+vmap       sgate        ./libraries/sgate       
+ensure_lib              ./libraries/altera_mf   
+vmap       altera_mf    ./libraries/altera_mf   
+ensure_lib              ./libraries/altera_lnsim
+vmap       altera_lnsim ./libraries/altera_lnsim
+ensure_lib              ./libraries/cyclonev    
+vmap       cyclonev     ./libraries/cyclonev    
+
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+  echo "\[exec\] dev_com"
+  eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v"    -work cyclonev    
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+  echo "\[exec\] com"
+  eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_hdmi2.vho"
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+  echo "\[exec\] elab"
+  eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -dbg -O2 option
+alias elab_debug {
+  echo "\[exec\] elab_debug"
+  eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+  dev_com
+  com
+  elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -dbg -O2
+alias ld_debug "
+  dev_com
+  com
+  elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+  echo "List Of Command Line Aliases"
+  echo
+  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
+  echo
+  echo "dev_com                                           -- Compile device library files"
+  echo
+  echo "com                                               -- Compile the design files in correct order"
+  echo
+  echo "elab                                              -- Elaborate top level design"
+  echo
+  echo "elab_debug                                        -- Elaborate the top level design with -dbg -O2 option"
+  echo
+  echo "ld                                                -- Compile all the design files and elaborate the top level design"
+  echo
+  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -dbg -O2"
+  echo
+  echo 
+  echo
+  echo "List Of Variables"
+  echo
+  echo "TOP_LEVEL_NAME                                    -- Top level module name."
+  echo "                                                     For most designs, this should be overridden"
+  echo "                                                     to enable the elab/elab_debug aliases."
+  echo
+  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
+  echo
+  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
+  echo
+  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
+  echo
+  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo
+  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h
Index: eclaireXL_ITX/pll_hdmi2.ppf
===================================================================
--- eclaireXL_ITX/pll_hdmi2.ppf	(nonexistent)
+++ eclaireXL_ITX/pll_hdmi2.ppf	(revision 974)
@@ -0,0 +1,14 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<pinplan
+ variation_name="pll_hdmi2"
+ megafunction_name="ALTERA_PLL"
+ intended_family="Cyclone V"
+ specifies="all_ports">
+ <global>
+  <pin name="refclk" direction="input" scope="external" />
+  <pin name="rst" direction="input" scope="external" />
+  <pin name="outclk_0" direction="output" scope="external" />
+  <pin name="outclk_1" direction="output" scope="external" />
+  <pin name="locked" direction="output" scope="external" />
+ </global>
+</pinplan>
Index: eclaireXL_ITX/pll_hdmi2.spd
===================================================================
--- eclaireXL_ITX/pll_hdmi2.spd	(nonexistent)
+++ eclaireXL_ITX/pll_hdmi2.spd	(revision 974)
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<simPackage>
+ <file path="pll_hdmi2_sim/pll_hdmi2.vho" type="VHDL" />
+ <topLevel name="pll_hdmi2" />
+ <deviceFamily name="cyclonev" />
+</simPackage>
Index: eclaireXL_ITX/atari800core_eclaireXLv2.vhd
===================================================================
--- eclaireXL_ITX/atari800core_eclaireXLv2.vhd	(revision 973)
+++ eclaireXL_ITX/atari800core_eclaireXLv2.vhd	(revision 974)
@@ -22,7 +22,9 @@
 		-- For initial port may help to have no
 		internal_rom : integer := 1;  -- if 0 expects it in sdram,is 1:16k os+basic, is 2:... TODO
 		internal_ram : integer := 16384;  -- at start of memory map
-		sid : integer := 0
+		sid : integer := 0;
+		enable_area_scaler : integer := 1;
+		enable_polyphasic_scaler : integer := 0
 	);
 	PORT
 	(
@@ -152,7 +154,17 @@
 	);
 end component;
 
-component pll_hdmi
+component pll_hdmi is
+  port (
+			 refclk    : in  std_logic := '0'; --    refclk.clk
+			 rst       : in  std_logic := '0'; --     reset.reset
+			 outclk_0  : out std_logic;        --   outclk0.clk
+			 locked    : out std_logic        --    locked.export
+  );
+end component;
+
+
+component pll_hdmi2
 	port (
 		refclk   : in  std_logic := '0'; --  refclk.clk
 		rst      : in  std_logic := '0'; --   reset.reset
@@ -199,16 +211,15 @@
 	);
 end component;
 
-component ddioclkctrl is
-	port (
-		inclk3x   : in  std_logic                    := '0';             --  altclkctrl_input.inclk3x
-		inclk2x   : in  std_logic                    := '0';             --                  .inclk2x
-		inclk1x   : in  std_logic                    := '0';             --                  .inclk1x
-		inclk0x   : in  std_logic                    := '0';             --                  .inclk0x
-		clkselect : in  std_logic_vector(1 downto 0) := (others => '0'); --                  .clkselect
-		ena       : in  std_logic                    := '0';             --                  .ena
-		outclk    : out std_logic                                        -- altclkctrl_output.outclk
-	);
+component clkctrl2 is
+  port (
+		inclk3x   : in  std_logic                    := 'X';             -- inclk3x
+		inclk2x   : in  std_logic                    := 'X';             -- inclk2x
+		inclk1x   : in  std_logic                    := 'X';             -- inclk1x
+		inclk0x   : in  std_logic                    := 'X';             -- inclk0x
+		clkselect : in  std_logic_vector(1 downto 0) := (others => 'X'); -- clkselect
+		outclk    : out std_logic                                        -- outclk
+  );
 end component;
 
 component pll_usb is
@@ -249,7 +260,8 @@
 
 
 	-- SYSTEM
-	SIGNAL GCLOCK_50 : STD_LOGIC; -- Only 2 fplls can use the pin!
+	SIGNAL GCLOCK_54 : STD_LOGIC; -- Only 2 fplls can use the pin!
+	SIGNAL GCLOCK_148_5 : STD_LOGIC; -- Only 2 fplls can use the pin!
 	SIGNAL CLK : STD_LOGIC;
 	SIGNAL CLK_1x : STD_LOGIC;
 	SIGNAL CLK_114 : STD_LOGIC;
@@ -260,6 +272,13 @@
 
  	SIGNAL CLK_PIXEL_IN : STD_LOGIC;
  	SIGNAL CLK_HDMI_IN : STD_LOGIC;
+	
+	signal CLK_PIXEL_SWITCH : STD_LOGIC;
+ 	--SIGNAL CLK_7425_PIXEL_IN : STD_LOGIC;
+ 	--SIGNAL CLK_7425_HDMI_IN : STD_LOGIC;
+ 	--SIGNAL CLK_27_PIXEL_IN : STD_LOGIC;
+ 	--SIGNAL CLK_27_HDMI_IN : STD_LOGIC;
+	signal clk_hdmi_select : std_logic_vector(2 downto 0);
 
 	SIGNAL CLK_raw : STD_LOGIC;
 	SIGNAL CLK_1x_raw : STD_LOGIC;
@@ -500,6 +519,8 @@
 	signal pll_acore_locked : std_logic;
 
 	signal pll_hdmi_locked : std_logic;
+	signal pll_hdmi1_locked : std_logic;
+	signal pll_hdmi2_locked : std_logic;	
 
 	signal pll_pause_counter_reg : std_logic_vector(25 downto 0);
 	signal pll_pause_counter_next : std_logic_vector(25 downto 0);
@@ -866,7 +887,7 @@
 	outclk => CLK_114
 );
 
-clkctrl2: clkctrl 
+clkctrl2i: clkctrl 
 port map (
 	inclk  => DRAM_CLK_raw,
 	ena    => pll_enable_reg,
@@ -976,11 +997,63 @@
 );
 
 pll_hdmi_inst : pll_hdmi
-PORT MAP(refclk => GCLOCK_50,
-		 outclk_0 => CLK_PIXEL_IN, -- 27MHz 
-		 outclk_1 => CLK_HDMI_IN,  -- 5*27MHz
-		 locked => PLL_HDMI_LOCKED);
+PORT MAP(refclk => GCLOCK_54,
+		 outclk_0 => GCLOCK_148_5,
+		 locked => open);
+		 
+		 
 
+    u0 : clkctrl2
+        port map (
+            inclk3x   => GCLOCK_54,   --  altclkctrl_input.inclk3x
+            inclk2x   => GCLOCK_148_5,   --                  .inclk2x
+--            inclk1x   => CLOCK_50,   --                  .inclk1x < builds/works
+--            inclk0x   => CLOCK_50,   --                  .inclk0x
+--            inclk1x   => CLKGEN_CLK2,   --                  .inclk1x < fails to build
+--            inclk0x   => CLKGEN_CLK0,   --                  .inclk0x
+            inclk1x   => CLKGEN_CLK2,   --                  .inclk1x
+            inclk0x   => CLOCK_50,   --                  .inclk0x				
+            clkselect => clk_hdmi_select(1 downto 0), --                  .clkselect
+            outclk    => CLK_PIXEL_SWITCH     -- altclkctrl_output.outclk
+        );
+		  
+--CLK_HDMI_IN <= CLK_PIXEL_IN;
+
+		 
+		 
+pll_hdmi2_inst : pll_hdmi2
+PORT MAP(refclk => CLK_PIXEL_SWITCH,
+		 locked => PLL_HDMI_LOCKED,
+		 outclk_0 => CLK_PIXEL_IN,
+		 outclk_1 => CLK_HDMI_IN);
+		 
+--PLL_HDMI_LOCKED <= PLL_HDMI1_LOCKED and PLL_HDMI2_LOCKED;
+
+--CLK_PIXEL_IN <= CLK_7425_PIXEL_IN;
+--CLK_HDMI_IN <= CLK_7425_HDMI_IN;
+		 
+--clkctrl2_1: clkctrl2
+--port map (
+--	inclk0x => CLOCK_50,
+--	inclk1x => '0',
+--	  => CLK_7425_PIXEL_IN,
+--	inclk3x  => CLK_27_PIXEL_IN,
+--	clkselect    => '1'&clk_hdmi_select,
+--	ena => '1',
+--	outclk => CLK_PIXEL_IN
+--);
+--
+--clkctrl2_2: clkctrl2
+--port map (
+--	inclk0x => CLOCK_50,
+--	inclk1x => '0',
+--	inclk2x  => ,
+--	inclk3x  => CLK_27_HDMI_IN,	
+--	clkselect    => '1'&clk_hdmi_select,
+--	ena => '1',
+--	outclk => CLK_HDMI_IN
+--);
+--		 
 --end generate;
 
 
@@ -1005,7 +1078,7 @@
 pllusbinstance : pll_usb
 PORT MAP(refclk => CLOCK_50, 
 		 outclk_0 => CLK_USB,
-		 outclk_1 => GCLOCK_50,
+		 outclk_1 => GCLOCK_54,
 		 locked => open);
 
 
@@ -1237,7 +1310,7 @@
 		CLK => CLK,
 		RESET_N => RESET_N and sdram_reset_n,
 
-		-- dma bus master (with many waitstates...)
+		-- dma bus master (with manclk_hdmi_selecty waitstates...)
 		ZPU_ADDR_FETCH => dma_addr_fetch,
 		ZPU_DATA_OUT => dma_write_data,
 		ZPU_FETCH => dma_fetch,
@@ -1308,7 +1381,7 @@
 		i2c0_scl => clkgen_scl,
 
 		i2c1_sda => vid_sda,
-		i2c1_scl => vid_scl
+		i2c1_scl => vid_scl	
 	);
 
 	pause_atari <= zpu_out1(0);
@@ -1553,11 +1626,16 @@
 
 -- HDMI
 scandoubler_hdmi_int : work.scandoubler_hdmi
+GENERIC MAP
+(
+	enable_area_scaler => enable_area_scaler,
+	enable_polyphasic_scaler => enable_polyphasic_scaler
+)
 PORT MAP
 ( 
 	CLK_ATARI_IN => CLK,
 
-	RESET_N => RESET_N and SDRAM_RESET_N and not(reset_atari),
+	RESET_N => RESET_N,
 
 	audio_left => audio_l_pcm,
 	audio_right => audio_r_pcm,
@@ -1575,6 +1653,7 @@
 	--HDMI clock domain
 	CLK_HDMI_IN => clk_hdmi_in,
 	CLK_PIXEL_IN => clk_pixel_in,
+	CLK_HDMI_SELECT => clk_hdmi_select,
 
 	O_hsync => adj_hsync,
 	O_vsync => adj_vsync,
@@ -1585,7 +1664,11 @@
 
 	-- TO TV...
 	O_TMDS_H => tmds_h,
-	O_TMDS_L => tmds_l
+	O_TMDS_L => tmds_l,
+	
+	-- I2C
+	sda => clkgen_sda,
+	scl => clkgen_scl
 );
 
 END vhdl;
Index: eclaireXL_ITX/clkctrl.sopcinfo
===================================================================
--- eclaireXL_ITX/clkctrl.sopcinfo	(revision 973)
+++ eclaireXL_ITX/clkctrl.sopcinfo	(revision 974)
@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
 <EnsembleReport name="clkctrl" kind="clkctrl" version="1.0" fabric="QSYS">
- <!-- Format version 16.1 196 (Future versions may contain additional information.) -->
- <!-- 2016.12.27.22:17:25 -->
+ <!-- Format version 18.0 614 (Future versions may contain additional information.) -->
+ <!-- 2020.02.12.21:10:43 -->
  <!-- A collection of modules and connections -->
  <parameter name="AUTO_GENERATION_ID">
   <type>java.lang.Integer</type>
-  <value>1482877045</value>
+  <value>1581538243</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
@@ -32,7 +32,7 @@
  </parameter>
  <parameter name="AUTO_DEVICE">
   <type>java.lang.String</type>
-  <value>5CEBA2F23C8</value>
+  <value>5CEBA4F23C8</value>
   <derived>false</derived>
   <enabled>true</enabled>
   <visible>false</visible>
@@ -68,7 +68,7 @@
  <module
    name="altclkctrl_0"
    kind="altclkctrl"
-   version="16.1"
+   version="18.0"
    path="altclkctrl_0">
   <!-- Describes a single module. Module parameters are
 the requested settings for a module instance. -->
@@ -137,7 +137,7 @@
    <visible>true</visible>
    <valid>true</valid>
   </parameter>
-  <interface name="altclkctrl_input" kind="conduit_end" version="16.1">
+  <interface name="altclkctrl_input" kind="conduit_end" version="18.0">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -192,7 +192,7 @@
     <role>ena</role>
    </port>
   </interface>
-  <interface name="altclkctrl_output" kind="conduit_end" version="16.1">
+  <interface name="altclkctrl_output" kind="conduit_end" version="18.0">
    <!-- The connection points exposed by a module instance for the
 particular module parameters. Connection points and their
 parameters are a RESULT of the module parameters. -->
@@ -247,8 +247,8 @@
   <name>altclkctrl</name>
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IModule</subtype>
-  <displayName>ALTCLKCTRL</displayName>
-  <version>16.1</version>
+  <displayName>ALTCLKCTRL Intel FPGA IP</displayName>
+  <version>18.0</version>
  </plugin>
  <plugin>
   <instanceCount>2</instanceCount>
@@ -256,8 +256,8 @@
   <type>com.altera.entityinterfaces.IElementClass</type>
   <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
   <displayName>Conduit</displayName>
-  <version>16.1</version>
+  <version>18.0</version>
  </plugin>
- <reportVersion>16.1 196</reportVersion>
+ <reportVersion>18.0 614</reportVersion>
  <uniqueIdentifier></uniqueIdentifier>
 </EnsembleReport>
Index: eclaireXL_ITX/clkctrl2/clkctrl2.bsf
===================================================================
--- eclaireXL_ITX/clkctrl2/clkctrl2.bsf	(nonexistent)
+++ eclaireXL_ITX/clkctrl2/clkctrl2.bsf	(revision 974)
@@ -0,0 +1,91 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2018  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 288 168)
+	(text "clkctrl2" (rect 123 -1 150 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 152 20 164)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "inclk3x" (rect 0 0 25 12)(font "Arial" (font_size 8)))
+		(text "inclk3x" (rect 4 61 46 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 96 72)(line_width 1))
+	)
+	(port
+		(pt 0 88)
+		(input)
+		(text "inclk2x" (rect 0 0 25 12)(font "Arial" (font_size 8)))
+		(text "inclk2x" (rect 4 77 46 88)(font "Arial" (font_size 8)))
+		(line (pt 0 88)(pt 96 88)(line_width 1))
+	)
+	(port
+		(pt 0 104)
+		(input)
+		(text "inclk1x" (rect 0 0 24 12)(font "Arial" (font_size 8)))
+		(text "inclk1x" (rect 4 93 46 104)(font "Arial" (font_size 8)))
+		(line (pt 0 104)(pt 96 104)(line_width 1))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "inclk0x" (rect 0 0 25 12)(font "Arial" (font_size 8)))
+		(text "inclk0x" (rect 4 109 46 120)(font "Arial" (font_size 8)))
+		(line (pt 0 120)(pt 96 120)(line_width 1))
+	)
+	(port
+		(pt 0 136)
+		(input)
+		(text "clkselect[1..0]" (rect 0 0 51 12)(font "Arial" (font_size 8)))
+		(text "clkselect[1..0]" (rect 4 125 94 136)(font "Arial" (font_size 8)))
+		(line (pt 0 136)(pt 96 136)(line_width 3))
+	)
+	(port
+		(pt 288 72)
+		(output)
+		(text "outclk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
+		(text "outclk" (rect 258 61 294 72)(font "Arial" (font_size 8)))
+		(line (pt 288 72)(pt 176 72)(line_width 1))
+	)
+	(drawing
+		(text "altclkctrl_input" (rect 13 43 122 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "inclk3x" (rect 101 67 244 144)(font "Arial" (color 0 0 0)))
+		(text "inclk2x" (rect 101 83 244 176)(font "Arial" (color 0 0 0)))
+		(text "inclk1x" (rect 101 99 244 208)(font "Arial" (color 0 0 0)))
+		(text "inclk0x" (rect 101 115 244 240)(font "Arial" (color 0 0 0)))
+		(text "clkselect" (rect 101 131 256 272)(font "Arial" (color 0 0 0)))
+		(text "altclkctrl_output" (rect 177 43 456 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "outclk" (rect 148 67 332 144)(font "Arial" (color 0 0 0)))
+		(text " clkctrl2 " (rect 254 152 568 314)(font "Arial" ))
+		(line (pt 96 32)(pt 176 32)(line_width 1))
+		(line (pt 176 32)(pt 176 152)(line_width 1))
+		(line (pt 96 152)(pt 176 152)(line_width 1))
+		(line (pt 96 32)(pt 96 152)(line_width 1))
+		(line (pt 97 52)(pt 97 140)(line_width 1))
+		(line (pt 98 52)(pt 98 140)(line_width 1))
+		(line (pt 175 52)(pt 175 76)(line_width 1))
+		(line (pt 174 52)(pt 174 76)(line_width 1))
+		(line (pt 0 0)(pt 288 0)(line_width 1))
+		(line (pt 288 0)(pt 288 168)(line_width 1))
+		(line (pt 0 168)(pt 288 168)(line_width 1))
+		(line (pt 0 0)(pt 0 168)(line_width 1))
+	)
+)
Index: eclaireXL_ITX/clkctrl2/clkctrl2.cmp
===================================================================
--- eclaireXL_ITX/clkctrl2/clkctrl2.cmp	(nonexistent)
+++ eclaireXL_ITX/clkctrl2/clkctrl2.cmp	(revision 974)
@@ -0,0 +1,11 @@
+	component clkctrl2 is
+		port (
+			inclk3x   : in  std_logic                    := 'X';             -- inclk3x
+			inclk2x   : in  std_logic                    := 'X';             -- inclk2x
+			inclk1x   : in  std_logic                    := 'X';             -- inclk1x
+			inclk0x   : in  std_logic                    := 'X';             -- inclk0x
+			clkselect : in  std_logic_vector(1 downto 0) := (others => 'X'); -- clkselect
+			outclk    : out std_logic                                        -- outclk
+		);
+	end component clkctrl2;
+
Index: eclaireXL_ITX/clkctrl2/clkctrl2.html
===================================================================
--- eclaireXL_ITX/clkctrl2/clkctrl2.html	(nonexistent)
+++ eclaireXL_ITX/clkctrl2/clkctrl2.html	(revision 974)
@@ -0,0 +1,157 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
+
+<html xmlns="http://www.w3.org/1999/xhtml">
+ <head>
+  <title>datasheet for clkctrl2</title>
+  <style type="text/css">
+body { font-family:arial ;}
+a { text-decoration:underline ; color:#003000 ;}
+a:hover { text-decoration:underline ; color:0030f0 ;}
+td { padding : 5px ;}
+table.topTitle { width:100% ;}
+table.topTitle td.l { text-align:left ; font-weight: bold ; font-size:30px ;}
+table.topTitle td.r { text-align:right ; font-weight: bold ; font-size:16px ;}
+table.blueBar { width : 100% ; border-spacing : 0px ;}
+table.blueBar td { background:#0036ff ; font-size:12px ; color : white ; text-align : left ; font-weight : bold ;}
+table.blueBar td.l { text-align : left ;}
+table.blueBar td.r { text-align : right ;}
+table.items { width:100% ; border-collapse:collapse ;}
+table.items td.label { font-weight:bold ; font-size:16px ; vertical-align:top ;}
+table.items td.mono { font-family:courier ; font-size:12px ; white-space:pre ;}
+div.label { font-weight:bold ; font-size:16px ; vertical-align:top ; text-align:center ;}
+table.grid { border-collapse:collapse ;}
+table.grid td { border:1px solid #bbb ; font-size:12px ;}
+body { font-family:arial ;}
+table.x { font-family:courier ; border-collapse:collapse ; padding:2px ;}
+table.x td { border:1px solid #bbb ;}
+td.tableTitle { font-weight:bold ; text-align:center ;}
+table.grid { border-collapse:collapse ;}
+table.grid td { border:1px solid #bbb ;}
+table.grid td.tableTitle { font-weight:bold ; text-align:center ;}
+table.mmap { border-collapse:collapse ; text-size:11px ; border:1px solid #d8d8d8 ;}
+table.mmap td { border-color:#d8d8d8 ; border-width:1px ; border-style:solid ;}
+table.mmap td.empty { border-style:none ; background-color:#f0f0f0 ;}
+table.mmap td.slavemodule { text-align:left ; font-size:11px ; border-style:solid solid none solid ;}
+table.mmap td.slavem { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid none solid ;}
+table.mmap td.slaveb { text-align:right ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
+table.mmap td.mastermodule { text-align:center ; font-size:11px ; border-style:solid solid none solid ;}
+table.mmap td.masterlr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid solid ;}
+table.mmap td.masterl { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid solid ;}
+table.mmap td.masterm { text-align:center ; font-size:9px ; font-style:italic ; border-style:none none solid none ;}
+table.mmap td.masterr { text-align:center ; font-size:9px ; font-style:italic ; border-style:none solid solid none ;}
+table.mmap td.addr { font-family:courier ; font-size:9px ; text-align:right ;}
+table.connectionboxes { border-collapse:separate ; border-spacing:0px ; font-family:arial ;}
+table.connectionboxes td.from { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
+table.connectionboxes td.to { font-size:9px ; font-style:italic ; vertical-align:top ; text-align:right ;}
+table.connectionboxes td.lefthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:right ;}
+table.connectionboxes td.righthandwire { border-bottom:1px solid black ; font-size:9px ; font-style:italic ; vertical-align:bottom ; text-align:left ;}
+table.connectionboxes td.righthandlabel { font-size:11px ; vertical-align:bottom ; text-align:left ;}
+table.connectionboxes td.neighbor { padding:3px ; border:1px solid black ; font-size: 11px ; background:#e8e8e8 ; vertical-align:center ; text-align:center ;}
+table.connectionboxes td.main { padding:8px ; border:1px solid black ; font-size: 14px ; font-weight:bold ; background:#ffffff ; vertical-align:center ; text-align:center ;}
+.parametersbox { border:1px solid #d0d0d0 ; display:inline-block ; max-height:160px ; overflow:auto ; width:360px ; font-size:10px ;}
+.flowbox { display:inline-block ;}
+.parametersbox table { font-size:10px ;}
+td.parametername { font-style:italic ;}
+td.parametervalue { font-weight:bold ;}
+div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; border-top:1px solid #707070 ; border-bottom:1px solid #707070 ; padding:20px ; margin:20px ; width:auto ;}</style>
+ </head>
+ <body>
+  <table class="topTitle">
+   <tr>
+    <td class="l">clkctrl2</td>
+    <td class="r">
+     <br/>
+     <br/>
+    </td>
+   </tr>
+  </table>
+  <table class="blueBar">
+   <tr>
+    <td class="l">2020.02.02.21:08:21</td>
+    <td class="r">Datasheet</td>
+   </tr>
+  </table>
+  <div style="width:100% ;  height:10px"> </div>
+  <div class="label">Overview</div>
+  <div class="greydiv">
+   <div style="display:inline-block ; text-align:left">
+    <table class="connectionboxes">
+     <tr style="height:6px">
+      <td></td>
+     </tr>
+    </table>
+   </div><span style="display:inline-block ; width:28px"> </span>
+   <div style="display:inline-block ; text-align:left"><span>
+     <br/></span>
+   </div>
+  </div>
+  <div style="width:100% ;  height:10px"> </div>
+  <div class="label">Memory Map</div>
+  <table class="mmap">
+   <tr>
+    <td class="empty" rowspan="2"></td>
+   </tr>
+  </table>
+  <a name="module_altclkctrl_0"> </a>
+  <div>
+   <hr/>
+   <h2>altclkctrl_0</h2>altclkctrl v18.0
+   <br/>
+   <br/>
+   <br/>
+   <table class="flowbox">
+    <tr>
+     <td class="parametersbox">
+      <h2>Parameters</h2>
+      <table>
+       <tr>
+        <td class="parametername">DEVICE_FAMILY</td>
+        <td class="parametervalue">CYCLONEV</td>
+       </tr>
+       <tr>
+        <td class="parametername">CLOCK_TYPE</td>
+        <td class="parametervalue">0</td>
+       </tr>
+       <tr>
+        <td class="parametername">NUMBER_OF_CLOCKS</td>
+        <td class="parametervalue">4</td>
+       </tr>
+       <tr>
+        <td class="parametername">ENA_REGISTER_MODE</td>
+        <td class="parametervalue">1</td>
+       </tr>
+       <tr>
+        <td class="parametername">GUI_USE_ENA</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION</td>
+        <td class="parametervalue">false</td>
+       </tr>
+       <tr>
+        <td class="parametername">deviceFamily</td>
+        <td class="parametervalue">UNKNOWN</td>
+       </tr>
+       <tr>
+        <td class="parametername">generateLegacySim</td>
+        <td class="parametervalue">false</td>
+       </tr>
+      </table>
+     </td>
+    </tr>
+   </table>&#160;&#160;
+   <table class="flowbox">
+    <tr>
+     <td class="parametersbox">
+      <h2>Software Assignments</h2>(none)</td>
+    </tr>
+   </table>
+  </div>
+  <table class="blueBar">
+   <tr>
+    <td class="l">generation took 0.00 seconds</td>
+    <td class="r">rendering took 0.01 seconds</td>
+   </tr>
+  </table>
+ </body>
+</html>
Index: eclaireXL_ITX/clkctrl2/clkctrl2.ppf
===================================================================
--- eclaireXL_ITX/clkctrl2/clkctrl2.ppf	(nonexistent)
+++ eclaireXL_ITX/clkctrl2/clkctrl2.ppf	(revision 974)
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<pinplan
+ variation_name="altclkctrl_0"
+ megafunction_name="ALTCLKCTRL"
+ intended_family="Cyclone V"
+ specifies="all_ports">
+ <global>
+  <pin name="inclk3x" direction="input" scope="external" />
+  <pin name="inclk2x" direction="input" scope="external" />
+  <pin name="inclk1x" direction="input" scope="external" />
+  <pin name="inclk0x" direction="input" scope="external" />
+  <pin name="clkselect[1..0]" direction="input" scope="external" />
+  <pin name="outclk" direction="output" scope="external" />
+ </global>
+</pinplan>
Index: eclaireXL_ITX/clkctrl2/clkctrl2.xml
===================================================================
--- eclaireXL_ITX/clkctrl2/clkctrl2.xml	(nonexistent)
+++ eclaireXL_ITX/clkctrl2/clkctrl2.xml	(revision 974)
@@ -0,0 +1,136 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<deploy
+ date="2020.02.02.21:08:21"
+ outputDirectory="/home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2/">
+ <perimeter>
+  <parameter
+     name="AUTO_GENERATION_ID"
+     type="Integer"
+     defaultValue="0"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_UNIQUE_ID"
+     type="String"
+     defaultValue=""
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_FAMILY"
+     type="String"
+     defaultValue="Cyclone V"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE"
+     type="String"
+     defaultValue="5CEBA4F23C8"
+     onHdl="0"
+     affectsHdl="1" />
+  <parameter
+     name="AUTO_DEVICE_SPEEDGRADE"
+     type="String"
+     defaultValue="8"
+     onHdl="0"
+     affectsHdl="1" />
+  <interface name="altclkctrl_input" kind="conduit" start="0">
+   <property name="associatedClock" value="" />
+   <property name="associatedReset" value="" />
+   <port name="inclk3x" direction="input" role="inclk3x" width="1" />
+   <port name="inclk2x" direction="input" role="inclk2x" width="1" />
+   <port name="inclk1x" direction="input" role="inclk1x" width="1" />
+   <port name="inclk0x" direction="input" role="inclk0x" width="1" />
+   <port name="clkselect" direction="input" role="clkselect" width="2" />
+  </interface>
+  <interface name="altclkctrl_output" kind="conduit" start="0">
+   <property name="associatedClock" value="" />
+   <property name="associatedReset" value="" />
+   <port name="outclk" direction="output" role="outclk" width="1" />
+  </interface>
+ </perimeter>
+ <entity
+   path=""
+   parameterizationKey="clkctrl2:1.0:AUTO_DEVICE=5CEBA4F23C8,AUTO_DEVICE_FAMILY=Cyclone V,AUTO_DEVICE_SPEEDGRADE=8,AUTO_GENERATION_ID=1580674101,AUTO_UNIQUE_ID=(altclkctrl:18.0:CLOCK_TYPE=0,DEVICE_FAMILY=Cyclone V,ENA_REGISTER_MODE=1,GUI_USE_ENA=false,NUMBER_OF_CLOCKS=4,USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=false)"
+   instancePathKey="clkctrl2"
+   kind="clkctrl2"
+   version="1.0"
+   name="clkctrl2">
+  <parameter name="AUTO_GENERATION_ID" value="1580674101" />
+  <parameter name="AUTO_DEVICE" value="5CEBA4F23C8" />
+  <parameter name="AUTO_DEVICE_FAMILY" value="Cyclone V" />
+  <parameter name="AUTO_UNIQUE_ID" value="" />
+  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="8" />
+  <generatedFiles>
+   <file
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2/synthesis/clkctrl2.vhd"
+       type="VHDL" />
+  </generatedFiles>
+  <childGeneratedFiles>
+   <file
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2/synthesis/submodules/clkctrl2_altclkctrl_0.v"
+       type="VERILOG"
+       attributes="" />
+  </childGeneratedFiles>
+  <sourceFiles>
+   <file
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2.qsys" />
+  </sourceFiles>
+  <childSourceFiles>
+   <file
+       path="/home/markw/intelFPGA_lite/18.0/ip/altera/megafunctions/altclkctrl/altclkctrl_hw.tcl" />
+  </childSourceFiles>
+  <messages>
+   <message level="Debug" culprit="clkctrl2">queue size: 0 starting:clkctrl2 "clkctrl2"</message>
+   <message level="Progress" culprit="min"></message>
+   <message level="Progress" culprit="max"></message>
+   <message level="Progress" culprit="current"></message>
+   <message level="Debug">Transform: CustomInstructionTransform</message>
+   <message level="Debug">No custom instruction connections, skipping transform </message>
+   <message level="Debug" culprit="merlin_custom_instruction_transform"><![CDATA[After transform: <b>1</b> modules, <b>0</b> connections]]></message>
+   <message level="Debug">Transform: MMTransform</message>
+   <message level="Debug">Transform: InterruptMapperTransform</message>
+   <message level="Debug">Transform: InterruptSyncTransform</message>
+   <message level="Debug">Transform: InterruptFanoutTransform</message>
+   <message level="Debug">Transform: AvalonStreamingTransform</message>
+   <message level="Debug">Transform: ResetAdaptation</message>
+   <message level="Debug" culprit="clkctrl2"><![CDATA["<b>clkctrl2</b>" reuses <b>altclkctrl</b> "<b>submodules/clkctrl2_altclkctrl_0</b>"]]></message>
+   <message level="Debug" culprit="clkctrl2">queue size: 0 starting:altclkctrl "submodules/clkctrl2_altclkctrl_0"</message>
+   <message level="Info" culprit="altclkctrl_0">Generating top-level entity clkctrl2_altclkctrl_0.</message>
+   <message level="Debug" culprit="altclkctrl_0">Current quartus bindir: /home/markw/intelFPGA_lite/18.0/quartus/linux64/.</message>
+   <message level="Info" culprit="altclkctrl_0"><![CDATA["<b>clkctrl2</b>" instantiated <b>altclkctrl</b> "<b>altclkctrl_0</b>"]]></message>
+  </messages>
+ </entity>
+ <entity
+   path="submodules/"
+   parameterizationKey="altclkctrl:18.0:CLOCK_TYPE=0,DEVICE_FAMILY=Cyclone V,ENA_REGISTER_MODE=1,GUI_USE_ENA=false,NUMBER_OF_CLOCKS=4,USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION=false"
+   instancePathKey="clkctrl2:.:altclkctrl_0"
+   kind="altclkctrl"
+   version="18.0"
+   name="clkctrl2_altclkctrl_0">
+  <parameter name="NUMBER_OF_CLOCKS" value="4" />
+  <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
+  <parameter name="GUI_USE_ENA" value="false" />
+  <parameter name="DEVICE_FAMILY" value="Cyclone V" />
+  <parameter name="ENA_REGISTER_MODE" value="1" />
+  <parameter name="CLOCK_TYPE" value="0" />
+  <generatedFiles>
+   <file
+       path="/home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2/synthesis/submodules/clkctrl2_altclkctrl_0.v"
+       type="VERILOG"
+       attributes="" />
+  </generatedFiles>
+  <childGeneratedFiles/>
+  <sourceFiles>
+   <file
+       path="/home/markw/intelFPGA_lite/18.0/ip/altera/megafunctions/altclkctrl/altclkctrl_hw.tcl" />
+  </sourceFiles>
+  <childSourceFiles/>
+  <instantiator instantiator="clkctrl2" as="altclkctrl_0" />
+  <messages>
+   <message level="Debug" culprit="clkctrl2">queue size: 0 starting:altclkctrl "submodules/clkctrl2_altclkctrl_0"</message>
+   <message level="Info" culprit="altclkctrl_0">Generating top-level entity clkctrl2_altclkctrl_0.</message>
+   <message level="Debug" culprit="altclkctrl_0">Current quartus bindir: /home/markw/intelFPGA_lite/18.0/quartus/linux64/.</message>
+   <message level="Info" culprit="altclkctrl_0"><![CDATA["<b>clkctrl2</b>" instantiated <b>altclkctrl</b> "<b>altclkctrl_0</b>"]]></message>
+  </messages>
+ </entity>
+</deploy>
Index: eclaireXL_ITX/clkctrl2/clkctrl2_bb.v
===================================================================
--- eclaireXL_ITX/clkctrl2/clkctrl2_bb.v	(nonexistent)
+++ eclaireXL_ITX/clkctrl2/clkctrl2_bb.v	(revision 974)
@@ -0,0 +1,16 @@
+
+module clkctrl2 (
+	inclk3x,
+	inclk2x,
+	inclk1x,
+	inclk0x,
+	clkselect,
+	outclk);	
+
+	input		inclk3x;
+	input		inclk2x;
+	input		inclk1x;
+	input		inclk0x;
+	input	[1:0]	clkselect;
+	output		outclk;
+endmodule
Index: eclaireXL_ITX/clkctrl2/clkctrl2_generation.rpt
===================================================================
--- eclaireXL_ITX/clkctrl2/clkctrl2_generation.rpt	(nonexistent)
+++ eclaireXL_ITX/clkctrl2/clkctrl2_generation.rpt	(revision 974)
@@ -0,0 +1,35 @@
+Info: Starting: Create block symbol file (.bsf)
+Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2 --family="Cyclone V" --part=5CEBA4F23C8
+Progress: Loading build_A4EBArom/clkctrl2.qsys
+Progress: Reading input file
+Progress: Adding altclkctrl_0 [altclkctrl 18.0]
+Progress: Parameterizing module altclkctrl_0
+Progress: Building connections
+Progress: Parameterizing connections
+Progress: Validating
+Progress: Done reading input file
+: clkctrl2.altclkctrl_0: Targeting device family: Cyclone V.
+: clkctrl2.altclkctrl_0: Selecting AUTO allows the compiler to pick the best clock buffer to use, while other values restrict usage to only the given clock buffer.
+: clkctrl2.altclkctrl_0: The register mode of port 'ena' is unavailable while 'ena' port not added. 
+Info: qsys-generate succeeded.
+Info: Finished: Create block symbol file (.bsf)
+Info: 
+Info: Starting: Create HDL design files for synthesis
+Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2/synthesis --family="Cyclone V" --part=5CEBA4F23C8
+Progress: Loading build_A4EBArom/clkctrl2.qsys
+Progress: Reading input file
+Progress: Adding altclkctrl_0 [altclkctrl 18.0]
+Progress: Parameterizing module altclkctrl_0
+Progress: Building connections
+Progress: Parameterizing connections
+Progress: Validating
+Progress: Done reading input file
+: clkctrl2.altclkctrl_0: Targeting device family: Cyclone V.
+: clkctrl2.altclkctrl_0: Selecting AUTO allows the compiler to pick the best clock buffer to use, while other values restrict usage to only the given clock buffer.
+: clkctrl2.altclkctrl_0: The register mode of port 'ena' is unavailable while 'ena' port not added. 
+Info: clkctrl2: Generating clkctrl2 "clkctrl2" for QUARTUS_SYNTH
+Info: altclkctrl_0: Generating top-level entity clkctrl2_altclkctrl_0.
+Info: altclkctrl_0: "clkctrl2" instantiated altclkctrl "altclkctrl_0"
+Info: clkctrl2: Done "clkctrl2" with 2 modules, 2 files
+Info: qsys-generate succeeded.
+Info: Finished: Create HDL design files for synthesis
Index: eclaireXL_ITX/clkctrl2/clkctrl2_generation_previous.rpt
===================================================================
--- eclaireXL_ITX/clkctrl2/clkctrl2_generation_previous.rpt	(nonexistent)
+++ eclaireXL_ITX/clkctrl2/clkctrl2_generation_previous.rpt	(revision 974)
@@ -0,0 +1,33 @@
+Info: Starting: Create block symbol file (.bsf)
+Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2 --family="Cyclone V" --part=5CEBA4F23C8
+Progress: Loading build_A4EBArom/clkctrl2.qsys
+Progress: Reading input file
+Progress: Adding altclkctrl_0 [altclkctrl 18.0]
+Progress: Parameterizing module altclkctrl_0
+Progress: Building connections
+Progress: Parameterizing connections
+Progress: Validating
+Progress: Done reading input file
+: clkctrl2.altclkctrl_0: Targeting device family: Cyclone V.
+: clkctrl2.altclkctrl_0: Selecting AUTO allows the compiler to pick the best clock buffer to use, while other values restrict usage to only the given clock buffer.
+Info: qsys-generate succeeded.
+Info: Finished: Create block symbol file (.bsf)
+Info: 
+Info: Starting: Create HDL design files for synthesis
+Info: qsys-generate /home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/trunk/atari_800xl/eclaireXL_ITX/build_A4EBArom/clkctrl2/synthesis --family="Cyclone V" --part=5CEBA4F23C8
+Progress: Loading build_A4EBArom/clkctrl2.qsys
+Progress: Reading input file
+Progress: Adding altclkctrl_0 [altclkctrl 18.0]
+Progress: Parameterizing module altclkctrl_0
+Progress: Building connections
+Progress: Parameterizing connections
+Progress: Validating
+Progress: Done reading input file
+: clkctrl2.altclkctrl_0: Targeting device family: Cyclone V.
+: clkctrl2.altclkctrl_0: Selecting AUTO allows the compiler to pick the best clock buffer to use, while other values restrict usage to only the given clock buffer.
+Info: clkctrl2: Generating clkctrl2 "clkctrl2" for QUARTUS_SYNTH
+Info: altclkctrl_0: Generating top-level entity clkctrl2_altclkctrl_0.
+Info: altclkctrl_0: "clkctrl2" instantiated altclkctrl "altclkctrl_0"
+Info: clkctrl2: Done "clkctrl2" with 2 modules, 2 files
+Info: qsys-generate succeeded.
+Info: Finished: Create HDL design files for synthesis
Index: eclaireXL_ITX/clkctrl2/clkctrl2_inst.v
===================================================================
--- eclaireXL_ITX/clkctrl2/clkctrl2_inst.v	(nonexistent)
+++ eclaireXL_ITX/clkctrl2/clkctrl2_inst.v	(revision 974)
@@ -0,0 +1,9 @@
+	clkctrl2 u0 (
+		.inclk3x   (<connected-to-inclk3x>),   //  altclkctrl_input.inclk3x
+		.inclk2x   (<connected-to-inclk2x>),   //                  .inclk2x
+		.inclk1x   (<connected-to-inclk1x>),   //                  .inclk1x
+		.inclk0x   (<connected-to-inclk0x>),   //                  .inclk0x
+		.clkselect (<connected-to-clkselect>), //                  .clkselect
+		.outclk    (<connected-to-outclk>)     // altclkctrl_output.outclk
+	);
+
Index: eclaireXL_ITX/clkctrl2/clkctrl2_inst.vhd
===================================================================
--- eclaireXL_ITX/clkctrl2/clkctrl2_inst.vhd	(nonexistent)
+++ eclaireXL_ITX/clkctrl2/clkctrl2_inst.vhd	(revision 974)
@@ -0,0 +1,21 @@
+	component clkctrl2 is
+		port (
+			inclk3x   : in  std_logic                    := 'X';             -- inclk3x
+			inclk2x   : in  std_logic                    := 'X';             -- inclk2x
+			inclk1x   : in  std_logic                    := 'X';             -- inclk1x
+			inclk0x   : in  std_logic                    := 'X';             -- inclk0x
+			clkselect : in  std_logic_vector(1 downto 0) := (others => 'X'); -- clkselect
+			outclk    : out std_logic                                        -- outclk
+		);
+	end component clkctrl2;
+
+	u0 : component clkctrl2
+		port map (
+			inclk3x   => CONNECTED_TO_inclk3x,   --  altclkctrl_input.inclk3x
+			inclk2x   => CONNECTED_TO_inclk2x,   --                  .inclk2x
+			inclk1x   => CONNECTED_TO_inclk1x,   --                  .inclk1x
+			inclk0x   => CONNECTED_TO_inclk0x,   --                  .inclk0x
+			clkselect => CONNECTED_TO_clkselect, --                  .clkselect
+			outclk    => CONNECTED_TO_outclk     -- altclkctrl_output.outclk
+		);
+
Index: eclaireXL_ITX/clkctrl2/synthesis/clkctrl2.debuginfo
===================================================================
--- eclaireXL_ITX/clkctrl2/synthesis/clkctrl2.debuginfo	(nonexistent)
+++ eclaireXL_ITX/clkctrl2/synthesis/clkctrl2.debuginfo	(revision 974)
@@ -0,0 +1,363 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="clkctrl2" kind="system" version="18.0" fabric="QSYS">
+ <!-- Format version 18.0 614 (Future versions may contain additional information.) -->
+ <!-- 2020.02.02.21:08:21 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="clockCrossingAdapter">
+  <type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
+  <value>HANDSHAKE</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="device">
+  <type>java.lang.String</type>
+  <value>5CEBA4F23C8</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>CYCLONEV</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="deviceSpeedGrade">
+  <type>java.lang.String</type>
+  <value>8</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="fabricMode">
+  <type>com.altera.sopcmodel.ensemble.Ensemble$EFabricMode</type>
+  <value>QSYS</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="generationId">
+  <type>int</type>
+  <value>1580674101</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="globalResetBus">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hdlLanguage">
+  <type>com.altera.entityinterfaces.moduleext.IModuleGenerateHDL$HDLLanguage</type>
+  <value>VERILOG</value>
+  <derived>false</derived>
+  <enabled>false</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="hideFromIPCatalog">
+  <type>boolean</type>
+  <value>true</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="lockedInterfaceDefinition">
+  <type>com.altera.sopcmodel.definition.BoundaryDefinition</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="maxAdditionalLatency">
+  <type>int</type>
+  <value>1</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="projectName">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="sopcBorderPoints">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="systemHash">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="testBenchDutName">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="timeStamp">
+  <type>long</type>
+  <value>0</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <parameter name="useTestBenchNamingPattern">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+ </parameter>
+ <module
+   name="altclkctrl_0"
+   kind="altclkctrl"
+   version="18.0"
+   path="altclkctrl_0">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>CYCLONEV</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="CLOCK_TYPE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUMBER_OF_CLOCKS">
+   <type>int</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENA_REGISTER_MODE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="GUI_USE_ENA">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="altclkctrl_input" kind="conduit_end" version="18.0">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>ui.blockdiagram.direction</name>
+    <value>input</value>
+   </assignment>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>inclk3x</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>inclk3x</role>
+   </port>
+   <port>
+    <name>inclk2x</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>inclk2x</role>
+   </port>
+   <port>
+    <name>inclk1x</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>inclk1x</role>
+   </port>
+   <port>
+    <name>inclk0x</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>inclk0x</role>
+   </port>
+   <port>
+    <name>clkselect</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>clkselect</role>
+   </port>
+  </interface>
+  <interface name="altclkctrl_output" kind="conduit_end" version="18.0">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>ui.blockdiagram.direction</name>
+    <value>output</value>
+   </assignment>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>outclk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>outclk</role>
+   </port>
+  </interface>
+ </module>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altclkctrl</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>ALTCLKCTRL Intel FPGA IP</displayName>
+  <version>18.0</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>conduit_end</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Conduit</displayName>
+  <version>18.0</version>
+ </plugin>
+ <reportVersion>18.0 614</reportVersion>
+ <uniqueIdentifier>F44D30F4F5CE000001700784B163</uniqueIdentifier>
+</EnsembleReport>
Index: eclaireXL_ITX/clkctrl2/synthesis/clkctrl2.qip
===================================================================
--- eclaireXL_ITX/clkctrl2/synthesis/clkctrl2.qip	(nonexistent)
+++ eclaireXL_ITX/clkctrl2/synthesis/clkctrl2.qip	(revision 974)
@@ -0,0 +1,39 @@
+set_global_assignment -entity "clkctrl2" -library "clkctrl2" -name IP_TOOL_NAME "Qsys"
+set_global_assignment -entity "clkctrl2" -library "clkctrl2" -name IP_TOOL_VERSION "18.0"
+set_global_assignment -entity "clkctrl2" -library "clkctrl2" -name IP_TOOL_ENV "Qsys"
+set_global_assignment -library "clkctrl2" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../clkctrl2.sopcinfo"]
+set_global_assignment -entity "clkctrl2" -library "clkctrl2" -name SLD_INFO "QSYS_NAME clkctrl2 HAS_SOPCINFO 1 GENERATION_ID 1580674101"
+set_global_assignment -library "clkctrl2" -name MISC_FILE [file join $::quartus(qip_path) "../clkctrl2.cmp"]
+set_global_assignment -library "clkctrl2" -name SLD_FILE [file join $::quartus(qip_path) "clkctrl2.debuginfo"]
+set_global_assignment -entity "clkctrl2" -library "clkctrl2" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
+set_global_assignment -entity "clkctrl2" -library "clkctrl2" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -entity "clkctrl2" -library "clkctrl2" -name IP_QSYS_MODE "STANDALONE"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -library "clkctrl2" -name MISC_FILE [file join $::quartus(qip_path) "../../clkctrl2.qsys"]
+set_global_assignment -entity "clkctrl2" -library "clkctrl2" -name IP_COMPONENT_NAME "Y2xrY3RybDI="
+set_global_assignment -entity "clkctrl2" -library "clkctrl2" -name IP_COMPONENT_DISPLAY_NAME "Y2xrY3RybDI="
+set_global_assignment -entity "clkctrl2" -library "clkctrl2" -name IP_COMPONENT_REPORT_HIERARCHY "On"
+set_global_assignment -entity "clkctrl2" -library "clkctrl2" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "clkctrl2" -library "clkctrl2" -name IP_COMPONENT_VERSION "MS4w"
+set_global_assignment -entity "clkctrl2" -library "clkctrl2" -name IP_COMPONENT_PARAMETER "QVVUT19HRU5FUkFUSU9OX0lE::MTU4MDY3NDEwMQ==::QXV0byBHRU5FUkFUSU9OX0lE"
+set_global_assignment -entity "clkctrl2" -library "clkctrl2" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfRkFNSUxZ::Q3ljbG9uZSBW::QXV0byBERVZJQ0VfRkFNSUxZ"
+set_global_assignment -entity "clkctrl2" -library "clkctrl2" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0U=::NUNFQkE0RjIzQzg=::QXV0byBERVZJQ0U="
+set_global_assignment -entity "clkctrl2" -library "clkctrl2" -name IP_COMPONENT_PARAMETER "QVVUT19ERVZJQ0VfU1BFRURHUkFERQ==::OA==::QXV0byBERVZJQ0VfU1BFRURHUkFERQ=="
+set_global_assignment -entity "clkctrl2_altclkctrl_0" -library "clkctrl2" -name IP_COMPONENT_NAME "Y2xrY3RybDJfYWx0Y2xrY3RybF8w"
+set_global_assignment -entity "clkctrl2_altclkctrl_0" -library "clkctrl2" -name IP_COMPONENT_DISPLAY_NAME "QUxUQ0xLQ1RSTCBJbnRlbCBGUEdBIElQ"
+set_global_assignment -entity "clkctrl2_altclkctrl_0" -library "clkctrl2" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "clkctrl2_altclkctrl_0" -library "clkctrl2" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "clkctrl2_altclkctrl_0" -library "clkctrl2" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "clkctrl2_altclkctrl_0" -library "clkctrl2" -name IP_COMPONENT_VERSION "MTguMA=="
+set_global_assignment -entity "clkctrl2_altclkctrl_0" -library "clkctrl2" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::Q3ljbG9uZSBW::RGV2aWNlIEZhbWlseQ=="
+set_global_assignment -entity "clkctrl2_altclkctrl_0" -library "clkctrl2" -name IP_COMPONENT_PARAMETER "Q0xPQ0tfVFlQRQ==::MA==::SG93IGRvIHlvdSB3YW50IHRvIHVzZSB0aGUgQUxUQ0xLQ1RSTD8="
+set_global_assignment -entity "clkctrl2_altclkctrl_0" -library "clkctrl2" -name IP_COMPONENT_PARAMETER "TlVNQkVSX09GX0NMT0NLUw==::NA==::SG93IG1hbnkgY2xvY2sgaW5wdXRzIHdvdWxkIHlvdSBsaWtlPw=="
+set_global_assignment -entity "clkctrl2_altclkctrl_0" -library "clkctrl2" -name IP_COMPONENT_PARAMETER "R1VJX1VTRV9FTkE=::ZmFsc2U=::Q3JlYXRlICdlbmEnIHBvcnQgdG8gZW5hYmxlIG9yIGRpc2FibGUgdGhlIGNsb2NrIG5ldHdvcmsgZHJpdmVuIGJ5IHRoaXMgYnVmZmVyPw=="
+set_global_assignment -entity "clkctrl2_altclkctrl_0" -library "clkctrl2" -name IP_COMPONENT_PARAMETER "VVNFX0dMSVRDSF9GUkVFX1NXSVRDSF9PVkVSX0lNUExFTUVOVEFUSU9O::ZmFsc2U=::RW5zdXJlIGdsaXRjaC1mcmVlIHN3aXRjaG92ZXIgaW1wbGVtZW50YXRpb24="
+
+set_global_assignment -library "clkctrl2" -name VHDL_FILE [file join $::quartus(qip_path) "clkctrl2.vhd"]
+set_global_assignment -library "clkctrl2" -name VERILOG_FILE [file join $::quartus(qip_path) "submodules/clkctrl2_altclkctrl_0.v"]
+
+set_global_assignment -entity "clkctrl2_altclkctrl_0" -library "clkctrl2" -name IP_TOOL_NAME "altclkctrl"
+set_global_assignment -entity "clkctrl2_altclkctrl_0" -library "clkctrl2" -name IP_TOOL_VERSION "18.0"
+set_global_assignment -entity "clkctrl2_altclkctrl_0" -library "clkctrl2" -name IP_TOOL_ENV "Qsys"
Index: eclaireXL_ITX/clkctrl2/synthesis/clkctrl2.vhd
===================================================================
--- eclaireXL_ITX/clkctrl2/synthesis/clkctrl2.vhd	(nonexistent)
+++ eclaireXL_ITX/clkctrl2/synthesis/clkctrl2.vhd	(revision 974)
@@ -0,0 +1,44 @@
+-- clkctrl2.vhd
+
+-- Generated using ACDS version 18.0 614
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity clkctrl2 is
+	port (
+		inclk3x   : in  std_logic                    := '0';             --  altclkctrl_input.inclk3x
+		inclk2x   : in  std_logic                    := '0';             --                  .inclk2x
+		inclk1x   : in  std_logic                    := '0';             --                  .inclk1x
+		inclk0x   : in  std_logic                    := '0';             --                  .inclk0x
+		clkselect : in  std_logic_vector(1 downto 0) := (others => '0'); --                  .clkselect
+		outclk    : out std_logic                                        -- altclkctrl_output.outclk
+	);
+end entity clkctrl2;
+
+architecture rtl of clkctrl2 is
+	component clkctrl2_altclkctrl_0 is
+		port (
+			inclk3x   : in  std_logic                    := 'X';             -- inclk3x
+			inclk2x   : in  std_logic                    := 'X';             -- inclk2x
+			inclk1x   : in  std_logic                    := 'X';             -- inclk1x
+			inclk0x   : in  std_logic                    := 'X';             -- inclk0x
+			clkselect : in  std_logic_vector(1 downto 0) := (others => 'X'); -- clkselect
+			outclk    : out std_logic                                        -- outclk
+		);
+	end component clkctrl2_altclkctrl_0;
+
+begin
+
+	altclkctrl_0 : component clkctrl2_altclkctrl_0
+		port map (
+			inclk3x   => inclk3x,   --  altclkctrl_input.inclk3x
+			inclk2x   => inclk2x,   --                  .inclk2x
+			inclk1x   => inclk1x,   --                  .inclk1x
+			inclk0x   => inclk0x,   --                  .inclk0x
+			clkselect => clkselect, --                  .clkselect
+			outclk    => outclk     -- altclkctrl_output.outclk
+		);
+
+end architecture rtl; -- of clkctrl2
Index: eclaireXL_ITX/clkctrl2/synthesis/submodules/clkctrl2_altclkctrl_0.v
===================================================================
--- eclaireXL_ITX/clkctrl2/synthesis/submodules/clkctrl2_altclkctrl_0.v	(nonexistent)
+++ eclaireXL_ITX/clkctrl2/synthesis/submodules/clkctrl2_altclkctrl_0.v	(revision 974)
@@ -0,0 +1,135 @@
+//altclkctrl CBX_SINGLE_OUTPUT_FILE="ON" CLOCK_TYPE="AUTO" DEVICE_FAMILY="Cyclone V" USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION="OFF" clkselect ena inclk outclk
+//VERSION_BEGIN 18.0 cbx_altclkbuf 2018:04:18:06:50:44:SJ cbx_cycloneii 2018:04:18:06:50:44:SJ cbx_lpm_add_sub 2018:04:18:06:50:44:SJ cbx_lpm_compare 2018:04:18:06:50:44:SJ cbx_lpm_decode 2018:04:18:06:50:44:SJ cbx_lpm_mux 2018:04:18:06:50:44:SJ cbx_mgl 2018:04:18:07:37:08:SJ cbx_nadder 2018:04:18:06:50:44:SJ cbx_stratix 2018:04:18:06:50:44:SJ cbx_stratixii 2018:04:18:06:50:44:SJ cbx_stratixiii 2018:04:18:06:50:44:SJ cbx_stratixv 2018:04:18:06:50:44:SJ  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+
+// Copyright (C) 2018  Intel Corporation. All rights reserved.
+//  Your use of Intel Corporation's design tools, logic functions 
+//  and other software and tools, and its AMPP partner logic 
+//  functions, and any output files from any of the foregoing 
+//  (including device programming or simulation files), and any 
+//  associated documentation or information are expressly subject 
+//  to the terms and conditions of the Intel Program License 
+//  Subscription Agreement, the Intel Quartus Prime License Agreement,
+//  the Intel FPGA IP License Agreement, or other applicable license
+//  agreement, including, without limitation, that your use is for
+//  the sole purpose of programming logic devices manufactured by
+//  Intel and sold by Intel or its authorized distributors.  Please
+//  refer to the applicable agreement for further details.
+
+
+
+//synthesis_resources = cyclonev_clkena 1 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  clkctrl2_altclkctrl_0_sub
+	( 
+	clkselect,
+	ena,
+	inclk,
+	outclk) /* synthesis synthesis_clearbox=1 */;
+	input   [1:0]  clkselect;
+	input   ena;
+	input   [3:0]  inclk;
+	output   outclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0   [1:0]  clkselect;
+	tri1   ena;
+	tri0   [3:0]  inclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire  wire_sd2_outclk;
+	wire  wire_sd1_outclk;
+	wire  [1:0]  clkselect_wire;
+	wire  [3:0]  inclk_wire;
+
+	cyclonev_clkselect   sd2
+	( 
+	.clkselect(clkselect_wire),
+	.inclk(inclk_wire),
+	.outclk(wire_sd2_outclk));
+	cyclonev_clkena   sd1
+	( 
+	.ena(ena),
+	.enaout(),
+	.inclk(wire_sd2_outclk),
+	.outclk(wire_sd1_outclk));
+	defparam
+		sd1.clock_type = "Auto",
+		sd1.ena_register_mode = "always enabled",
+		sd1.lpm_type = "cyclonev_clkena";
+	assign
+		clkselect_wire = {clkselect},
+		inclk_wire = {inclk},
+		outclk = wire_sd1_outclk;
+endmodule //clkctrl2_altclkctrl_0_sub
+//VALID FILE // (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module  clkctrl2_altclkctrl_0  (
+    clkselect,
+    inclk0x,
+    inclk1x,
+    inclk2x,
+    inclk3x,
+    outclk);
+
+    input  [1:0]  clkselect;
+    input    inclk0x;
+    input    inclk1x;
+    input    inclk2x;
+    input    inclk3x;
+    output   outclk;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+    tri0 [1:0]  clkselect;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+    wire  sub_wire0;
+    wire  outclk;
+    wire  sub_wire1;
+    wire  sub_wire2;
+    wire [3:0] sub_wire3;
+    wire  sub_wire4;
+    wire  sub_wire5;
+    wire  sub_wire6;
+
+    assign  outclk = sub_wire0;
+    assign  sub_wire1 = 1'h1;
+    assign  sub_wire2 = inclk0x;
+    assign sub_wire3[3:0] = {sub_wire6, sub_wire5, sub_wire4, sub_wire2};
+    assign  sub_wire4 = inclk1x;
+    assign  sub_wire5 = inclk2x;
+    assign  sub_wire6 = inclk3x;
+
+    clkctrl2_altclkctrl_0_sub  clkctrl2_altclkctrl_0_sub_component (
+                .clkselect (clkselect),
+                .ena (sub_wire1),
+                .inclk (sub_wire3),
+                .outclk (sub_wire0));
+
+endmodule
\ No newline at end of file
Index: eclaireXL_ITX/clkctrl2.qsys
===================================================================
--- eclaireXL_ITX/clkctrl2.qsys	(nonexistent)
+++ eclaireXL_ITX/clkctrl2.qsys	(revision 974)
@@ -0,0 +1,76 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<system name="$${FILENAME}">
+ <component
+   name="$${FILENAME}"
+   displayName="$${FILENAME}"
+   version="1.0"
+   description=""
+   tags="INTERNAL_COMPONENT=true"
+   categories="" />
+ <parameter name="bonusData"><![CDATA[bonusData 
+{
+   element altclkctrl_0
+   {
+      datum _sortIndex
+      {
+         value = "0";
+         type = "int";
+      }
+   }
+}
+]]></parameter>
+ <parameter name="clockCrossingAdapter" value="HANDSHAKE" />
+ <parameter name="device" value="5CEBA4F23C8" />
+ <parameter name="deviceFamily" value="Cyclone V" />
+ <parameter name="deviceSpeedGrade" value="8" />
+ <parameter name="fabricMode" value="QSYS" />
+ <parameter name="generateLegacySim" value="false" />
+ <parameter name="generationId" value="0" />
+ <parameter name="globalResetBus" value="false" />
+ <parameter name="hdlLanguage" value="VERILOG" />
+ <parameter name="hideFromIPCatalog" value="true" />
+ <parameter name="lockedInterfaceDefinition" value="" />
+ <parameter name="maxAdditionalLatency" value="1" />
+ <parameter name="projectName" value="" />
+ <parameter name="sopcBorderPoints" value="false" />
+ <parameter name="systemHash" value="0" />
+ <parameter name="testBenchDutName" value="" />
+ <parameter name="timeStamp" value="0" />
+ <parameter name="useTestBenchNamingPattern" value="false" />
+ <instanceScript></instanceScript>
+ <interface
+   name="altclkctrl_input"
+   internal="altclkctrl_0.altclkctrl_input"
+   type="conduit"
+   dir="end">
+  <port name="inclk3x" internal="inclk3x" />
+  <port name="inclk2x" internal="inclk2x" />
+  <port name="inclk1x" internal="inclk1x" />
+  <port name="inclk0x" internal="inclk0x" />
+  <port name="clkselect" internal="clkselect" />
+ </interface>
+ <interface
+   name="altclkctrl_output"
+   internal="altclkctrl_0.altclkctrl_output"
+   type="conduit"
+   dir="end">
+  <port name="outclk" internal="outclk" />
+ </interface>
+ <module
+   name="altclkctrl_0"
+   kind="altclkctrl"
+   version="18.0"
+   enabled="1"
+   autoexport="1">
+  <parameter name="CLOCK_TYPE" value="0" />
+  <parameter name="DEVICE_FAMILY" value="Cyclone V" />
+  <parameter name="ENA_REGISTER_MODE" value="1" />
+  <parameter name="GUI_USE_ENA" value="false" />
+  <parameter name="NUMBER_OF_CLOCKS" value="4" />
+  <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION" value="false" />
+ </module>
+ <interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
+ <interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
+ <interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
+</system>
Index: eclaireXL_ITX/clkctrl2.sopcinfo
===================================================================
--- eclaireXL_ITX/clkctrl2.sopcinfo	(nonexistent)
+++ eclaireXL_ITX/clkctrl2.sopcinfo	(revision 974)
@@ -0,0 +1,281 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<EnsembleReport name="clkctrl2" kind="clkctrl2" version="1.0" fabric="QSYS">
+ <!-- Format version 18.0 614 (Future versions may contain additional information.) -->
+ <!-- 2020.02.12.21:10:38 -->
+ <!-- A collection of modules and connections -->
+ <parameter name="AUTO_GENERATION_ID">
+  <type>java.lang.Integer</type>
+  <value>1581538238</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>GENERATION_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_UNIQUE_ID">
+  <type>java.lang.String</type>
+  <value></value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>UNIQUE_ID</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_FAMILY">
+  <type>java.lang.String</type>
+  <value>CYCLONEV</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE">
+  <type>java.lang.String</type>
+  <value>5CEBA4F23C8</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE</sysinfo_type>
+ </parameter>
+ <parameter name="AUTO_DEVICE_SPEEDGRADE">
+  <type>java.lang.String</type>
+  <value>8</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_SPEEDGRADE</sysinfo_type>
+ </parameter>
+ <parameter name="deviceFamily">
+  <type>java.lang.String</type>
+  <value>Cyclone V</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>false</visible>
+  <valid>true</valid>
+  <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+ </parameter>
+ <parameter name="generateLegacySim">
+  <type>boolean</type>
+  <value>false</value>
+  <derived>false</derived>
+  <enabled>true</enabled>
+  <visible>true</visible>
+  <valid>true</valid>
+ </parameter>
+ <module
+   name="altclkctrl_0"
+   kind="altclkctrl"
+   version="18.0"
+   path="altclkctrl_0">
+  <!-- Describes a single module. Module parameters are
+the requested settings for a module instance. -->
+  <parameter name="DEVICE_FAMILY">
+   <type>java.lang.String</type>
+   <value>CYCLONEV</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>false</visible>
+   <valid>true</valid>
+   <sysinfo_type>DEVICE_FAMILY</sysinfo_type>
+  </parameter>
+  <parameter name="CLOCK_TYPE">
+   <type>int</type>
+   <value>0</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="NUMBER_OF_CLOCKS">
+   <type>int</type>
+   <value>4</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="ENA_REGISTER_MODE">
+   <type>int</type>
+   <value>1</value>
+   <derived>false</derived>
+   <enabled>false</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="GUI_USE_ENA">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="USE_GLITCH_FREE_SWITCH_OVER_IMPLEMENTATION">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="deviceFamily">
+   <type>java.lang.String</type>
+   <value>UNKNOWN</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <parameter name="generateLegacySim">
+   <type>boolean</type>
+   <value>false</value>
+   <derived>false</derived>
+   <enabled>true</enabled>
+   <visible>true</visible>
+   <valid>true</valid>
+  </parameter>
+  <interface name="altclkctrl_input" kind="conduit_end" version="18.0">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>ui.blockdiagram.direction</name>
+    <value>input</value>
+   </assignment>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>inclk3x</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>inclk3x</role>
+   </port>
+   <port>
+    <name>inclk2x</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>inclk2x</role>
+   </port>
+   <port>
+    <name>inclk1x</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>inclk1x</role>
+   </port>
+   <port>
+    <name>inclk0x</name>
+    <direction>Input</direction>
+    <width>1</width>
+    <role>inclk0x</role>
+   </port>
+   <port>
+    <name>clkselect</name>
+    <direction>Input</direction>
+    <width>2</width>
+    <role>clkselect</role>
+   </port>
+  </interface>
+  <interface name="altclkctrl_output" kind="conduit_end" version="18.0">
+   <!-- The connection points exposed by a module instance for the
+particular module parameters. Connection points and their
+parameters are a RESULT of the module parameters. -->
+   <assignment>
+    <name>ui.blockdiagram.direction</name>
+    <value>output</value>
+   </assignment>
+   <parameter name="associatedClock">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="associatedReset">
+    <type>java.lang.String</type>
+    <value></value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="deviceFamily">
+    <type>java.lang.String</type>
+    <value>UNKNOWN</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <parameter name="generateLegacySim">
+    <type>boolean</type>
+    <value>false</value>
+    <derived>false</derived>
+    <enabled>true</enabled>
+    <visible>true</visible>
+    <valid>true</valid>
+   </parameter>
+   <type>conduit</type>
+   <isStart>false</isStart>
+   <port>
+    <name>outclk</name>
+    <direction>Output</direction>
+    <width>1</width>
+    <role>outclk</role>
+   </port>
+  </interface>
+ </module>
+ <plugin>
+  <instanceCount>1</instanceCount>
+  <name>altclkctrl</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IModule</subtype>
+  <displayName>ALTCLKCTRL Intel FPGA IP</displayName>
+  <version>18.0</version>
+ </plugin>
+ <plugin>
+  <instanceCount>2</instanceCount>
+  <name>conduit_end</name>
+  <type>com.altera.entityinterfaces.IElementClass</type>
+  <subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
+  <displayName>Conduit</displayName>
+  <version>18.0</version>
+ </plugin>
+ <reportVersion>18.0 614</reportVersion>
+ <uniqueIdentifier></uniqueIdentifier>
+</EnsembleReport>
Index: eclaireXL_ITX/hdmi/hdmi_line_buffer.cmp
===================================================================
--- eclaireXL_ITX/hdmi/hdmi_line_buffer.cmp	(revision 973)
+++ eclaireXL_ITX/hdmi/hdmi_line_buffer.cmp	(revision 974)
@@ -1,4 +1,4 @@
---Copyright (C) 2016  Intel Corporation. All rights reserved.
+--Copyright (C) 2018  Intel Corporation. All rights reserved.
 --Your use of Intel Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -6,12 +6,11 @@
 --associated documentation or information are expressly subject 
 --to the terms and conditions of the Intel Program License 
 --Subscription Agreement, the Intel Quartus Prime License Agreement,
---the Intel MegaCore Function License Agreement, or other 
---applicable license agreement, including, without limitation, 
---that your use is for the sole purpose of programming logic 
---devices manufactured by Intel and sold by Intel or its 
---authorized distributors.  Please refer to the applicable 
---agreement for further details.
+--the Intel FPGA IP License Agreement, or other applicable license
+--agreement, including, without limitation, that your use is for
+--the sole purpose of programming logic devices manufactured by
+--Intel and sold by Intel or its authorized distributors.  Please
+--refer to the applicable agreement for further details.
 
 
 component hdmi_line_buffer
@@ -18,11 +17,11 @@
 	PORT
 	(
 		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		rdaddress		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		rdaddress		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
 		rdclock		: IN STD_LOGIC ;
-		wraddress		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		wraddress		: IN STD_LOGIC_VECTOR (13 DOWNTO 0);
 		wrclock		: IN STD_LOGIC  := '1';
 		wren		: IN STD_LOGIC  := '0';
-		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+		q		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
 	);
 end component;
Index: eclaireXL_ITX/hdmi/hdmi_line_buffer.qip
===================================================================
--- eclaireXL_ITX/hdmi/hdmi_line_buffer.qip	(revision 973)
+++ eclaireXL_ITX/hdmi/hdmi_line_buffer.qip	(revision 974)
@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
-set_global_assignment -name IP_TOOL_VERSION "16.1"
+set_global_assignment -name IP_TOOL_VERSION "18.0"
 set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "hdmi_line_buffer.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hdmi_line_buffer.cmp"]
Index: eclaireXL_ITX/hdmi/hdmi_line_buffer.vhd
===================================================================
--- eclaireXL_ITX/hdmi/hdmi_line_buffer.vhd	(revision 973)
+++ eclaireXL_ITX/hdmi/hdmi_line_buffer.vhd	(revision 974)
@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 16.1.0 Build 196 10/24/2016 SJ Lite Edition
+-- 18.0.0 Build 614 04/24/2018 SJ Lite Edition
 -- ************************************************************
 
 
---Copyright (C) 2016  Intel Corporation. All rights reserved.
+--Copyright (C) 2018  Intel Corporation. All rights reserved.
 --Your use of Intel Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -26,12 +26,11 @@
 --associated documentation or information are expressly subject 
 --to the terms and conditions of the Intel Program License 
 --Subscription Agreement, the Intel Quartus Prime License Agreement,
---the Intel MegaCore Function License Agreement, or other 
---applicable license agreement, including, without limitation, 
---that your use is for the sole purpose of programming logic 
---devices manufactured by Intel and sold by Intel or its 
---authorized distributors.  Please refer to the applicable 
---agreement for further details.
+--the Intel FPGA IP License Agreement, or other applicable license
+--agreement, including, without limitation, that your use is for
+--the sole purpose of programming logic devices manufactured by
+--Intel and sold by Intel or its authorized distributors.  Please
+--refer to the applicable agreement for further details.
 
 
 LIBRARY ieee;
@@ -44,12 +43,12 @@
 	PORT
 	(
 		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		rdaddress		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		rdaddress		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
 		rdclock		: IN STD_LOGIC ;
-		wraddress		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		wraddress		: IN STD_LOGIC_VECTOR (13 DOWNTO 0);
 		wrclock		: IN STD_LOGIC  := '1';
 		wren		: IN STD_LOGIC  := '0';
-		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+		q		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
 	);
 END hdmi_line_buffer;
 
@@ -56,10 +55,10 @@
 
 ARCHITECTURE SYN OF hdmi_line_buffer IS
 
-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (63 DOWNTO 0);
 
 BEGIN
-	q    <= sub_wire0(7 DOWNTO 0);
+	q    <= sub_wire0(63 DOWNTO 0);
 
 	altsyncram_component : altsyncram
 	GENERIC MAP (
@@ -70,16 +69,16 @@
 		clock_enable_output_b => "BYPASS",
 		intended_device_family => "Cyclone V",
 		lpm_type => "altsyncram",
-		numwords_a => 8192,
-		numwords_b => 8192,
+		numwords_a => 16384,
+		numwords_b => 2048,
 		operation_mode => "DUAL_PORT",
 		outdata_aclr_b => "NONE",
 		outdata_reg_b => "UNREGISTERED",
 		power_up_uninitialized => "FALSE",
-		widthad_a => 13,
-		widthad_b => 13,
+		widthad_a => 14,
+		widthad_b => 11,
 		width_a => 8,
-		width_b => 8,
+		width_b => 64,
 		width_byteena_a => 1
 	)
 	PORT MAP (
@@ -129,7 +128,7 @@
 -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
 -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
 -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
--- Retrieval info: PRIVATE: MEMSIZE NUMERIC "65536"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072"
 -- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
 -- Retrieval info: PRIVATE: MIFfilename STRING ""
 -- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
@@ -148,11 +147,11 @@
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 -- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
 -- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
--- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "1"
 -- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
--- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "64"
 -- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
--- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "64"
 -- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
 -- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
 -- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
@@ -166,31 +165,31 @@
 -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
--- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
--- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "8192"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
 -- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
 -- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
 -- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
 -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
--- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
--- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "13"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
 -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
--- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "64"
 -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
 -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
--- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
--- Retrieval info: USED_PORT: rdaddress 0 0 13 0 INPUT NODEFVAL "rdaddress[12..0]"
+-- Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL "q[63..0]"
+-- Retrieval info: USED_PORT: rdaddress 0 0 11 0 INPUT NODEFVAL "rdaddress[10..0]"
 -- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"
--- Retrieval info: USED_PORT: wraddress 0 0 13 0 INPUT NODEFVAL "wraddress[12..0]"
+-- Retrieval info: USED_PORT: wraddress 0 0 14 0 INPUT NODEFVAL "wraddress[13..0]"
 -- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"
 -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
--- Retrieval info: CONNECT: @address_a 0 0 13 0 wraddress 0 0 13 0
--- Retrieval info: CONNECT: @address_b 0 0 13 0 rdaddress 0 0 13 0
+-- Retrieval info: CONNECT: @address_a 0 0 14 0 wraddress 0 0 14 0
+-- Retrieval info: CONNECT: @address_b 0 0 11 0 rdaddress 0 0 11 0
 -- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
 -- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
 -- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
--- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
+-- Retrieval info: CONNECT: q 0 0 64 0 @q_b 0 0 64 0
 -- Retrieval info: GEN_FILE: TYPE_NORMAL hdmi_line_buffer.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL hdmi_line_buffer.inc FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL hdmi_line_buffer.cmp TRUE
Index: eclaireXL_ITX/hdmi/scandoubler_hdmi.vhdl
===================================================================
--- eclaireXL_ITX/hdmi/scandoubler_hdmi.vhdl	(revision 973)
+++ eclaireXL_ITX/hdmi/scandoubler_hdmi.vhdl	(revision 974)
@@ -10,8 +10,13 @@
 use ieee.numeric_std.all;
 USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 use IEEE.STD_LOGIC_MISC.all;
+use work.pixels.all;
 
 ENTITY scandoubler_hdmi IS
+GENERIC(
+	enable_area_scaler : integer;
+	enable_polyphasic_scaler : integer
+);
 PORT 
 ( 
 	-- Atari clock_domain
@@ -36,6 +41,7 @@
 	--HDMI clock domain
 	CLK_HDMI_IN : IN STD_LOGIC;   -- 135MHz exactly
 	CLK_PIXEL_IN : IN STD_LOGIC;  -- 27 MHz exactly (aligned with HDMI)
+	CLK_HDMI_SELECT : OUT STD_LOGIC_VECTOR(2 downto 0); 
 
 	-- VGA output - in clk pixel domain
 	O_hsync : out std_logic;
@@ -47,7 +53,11 @@
 
 	-- TO TV...
 	O_TMDS_H : OUT STD_LOGIC_VECTOR(7 downto 0);
-	O_TMDS_L : OUT STD_LOGIC_VECTOR(7 downto 0)
+	O_TMDS_L : OUT STD_LOGIC_VECTOR(7 downto 0);
+	
+	-- I2C params
+	scl : inout std_logic;
+	sda : inout std_logic
 );
 END scandoubler_hdmi;
 
@@ -57,12 +67,12 @@
 	PORT
 	(
 		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-		rdaddress		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		rdaddress		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
 		rdclock		: IN STD_LOGIC ;
-		wraddress		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		wraddress		: IN STD_LOGIC_VECTOR (13 DOWNTO 0);
 		wrclock		: IN STD_LOGIC  := '1';
 		wren		: IN STD_LOGIC  := '0';
-		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+		q		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
 	);
 END component;
 
@@ -71,9 +81,6 @@
 -- TODO: NTSC!
 -- ModeLine " 720x 480@59.94Hz"  27.00  720  736  798  858  480  489  495  525 -HSync -VSync
 
-signal hcnt		: std_logic_vector(11 downto 0) := "000000000000"; 	-- horizontal pixel counter
-signal vcnt		: std_logic_vector(11 downto 0) := "000000000000"; 	-- vertical line counter
-
 signal hsync_next		: std_logic;
 signal vsync_next		: std_logic;
 signal blank_next		: std_logic;
@@ -100,39 +107,69 @@
 signal hs_blue_reg2		: std_logic_vector(7 downto 4);
 
 --
-signal cap_vsync_shift_next : std_logic_vector(3 downto 0);
-signal cap_vsync_shift_reg : std_logic_vector(3 downto 0);
-signal cap_vcount_next : std_logic_vector(1 downto 0);
-signal cap_vcount_reg : std_logic_vector(1 downto 0);
+signal cap_vcount_next : std_logic_vector(2 downto 0);
+signal cap_vcount_reg : std_logic_vector(2 downto 0);
 signal cap_hcount_next : std_logic_vector(10 downto 0);
 signal cap_hcount_reg : std_logic_vector(10 downto 0);
 signal cap_vsync_reg : std_logic;
 signal cap_hsync_reg : std_logic;
-signal cap_frame_start : std_logic;
+signal cap_frame_start_flip_next : std_logic;
+signal cap_frame_start_flip_reg : std_logic;
 signal cap_line_start_raw : std_logic;
 signal cap_line_start : std_logic;
 signal cap_format : std_logic_vector(1 downto 0);
+signal cap_line_start_flip_next : std_logic;
+signal cap_line_start_flip_reg : std_logic;
+signal cap_vcount_delay_reg : std_logic_vector(14 downto 0);
+signal cap_vcount_delay_next : std_logic_vector(14 downto 0);
 
--- 
-signal out_colour_raw : std_logic_vector(7 downto 0);
-signal out_colour : std_logic_vector(7 downto 0);
+-- area scaling setup
+signal out_colour_raw_lines : std_logic_vector(63 downto 0);
+
+signal out_haddr_next : std_logic_vector(10 downto 0);
+signal out_haddr_reg : std_logic_vector(10 downto 0);
+
+signal out_vaddr_next : std_logic_vector(8 downto 0);
+signal out_vaddr_reg : std_logic_vector(8 downto 0);
+
+signal out_vaddr_in_next : std_logic_vector(8 downto 0);
+signal out_vaddr_in_reg : std_logic_vector(8 downto 0);
+
+signal out_pixels_next : t_Pixel4x4;
+signal out_pixels_reg : t_Pixel4x4;
+
+signal out_next_x : std_logic;
+signal out_next_x_reg : std_logic;
+signal out_next_x_size : std_logic_vector(1 downto 0);
+signal out_next_y : std_logic;
+
+-- crtc
+signal crtc_inc_line : std_logic;
+signal crtc_inc_frame : std_logic;
+signal crtc_hsync : std_logic;
+signal crtc_vsync : std_logic;
+signal crtc_blank : std_logic;
+signal crtc_field2 : std_logic;
+signal crtc_video_id_code : std_logic_vector(7 downto 0);
+signal crtc_scaler_select : std_logic;
+
+signal out_resync_required_reg : std_logic;
+signal out_resync_required_next : std_logic;
+
+--signal out_colour_raw : std_logic_vector(7 downto 0);
+signal out_colour : std_logic_vector(31 downto 0);
 signal out_pal : std_logic;
 signal out_scanlines : std_logic;
 signal out_csync : std_logic;
+signal out_frame_start_flip_next : std_logic;
+signal out_frame_start_flip_reg : std_logic;
 signal out_frame_start : std_logic;
+signal out_line_start_flip_next : std_logic;
+signal out_line_start_flip_reg : std_logic;
+signal out_line_start : std_logic;
+signal out_resync_frame_start : std_logic;
 signal out_format : std_logic_vector(1 downto 0);
 
--- Horizontal Timing   
-signal h_pixels_across	: integer;
-signal h_sync_on		: integer;
-signal h_sync_off		: integer;
-signal h_end_count		: integer;
--- Vertical Timing 
-signal v_pixels_down		: integer;
-signal v_sync_on		: integer;
-signal v_sync_off		: integer;
-signal v_end_count		: integer;
-
 -- signed audio
 signal audio_left_signed : std_logic_vector(15 downto 0);
 signal audio_right_signed: std_logic_vector(15 downto 0);
@@ -158,12 +195,23 @@
 signal encoded_green_reg : std_logic_vector(9 downto 0);
 signal encoded_blue_reg  : std_logic_vector(9 downto 0);
 
-signal mod5	: std_logic_vector(2 downto 0) := "000";	-- modulus 5 counter
-signal shift_r	: std_logic_vector(9 downto 0) := "0000000000";
-signal shift_g	: std_logic_vector(9 downto 0) := "0000000000";
-signal shift_b	: std_logic_vector(9 downto 0) := "0000000000";
-signal shift_clk : std_logic_vector(9 downto 0) := "0000000000";
+-- fast regs
+signal mod5_reg	: std_logic_vector(4 downto 0) := "00000";	-- modulus 5 counter
+signal mod5_next	: std_logic_vector(4 downto 0) := "00000";	-- modulus 5 counter
+signal shift_r_reg	: std_logic_vector(9 downto 0) := "0000000000";
+signal shift_g_reg	: std_logic_vector(9 downto 0) := "0000000000";
+signal shift_b_reg	: std_logic_vector(9 downto 0) := "0000000000";
+signal shift_clk_reg : std_logic_vector(9 downto 0) := "0000000000";
 
+signal nshift_r_reg	: std_logic_vector(9 downto 0) := "0000000000";
+signal nshift_g_reg	: std_logic_vector(9 downto 0) := "0000000000";
+signal nshift_b_reg	: std_logic_vector(9 downto 0) := "0000000000";
+signal nshift_clk_reg : std_logic_vector(9 downto 0) := "0000000000";	
+
+signal shift_r_next	: std_logic_vector(9 downto 0) := "0000000000";
+signal shift_g_next	: std_logic_vector(9 downto 0) := "0000000000";
+signal shift_b_next	: std_logic_vector(9 downto 0) := "0000000000";	
+signal shift_clk_next : std_logic_vector(9 downto 0) := "0000000000";
 	
 BEGIN
 
@@ -179,13 +227,17 @@
 		cap_vcount_reg <= (others=>'0');
 		cap_vsync_reg <= '0';
 		cap_hsync_reg <= '0';
-		cap_vsync_shift_reg <= (others=>'0');
+		cap_line_start_flip_reg <= '0';
+		cap_frame_start_flip_reg <= '0';
+		cap_vcount_delay_reg <= (others=>'0');
 	elsif (CLK_ATARI_IN'event and CLK_ATARI_IN='1') then
 		cap_hcount_reg <= cap_hcount_next;
 		cap_vcount_reg <= cap_vcount_next;
 		cap_vsync_reg <= vsync_in;
 		cap_hsync_reg <= hsync_in;
-		cap_vsync_shift_reg <= cap_vsync_shift_next;
+		cap_line_start_flip_reg <= cap_line_start_flip_next;
+		cap_frame_start_flip_reg <= cap_frame_start_flip_next;
+		cap_vcount_delay_reg <= cap_vcount_delay_next;
 	end if;
 end process;
 
@@ -192,7 +244,7 @@
 cap_line_start_raw <= not(hsync_in) and cap_hsync_reg;
 hsync_delay : entity work.delay_line
 	generic map (COUNT=>184)
-	port map(clk=>clk_atari_in,sync_reset=>'0',data_in=>cap_line_start_raw,enable=>colour_enable,reset_n=>'1',data_out=>cap_line_start);			
+	port map(clk=>clk_atari_in,sync_reset=>'0',data_in=>cap_line_start_raw,enable=>colour_enable,reset_n=>'1',data_out=>cap_line_start);				
 
 -- our location
 process(cap_hcount_reg, colour_enable, cap_line_start)
@@ -214,35 +266,48 @@
 	end if;
 end process;
 
-process(cap_vcount_reg, cap_line_start, cap_vsync_reg, vsync_in, cap_vsync_shift_reg)
+process(cap_vcount_reg, cap_line_start, cap_vsync_reg, vsync_in, cap_frame_start_flip_reg, cap_line_start_flip_reg, cap_vcount_delay_reg)
 begin
 	cap_vcount_next <= cap_vcount_reg;
-	cap_vsync_shift_next <= cap_vsync_shift_reg;
+	cap_frame_start_flip_next <= cap_frame_start_flip_reg;
+	cap_line_start_flip_next <= cap_line_start_flip_reg;
+	cap_vcount_delay_next <= cap_vcount_delay_reg;
+	
 	if (cap_line_start = '1') then
 		cap_vcount_next <= std_logic_vector(unsigned(cap_vcount_reg)+1);
-		cap_vsync_shift_next <= cap_vsync_shift_reg(2 downto 0)&'0';
+		cap_line_start_flip_next <= not(cap_line_start_flip_reg);		
+		
+		cap_vcount_delay_next(14 downto 0) <= cap_vcount_delay_reg(13 downto 0)&'0';
+		
+		if (cap_vcount_delay_reg(14) = '1') then		
+			cap_vcount_next <= (others=>'0');		
+			cap_frame_start_flip_next <= not(cap_frame_start_flip_reg);		
+		end if;
 	end if;
+	
 	if (cap_vsync_reg = '1' and vsync_in = '0') then
-		cap_vcount_next <= (others=>'0');
-		cap_vsync_shift_next <= "0001";
+		cap_vcount_delay_next(0) <= '1';
 	end if;
 end process;
 
-cap_frame_start <= cap_vsync_shift_reg(2);
-
 hdmi_line_buffer_inst : hdmi_line_buffer
 port map 
 	(
-		data		=> colour_in and colour_mask,
-		wraddress	=> cap_vcount_reg&cap_hcount_reg,
+		-- 8 bit write
+		-- 4 lines
+		-- low bit is line, so we can read all lines at once
+		data		=> colour_in and colour_mask, --"00000"&cap_vcount_reg(2 downto 0),
+		--data		=> "0000"&cap_hcount_reg(3 downto 0),
+		--data		=> "0000"&cap_hcount_reg(0 downto 0)&"000",
+		wraddress	=> cap_hcount_reg&cap_vcount_reg,
 		wrclock		=> CLK_ATARI_IN,
 		wren		=> colour_enable, -- 1824 times/line
 
-		rdaddress	=> vcnt(2 downto 1)&hcnt(9 downto 0)&'0',
+		-- 32 bit read (to read all lines at once!)
+		rdaddress	=> out_haddr_next,
 		rdclock		=> CLK_PIXEL_IN,
-		q		=> out_colour_raw
+		q		=> out_colour_raw_lines
 	);
-
 -- Audio should be signed
 
 audio_left_signed  <= std_logic_vector(to_signed(to_integer(unsigned(audio_left))-32768,16));
@@ -262,73 +327,208 @@
 	port map (clk=>clk_pixel_in, raw=>csync_on, sync=>out_csync);						
 
 cap_vsync_synchronizer : entity work.synchronizer
-	port map (clk=>clk_pixel_in, raw=>cap_frame_start, sync=>out_frame_start);						
+	port map (clk=>clk_pixel_in, raw=>cap_frame_start_flip_reg, sync=>out_frame_start_flip_next);			
+cap_hsync_synchronizer : entity work.synchronizer
+	port map (clk=>clk_pixel_in, raw=>cap_line_start_flip_reg, sync=>out_line_start_flip_next);
+	
 cap_format0_synchronizer : entity work.synchronizer
 	port map (clk=>clk_pixel_in, raw=>format(0), sync=>out_format(0));						
 cap_format1_synchronizer : entity work.synchronizer
 	port map (clk=>clk_pixel_in, raw=>format(1), sync=>out_format(1));						
 
-out_colour(7 downto 4) <= out_colour_raw(7 downto 4);
-out_colour(3 downto 0) <= out_colour_raw(3 downto 0) when (not(out_scanlines) or vcnt(0))='1' else '0'&out_colour_raw(3 downto 1);
+process(out_colour_raw_lines,out_vaddr_reg)
+begin
+	out_colour <= (others=>'0');
 
--- colour palette
--- TODO- share!!
-palette4 : entity work.gtia_palette
-	port map (PAL=>out_pal,ATARI_COLOUR=>out_colour, R_next=>red_next, G_next=>green_next, B_next=>blue_next);		
-	
--- extract from fifo to line buffer (720 pixels)
--- sync vsync between sides...
+	case out_vaddr_reg(2 downto 0) is
+	when "000" => 
+		out_colour <= out_colour_raw_lines(31 downto 0);
+	when "001" => 
+		out_colour <= out_colour_raw_lines(39 downto 8);
+	when "010" => 
+		out_colour <= out_colour_raw_lines(47 downto 16);
+	when "011" => 
+		out_colour <= out_colour_raw_lines(55 downto 24);
+	when "100" => 
+		out_colour <= out_colour_raw_lines(63 downto 32);
+	when "101" => 
+		out_colour(23 downto 0) <= out_colour_raw_lines(63 downto 40);
+		out_colour(31 downto 24) <= out_colour_raw_lines(7 downto 0);
+	when "110" => 
+		out_colour(15 downto 0) <= out_colour_raw_lines(63 downto 48);
+		out_colour(31 downto 16) <= out_colour_raw_lines(15 downto 0);
+	when "111" => 
+		out_colour(7 downto 0) <= out_colour_raw_lines(63 downto 56);		
+		out_colour(31 downto 8) <= out_colour_raw_lines(23 downto 0);
+	end case;
+end process;
 
-process (clk_pixel_in, hcnt, out_frame_start)
+--1 2
+--3 4
+-- shift pixels, when next requested
+-- moving to the right
+process(crtc_inc_line, out_next_x, out_next_x_size, out_haddr_reg)
 begin
-	if clk_pixel_in'event and clk_pixel_in = '1' then
-		if hcnt = h_end_count then
-			hcnt <= (others => '0');
-		else
-			hcnt <= hcnt + 1;
-		end if;
-		if hcnt = h_sync_on then
-			if (vcnt = v_end_count) then
-				vcnt <= (others => '0');
-			else
-				vcnt <= vcnt + 1;
-			end if;
-		end if;
+	out_haddr_next <= out_haddr_reg;
 
-		if (out_frame_start='1' and (vcnt <= (v_sync_off-4) or vcnt >= (v_sync_off+4))) then
-			vcnt <= std_logic_vector(to_unsigned(v_sync_off,12));
-		end if;
+	if (out_next_x='1') then
+		out_haddr_next <= std_logic_vector(unsigned(out_haddr_reg) + unsigned(out_next_x_size)); --read next address, next cycle
 	end if;
+
+	if (crtc_inc_line='1') then
+		out_haddr_next <= (others=>'0') ; --"00000000100"; --param?
+	end if;
 end process;
 
-hsync_next	<= '0' when (hcnt <= h_sync_on) or (hcnt > h_sync_off) else '1';
-vsync_next	<= '0' when (vcnt <= v_sync_on) or (vcnt > v_sync_off) else '1';
-blank_next	<= '1' when (hcnt > h_pixels_across) or (vcnt > v_pixels_down) else '0';
+process(out_pixels_reg, out_next_x_reg,crtc_inc_line)
+begin
+	for i in 0 to 2 loop
+		for j in 0 to 3 loop
+				out_pixels_next(pixel4x4_idx(i,j)) <= out_pixels_reg(pixel4x4_idx(i,j));
+		end loop;
+	end loop;
+	--out_pixels_next(0 to 2,0 to 3,0 to 2) <= out_pixels_reg(0 to 2,0 to 3,0 to 2);
 
--- TODO -- allow ZPU to write these - simple CRTC!
-process(out_pal)
+	if (out_next_x_reg='1') then		
+		for i in 0 to 2 loop
+			for j in 0 to 3 loop
+					out_pixels_next(pixel4x4_idx(i,j)) <= out_pixels_reg(pixel4x4_idx(i+1,j));
+			end loop;
+		end loop;		
+		--out_pixels_next(0 to 2,0 to 3,0 to 2) <= out_pixels_reg(1 to 3,0 to 3,0 to 2);
+	end if;
+
+	if (crtc_inc_line='1') then
+		for i in 0 to 2 loop
+			for j in 0 to 3 loop
+				out_pixels_next(pixel4x4_idx(i,j)).red <= x"00";
+				out_pixels_next(pixel4x4_idx(i,j)).green <= x"00";
+				out_pixels_next(pixel4x4_idx(i,j)).blue <= x"00";
+			end loop;
+		end loop;			
+		--out_pixels_next(0 to 2,0 to 3,0 to 2) <= (others=>'0');
+	end if;
+end process;
+
+process(out_next_y, out_vaddr_reg, crtc_inc_frame)
 begin
-	if (out_pal = '1') then
-		h_pixels_across	 <= 720 - 1;
-		h_sync_on <= 732 - 1;
-		h_sync_off <= 795 - 1;
-		h_end_count <= 864 - 1;
-		v_pixels_down <= 576 - 1;
-		v_sync_on <=  581 - 1;
-		v_sync_off <= 586 - 1;
-		v_end_count <=  625 - 1;
-	else
-		h_pixels_across	 <= 720 - 1;
-		h_sync_on <= 736 -1;
-		h_sync_off <= 798 -1;
-		h_end_count <= 858 -1;
-		v_pixels_down <= 480 -1;
-		v_sync_on <=  489 -1;
-		v_sync_off <= 495 -1;
-		v_end_count <=  525 -1;
+	out_vaddr_next <= out_vaddr_reg;
+
+	if (out_next_y='1') then
+		out_vaddr_next <= out_vaddr_reg + 1; 
 	end if;
+
+	if (crtc_inc_frame='1') then
+		out_vaddr_next <= (others=>'0');
+	end if;
 end process;
 
+-- colour palette
+-- TODO- share!!
+palette4 : entity work.gtia_palette
+	port map (PAL=>out_pal,ATARI_COLOUR=>out_colour(7 downto 0), R_next=>out_pixels_next(pixel4x4_idx(3,0)).red, G_next=>out_pixels_next(pixel4x4_idx(3,0)).green, B_next=>out_pixels_next(pixel4x4_idx(3,0)).blue);		
+palette5 : entity work.gtia_palette
+	port map (PAL=>out_pal,ATARI_COLOUR=>out_colour(15 downto 8), R_next=>out_pixels_next(pixel4x4_idx(3,1)).red, G_next=>out_pixels_next(pixel4x4_idx(3,1)).green, B_next=>out_pixels_next(pixel4x4_idx(3,1)).blue);		
+palette6 : entity work.gtia_palette
+	port map (PAL=>out_pal,ATARI_COLOUR=>out_colour(23 downto 16), R_next=>out_pixels_next(pixel4x4_idx(3,2)).red, G_next=>out_pixels_next(pixel4x4_idx(3,2)).green, B_next=>out_pixels_next(pixel4x4_idx(3,2)).blue);		
+palette7 : entity work.gtia_palette
+	port map (PAL=>out_pal,ATARI_COLOUR=>out_colour(31 downto 24), R_next=>out_pixels_next(pixel4x4_idx(3,3)).red, G_next=>out_pixels_next(pixel4x4_idx(3,3)).green, B_next=>out_pixels_next(pixel4x4_idx(3,3)).blue);			
+
+multiscale_impl : entity work.multiscale
+	generic map(
+		enable_area => enable_area_scaler,
+		enable_polyphasic => enable_polyphasic_scaler
+   )
+	port map 
+	(
+		CLOCK => clk_pixel_in,
+		RESET_N => reset_n,
+		
+		scaler_select => crtc_scaler_select,
+
+		pixels => out_pixels_reg,
+		next_y_in => crtc_inc_line,      --reset_x
+		next_frame_in => crtc_inc_frame, --reset y
+		next_x => out_next_x,
+		next_y => out_next_y,
+		next_x_size => out_next_x_size,
+		field2 => crtc_field2, -- field 2 is half lower
+		
+		hsync_in => crtc_hsync,
+		vsync_in => crtc_vsync,
+		blank_in => crtc_blank,
+
+		r => red_next,
+		g => green_next,
+		b => blue_next,
+		hsync => hsync_next,
+		vsync => vsync_next,
+		blank => blank_next,
+				
+		sda => sda,
+		scl => scl		
+	);	
+
+-- Resynchronization logic
+-- Compare what is in line buffer, with what we are reading	
+	out_frame_start <= out_frame_start_flip_reg xor out_frame_start_flip_next;
+	out_line_start <= out_line_start_flip_reg xor out_line_start_flip_next;
+
+	process(out_vaddr_in_reg, out_frame_start, out_line_start)
+	begin
+		out_vaddr_in_next <= out_vaddr_in_reg;
+
+		if (out_frame_start='1') then
+			out_vaddr_in_next <= (others=>'0');		
+		elsif (out_line_start='1') then
+			out_vaddr_in_next <= out_vaddr_in_reg+1;
+		end if;
+	end process;	
+	
+	process(out_frame_start,out_resync_required_reg,out_vaddr_in_reg,out_vaddr_reg)		
+		variable lowerbound : std_logic_vector(8 downto 0);
+		variable upperbound : std_logic_vector(8 downto 0);
+	begin		
+		out_resync_required_next <= out_resync_required_reg;
+		out_resync_frame_start <= '0';			
+		
+		lowerbound := out_vaddr_in_reg-7;
+		upperbound := out_vaddr_in_reg-4;
+		
+		if (not(out_vaddr_reg>=lowerbound and out_vaddr_reg<=upperbound) and or_reduce(out_vaddr_reg(7 downto 3))='1' and or_reduce(out_vaddr_in_reg(7 downto 3))='1') then
+			out_resync_required_next <= '1';
+		end if;
+		
+		if (out_resync_required_reg='1' and out_vaddr_in_reg="00000110") then
+			out_resync_required_next <= '0';
+			out_resync_frame_start <= '1';
+		end if;	
+	end process;
+
+crtc_impl : entity work.crtc
+	port map
+	(
+		clk_pixel => clk_pixel_in,
+		reset_n => reset_n,
+
+		resync_start_frame => out_resync_frame_start,
+
+		hsync => crtc_hsync,
+		vsync => crtc_vsync,
+		blank => crtc_blank,
+
+		inc_line => crtc_inc_line,
+		inc_frame => crtc_inc_frame,
+		field2 => crtc_field2, -- field 2 is half lower		
+
+		clock_select => clk_hdmi_select,
+		video_id_code => crtc_video_id_code,
+		scaler_select => crtc_scaler_select,
+
+		sda => sda,
+		scl => scl
+	);
+
 hdmiav_inst : entity work.hdmi
 port map (
 	I_CLK_PIXEL => clk_pixel_in,
@@ -341,6 +541,7 @@
 	I_R		=> red_reg,
 	I_G		=> green_reg,
 	I_B		=> blue_reg,
+	I_VIDEO_ID_CODE => crtc_video_id_code,
 	O_R	=> hdmi_encoded_red,
 	O_G	=> hdmi_encoded_green,
 	O_B	=> hdmi_encoded_blue);
@@ -381,25 +582,48 @@
 	end case;
 end process;
 
-process (CLK_HDMI_IN)
+process (CLK_HDMI_IN,RESET_N)
 begin
-	if (CLK_HDMI_IN'event and CLK_HDMI_IN = '1') then
-		if mod5(2) = '1' then
-			mod5 <= "000";
-			shift_r <= encoded_red_reg;
-			shift_g <= encoded_green_reg;
-			shift_b <= encoded_blue_reg;
-			shift_clk <= "0000011111";
-		else
-			mod5 <= mod5 + "001";
-			shift_r <= "00" & shift_r(9 downto 2);
-			shift_g <= "00" & shift_g(9 downto 2);
-			shift_b <= "00" & shift_b(9 downto 2);
-			shift_clk <= "00" & shift_clk(9 downto 2);
-		end if;
+	if (RESET_N='0') then
+		mod5_reg <= "00001";
+		shift_r_reg <= (others=>'0');
+		shift_g_reg <= (others=>'0');
+		shift_b_reg <= (others=>'0');
+		shift_clk_reg <= (others=>'0');
+		nshift_r_reg <= (others=>'0');
+		nshift_g_reg <= (others=>'0');
+		nshift_b_reg <= (others=>'0');
+		nshift_clk_reg <= (others=>'0');
+	elsif (CLK_HDMI_IN'event and CLK_HDMI_IN = '1') then
+		mod5_reg <= mod5_next;
+		shift_r_reg <= shift_r_next;
+		shift_g_reg <= shift_g_next;
+		shift_b_reg <= shift_b_next;
+		shift_clk_reg <= shift_clk_next;
+		nshift_r_reg <= not(shift_r_next);
+		nshift_g_reg <= not(shift_g_next);
+		nshift_b_reg <= not(shift_b_next);
+		nshift_clk_reg <= not(shift_clk_next);
 	end if;
 end process;
+	
+process(encoded_red_reg,encoded_green_reg,encoded_blue_reg,shift_r_reg,shift_g_reg,shift_b_reg,mod5_reg,shift_clk_reg)
+begin		
+	mod5_next <= mod5_reg(3 downto 0)&mod5_reg(4);
 
+	if mod5_reg(0) = '1' then			
+		shift_r_next <= encoded_red_reg;
+		shift_g_next <= encoded_green_reg;
+		shift_b_next <= encoded_blue_reg;
+		shift_clk_next <= "0000011111";
+	else
+		shift_r_next <= "00" & shift_r_reg(9 downto 2);
+		shift_g_next <= "00" & shift_g_reg(9 downto 2);
+		shift_b_next <= "00" & shift_b_reg(9 downto 2);
+		shift_clk_next <= "00" & shift_clk_reg(9 downto 2);
+	end if;		
+end process;
+	
 
 process(clk_pixel_in)
 begin
@@ -409,6 +633,18 @@
 		audio_right_reg1 <= audio_right_signed;
 		audio_right_reg2 <= audio_right_reg1;
 
+		out_haddr_reg <= out_haddr_next;
+		out_vaddr_reg <= out_vaddr_next;
+		out_vaddr_in_reg <= out_vaddr_in_next;
+
+		out_pixels_reg <= out_pixels_next;
+		out_next_x_reg <= out_next_x;
+
+		out_frame_start_flip_reg <= out_frame_start_flip_next;
+		out_line_start_flip_reg <= out_line_start_flip_next;
+		
+		out_resync_required_reg <= out_resync_required_next;
+		
 		hsync_reg <= hsync_next;
 		vsync_reg <= vsync_next;
 		blank_reg <= blank_next;
@@ -457,10 +693,9 @@
 O_blue <= hs_blue_reg2(7 downto 4)&hs_blue_reg(3 downto 0);
 
 -- TMDS outputs - with specified timings
-O_TMDS_H <= shift_r(0) & not(shift_r(0)) & shift_g(0) & not(shift_g(0)) & shift_b(0) & not(shift_b(0)) & shift_clk(0) & not(shift_clk(0));
-O_TMDS_L <= shift_r(1) & not(shift_r(1)) & shift_g(1) & not(shift_g(1)) & shift_b(1) & not(shift_b(1)) & shift_clk(1) & not(shift_clk(1));
+O_TMDS_H <= shift_r_reg(0) & nshift_r_reg(0) & shift_g_reg(0) & nshift_g_reg(0) & shift_b_reg(0) & nshift_b_reg(0) & shift_clk_reg(0) & nshift_clk_reg(0);
+O_TMDS_L <= shift_r_reg(1) & nshift_r_reg(1) & shift_g_reg(1) & nshift_g_reg(1) & shift_b_reg(1) & nshift_b_reg(1) & shift_clk_reg(1) & nshift_clk_reg(1);
 
-
 end vhdl;
 
 
Index: eclaireXL_ITX/pll_hdmi/pll_hdmi_0002.qip
===================================================================
--- eclaireXL_ITX/pll_hdmi/pll_hdmi_0002.qip	(revision 973)
+++ eclaireXL_ITX/pll_hdmi/pll_hdmi_0002.qip	(revision 974)
@@ -1,4 +1,4 @@
 set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
  
-set_instance_assignment -name PLL_AUTO_RESET OFF -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
 set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi_0002*|altera_pll:altera_pll_i*|*"
Index: eclaireXL_ITX/pll_hdmi/pll_hdmi_0002.v
===================================================================
--- eclaireXL_ITX/pll_hdmi/pll_hdmi_0002.v	(revision 973)
+++ eclaireXL_ITX/pll_hdmi/pll_hdmi_0002.v	(revision 974)
@@ -10,9 +10,6 @@
 	// interface 'outclk0'
 	output wire outclk_0,
 
-	// interface 'outclk1'
-	output wire outclk_1,
-
 	// interface 'locked'
 	output wire locked
 );
@@ -19,13 +16,13 @@
 
 	altera_pll #(
 		.fractional_vco_multiplier("false"),
-		.reference_clock_frequency("50.0 MHz"),
+		.reference_clock_frequency("54.0 MHz"),
 		.operation_mode("normal"),
-		.number_of_clocks(2),
-		.output_clock_frequency0("27.000000 MHz"),
+		.number_of_clocks(1),
+		.output_clock_frequency0("148.500000 MHz"),
 		.phase_shift0("0 ps"),
 		.duty_cycle0(50),
-		.output_clock_frequency1("135.000000 MHz"),
+		.output_clock_frequency1("0 MHz"),
 		.phase_shift1("0 ps"),
 		.duty_cycle1(50),
 		.output_clock_frequency2("0 MHz"),
@@ -80,7 +77,7 @@
 		.pll_subtype("General")
 	) altera_pll_i (
 		.rst	(rst),
-		.outclk	({outclk_1, outclk_0}),
+		.outclk	({outclk_0}),
 		.locked	(locked),
 		.fboutclk	( ),
 		.fbclk	(1'b0),
Index: eclaireXL_ITX/pll_hdmi.bsf
===================================================================
--- eclaireXL_ITX/pll_hdmi.bsf	(revision 973)
+++ eclaireXL_ITX/pll_hdmi.bsf	(revision 974)
@@ -4,7 +4,7 @@
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 2016  Intel Corporation. All rights reserved.
+Copyright (C) 2018  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -12,18 +12,17 @@
 associated documentation or information are expressly subject 
 to the terms and conditions of the Intel Program License 
 Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Intel and sold by Intel or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
 */
 (header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 160 184)
+	(rect 0 0 160 144)
 	(text "pll_hdmi" (rect 56 -1 87 11)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 168 20 180)(font "Arial" ))
+	(text "inst" (rect 8 128 20 140)(font "Arial" ))
 	(port
 		(pt 0 72)
 		(input)
@@ -48,17 +47,10 @@
 	(port
 		(pt 160 112)
 		(output)
-		(text "outclk_1" (rect 0 0 31 12)(font "Arial" (font_size 8)))
-		(text "outclk_1" (rect 119 101 167 112)(font "Arial" (font_size 8)))
+		(text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8)))
+		(text "locked" (rect 127 101 163 112)(font "Arial" (font_size 8)))
 		(line (pt 160 112)(pt 112 112)(line_width 1))
 	)
-	(port
-		(pt 160 152)
-		(output)
-		(text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8)))
-		(text "locked" (rect 127 141 163 152)(font "Arial" (font_size 8)))
-		(line (pt 160 152)(pt 112 152)(line_width 1))
-	)
 	(drawing
 		(text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9)))
 		(text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0)))
@@ -66,15 +58,13 @@
 		(text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0)))
 		(text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9)))
 		(text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0)))
-		(text "outclk1" (rect 113 83 268 179)(font "Arial" (color 128 0 0)(font_size 9)))
-		(text "clk" (rect 97 107 212 224)(font "Arial" (color 0 0 0)))
-		(text "locked" (rect 113 123 262 259)(font "Arial" (color 128 0 0)(font_size 9)))
-		(text "export" (rect 82 147 200 304)(font "Arial" (color 0 0 0)))
-		(text " altera_pll " (rect 118 168 308 346)(font "Arial" ))
+		(text "locked" (rect 113 83 262 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 82 107 200 224)(font "Arial" (color 0 0 0)))
+		(text " altera_pll " (rect 118 128 308 266)(font "Arial" ))
 		(line (pt 48 32)(pt 112 32)(line_width 1))
-		(line (pt 112 32)(pt 112 168)(line_width 1))
-		(line (pt 48 168)(pt 112 168)(line_width 1))
-		(line (pt 48 32)(pt 48 168)(line_width 1))
+		(line (pt 112 32)(pt 112 128)(line_width 1))
+		(line (pt 48 128)(pt 112 128)(line_width 1))
+		(line (pt 48 32)(pt 48 128)(line_width 1))
 		(line (pt 49 52)(pt 49 76)(line_width 1))
 		(line (pt 50 52)(pt 50 76)(line_width 1))
 		(line (pt 49 92)(pt 49 116)(line_width 1))
@@ -83,11 +73,9 @@
 		(line (pt 110 52)(pt 110 76)(line_width 1))
 		(line (pt 111 92)(pt 111 116)(line_width 1))
 		(line (pt 110 92)(pt 110 116)(line_width 1))
-		(line (pt 111 132)(pt 111 156)(line_width 1))
-		(line (pt 110 132)(pt 110 156)(line_width 1))
 		(line (pt 0 0)(pt 160 0)(line_width 1))
-		(line (pt 160 0)(pt 160 184)(line_width 1))
-		(line (pt 0 184)(pt 160 184)(line_width 1))
-		(line (pt 0 0)(pt 0 184)(line_width 1))
+		(line (pt 160 0)(pt 160 144)(line_width 1))
+		(line (pt 0 144)(pt 160 144)(line_width 1))
+		(line (pt 0 0)(pt 0 144)(line_width 1))
 	)
 )
Index: eclaireXL_ITX/pll_hdmi.ppf
===================================================================
--- eclaireXL_ITX/pll_hdmi.ppf	(revision 973)
+++ eclaireXL_ITX/pll_hdmi.ppf	(revision 974)
@@ -8,7 +8,6 @@
   <pin name="refclk" direction="input" scope="external" />
   <pin name="rst" direction="input" scope="external" />
   <pin name="outclk_0" direction="output" scope="external" />
-  <pin name="outclk_1" direction="output" scope="external" />
   <pin name="locked" direction="output" scope="external" />
  </global>
 </pinplan>
Index: eclaireXL_ITX/pll_hdmi.sip
===================================================================
--- eclaireXL_ITX/pll_hdmi.sip	(revision 973)
+++ eclaireXL_ITX/pll_hdmi.sip	(revision 974)
@@ -1,5 +1,5 @@
 set_global_assignment -entity "pll_hdmi" -library "lib_pll_hdmi" -name IP_TOOL_NAME "altera_pll"
-set_global_assignment -entity "pll_hdmi" -library "lib_pll_hdmi" -name IP_TOOL_VERSION "16.1"
+set_global_assignment -entity "pll_hdmi" -library "lib_pll_hdmi" -name IP_TOOL_VERSION "18.0"
 set_global_assignment -entity "pll_hdmi" -library "lib_pll_hdmi" -name IP_TOOL_ENV "mwpim"
 set_global_assignment -library "lib_pll_hdmi" -name SPD_FILE [file join $::quartus(sip_path) "pll_hdmi.spd"]
 
Index: eclaireXL_ITX/pll_hdmi2/pll_hdmi2_0002.qip
===================================================================
--- eclaireXL_ITX/pll_hdmi2/pll_hdmi2_0002.qip	(nonexistent)
+++ eclaireXL_ITX/pll_hdmi2/pll_hdmi2_0002.qip	(revision 974)
@@ -0,0 +1,4 @@
+set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*pll_hdmi2_0002*|altera_pll:altera_pll_i*|*"
+ 
+set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_hdmi2_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_hdmi2_0002*|altera_pll:altera_pll_i*|*"
Index: eclaireXL_ITX/pll_hdmi2.bsf
===================================================================
--- eclaireXL_ITX/pll_hdmi2.bsf	(nonexistent)
+++ eclaireXL_ITX/pll_hdmi2.bsf	(revision 974)
@@ -0,0 +1,92 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2018  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 184)
+	(text "pll_hdmi2" (rect 53 -1 89 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 168 20 180)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
+		(text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 48 72)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8)))
+		(text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 48 112)(line_width 1))
+	)
+	(port
+		(pt 160 72)
+		(output)
+		(text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8)))
+		(text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8)))
+		(line (pt 160 72)(pt 112 72)(line_width 1))
+	)
+	(port
+		(pt 160 112)
+		(output)
+		(text "outclk_1" (rect 0 0 31 12)(font "Arial" (font_size 8)))
+		(text "outclk_1" (rect 119 101 167 112)(font "Arial" (font_size 8)))
+		(line (pt 160 112)(pt 112 112)(line_width 1))
+	)
+	(port
+		(pt 160 152)
+		(output)
+		(text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8)))
+		(text "locked" (rect 127 141 163 152)(font "Arial" (font_size 8)))
+		(line (pt 160 152)(pt 112 152)(line_width 1))
+	)
+	(drawing
+		(text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0)))
+		(text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0)))
+		(text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0)))
+		(text "outclk1" (rect 113 83 268 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 97 107 212 224)(font "Arial" (color 0 0 0)))
+		(text "locked" (rect 113 123 262 259)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 82 147 200 304)(font "Arial" (color 0 0 0)))
+		(text " altera_pll " (rect 118 168 308 346)(font "Arial" ))
+		(line (pt 48 32)(pt 112 32)(line_width 1))
+		(line (pt 112 32)(pt 112 168)(line_width 1))
+		(line (pt 48 168)(pt 112 168)(line_width 1))
+		(line (pt 48 32)(pt 48 168)(line_width 1))
+		(line (pt 49 52)(pt 49 76)(line_width 1))
+		(line (pt 50 52)(pt 50 76)(line_width 1))
+		(line (pt 49 92)(pt 49 116)(line_width 1))
+		(line (pt 50 92)(pt 50 116)(line_width 1))
+		(line (pt 111 52)(pt 111 76)(line_width 1))
+		(line (pt 110 52)(pt 110 76)(line_width 1))
+		(line (pt 111 92)(pt 111 116)(line_width 1))
+		(line (pt 110 92)(pt 110 116)(line_width 1))
+		(line (pt 111 132)(pt 111 156)(line_width 1))
+		(line (pt 110 132)(pt 110 156)(line_width 1))
+		(line (pt 0 0)(pt 160 0)(line_width 1))
+		(line (pt 160 0)(pt 160 184)(line_width 1))
+		(line (pt 0 184)(pt 160 184)(line_width 1))
+		(line (pt 0 0)(pt 0 184)(line_width 1))
+	)
+)
Index: eclaireXL_ITX/pll_hdmi2.qip
===================================================================
--- eclaireXL_ITX/pll_hdmi2.qip	(nonexistent)
+++ eclaireXL_ITX/pll_hdmi2.qip	(revision 974)
@@ -0,0 +1,337 @@
+set_global_assignment -entity "pll_hdmi2" -library "pll_hdmi2" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_hdmi2" -library "pll_hdmi2" -name IP_TOOL_VERSION "18.0"
+set_global_assignment -entity "pll_hdmi2" -library "pll_hdmi2" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "pll_hdmi2" -name MISC_FILE [file join $::quartus(qip_path) "pll_hdmi2.cmp"]
+set_global_assignment -entity "pll_hdmi2" -library "pll_hdmi2" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
+set_global_assignment -entity "pll_hdmi2" -library "pll_hdmi2" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -entity "pll_hdmi2" -library "pll_hdmi2" -name IP_QSYS_MODE "UNKNOWN"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -entity "pll_hdmi2" -library "pll_hdmi2" -name IP_COMPONENT_NAME "cGxsX2hkbWky"
+set_global_assignment -entity "pll_hdmi2" -library "pll_hdmi2" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "pll_hdmi2" -library "pll_hdmi2" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_hdmi2" -library "pll_hdmi2" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_hdmi2" -library "pll_hdmi2" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "pll_hdmi2" -library "pll_hdmi2" -name IP_COMPONENT_VERSION "MTguMA=="
+set_global_assignment -entity "pll_hdmi2" -library "pll_hdmi2" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_NAME "cGxsX2hkbWkyXzAwMDI="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_VERSION "MTguMA=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::MTQ4LjU=::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::MTQ4LjUgTUh6::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::ZGlyZWN0::T3BlcmF0aW9uIE1vZGU="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::ZGlyZWN0::b3BlcmF0aW9uX21vZGU="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::Mg==::TnVtYmVyIE9mIENsb2Nrcw=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::Mg==::bnVtYmVyX29mX2Nsb2Nrcw=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NzQuMjU=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::NQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MTA=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MzcxLjI1::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::NQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::Mg==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NzQuMjUwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MzcxLjI1MDAwMCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T24=::UExMIEF1dG8gUmVzZXQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MywyLDEsMSxmYWxzZSxmYWxzZSx0cnVlLGZhbHNlLDMsMiwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDI1NiwyNTYsMSwwLHBoX211eF9jbGssdHJ1ZSxmYWxzZSwyLDMwLDIwMDAsMzcxLjI1IE1IeiwxLG5vbmUsZ2xiLG1fY250LHBoX211eF9jbGssdHJ1ZQ==::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
+
+set_global_assignment -library "pll_hdmi2" -name VHDL_FILE [file join $::quartus(qip_path) "pll_hdmi2.vhd"]
+set_global_assignment -library "pll_hdmi2" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_hdmi2/pll_hdmi2_0002.v"]
+set_global_assignment -library "pll_hdmi2" -name QIP_FILE [file join $::quartus(qip_path) "pll_hdmi2/pll_hdmi2_0002.qip"]
+
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_TOOL_VERSION "18.0"
+set_global_assignment -entity "pll_hdmi2_0002" -library "pll_hdmi2" -name IP_TOOL_ENV "mwpim"
Index: eclaireXL_ITX/pll_hdmi2.vhd
===================================================================
--- eclaireXL_ITX/pll_hdmi2.vhd	(nonexistent)
+++ eclaireXL_ITX/pll_hdmi2.vhd	(revision 974)
@@ -0,0 +1,274 @@
+-- megafunction wizard: %PLL Intel FPGA IP v18.0%
+-- GENERATION: XML
+-- pll_hdmi2.vhd
+
+-- Generated using ACDS version 18.0 614
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity pll_hdmi2 is
+	port (
+		refclk   : in  std_logic := '0'; --  refclk.clk
+		rst      : in  std_logic := '0'; --   reset.reset
+		outclk_0 : out std_logic;        -- outclk0.clk
+		outclk_1 : out std_logic;        -- outclk1.clk
+		locked   : out std_logic         --  locked.export
+	);
+end entity pll_hdmi2;
+
+architecture rtl of pll_hdmi2 is
+	component pll_hdmi2_0002 is
+		port (
+			refclk   : in  std_logic := 'X'; -- clk
+			rst      : in  std_logic := 'X'; -- reset
+			outclk_0 : out std_logic;        -- clk
+			outclk_1 : out std_logic;        -- clk
+			locked   : out std_logic         -- export
+		);
+	end component pll_hdmi2_0002;
+
+begin
+
+	pll_hdmi2_inst : component pll_hdmi2_0002
+		port map (
+			refclk   => refclk,   --  refclk.clk
+			rst      => rst,      --   reset.reset
+			outclk_0 => outclk_0, -- outclk0.clk
+			outclk_1 => outclk_1, -- outclk1.clk
+			locked   => locked    --  locked.export
+		);
+
+end architecture rtl; -- of pll_hdmi2
+-- Retrieval info: <?xml version="1.0"?>
+--<!--
+--	Generated by Altera MegaWizard Launcher Utility version 1.0
+--	************************************************************
+--	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--	************************************************************
+--	Copyright (C) 1991-2020 Altera Corporation
+--	Any megafunction design, and related net list (encrypted or decrypted),
+--	support information, device programming or simulation file, and any other
+--	associated documentation or information provided by Altera or a partner
+--	under Altera's Megafunction Partnership Program may be used only to
+--	program PLD devices (but not masked PLD devices) from Altera.  Any other
+--	use of such megafunction design, net list, support information, device
+--	programming or simulation file, or any other related documentation or
+--	information is prohibited for any other purpose, including, but not
+--	limited to modification, reverse engineering, de-compiling, or use with
+--	any other silicon devices, unless such use is explicitly licensed under
+--	a separate agreement with Altera or a megafunction partner.  Title to
+--	the intellectual property, including patents, copyrights, trademarks,
+--	trade secrets, or maskworks, embodied in any such megafunction design,
+--	net list, support information, device programming or simulation file, or
+--	any other related documentation or information provided by Altera or a
+--	megafunction partner, remains with Altera, the megafunction partner, or
+--	their respective licensors.  No other licenses, including any licenses
+--	needed under any third party's intellectual property, are provided herein.
+---->
+-- Retrieval info: <instance entity-name="altera_pll" version="18.0" >
+-- Retrieval info: 	<generic name="debug_print_output" value="false" />
+-- Retrieval info: 	<generic name="debug_use_rbc_taf_method" value="false" />
+-- Retrieval info: 	<generic name="device_family" value="Cyclone V" />
+-- Retrieval info: 	<generic name="device" value="5CEBA2F17A7" />
+-- Retrieval info: 	<generic name="gui_device_speed_grade" value="1" />
+-- Retrieval info: 	<generic name="gui_pll_mode" value="Integer-N PLL" />
+-- Retrieval info: 	<generic name="gui_reference_clock_frequency" value="148.5" />
+-- Retrieval info: 	<generic name="gui_channel_spacing" value="0.0" />
+-- Retrieval info: 	<generic name="gui_operation_mode" value="direct" />
+-- Retrieval info: 	<generic name="gui_feedback_clock" value="Global Clock" />
+-- Retrieval info: 	<generic name="gui_fractional_cout" value="32" />
+-- Retrieval info: 	<generic name="gui_dsm_out_sel" value="1st_order" />
+-- Retrieval info: 	<generic name="gui_use_locked" value="true" />
+-- Retrieval info: 	<generic name="gui_en_adv_params" value="false" />
+-- Retrieval info: 	<generic name="gui_number_of_clocks" value="2" />
+-- Retrieval info: 	<generic name="gui_multiply_factor" value="1" />
+-- Retrieval info: 	<generic name="gui_frac_multiply_factor" value="1" />
+-- Retrieval info: 	<generic name="gui_divide_factor_n" value="1" />
+-- Retrieval info: 	<generic name="gui_cascade_counter0" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency0" value="74.25" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c0" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units0" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift0" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg0" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift0" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle0" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter1" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency1" value="371.25" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c1" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units1" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift1" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg1" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift1" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle1" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter2" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency2" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c2" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units2" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift2" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg2" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift2" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle2" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter3" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency3" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c3" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units3" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift3" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg3" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift3" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle3" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter4" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency4" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c4" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units4" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift4" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg4" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift4" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle4" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter5" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency5" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c5" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units5" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift5" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg5" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift5" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle5" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter6" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency6" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c6" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units6" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift6" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg6" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift6" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle6" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter7" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency7" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c7" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units7" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift7" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg7" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift7" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle7" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter8" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency8" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c8" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units8" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift8" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg8" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift8" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle8" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter9" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency9" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c9" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units9" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift9" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg9" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift9" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle9" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter10" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency10" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c10" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units10" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift10" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg10" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift10" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle10" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter11" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency11" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c11" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units11" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift11" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg11" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift11" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle11" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter12" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency12" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c12" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units12" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift12" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg12" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift12" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle12" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter13" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency13" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c13" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units13" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift13" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg13" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift13" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle13" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter14" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency14" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c14" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units14" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift14" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg14" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift14" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle14" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter15" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency15" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c15" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units15" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift15" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg15" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift15" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle15" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter16" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency16" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c16" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units16" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift16" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg16" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift16" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle16" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter17" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency17" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c17" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units17" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift17" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg17" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift17" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle17" value="50" />
+-- Retrieval info: 	<generic name="gui_pll_auto_reset" value="On" />
+-- Retrieval info: 	<generic name="gui_pll_bandwidth_preset" value="Auto" />
+-- Retrieval info: 	<generic name="gui_en_reconf" value="false" />
+-- Retrieval info: 	<generic name="gui_en_dps_ports" value="false" />
+-- Retrieval info: 	<generic name="gui_en_phout_ports" value="false" />
+-- Retrieval info: 	<generic name="gui_phout_division" value="1" />
+-- Retrieval info: 	<generic name="gui_mif_generate" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_mif_dps" value="false" />
+-- Retrieval info: 	<generic name="gui_dps_cntr" value="C0" />
+-- Retrieval info: 	<generic name="gui_dps_num" value="1" />
+-- Retrieval info: 	<generic name="gui_dps_dir" value="Positive" />
+-- Retrieval info: 	<generic name="gui_refclk_switch" value="false" />
+-- Retrieval info: 	<generic name="gui_refclk1_frequency" value="100.0" />
+-- Retrieval info: 	<generic name="gui_switchover_mode" value="Automatic Switchover" />
+-- Retrieval info: 	<generic name="gui_switchover_delay" value="0" />
+-- Retrieval info: 	<generic name="gui_active_clk" value="false" />
+-- Retrieval info: 	<generic name="gui_clk_bad" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_cascade_out" value="false" />
+-- Retrieval info: 	<generic name="gui_cascade_outclk_index" value="0" />
+-- Retrieval info: 	<generic name="gui_enable_cascade_in" value="false" />
+-- Retrieval info: 	<generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
+-- Retrieval info: </instance>
+-- IPFS_FILES : pll_hdmi2.vho
+-- RELATED_FILES: pll_hdmi2.vhd, pll_hdmi2_0002.v
Index: eclaireXL_ITX/pll_hdmi2_sim/cadence/cds.lib
===================================================================
--- eclaireXL_ITX/pll_hdmi2_sim/cadence/cds.lib	(nonexistent)
+++ eclaireXL_ITX/pll_hdmi2_sim/cadence/cds.lib	(revision 974)
@@ -0,0 +1,17 @@
+
+DEFINE std            $CDS_ROOT/tools/inca/files/STD/           
+DEFINE synopsys       $CDS_ROOT/tools/inca/files/SYNOPSYS/      
+DEFINE ieee           $CDS_ROOT/tools/inca/files/IEEE/          
+DEFINE ambit          $CDS_ROOT/tools/inca/files/AMBIT/         
+DEFINE vital_memory   $CDS_ROOT/tools/inca/files/VITAL_MEMORY/  
+DEFINE ncutils        $CDS_ROOT/tools/inca/files/NCUTILS/       
+DEFINE ncinternal     $CDS_ROOT/tools/inca/files/NCINTERNAL/    
+DEFINE ncmodels       $CDS_ROOT/tools/inca/files/NCMODELS/      
+DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work           ./libraries/work/                         
+DEFINE altera         ./libraries/altera/                       
+DEFINE lpm            ./libraries/lpm/                          
+DEFINE sgate          ./libraries/sgate/                        
+DEFINE altera_mf      ./libraries/altera_mf/                    
+DEFINE altera_lnsim   ./libraries/altera_lnsim/                 
+DEFINE cyclonev       ./libraries/cyclonev/                     
Index: eclaireXL_ITX/pll_hdmi2_sim/pll_hdmi2.vho
===================================================================
--- eclaireXL_ITX/pll_hdmi2_sim/pll_hdmi2.vho	(nonexistent)
+++ eclaireXL_ITX/pll_hdmi2_sim/pll_hdmi2.vho	(revision 974)
@@ -0,0 +1,308 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 18.0 cbx_mgl 2018:04:18:07:37:08:SJ cbx_simgen 2018:04:18:06:50:44:SJ  VERSION_END
+
+
+-- Copyright (C) 2018  Intel Corporation. All rights reserved.
+-- Your use of Intel Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Intel Program License 
+-- Subscription Agreement, the Intel Quartus Prime License Agreement,
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors.  Please
+-- refer to the applicable agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Intel disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY altera_lnsim;
+ USE altera_lnsim.altera_lnsim_components.all;
+
+--synthesis_resources = altera_pll 1 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  pll_hdmi2 IS 
+	 PORT 
+	 ( 
+		 locked	:	OUT  STD_LOGIC;
+		 outclk_0	:	OUT  STD_LOGIC;
+		 outclk_1	:	OUT  STD_LOGIC;
+		 refclk	:	IN  STD_LOGIC;
+		 rst	:	IN  STD_LOGIC
+	 ); 
+ END pll_hdmi2;
+
+ ARCHITECTURE RTL OF pll_hdmi2 IS
+
+	 ATTRIBUTE synthesis_clearbox : natural;
+	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+	 SIGNAL  wire_gnd	:	STD_LOGIC;
+	 SIGNAL  wire_pll_hdmi2_altera_pll_altera_pll_i_1098_locked	:	STD_LOGIC;
+	 SIGNAL  wire_pll_hdmi2_altera_pll_altera_pll_i_1098_outclk	:	STD_LOGIC_VECTOR (1 DOWNTO 0);
+ BEGIN
+
+	wire_gnd <= '0';
+	locked <= wire_pll_hdmi2_altera_pll_altera_pll_i_1098_locked;
+	outclk_0 <= wire_pll_hdmi2_altera_pll_altera_pll_i_1098_outclk(0);
+	outclk_1 <= wire_pll_hdmi2_altera_pll_altera_pll_i_1098_outclk(1);
+	pll_hdmi2_altera_pll_altera_pll_i_1098 :  altera_pll
+	  GENERIC MAP (
+		c_cnt_bypass_en0 => "false",
+		c_cnt_bypass_en1 => "false",
+		c_cnt_bypass_en10 => "false",
+		c_cnt_bypass_en11 => "false",
+		c_cnt_bypass_en12 => "false",
+		c_cnt_bypass_en13 => "false",
+		c_cnt_bypass_en14 => "false",
+		c_cnt_bypass_en15 => "false",
+		c_cnt_bypass_en16 => "false",
+		c_cnt_bypass_en17 => "false",
+		c_cnt_bypass_en2 => "false",
+		c_cnt_bypass_en3 => "false",
+		c_cnt_bypass_en4 => "false",
+		c_cnt_bypass_en5 => "false",
+		c_cnt_bypass_en6 => "false",
+		c_cnt_bypass_en7 => "false",
+		c_cnt_bypass_en8 => "false",
+		c_cnt_bypass_en9 => "false",
+		c_cnt_hi_div0 => 1,
+		c_cnt_hi_div1 => 1,
+		c_cnt_hi_div10 => 1,
+		c_cnt_hi_div11 => 1,
+		c_cnt_hi_div12 => 1,
+		c_cnt_hi_div13 => 1,
+		c_cnt_hi_div14 => 1,
+		c_cnt_hi_div15 => 1,
+		c_cnt_hi_div16 => 1,
+		c_cnt_hi_div17 => 1,
+		c_cnt_hi_div2 => 1,
+		c_cnt_hi_div3 => 1,
+		c_cnt_hi_div4 => 1,
+		c_cnt_hi_div5 => 1,
+		c_cnt_hi_div6 => 1,
+		c_cnt_hi_div7 => 1,
+		c_cnt_hi_div8 => 1,
+		c_cnt_hi_div9 => 1,
+		c_cnt_in_src0 => "ph_mux_clk",
+		c_cnt_in_src1 => "ph_mux_clk",
+		c_cnt_in_src10 => "ph_mux_clk",
+		c_cnt_in_src11 => "ph_mux_clk",
+		c_cnt_in_src12 => "ph_mux_clk",
+		c_cnt_in_src13 => "ph_mux_clk",
+		c_cnt_in_src14 => "ph_mux_clk",
+		c_cnt_in_src15 => "ph_mux_clk",
+		c_cnt_in_src16 => "ph_mux_clk",
+		c_cnt_in_src17 => "ph_mux_clk",
+		c_cnt_in_src2 => "ph_mux_clk",
+		c_cnt_in_src3 => "ph_mux_clk",
+		c_cnt_in_src4 => "ph_mux_clk",
+		c_cnt_in_src5 => "ph_mux_clk",
+		c_cnt_in_src6 => "ph_mux_clk",
+		c_cnt_in_src7 => "ph_mux_clk",
+		c_cnt_in_src8 => "ph_mux_clk",
+		c_cnt_in_src9 => "ph_mux_clk",
+		c_cnt_lo_div0 => 1,
+		c_cnt_lo_div1 => 1,
+		c_cnt_lo_div10 => 1,
+		c_cnt_lo_div11 => 1,
+		c_cnt_lo_div12 => 1,
+		c_cnt_lo_div13 => 1,
+		c_cnt_lo_div14 => 1,
+		c_cnt_lo_div15 => 1,
+		c_cnt_lo_div16 => 1,
+		c_cnt_lo_div17 => 1,
+		c_cnt_lo_div2 => 1,
+		c_cnt_lo_div3 => 1,
+		c_cnt_lo_div4 => 1,
+		c_cnt_lo_div5 => 1,
+		c_cnt_lo_div6 => 1,
+		c_cnt_lo_div7 => 1,
+		c_cnt_lo_div8 => 1,
+		c_cnt_lo_div9 => 1,
+		c_cnt_odd_div_duty_en0 => "false",
+		c_cnt_odd_div_duty_en1 => "false",
+		c_cnt_odd_div_duty_en10 => "false",
+		c_cnt_odd_div_duty_en11 => "false",
+		c_cnt_odd_div_duty_en12 => "false",
+		c_cnt_odd_div_duty_en13 => "false",
+		c_cnt_odd_div_duty_en14 => "false",
+		c_cnt_odd_div_duty_en15 => "false",
+		c_cnt_odd_div_duty_en16 => "false",
+		c_cnt_odd_div_duty_en17 => "false",
+		c_cnt_odd_div_duty_en2 => "false",
+		c_cnt_odd_div_duty_en3 => "false",
+		c_cnt_odd_div_duty_en4 => "false",
+		c_cnt_odd_div_duty_en5 => "false",
+		c_cnt_odd_div_duty_en6 => "false",
+		c_cnt_odd_div_duty_en7 => "false",
+		c_cnt_odd_div_duty_en8 => "false",
+		c_cnt_odd_div_duty_en9 => "false",
+		c_cnt_ph_mux_prst0 => 0,
+		c_cnt_ph_mux_prst1 => 0,
+		c_cnt_ph_mux_prst10 => 0,
+		c_cnt_ph_mux_prst11 => 0,
+		c_cnt_ph_mux_prst12 => 0,
+		c_cnt_ph_mux_prst13 => 0,
+		c_cnt_ph_mux_prst14 => 0,
+		c_cnt_ph_mux_prst15 => 0,
+		c_cnt_ph_mux_prst16 => 0,
+		c_cnt_ph_mux_prst17 => 0,
+		c_cnt_ph_mux_prst2 => 0,
+		c_cnt_ph_mux_prst3 => 0,
+		c_cnt_ph_mux_prst4 => 0,
+		c_cnt_ph_mux_prst5 => 0,
+		c_cnt_ph_mux_prst6 => 0,
+		c_cnt_ph_mux_prst7 => 0,
+		c_cnt_ph_mux_prst8 => 0,
+		c_cnt_ph_mux_prst9 => 0,
+		c_cnt_prst0 => 1,
+		c_cnt_prst1 => 1,
+		c_cnt_prst10 => 1,
+		c_cnt_prst11 => 1,
+		c_cnt_prst12 => 1,
+		c_cnt_prst13 => 1,
+		c_cnt_prst14 => 1,
+		c_cnt_prst15 => 1,
+		c_cnt_prst16 => 1,
+		c_cnt_prst17 => 1,
+		c_cnt_prst2 => 1,
+		c_cnt_prst3 => 1,
+		c_cnt_prst4 => 1,
+		c_cnt_prst5 => 1,
+		c_cnt_prst6 => 1,
+		c_cnt_prst7 => 1,
+		c_cnt_prst8 => 1,
+		c_cnt_prst9 => 1,
+		clock_name_0 => "UNUSED",
+		clock_name_1 => "UNUSED",
+		clock_name_2 => "UNUSED",
+		clock_name_3 => "UNUSED",
+		clock_name_4 => "UNUSED",
+		clock_name_5 => "UNUSED",
+		clock_name_6 => "UNUSED",
+		clock_name_7 => "UNUSED",
+		clock_name_8 => "UNUSED",
+		clock_name_global_0 => "false",
+		clock_name_global_1 => "false",
+		clock_name_global_2 => "false",
+		clock_name_global_3 => "false",
+		clock_name_global_4 => "false",
+		clock_name_global_5 => "false",
+		clock_name_global_6 => "false",
+		clock_name_global_7 => "false",
+		clock_name_global_8 => "false",
+		data_rate => 0,
+		deserialization_factor => 4,
+		duty_cycle0 => 50,
+		duty_cycle1 => 50,
+		duty_cycle10 => 50,
+		duty_cycle11 => 50,
+		duty_cycle12 => 50,
+		duty_cycle13 => 50,
+		duty_cycle14 => 50,
+		duty_cycle15 => 50,
+		duty_cycle16 => 50,
+		duty_cycle17 => 50,
+		duty_cycle2 => 50,
+		duty_cycle3 => 50,
+		duty_cycle4 => 50,
+		duty_cycle5 => 50,
+		duty_cycle6 => 50,
+		duty_cycle7 => 50,
+		duty_cycle8 => 50,
+		duty_cycle9 => 50,
+		fractional_vco_multiplier => "false",
+		m_cnt_bypass_en => "false",
+		m_cnt_hi_div => 1,
+		m_cnt_lo_div => 1,
+		m_cnt_odd_div_duty_en => "false",
+		mimic_fbclk_type => "gclk",
+		n_cnt_bypass_en => "false",
+		n_cnt_hi_div => 1,
+		n_cnt_lo_div => 1,
+		n_cnt_odd_div_duty_en => "false",
+		number_of_clocks => 2,
+		operation_mode => "direct",
+		output_clock_frequency0 => "74.250000 MHz",
+		output_clock_frequency1 => "371.250000 MHz",
+		output_clock_frequency10 => "0 MHz",
+		output_clock_frequency11 => "0 MHz",
+		output_clock_frequency12 => "0 MHz",
+		output_clock_frequency13 => "0 MHz",
+		output_clock_frequency14 => "0 MHz",
+		output_clock_frequency15 => "0 MHz",
+		output_clock_frequency16 => "0 MHz",
+		output_clock_frequency17 => "0 MHz",
+		output_clock_frequency2 => "0 MHz",
+		output_clock_frequency3 => "0 MHz",
+		output_clock_frequency4 => "0 MHz",
+		output_clock_frequency5 => "0 MHz",
+		output_clock_frequency6 => "0 MHz",
+		output_clock_frequency7 => "0 MHz",
+		output_clock_frequency8 => "0 MHz",
+		output_clock_frequency9 => "0 MHz",
+		phase_shift0 => "0 ps",
+		phase_shift1 => "0 ps",
+		phase_shift10 => "0 ps",
+		phase_shift11 => "0 ps",
+		phase_shift12 => "0 ps",
+		phase_shift13 => "0 ps",
+		phase_shift14 => "0 ps",
+		phase_shift15 => "0 ps",
+		phase_shift16 => "0 ps",
+		phase_shift17 => "0 ps",
+		phase_shift2 => "0 ps",
+		phase_shift3 => "0 ps",
+		phase_shift4 => "0 ps",
+		phase_shift5 => "0 ps",
+		phase_shift6 => "0 ps",
+		phase_shift7 => "0 ps",
+		phase_shift8 => "0 ps",
+		phase_shift9 => "0 ps",
+		pll_auto_clk_sw_en => "false",
+		pll_bw_sel => "low",
+		pll_bwctrl => 0,
+		pll_clk_loss_sw_en => "false",
+		pll_clk_sw_dly => 0,
+		pll_clkin_0_src => "clk_0",
+		pll_clkin_1_src => "clk_0",
+		pll_cp_current => 0,
+		pll_dsm_out_sel => "1st_order",
+		pll_extclk_0_cnt_src => "pll_extclk_cnt_src_vss",
+		pll_extclk_1_cnt_src => "pll_extclk_cnt_src_vss",
+		pll_fbclk_mux_1 => "glb",
+		pll_fbclk_mux_2 => "fb_1",
+		pll_fractional_cout => 24,
+		pll_fractional_division => 1,
+		pll_m_cnt_in_src => "ph_mux_clk",
+		pll_manu_clk_sw_en => "false",
+		pll_output_clk_frequency => "0 MHz",
+		pll_slf_rst => "false",
+		pll_subtype => "General",
+		pll_type => "General",
+		pll_vco_div => 1,
+		pll_vcoph_div => 1,
+		refclk1_frequency => "0 MHz",
+		reference_clock_frequency => "148.5 MHz",
+		sim_additional_refclk_cycles_to_lock => 0
+	  )
+	  PORT MAP ( 
+		fbclk => wire_gnd,
+		locked => wire_pll_hdmi2_altera_pll_altera_pll_i_1098_locked,
+		outclk => wire_pll_hdmi2_altera_pll_altera_pll_i_1098_outclk,
+		refclk => refclk,
+		rst => rst
+	  );
+
+ END RTL; --pll_hdmi2
+--synopsys translate_on
+--VALID FILE
Index: eclaireXL_ITX/pll_hdmi_sim/aldec/rivierapro_setup.tcl
===================================================================
--- eclaireXL_ITX/pll_hdmi_sim/aldec/rivierapro_setup.tcl	(revision 973)
+++ eclaireXL_ITX/pll_hdmi_sim/aldec/rivierapro_setup.tcl	(revision 974)
@@ -1,5 +1,5 @@
 
-# (C) 2001-2016 Altera Corporation. All rights reserved.
+# (C) 2001-2020 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 16.1 196 linux 2016.11.30.20:30:39
+# ACDS 18.0 614 linux 2020.02.02.21:06:19
 # ----------------------------------------
 # Auto-generated simulation script rivierapro_setup.tcl
 # ----------------------------------------
@@ -47,6 +47,8 @@
 # #
 # # Set any compilation options you require (this is unusual).
 # set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
 # #
 # # Call command to compile the Quartus EDA simulation library.
 # dev_com
@@ -111,12 +113,18 @@
 }
 
 if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/home/markw/fpga/intelFPGA_lite/16.1/quartus/"
+  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/18.0/quartus/"
 }
 
 if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
   set USER_DEFINED_COMPILE_OPTIONS ""
 }
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
 if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
   set USER_DEFINED_ELAB_OPTIONS ""
 }
@@ -170,23 +178,23 @@
 # Compile device library files
 alias dev_com {
   echo "\[exec\] dev_com"
-  eval vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
-  vlog  $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
-  vlog -v2k5 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v"    -work cyclonev    
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+  eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v"    -work cyclonev    
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
 }
 
 # ----------------------------------------
@@ -193,7 +201,7 @@
 # Compile the design files in correct order
 alias com {
   echo "\[exec\] com"
-  eval  vcom $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_hdmi.vho"
+  eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_hdmi.vho"
 }
 
 # ----------------------------------------
@@ -231,37 +239,41 @@
 alias h {
   echo "List Of Command Line Aliases"
   echo
-  echo "file_copy                     -- Copy ROM/RAM files to simulation directory"
+  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
   echo
-  echo "dev_com                       -- Compile device library files"
+  echo "dev_com                                           -- Compile device library files"
   echo
-  echo "com                           -- Compile the design files in correct order"
+  echo "com                                               -- Compile the design files in correct order"
   echo
-  echo "elab                          -- Elaborate top level design"
+  echo "elab                                              -- Elaborate top level design"
   echo
-  echo "elab_debug                    -- Elaborate the top level design with -dbg -O2 option"
+  echo "elab_debug                                        -- Elaborate the top level design with -dbg -O2 option"
   echo
-  echo "ld                            -- Compile all the design files and elaborate the top level design"
+  echo "ld                                                -- Compile all the design files and elaborate the top level design"
   echo
-  echo "ld_debug                      -- Compile all the design files and elaborate the top level design with -dbg -O2"
+  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -dbg -O2"
   echo
   echo 
   echo
   echo "List Of Variables"
   echo
-  echo "TOP_LEVEL_NAME                -- Top level module name."
-  echo "                                 For most designs, this should be overridden"
-  echo "                                 to enable the elab/elab_debug aliases."
+  echo "TOP_LEVEL_NAME                                    -- Top level module name."
+  echo "                                                     For most designs, this should be overridden"
+  echo "                                                     to enable the elab/elab_debug aliases."
   echo
-  echo "SYSTEM_INSTANCE_NAME          -- Instantiated system module name inside top level module."
+  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
   echo
-  echo "QSYS_SIMDIR                   -- Qsys base simulation directory."
+  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
   echo
-  echo "QUARTUS_INSTALL_DIR           -- Quartus installation directory."
+  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
   echo
-  echo "USER_DEFINED_COMPILE_OPTIONS  -- User-defined compile options, added to com/dev_com aliases."
+  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
   echo
-  echo "USER_DEFINED_ELAB_OPTIONS     -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo
+  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
 }
 file_copy
 h
Index: eclaireXL_ITX/pll_hdmi2_sim/mentor/msim_setup.tcl
===================================================================
--- eclaireXL_ITX/pll_hdmi2_sim/mentor/msim_setup.tcl	(nonexistent)
+++ eclaireXL_ITX/pll_hdmi2_sim/mentor/msim_setup.tcl	(revision 974)
@@ -0,0 +1,273 @@
+
+# (C) 2001-2020 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ----------------------------------------
+# Auto-generated simulation script msim_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     pll_hdmi2
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "mentor.do", and modify the text as directed.
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/mentor/msim_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog <compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run -a
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If pll_hdmi2 is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 18.0 614 linux 2020.02.02.21:28:40
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] { 
+  set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
+  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] { 
+  set TOP_LEVEL_NAME "pll_hdmi2"
+}
+
+if ![info exists QSYS_SIMDIR] { 
+  set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] { 
+  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/18.0/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
+  set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
+  set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+  echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib          ./libraries/     
+ensure_lib          ./libraries/work/
+vmap       work     ./libraries/work/
+vmap       work_lib ./libraries/work/
+if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+  ensure_lib              ./libraries/altera/      
+  vmap       altera       ./libraries/altera/      
+  ensure_lib              ./libraries/lpm/         
+  vmap       lpm          ./libraries/lpm/         
+  ensure_lib              ./libraries/sgate/       
+  vmap       sgate        ./libraries/sgate/       
+  ensure_lib              ./libraries/altera_mf/   
+  vmap       altera_mf    ./libraries/altera_mf/   
+  ensure_lib              ./libraries/altera_lnsim/
+  vmap       altera_lnsim ./libraries/altera_lnsim/
+  ensure_lib              ./libraries/cyclonev/    
+  vmap       cyclonev     ./libraries/cyclonev/    
+}
+
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+  echo "\[exec\] dev_com"
+  if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+    eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv"  -work altera_lnsim
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v"   -work cyclonev    
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+  }
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+  echo "\[exec\] com"
+  eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_hdmi2.vho"
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+  echo "\[exec\] elab"
+  eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with novopt option
+alias elab_debug {
+  echo "\[exec\] elab_debug"
+  eval vsim -novopt -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+  dev_com
+  com
+  elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -novopt
+alias ld_debug "
+  dev_com
+  com
+  elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+  echo "List Of Command Line Aliases"
+  echo
+  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
+  echo
+  echo "dev_com                                           -- Compile device library files"
+  echo
+  echo "com                                               -- Compile the design files in correct order"
+  echo
+  echo "elab                                              -- Elaborate top level design"
+  echo
+  echo "elab_debug                                        -- Elaborate the top level design with novopt option"
+  echo
+  echo "ld                                                -- Compile all the design files and elaborate the top level design"
+  echo
+  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -novopt"
+  echo
+  echo 
+  echo
+  echo "List Of Variables"
+  echo
+  echo "TOP_LEVEL_NAME                                    -- Top level module name."
+  echo "                                                     For most designs, this should be overridden"
+  echo "                                                     to enable the elab/elab_debug aliases."
+  echo
+  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
+  echo
+  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
+  echo
+  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
+  echo
+  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo
+  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h
Index: eclaireXL_ITX/pll_hdmi2_sim.f
===================================================================
--- eclaireXL_ITX/pll_hdmi2_sim.f	(nonexistent)
+++ eclaireXL_ITX/pll_hdmi2_sim.f	(revision 974)
@@ -0,0 +1 @@
+pll_hdmi2_sim/pll_hdmi2.vho
Index: eclaireXL_ITX/pll_hdmi_sim/pll_hdmi.vho
===================================================================
--- eclaireXL_ITX/pll_hdmi_sim/pll_hdmi.vho	(revision 973)
+++ eclaireXL_ITX/pll_hdmi_sim/pll_hdmi.vho	(revision 974)
@@ -1,8 +1,8 @@
 --IP Functional Simulation Model
---VERSION_BEGIN 16.1 cbx_mgl 2016:10:19:22:10:30:SJ cbx_simgen 2016:10:19:21:26:20:SJ  VERSION_END
+--VERSION_BEGIN 18.0 cbx_mgl 2018:04:18:07:37:08:SJ cbx_simgen 2018:04:18:06:50:44:SJ  VERSION_END
 
 
--- Copyright (C) 2016  Intel Corporation. All rights reserved.
+-- Copyright (C) 2018  Intel Corporation. All rights reserved.
 -- Your use of Intel Corporation's design tools, logic functions 
 -- and other software and tools, and its AMPP partner logic 
 -- functions, and any output files from any of the foregoing 
@@ -10,12 +10,11 @@
 -- associated documentation or information are expressly subject 
 -- to the terms and conditions of the Intel Program License 
 -- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel MegaCore Function License Agreement, or other 
--- applicable license agreement, including, without limitation, 
--- that your use is for the sole purpose of programming logic 
--- devices manufactured by Intel and sold by Intel or its 
--- authorized distributors.  Please refer to the applicable 
--- agreement for further details.
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors.  Please
+-- refer to the applicable agreement for further details.
 
 -- You may only use these simulation model output files for simulation
 -- purposes and expressly not for synthesis or any other purposes (in which
@@ -36,7 +35,6 @@
 	 ( 
 		 locked	:	OUT  STD_LOGIC;
 		 outclk_0	:	OUT  STD_LOGIC;
-		 outclk_1	:	OUT  STD_LOGIC;
 		 refclk	:	IN  STD_LOGIC;
 		 rst	:	IN  STD_LOGIC
 	 ); 
@@ -47,15 +45,14 @@
 	 ATTRIBUTE synthesis_clearbox : natural;
 	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
 	 SIGNAL  wire_gnd	:	STD_LOGIC;
-	 SIGNAL  wire_pll_hdmi_altera_pll_altera_pll_i_1098_locked	:	STD_LOGIC;
-	 SIGNAL  wire_pll_hdmi_altera_pll_altera_pll_i_1098_outclk	:	STD_LOGIC_VECTOR (1 DOWNTO 0);
+	 SIGNAL  wire_pll_hdmi_altera_pll_altera_pll_i_639_locked	:	STD_LOGIC;
+	 SIGNAL  wire_pll_hdmi_altera_pll_altera_pll_i_639_outclk	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
  BEGIN
 
 	wire_gnd <= '0';
-	locked <= wire_pll_hdmi_altera_pll_altera_pll_i_1098_locked;
-	outclk_0 <= wire_pll_hdmi_altera_pll_altera_pll_i_1098_outclk(0);
-	outclk_1 <= wire_pll_hdmi_altera_pll_altera_pll_i_1098_outclk(1);
-	pll_hdmi_altera_pll_altera_pll_i_1098 :  altera_pll
+	locked <= wire_pll_hdmi_altera_pll_altera_pll_i_639_locked;
+	outclk_0 <= wire_pll_hdmi_altera_pll_altera_pll_i_639_outclk(0);
+	pll_hdmi_altera_pll_altera_pll_i_639 :  altera_pll
 	  GENERIC MAP (
 		c_cnt_bypass_en0 => "false",
 		c_cnt_bypass_en1 => "false",
@@ -231,10 +228,10 @@
 		n_cnt_hi_div => 1,
 		n_cnt_lo_div => 1,
 		n_cnt_odd_div_duty_en => "false",
-		number_of_clocks => 2,
+		number_of_clocks => 1,
 		operation_mode => "normal",
-		output_clock_frequency0 => "27.000000 MHz",
-		output_clock_frequency1 => "135.000000 MHz",
+		output_clock_frequency0 => "148.500000 MHz",
+		output_clock_frequency1 => "0 MHz",
 		output_clock_frequency10 => "0 MHz",
 		output_clock_frequency11 => "0 MHz",
 		output_clock_frequency12 => "0 MHz",
@@ -293,13 +290,13 @@
 		pll_vco_div => 1,
 		pll_vcoph_div => 1,
 		refclk1_frequency => "0 MHz",
-		reference_clock_frequency => "50.0 MHz",
+		reference_clock_frequency => "54.0 MHz",
 		sim_additional_refclk_cycles_to_lock => 0
 	  )
 	  PORT MAP ( 
 		fbclk => wire_gnd,
-		locked => wire_pll_hdmi_altera_pll_altera_pll_i_1098_locked,
-		outclk => wire_pll_hdmi_altera_pll_altera_pll_i_1098_outclk,
+		locked => wire_pll_hdmi_altera_pll_altera_pll_i_639_locked,
+		outclk => wire_pll_hdmi_altera_pll_altera_pll_i_639_outclk,
 		refclk => refclk,
 		rst => rst
 	  );
Index: eclaireXL_ITX/pll_hdmi2_sim/cadence/ncsim_setup.sh
===================================================================
--- eclaireXL_ITX/pll_hdmi2_sim/cadence/ncsim_setup.sh	(nonexistent)
+++ eclaireXL_ITX/pll_hdmi2_sim/cadence/ncsim_setup.sh	(revision 974)
@@ -0,0 +1,198 @@
+
+# (C) 2001-2020 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 18.0 614 linux 2020.02.02.21:28:40
+
+# ----------------------------------------
+# ncsim - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     pll_hdmi2
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level shell script that compiles Altera simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "ncsim.sh", and modify text as directed.
+# 
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated files
+# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated - 
+# # into the location from which you launch the simulator, or incorporate
+# # into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# # - If necessary, specify any compilation options:
+# #   USER_DEFINED_COMPILE_OPTIONS
+# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# ncvlog <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME=<simulation top> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If pll_hdmi2 is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 18.0 614 linux 2020.02.02.21:28:40
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="pll_hdmi2"
+QSYS_SIMDIR="./../"
+QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/18.0/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for 
+# overwriting variables. An example usage:
+#   sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+  eval $expression
+  if [ $? -ne 0 ]; then
+    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+    exit $?
+  fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
+  :
+else
+  :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera/
+mkdir -p ./libraries/lpm/
+mkdir -p ./libraries/sgate/
+mkdir -p ./libraries/altera_mf/
+mkdir -p ./libraries/altera_lnsim/
+mkdir -p ./libraries/cyclonev/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+  ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v"  -work cyclonev    
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_hdmi2.vho"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+  export GENERIC_PARAM_COMPAT_CHECK=1
+  ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+  eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
+fi

Property changes on: eclaireXL_ITX/pll_hdmi2_sim/cadence/ncsim_setup.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: eclaireXL_ITX/pll_hdmi2_sim/synopsys/vcsmx/vcsmx_setup.sh
===================================================================
--- eclaireXL_ITX/pll_hdmi2_sim/synopsys/vcsmx/vcsmx_setup.sh	(nonexistent)
+++ eclaireXL_ITX/pll_hdmi2_sim/synopsys/vcsmx/vcsmx_setup.sh	(revision 974)
@@ -0,0 +1,198 @@
+
+# (C) 2001-2020 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 18.0 614 linux 2020.02.02.21:28:40
+
+# ----------------------------------------
+# vcsmx - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     pll_hdmi2
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level shell script that compiles Altera simulation libraries 
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
+# 
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated library
+# # setup "synopsys_sim.setup" into the location from which you launch the
+# # simulator, or incorporate into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# #
+# # - If necessary, specify any compilation options:
+# #   USER_DEFINED_COMPILE_OPTIONS
+# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# vlogan <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME="'-top <simulation top>'" \
+# QSYS_SIMDIR=<script generation output directory> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If pll_hdmi2 is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 18.0 614 linux 2020.02.02.21:28:40
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="pll_hdmi2"
+QSYS_SIMDIR="./../../"
+QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/18.0/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for 
+# overwriting variables. An example usage:
+#   sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+  eval $expression
+  if [ $? -ne 0 ]; then
+    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+    exit $?
+  fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `vcs -platform` != *"amd64"* ]]; then
+  :
+else
+  :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera/
+mkdir -p ./libraries/lpm/
+mkdir -p ./libraries/sgate/
+mkdir -p ./libraries/altera_mf/
+mkdir -p ./libraries/altera_lnsim/
+mkdir -p ./libraries/cyclonev/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+  vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev    
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+  vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_hdmi2.vho"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+  vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+  ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
+fi

Property changes on: eclaireXL_ITX/pll_hdmi2_sim/synopsys/vcsmx/vcsmx_setup.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: eclaireXL_ITX/pll_hdmi_sim/mentor/msim_setup.tcl
===================================================================
--- eclaireXL_ITX/pll_hdmi_sim/mentor/msim_setup.tcl	(revision 973)
+++ eclaireXL_ITX/pll_hdmi_sim/mentor/msim_setup.tcl	(revision 974)
@@ -1,5 +1,5 @@
 
-# (C) 2001-2016 Altera Corporation. All rights reserved.
+# (C) 2001-2020 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -46,6 +46,8 @@
 # #
 # # Set any compilation options you require (this is unusual).
 # set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
 # #
 # # Call command to compile the Quartus EDA simulation library.
 # dev_com
@@ -92,7 +94,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 16.1 196 linux 2016.11.30.20:30:39
+# ACDS 18.0 614 linux 2020.02.02.21:06:19
 
 # ----------------------------------------
 # Initialize variables
@@ -111,12 +113,18 @@
 }
 
 if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/home/markw/fpga/intelFPGA_lite/16.1/quartus/"
+  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/18.0/quartus/"
 }
 
 if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
   set USER_DEFINED_COMPILE_OPTIONS ""
 }
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
 if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
   set USER_DEFINED_ELAB_OPTIONS ""
 }
@@ -163,23 +171,23 @@
 alias dev_com {
   echo "\[exec\] dev_com"
   if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
-    eval  vlog -sv $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv"  -work altera_lnsim
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
-    eval  vlog $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v"   -work cyclonev    
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+    eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv"  -work altera_lnsim
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v"   -work cyclonev    
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
   }
 }
 
@@ -187,7 +195,7 @@
 # Compile the design files in correct order
 alias com {
   echo "\[exec\] com"
-  eval  vcom $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_hdmi.vho"
+  eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_hdmi.vho"
 }
 
 # ----------------------------------------
@@ -225,37 +233,41 @@
 alias h {
   echo "List Of Command Line Aliases"
   echo
-  echo "file_copy                     -- Copy ROM/RAM files to simulation directory"
+  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
   echo
-  echo "dev_com                       -- Compile device library files"
+  echo "dev_com                                           -- Compile device library files"
   echo
-  echo "com                           -- Compile the design files in correct order"
+  echo "com                                               -- Compile the design files in correct order"
   echo
-  echo "elab                          -- Elaborate top level design"
+  echo "elab                                              -- Elaborate top level design"
   echo
-  echo "elab_debug                    -- Elaborate the top level design with novopt option"
+  echo "elab_debug                                        -- Elaborate the top level design with novopt option"
   echo
-  echo "ld                            -- Compile all the design files and elaborate the top level design"
+  echo "ld                                                -- Compile all the design files and elaborate the top level design"
   echo
-  echo "ld_debug                      -- Compile all the design files and elaborate the top level design with -novopt"
+  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -novopt"
   echo
   echo 
   echo
   echo "List Of Variables"
   echo
-  echo "TOP_LEVEL_NAME                -- Top level module name."
-  echo "                                 For most designs, this should be overridden"
-  echo "                                 to enable the elab/elab_debug aliases."
+  echo "TOP_LEVEL_NAME                                    -- Top level module name."
+  echo "                                                     For most designs, this should be overridden"
+  echo "                                                     to enable the elab/elab_debug aliases."
   echo
-  echo "SYSTEM_INSTANCE_NAME          -- Instantiated system module name inside top level module."
+  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
   echo
-  echo "QSYS_SIMDIR                   -- Qsys base simulation directory."
+  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
   echo
-  echo "QUARTUS_INSTALL_DIR           -- Quartus installation directory."
+  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
   echo
-  echo "USER_DEFINED_COMPILE_OPTIONS  -- User-defined compile options, added to com/dev_com aliases."
+  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
   echo
-  echo "USER_DEFINED_ELAB_OPTIONS     -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo
+  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
 }
 file_copy
 h
Index: eclaireXL_ITX/pll_hdmi2_sim/cadence/hdl.var
===================================================================
--- eclaireXL_ITX/pll_hdmi2_sim/cadence/hdl.var	(nonexistent)
+++ eclaireXL_ITX/pll_hdmi2_sim/cadence/hdl.var	(revision 974)
@@ -0,0 +1,2 @@
+
+DEFINE WORK work
Index: eclaireXL_ITX/pll_hdmi2_sim/synopsys/vcsmx/synopsys_sim.setup
===================================================================
--- eclaireXL_ITX/pll_hdmi2_sim/synopsys/vcsmx/synopsys_sim.setup	(nonexistent)
+++ eclaireXL_ITX/pll_hdmi2_sim/synopsys/vcsmx/synopsys_sim.setup	(revision 974)
@@ -0,0 +1,11 @@
+
+WORK > DEFAULT
+DEFAULT:      ./libraries/work/        
+work:         ./libraries/work/        
+altera:       ./libraries/altera/      
+lpm:          ./libraries/lpm/         
+sgate:        ./libraries/sgate/       
+altera_mf:    ./libraries/altera_mf/   
+altera_lnsim: ./libraries/altera_lnsim/
+cyclonev:     ./libraries/cyclonev/    
+LIBRARY_SCAN = TRUE
Index: eclaireXL_ITX/pll_hdmi_sim/cadence/ncsim_setup.sh
===================================================================
--- eclaireXL_ITX/pll_hdmi_sim/cadence/ncsim_setup.sh	(revision 973)
+++ eclaireXL_ITX/pll_hdmi_sim/cadence/ncsim_setup.sh	(revision 974)
@@ -1,5 +1,5 @@
 
-# (C) 2001-2016 Altera Corporation. All rights reserved.
+# (C) 2001-2020 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 16.1 196 linux 2016.11.30.20:30:39
+# ACDS 18.0 614 linux 2020.02.02.21:06:19
 
 # ----------------------------------------
 # ncsim - auto-generated simulation script
@@ -55,12 +55,17 @@
 # # Run Quartus-generated IP simulation script once to compile Quartus EDA
 # # simulation libraries and Quartus-generated IP simulation files, and copy
 # # any ROM/RAM initialization files to the simulation directory.
-# # - If necessary, specify USER_DEFINED_COMPILE_OPTIONS.
+# # - If necessary, specify any compilation options:
+# #   USER_DEFINED_COMPILE_OPTIONS
+# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
 # #
 # source <script generation output directory>/cadence/ncsim_setup.sh \
 # SKIP_ELAB=1 \
 # SKIP_SIM=1 \
 # USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
 # QSYS_SIMDIR=<script generation output directory>
 # #
 # # Compile all design files and testbench files, including the top level.
@@ -101,12 +106,12 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 16.1 196 linux 2016.11.30.20:30:39
+# ACDS 18.0 614 linux 2020.02.02.21:06:19
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="pll_hdmi"
 QSYS_SIMDIR="./../"
-QUARTUS_INSTALL_DIR="/home/markw/fpga/intelFPGA_lite/16.1/quartus/"
+QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/18.0/quartus/"
 SKIP_FILE_COPY=0
 SKIP_DEV_COM=0
 SKIP_COM=0
@@ -154,29 +159,29 @@
 # ----------------------------------------
 # compile device library files
 if [ $SKIP_DEV_COM -eq 0 ]; then
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
-  ncvlog -sv $USER_DEFINED_COMPILE_OPTIONS  "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
-  ncvlog $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v"  -work cyclonev    
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+  ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v"  -work cyclonev    
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
 fi
 
 # ----------------------------------------
 # compile design files in correct order
 if [ $SKIP_COM -eq 0 ]; then
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_hdmi.vho"
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_hdmi.vho"
 fi
 
 # ----------------------------------------
Index: eclaireXL_ITX/pll_hdmi_sim/synopsys/vcsmx/vcsmx_setup.sh
===================================================================
--- eclaireXL_ITX/pll_hdmi_sim/synopsys/vcsmx/vcsmx_setup.sh	(revision 973)
+++ eclaireXL_ITX/pll_hdmi_sim/synopsys/vcsmx/vcsmx_setup.sh	(revision 974)
@@ -1,5 +1,5 @@
 
-# (C) 2001-2016 Altera Corporation. All rights reserved.
+# (C) 2001-2020 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 16.1 196 linux 2016.11.30.20:30:39
+# ACDS 18.0 614 linux 2020.02.02.21:06:19
 
 # ----------------------------------------
 # vcsmx - auto-generated simulation script
@@ -55,11 +55,17 @@
 # # simulation libraries and Quartus-generated IP simulation files, and copy
 # # any ROM/RAM initialization files to the simulation directory.
 # #
-# # - If necessary, specify USER_DEFINED_COMPILE_OPTIONS.
+# # - If necessary, specify any compilation options:
+# #   USER_DEFINED_COMPILE_OPTIONS
+# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
 # source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
 # SKIP_ELAB=1 \
 # SKIP_SIM=1 \
 # USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
 # QSYS_SIMDIR=<script generation output directory>
 # #
 # # Compile all design files and testbench files, including the top level.
@@ -101,12 +107,12 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 16.1 196 linux 2016.11.30.20:30:39
+# ACDS 18.0 614 linux 2020.02.02.21:06:19
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="pll_hdmi"
 QSYS_SIMDIR="./../../"
-QUARTUS_INSTALL_DIR="/home/markw/fpga/intelFPGA_lite/16.1/quartus/"
+QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/18.0/quartus/"
 SKIP_FILE_COPY=0
 SKIP_DEV_COM=0
 SKIP_COM=0
@@ -154,29 +160,29 @@
 # ----------------------------------------
 # compile device library files
 if [ $SKIP_DEV_COM -eq 0 ]; then
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
-  vlogan +v2k -sverilog $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
-  vlogan +v2k $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev    
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+  vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev    
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
 fi
 
 # ----------------------------------------
 # compile design files in correct order
 if [ $SKIP_COM -eq 0 ]; then
-  vhdlan -xlrm $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_hdmi.vho"
+  vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_hdmi.vho"
 fi
 
 # ----------------------------------------
Index: eclaireXL_ITX/pll_usb.qip
===================================================================
--- eclaireXL_ITX/pll_usb.qip	(revision 973)
+++ eclaireXL_ITX/pll_usb.qip	(revision 974)
@@ -1,5 +1,5 @@
 set_global_assignment -entity "pll_usb" -library "pll_usb" -name IP_TOOL_NAME "altera_pll"
-set_global_assignment -entity "pll_usb" -library "pll_usb" -name IP_TOOL_VERSION "16.1"
+set_global_assignment -entity "pll_usb" -library "pll_usb" -name IP_TOOL_VERSION "18.0"
 set_global_assignment -entity "pll_usb" -library "pll_usb" -name IP_TOOL_ENV "mwpim"
 set_global_assignment -library "pll_usb" -name MISC_FILE [file join $::quartus(qip_path) "pll_usb.cmp"]
 set_global_assignment -entity "pll_usb" -library "pll_usb" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
@@ -7,24 +7,24 @@
 set_global_assignment -entity "pll_usb" -library "pll_usb" -name IP_QSYS_MODE "UNKNOWN"
 set_global_assignment -name SYNTHESIS_ONLY_QIP ON
 set_global_assignment -entity "pll_usb" -library "pll_usb" -name IP_COMPONENT_NAME "cGxsX3VzYg=="
-set_global_assignment -entity "pll_usb" -library "pll_usb" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_usb" -library "pll_usb" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
 set_global_assignment -entity "pll_usb" -library "pll_usb" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "pll_usb" -library "pll_usb" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "pll_usb" -library "pll_usb" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
-set_global_assignment -entity "pll_usb" -library "pll_usb" -name IP_COMPONENT_VERSION "MTYuMQ=="
-set_global_assignment -entity "pll_usb" -library "pll_usb" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_usb" -library "pll_usb" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "pll_usb" -library "pll_usb" -name IP_COMPONENT_VERSION "MTguMA=="
+set_global_assignment -entity "pll_usb" -library "pll_usb" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_NAME "cGxsX3VzYl8wMDAy"
-set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_INTERNAL "Off"
-set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
-set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_VERSION "MTYuMQ=="
-set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_VERSION "MTguMA=="
+set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl"
-set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
-set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
+set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU="
+set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
@@ -43,9 +43,9 @@
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NDguMA==::RGVzaXJlZCBGcmVxdWVuY3k="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MjQ=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MjU=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::Mjc0ODc3ODk4NA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::OQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
@@ -53,11 +53,11 @@
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::NTAuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::NTQuMA==::RGVzaXJlZCBGcmVxdWVuY3k="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
-set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MjQ=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
-set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
-set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MjQ=::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::OA==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::Mjc0ODc3ODk4NA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::OA==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
@@ -65,7 +65,7 @@
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
-set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MC4w::RGVzaXJlZCBGcmVxdWVuY3k="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
@@ -259,7 +259,7 @@
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NDguMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
-set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::NTAuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
+set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::NTQuMDAwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
@@ -318,7 +318,7 @@
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
-set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MTIsMTIsMjU2LDI1NixmYWxzZSx0cnVlLGZhbHNlLGZhbHNlLDEzLDEyLDEsMCxwaF9tdXhfY2xrLGZhbHNlLHRydWUsMTIsMTIsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMSwyMCw0MDAwLDEyMDAuMCBNSHosMSxnY2xrLGdsYixmYl8xLHBoX211eF9jbGssdHJ1ZQ==::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NCw0LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSw1LDQsMSwwLHBoX211eF9jbGssZmFsc2UsdHJ1ZSw0LDQsMSwwLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMiwyMCw0MDAwLDQzMS45OTk5OTkgTUh6LDI3NDg3Nzg5ODQsZ2NsayxnbGIsZmJfMSxwaF9tdXhfY2xrLHRydWU=::UGFyYW1ldGVyIFZhbHVlcw=="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
@@ -333,5 +333,5 @@
 set_global_assignment -library "pll_usb" -name QIP_FILE [file join $::quartus(qip_path) "pll_usb/pll_usb_0002.qip"]
 
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_TOOL_NAME "altera_pll"
-set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_TOOL_VERSION "16.1"
+set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_TOOL_VERSION "18.0"
 set_global_assignment -entity "pll_usb_0002" -library "pll_usb" -name IP_TOOL_ENV "mwpim"
Index: eclaireXL_ITX/pll_usb_sim/cadence/ncsim_setup.sh
===================================================================
--- eclaireXL_ITX/pll_usb_sim/cadence/ncsim_setup.sh	(revision 973)
+++ eclaireXL_ITX/pll_usb_sim/cadence/ncsim_setup.sh	(revision 974)
@@ -1,5 +1,5 @@
 
-# (C) 2001-2016 Altera Corporation. All rights reserved.
+# (C) 2001-2020 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 16.1 196 linux 2016.12.30.21:53:15
+# ACDS 18.0 614 linux 2020.02.02.21:03:29
 
 # ----------------------------------------
 # ncsim - auto-generated simulation script
@@ -55,12 +55,17 @@
 # # Run Quartus-generated IP simulation script once to compile Quartus EDA
 # # simulation libraries and Quartus-generated IP simulation files, and copy
 # # any ROM/RAM initialization files to the simulation directory.
-# # - If necessary, specify USER_DEFINED_COMPILE_OPTIONS.
+# # - If necessary, specify any compilation options:
+# #   USER_DEFINED_COMPILE_OPTIONS
+# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
 # #
 # source <script generation output directory>/cadence/ncsim_setup.sh \
 # SKIP_ELAB=1 \
 # SKIP_SIM=1 \
 # USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
 # QSYS_SIMDIR=<script generation output directory>
 # #
 # # Compile all design files and testbench files, including the top level.
@@ -101,12 +106,12 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 16.1 196 linux 2016.12.30.21:53:15
+# ACDS 18.0 614 linux 2020.02.02.21:03:29
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="pll_usb"
 QSYS_SIMDIR="./../"
-QUARTUS_INSTALL_DIR="/home/markw/fpga/intelFPGA_lite/16.1/quartus/"
+QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/18.0/quartus/"
 SKIP_FILE_COPY=0
 SKIP_DEV_COM=0
 SKIP_COM=0
@@ -154,29 +159,29 @@
 # ----------------------------------------
 # compile device library files
 if [ $SKIP_DEV_COM -eq 0 ]; then
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
-  ncvlog -sv $USER_DEFINED_COMPILE_OPTIONS  "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
-  ncvlog $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v"  -work cyclonev    
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+  ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v"  -work cyclonev    
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
 fi
 
 # ----------------------------------------
 # compile design files in correct order
 if [ $SKIP_COM -eq 0 ]; then
-  ncvhdl -v93 $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_usb.vho"
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_usb.vho"
 fi
 
 # ----------------------------------------
Index: eclaireXL_ITX/scaler/areascale.vhd
===================================================================
--- eclaireXL_ITX/scaler/areascale.vhd	(nonexistent)
+++ eclaireXL_ITX/scaler/areascale.vhd	(revision 974)
@@ -0,0 +1,475 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+--USE ieee.std_logic_arith.all;
+--USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.all;
+use work.pixels.all;
+
+--TODO: scanlines!!
+--out_colour(7 downto 4) <= out_colour_raw(7 downto 4);
+--out_colour(3 downto 0) <= out_colour_raw(3 downto 0) when (not(out_scanlines) or vcnt(0))='1' else '0'&out_colour_raw(3 downto 1);
+
+ENTITY areascale IS
+  PORT(
+    clock   : IN     STD_LOGIC;                             --system clock
+    reset_n : IN     STD_LOGIC;                             --asynchronous reset
+
+    -- need to know:
+    -- block of 4 pixels (x,y:x+1,y:x,y+1:x+1,y+1)
+    -- relative scale ratios
+    --p1 : in std_logic_vector(23 downto 0); --RGB
+    --p2 : in std_logic_vector(23 downto 0); --RGB
+    --p3 : in std_logic_vector(23 downto 0); --RGB
+    --p4 : in std_logic_vector(23 downto 0); --RGB
+	 
+    pixels : in t_Pixel2x2;
+
+    -- next output line
+    next_y_in : in std_logic;
+    next_frame_in : in std_logic;
+    field2 : in std_logic;
+    
+    -- sync/blank from crtc -> need to be delayed in line with pipeline
+    hsync_in : in std_logic;
+    vsync_in : in std_logic;
+    blank_in : in std_logic; 
+	 
+    -- need to provide control signals:
+    next_x : OUT STD_LOGIC;
+    next_x_size : out std_logic_vector(1 downto 0);
+    next_y : OUT STD_LOGIC;	 
+
+    -- need to output
+    -- current pixel
+    r : out std_logic_vector(7 downto 0);
+    g : out std_logic_vector(7 downto 0);
+    b : out std_logic_vector(7 downto 0);
+    hsync : out std_logic;
+    vsync : out std_logic;
+    blank : out std_logic;
+	 
+    -- to set up params
+    sda : inout std_logic;
+    scl : inout std_logic	 
+  );
+END areascale;
+
+-- customscalex:568 customscaley:256 xdelta:640 ydelta:102 TA:65536
+ARCHITECTURE vhdl OF areascale IS
+	-- parameters
+	signal param_xthreshold_reg : unsigned(10 downto 0);
+	signal param_ythreshold_reg : unsigned(10 downto 0);
+	signal param_xdelta_reg : unsigned(10 downto 0);
+	signal param_ydelta_reg : unsigned(10 downto 0);
+	signal param_ydeltaeach_reg : unsigned(10 downto 0);	
+	signal param_xaddrskip_reg : unsigned(1 downto 0); -- We only support upscaling, so for some cases need to skip 2 pixels
+	signal params : std_logic_vector((11*6)-1 downto 0);
+
+	-- stage 1:5 Delay syncs in line with pipeline
+	signal hsync_next : std_logic_vector(6 downto 1);
+	signal hsync_reg : std_logic_vector(6 downto 1);
+	signal vsync_next : std_logic_vector(6 downto 1);
+	signal vsync_reg : std_logic_vector(6 downto 1);
+	signal blank_next : std_logic_vector(6 downto 1);
+	signal blank_reg : std_logic_vector(6 downto 1);
+	
+	-- stage 1 : Accumulators/ data request
+	signal xacc_next : unsigned(11 downto 0);
+	signal xacc_reg : unsigned(11 downto 0);
+	signal yacc_next : unsigned(11 downto 0);
+	signal yacc_reg : unsigned(11 downto 0);
+	
+	-- stage 2 : Area calc 
+	signal dl_next : unsigned(8 downto 0);
+	signal dl_reg : unsigned(8 downto 0);
+	signal dlO_next : unsigned(8 downto 0);
+	signal dlO_reg : unsigned(8 downto 0);
+	signal dt_next : unsigned(8 downto 0);
+	signal dt_reg : unsigned(8 downto 0);
+	signal dtO_next : unsigned(8 downto 0);
+	signal dtO_reg : unsigned(8 downto 0);	
+
+	-- stage 3 : Area calc mult
+	signal A1_next : unsigned(17 downto 0);
+	signal A1_reg : unsigned(17 downto 0);
+	signal A2_next : unsigned(17 downto 0);
+	signal A2_reg : unsigned(17 downto 0);
+	signal A3_next : unsigned(17 downto 0);
+	signal A3_reg : unsigned(17 downto 0);
+	signal A4_next : unsigned(17 downto 0);
+	signal A4_reg : unsigned(17 downto 0);
+
+	signal p1_s3_reg : t_Pixel;
+	signal p2_s3_reg : t_Pixel;
+	signal p3_s3_reg : t_Pixel;
+	signal p4_s3_reg : t_Pixel;
+	signal p1_s3_next : t_Pixel;
+	signal p2_s3_next : t_Pixel;
+	signal p3_s3_next : t_Pixel;
+	signal p4_s3_next : t_Pixel;
+
+	-- stage 4: Pixel scaling
+	signal f1_r_reg : unsigned(35 downto 0);
+	signal f2_r_reg : unsigned(35 downto 0);
+	signal f3_r_reg : unsigned(35 downto 0);
+	signal f4_r_reg : unsigned(35 downto 0);
+
+	signal f1_g_reg : unsigned(35 downto 0);
+	signal f2_g_reg : unsigned(35 downto 0);
+	signal f3_g_reg : unsigned(35 downto 0);
+	signal f4_g_reg : unsigned(35 downto 0);
+
+	signal f1_b_reg : unsigned(35 downto 0);
+	signal f2_b_reg : unsigned(35 downto 0);
+	signal f3_b_reg : unsigned(35 downto 0);
+	signal f4_b_reg : unsigned(35 downto 0);
+
+	signal f1_r_next : unsigned(35 downto 0);
+	signal f2_r_next : unsigned(35 downto 0);
+	signal f3_r_next : unsigned(35 downto 0);
+	signal f4_r_next : unsigned(35 downto 0);
+
+	signal f1_g_next : unsigned(35 downto 0);
+	signal f2_g_next : unsigned(35 downto 0);
+	signal f3_g_next : unsigned(35 downto 0);
+	signal f4_g_next : unsigned(35 downto 0);
+
+	signal f1_b_next : unsigned(35 downto 0);
+	signal f2_b_next : unsigned(35 downto 0);
+	signal f3_b_next : unsigned(35 downto 0);
+	signal f4_b_next : unsigned(35 downto 0);
+
+	-- stage 5: Pixel output
+	signal r_reg : std_logic_vector(7 downto 0);
+	signal r_next : std_logic_vector(7 downto 0);
+	signal g_reg : std_logic_vector(7 downto 0);
+	signal g_next : std_logic_vector(7 downto 0);
+	signal b_reg : std_logic_vector(7 downto 0);
+	signal b_next : std_logic_vector(7 downto 0);
+
+BEGIN
+	process(clock,reset_n)
+	begin
+		if (reset_n='0') then
+			-- multi stage 1-5
+			hsync_reg <= (others=>'0');
+			vsync_reg <= (others=>'0');
+			blank_reg <= (others=>'0');
+
+			-- stage 1
+			xacc_reg <= (others=>'0');
+			yacc_reg <= (others=>'0');
+
+			-- stage 2
+			dt_reg <= (others=>'0');
+			dl_reg <= (others=>'0');
+			dtO_reg <= (others=>'0');
+			dlO_reg <= (others=>'0');
+
+			-- stage 3
+			A1_reg <= (others=>'0');
+			A2_reg <= (others=>'0');
+			A3_reg <= (others=>'0');
+			A4_reg <= (others=>'0');
+
+			p1_s3_reg <= (others=>(others=>'0'));
+			p2_s3_reg <= (others=>(others=>'0'));
+			p3_s3_reg <= (others=>(others=>'0'));
+			p4_s3_reg <= (others=>(others=>'0'));
+
+			-- stage 4
+			f1_r_reg <= (others=>'0');
+			f2_r_reg <= (others=>'0');
+			f3_r_reg <= (others=>'0');
+			f4_r_reg <= (others=>'0');
+
+			f1_g_reg <= (others=>'0');
+			f2_g_reg <= (others=>'0');
+			f3_g_reg <= (others=>'0');
+			f4_g_reg <= (others=>'0');
+
+			f1_b_reg <= (others=>'0');
+			f2_b_reg <= (others=>'0');
+			f3_b_reg <= (others=>'0');
+			f4_b_reg <= (others=>'0');
+
+			-- stage 5
+			r_reg <= (others=>'0');
+			g_reg <= (others=>'0');
+			b_reg <= (others=>'0');
+
+		elsif (clock'event and clock='1') then
+			-- multi stage 1-5
+			hsync_reg <= hsync_next;
+			vsync_reg <= vsync_next;
+			blank_reg <= blank_next;			
+			
+			-- stage 1
+			xacc_reg <= xacc_next;
+			yacc_reg <= yacc_next;
+
+			-- stage 2
+			dt_reg <= dt_next;
+			dl_reg <= dl_next;
+			dtO_reg <= dtO_next;
+			dlO_reg <= dlO_next;
+
+			-- stage 3
+			A1_reg <= A1_next;
+			A2_reg <= A2_next;
+			A3_reg <= A3_next;
+			A4_reg <= A4_next;
+
+			p1_s3_reg <= p1_s3_next;
+			p2_s3_reg <= p2_s3_next;
+			p3_s3_reg <= p3_s3_next;
+			p4_s3_reg <= p4_s3_next;
+
+			-- stage 4
+			f1_r_reg <= f1_r_next;
+			f2_r_reg <= f2_r_next;
+			f3_r_reg <= f3_r_next;
+			f4_r_reg <= f4_r_next;
+
+			f1_g_reg <= f1_g_next;
+			f2_g_reg <= f2_g_next;
+			f3_g_reg <= f3_g_next;
+			f4_g_reg <= f4_g_next;
+
+			f1_b_reg <= f1_b_next;
+			f2_b_reg <= f2_b_next;
+			f3_b_reg <= f3_b_next;
+			f4_b_reg <= f4_b_next;
+
+			-- stage 5
+			r_reg <= r_next;
+			g_reg <= g_next;
+			b_reg <= b_next;
+
+		end if;
+	end process;
+	
+	-- temporary params, until i2c implemented
+	-- 720p
+--	param_xthreshold_next <= to_unsigned(699,10); -- these need to be inputs
+--	param_xdelta_next <= to_unsigned(393,10);
+--	param_ythreshold_next <= to_unsigned(400,9);
+--	param_ydelta_next <= to_unsigned(166,9);
+-- param_ydeltaeach_next <= to_unsigned(166,9);
+--	param_xaddrskip_next <= "10";
+
+	-- 1080i
+--	param_xthreshold_next <= to_unsigned(400,11); -- these need to be inputs
+--	param_xdelta_next <= to_unsigned(300,11);
+--	param_ythreshold_next <= to_unsigned(786,11);
+--	param_ydelta_next <= to_unsigned(218,11);
+--	param_ydeltaeach_next <= to_unsigned(437,11); --interlace, need to skip a line
+--	param_xaddrskip_next <= "01";
+
+
+-- params set from i2c
+	i2cregs : entity work.I2C_regs
+	generic map (
+		SLAVE_ADDR => "0000001",
+		regs => 6,
+		bits => 11
+	)
+	port map (
+		scl => scl,
+		sda => sda,
+		clk => clock,
+		rst => not(reset_n),
+		
+		reg => params			
+	);
+	
+	param_xthreshold_reg <= unsigned(params(11*1-1 downto 11*0));
+	param_xdelta_reg <= unsigned(params(11*2-1 downto 11*1));
+	param_ythreshold_reg <= unsigned(params(11*3-1 downto 11*2));
+	param_ydelta_reg <= unsigned(params(11*4-1 downto 11*3));
+	param_ydeltaeach_reg <= unsigned(params(11*5-1 downto 11*4));
+	param_xaddrskip_reg <= unsigned(params(11*5+2-1 downto 11*5));
+	
+--  Delay sync in line with pipeline: multi stage 1-5
+	process(hsync_reg,vsync_reg,blank_reg,hsync_in,vsync_in,blank_in)
+	begin		
+		hsync_next <= hsync_reg(5 downto 1)&hsync_in;
+		vsync_next <= vsync_reg(5 downto 1)&vsync_in;
+		blank_next <= blank_reg(5 downto 1)&blank_in;
+	end process;
+
+-- 	Compute accumulator - pipeline stage 1
+	process(xacc_reg,param_xdelta_reg,param_xthreshold_reg,next_y_in)
+	begin
+		next_x <= '0';
+		xacc_next <= xacc_reg+param_xdelta_reg;
+		if ((xacc_reg+param_xdelta_reg)>=param_xthreshold_reg) then
+			next_x <= '1'; -- when I ask for data, its on p1 in 2 cycles, i.e. pipeline stage 3
+			xacc_next <= xacc_reg+param_xdelta_reg-param_xthreshold_reg;
+		end if;
+
+		if (next_y_in ='1') then 
+			xacc_next <= (others=>'0');
+		end if;
+	end process;
+
+	process(yacc_reg,param_ydeltaeach_reg,param_ythreshold_reg,next_y_in,next_frame_in,field2)
+	begin
+		yacc_next <= yacc_reg;
+		next_y <= '0';
+
+		if (next_y_in='1') then
+			yacc_next <= yacc_reg+param_ydeltaeach_reg; 
+			if ((yacc_reg+param_ydeltaeach_reg)>=param_ythreshold_reg) then
+				next_y <= '1';
+				yacc_next <= yacc_reg+param_ydeltaeach_reg-param_ythreshold_reg;
+			end if;
+		end if;
+
+		if (next_frame_in='1') then
+			yacc_next <= (others=>'0');
+			if (field2='1') then --slightly lower on interlace field 2
+				yacc_next(9 downto 0) <= param_ythreshold_reg(10 downto 1);
+			end if;
+		end if;
+	end process;
+
+--      Area computation - pipeline stage 2
+--      dl = min(customscalex-xacc_i,xdelta);
+--      dt = min(customscaley-yacc_i,ydelta);
+--      
+--      dlO = (xdelta-dl);
+--      dtO = (ydelta-dt);
+--      
+--      A1 = dl*dt;   %M1
+--      A2 = dlO*dt;  %M2
+--      A3 = dl*dtO;  %M3
+--      A4 = TA-A3-A2-A1; %Save 1!
+	process(
+		param_xthreshold_reg,xacc_reg,param_xdelta_reg,
+		param_ythreshold_reg,yacc_reg,param_ydelta_reg)
+		variable dl : unsigned(10 downto 0);
+		variable dt : unsigned(10 downto 0);
+
+		variable dlO : unsigned(10 downto 0);
+		variable dtO : unsigned(10 downto 0);
+	begin
+		dl := param_xthreshold_reg-xacc_reg(10 downto 0);
+		if (dl>param_xdelta_reg) then
+			dl := param_xdelta_reg;
+		end if;
+
+		dt := param_ythreshold_reg-yacc_reg(10 downto 0);
+		if (dt>param_ydelta_reg) then
+			dt := param_ydelta_reg;
+		end if;
+
+		dlO:= param_xdelta_reg-dl;
+		dtO:= param_ydelta_reg-dt;
+
+		dt_next <= dt(8 downto 0);
+		dl_next <= dl(8 downto 0);
+		dtO_next <= dtO(8 downto 0);
+		dlO_next <= dlO(8 downto 0);
+	end process;
+
+--      Area computation - pipeline stage 3
+	process(dl_reg,dlO_reg,dt_reg,dtO_reg)
+	begin
+		-- dsp blocks 9x9 multipliers
+		-- 3 per block
+		A1_next <= dl_reg*dt_reg;
+		A2_next <= dlO_reg*dt_reg;
+		A3_next <= dl_reg*dtO_reg;
+		A4_next <= dlO_reg*dtO_reg; --can save this one (leaving for now)
+
+		--A1 <= to_unsigned(0,18);
+		--A2 <= to_unsigned(0,18);
+		--A3 <= to_unsigned(0,18);
+		--A4 <= to_unsigned(65535,18);
+	end process;
+
+	-- delay pixel data
+	process(pixels)
+	begin
+		p1_s3_next <= pixels(pixel2x2_idx(0,0));
+		p2_s3_next <= pixels(pixel2x2_idx(1,0));
+		p3_s3_next <= pixels(pixel2x2_idx(0,1));
+		p4_s3_next <= pixels(pixel2x2_idx(1,1));
+	end process;
+
+--      Pixel scaling computation - pipeline stage 4
+	-- Compute output
+	-- (p1*A1 + p2*A2 + p3*A3 + p4*A4)/65536
+	process(A1_reg,A2_reg,A3_reg,A4_reg,p1_s3_reg,p2_s3_reg,p3_s3_reg,p4_s3_reg)
+	begin
+		-- dsp blocks 18x18 multipliers
+		-- 2 per block
+		f1_r_next <= unsigned("0000000000"&p1_s3_reg.red)*A1_reg;
+		f2_r_next <= unsigned("0000000000"&p2_s3_reg.red)*A2_reg;
+		f3_r_next <= unsigned("0000000000"&p3_s3_reg.red)*A3_reg;
+		f4_r_next <= unsigned("0000000000"&p4_s3_reg.red)*A4_reg;
+
+		f1_g_next <= unsigned("0000000000"&p1_s3_reg.green)*A1_reg;
+		f2_g_next <= unsigned("0000000000"&p2_s3_reg.green)*A2_reg;
+		f3_g_next <= unsigned("0000000000"&p3_s3_reg.green)*A3_reg;
+		f4_g_next <= unsigned("0000000000"&p4_s3_reg.green)*A4_reg;
+
+		f1_b_next <= unsigned("0000000000"&p1_s3_reg.blue)*A1_reg;
+		f2_b_next <= unsigned("0000000000"&p2_s3_reg.blue)*A2_reg;
+		f3_b_next <= unsigned("0000000000"&p3_s3_reg.blue)*A3_reg;
+		f4_b_next <= unsigned("0000000000"&p4_s3_reg.blue)*A4_reg;
+	end process;
+
+--      Pixel scaling computation - pipeline stage 5
+	-- Compute output
+	-- (p1*A1 + p2*A2 + p3*A3 + p4*A4)/65536
+	process(
+		f1_r_reg,f2_r_reg,f3_r_reg,f4_r_reg,
+		f1_g_reg,f2_g_reg,f3_g_reg,f4_g_reg,
+		f1_b_reg,f2_b_reg,f3_b_reg,f4_b_reg)
+		variable sum_r : unsigned(9 downto 0);
+		variable sum_g : unsigned(9 downto 0);
+		variable sum_b : unsigned(9 downto 0);
+	begin
+		sum_r := (f1_r_reg(23 downto 14)+f2_r_reg(23 downto 14))+(f3_r_reg(23 downto 14)+f4_r_reg(23 downto 14));
+		sum_g := (f1_g_reg(23 downto 14)+f2_g_reg(23 downto 14))+(f3_g_reg(23 downto 14)+f4_g_reg(23 downto 14));
+		sum_b := (f1_b_reg(23 downto 14)+f2_b_reg(23 downto 14))+(f3_b_reg(23 downto 14)+f4_b_reg(23 downto 14));
+
+		r_next <= std_logic_vector(sum_r(9 downto 2));
+		g_next <= std_logic_vector(sum_g(9 downto 2));
+		b_next <= std_logic_vector(sum_b(9 downto 2));
+	end process;
+
+	-- outputnext_x_size
+	r<=r_reg;
+	g<=g_reg;
+	b<=b_reg;
+	hsync<=hsync_reg(6); -- TODO: why 6 and not 5?
+	vsync<=vsync_reg(6);
+	blank<=blank_reg(6); 
+	
+	next_x_size <= std_logic_vector(param_xaddrskip_reg);
+
+END vhdl;
+
+--              h_pixels_across  <= 720 - 1;
+--              h_sync_on <= 732 - 1;
+--              h_sync_off <= 795 - 1;
+--              h_end_count <= 864 - 1;
+--              v_pixels_down <= 576 - 1;
+--              v_sync_on <=  581 - 1;
+--              v_sync_off <= 586 - 1;
+--              v_end_count <=  625 - 1;
+
+--                --PAL
+--                h_pixels_across  <= 1280 - 1;
+--                h_sync_on <= 1720 - 1;
+--                h_sync_off <= 1760 - 1;
+--                h_end_count <= 1980 - 1;
+--                v_pixels_down <= 720 - 1;
+--                v_sync_on <=  725 - 1;
+--                v_sync_off <= 730 - 1;
+--                v_end_count <=  750 - 1;
+
+
Index: eclaireXL_ITX/scaler/polyphasicscale.vhd
===================================================================
--- eclaireXL_ITX/scaler/polyphasicscale.vhd	(nonexistent)
+++ eclaireXL_ITX/scaler/polyphasicscale.vhd	(revision 974)
@@ -0,0 +1,919 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+--USE ieee.std_logic_arith.all;
+--USE ieee.std_logic_unsigned.all;
+USE ieee.numeric_std.all;
+use work.pixels.all;
+
+--TODO: scanlines!!
+--out_colour(7 downto 4) <= out_colour_raw(7 downto 4);
+--out_colour(3 downto 0) <= out_colour_raw(3 downto 0) when (not(out_scanlines) or vcnt(0))='1' else '0'&out_colour_raw(3 downto 1);
+
+ENTITY polyphasicscale IS
+  PORT(
+    clock   : IN     STD_LOGIC;                             --system clock
+    reset_n : IN     STD_LOGIC;                             --asynchronous reset
+
+    -- input pixels
+    pixels : in t_Pixel4x4;
+
+    -- next output line
+    next_y_in : in std_logic;
+    next_frame_in : in std_logic;
+    field2 : in std_logic;
+    
+    -- sync/blank from crtc -> need to be delayed in line with pipeline
+    hsync_in : in std_logic;
+    vsync_in : in std_logic;
+    blank_in : in std_logic; 
+	 
+    -- need to provide control signals:
+    next_x : OUT STD_LOGIC;
+	 next_x_size : out std_logic_vector(1 downto 0);
+    next_y : OUT STD_LOGIC;	 
+
+    -- need to output
+    -- current pixel
+    r : out std_logic_vector(7 downto 0);
+    g : out std_logic_vector(7 downto 0);
+    b : out std_logic_vector(7 downto 0);
+    hsync : out std_logic;
+    vsync : out std_logic;
+    blank : out std_logic;
+	 
+    -- to set up params
+    sda : inout std_logic;
+    scl : inout std_logic	 
+  );
+END polyphasicscale;
+
+-- customscalex:568 customscaley:256 xdelta:640 ydelta:102 TA:65536
+ARCHITECTURE vhdl OF polyphasicscale IS
+	signal fixed_xthreshold_reg : unsigned(10 downto 0);
+	signal fixed_ythreshold_reg : unsigned(10 downto 0);
+	signal param_xdelta_reg : unsigned(10 downto 0);
+	signal param_ydeltaeach_reg : unsigned(10 downto 0);	
+	signal param_xaddrskip_reg : unsigned(1 downto 0);-- We only support upscaling, so for some cases need to skip 2 pixels
+	signal params : std_logic_vector((11*3)-1 downto 0);
+	
+	-- stage 1:5 Delay syncs in line with pipeline
+	signal hsync_next : std_logic_vector(6 downto 1);
+	signal hsync_reg : std_logic_vector(6 downto 1);
+	signal vsync_next : std_logic_vector(6 downto 1);
+	signal vsync_reg : std_logic_vector(6 downto 1);
+	signal blank_next : std_logic_vector(6 downto 1);
+	signal blank_reg : std_logic_vector(6 downto 1);
+	
+	-- stage 1 : Accumulators/ data request
+	signal xacc_next : unsigned(11 downto 0);
+	signal xacc_reg : unsigned(11 downto 0);
+	signal yacc_next : unsigned(11 downto 0);
+	signal yacc_reg : unsigned(11 downto 0);
+	signal next_x_delay1_next : std_logic;
+	signal next_x_delay1_reg : std_logic;	
+	
+	-- stage 2 : Coefs calc
+	type t_Coef is record
+		 c1  : signed(8 downto 0);
+		 c2  : signed(8 downto 0);
+		 c3  : signed(8 downto 0);
+		 c4  : signed(8 downto 0);
+	end record t_Coef;  	
+	
+	signal coefx_next: t_Coef;
+	signal coefx_reg : t_Coef;
+	signal coefx3_next: t_Coef;
+	signal coefx3_reg : t_Coef;	
+	signal coefx4_next: t_Coef;
+	signal coefx4_reg : t_Coef;		
+	signal coefy_next: t_Coef;
+	signal coefy_reg : t_Coef;
+	signal next_x_delay2_next : std_logic;
+	signal next_x_delay2_reg : std_logic;		
+
+	-- stage 3 : Y mult
+	signal ry1_next : signed(17 downto 0);
+	signal ry1_reg : signed(17 downto 0);
+	signal ry2_next : signed(17 downto 0);
+	signal ry2_reg : signed(17 downto 0);
+	signal ry3_next : signed(17 downto 0);
+	signal ry3_reg : signed(17 downto 0);
+	signal ry4_next : signed(17 downto 0);
+	signal ry4_reg : signed(17 downto 0);
+
+	signal gy1_next : signed(17 downto 0);
+	signal gy1_reg : signed(17 downto 0);
+	signal gy2_next : signed(17 downto 0);
+	signal gy2_reg : signed(17 downto 0);
+	signal gy3_next : signed(17 downto 0);
+	signal gy3_reg : signed(17 downto 0);
+	signal gy4_next : signed(17 downto 0);
+	signal gy4_reg : signed(17 downto 0);
+
+	signal by1_next : signed(17 downto 0);
+	signal by1_reg : signed(17 downto 0);
+	signal by2_next : signed(17 downto 0);
+	signal by2_reg : signed(17 downto 0);
+	signal by3_next : signed(17 downto 0);
+	signal by3_reg : signed(17 downto 0);
+	signal by4_next : signed(17 downto 0);
+	signal by4_reg : signed(17 downto 0);
+	signal next_x_delay3_next : std_logic;
+	signal next_x_delay3_reg : std_logic;	
+
+	-- stage 4: X pixels
+	signal pixel_rx1_next : signed(8 downto 0);
+	signal pixel_rx1_reg : signed(8 downto 0);
+	signal pixel_rx2_next : signed(8 downto 0);
+	signal pixel_rx2_reg : signed(8 downto 0);
+	signal pixel_rx3_next : signed(8 downto 0);
+	signal pixel_rx3_reg : signed(8 downto 0);
+	signal pixel_rx4_next : signed(8 downto 0);
+	signal pixel_rx4_reg : signed(8 downto 0);
+
+	signal pixel_gx1_next : signed(8 downto 0);
+	signal pixel_gx1_reg : signed(8 downto 0);
+	signal pixel_gx2_next : signed(8 downto 0);
+	signal pixel_gx2_reg : signed(8 downto 0);
+	signal pixel_gx3_next : signed(8 downto 0);
+	signal pixel_gx3_reg : signed(8 downto 0);
+	signal pixel_gx4_next : signed(8 downto 0);
+	signal pixel_gx4_reg : signed(8 downto 0);
+
+	signal pixel_bx1_next : signed(8 downto 0);
+	signal pixel_bx1_reg : signed(8 downto 0);
+	signal pixel_bx2_next : signed(8 downto 0);
+	signal pixel_bx2_reg : signed(8 downto 0);
+	signal pixel_bx3_next : signed(8 downto 0);
+	signal pixel_bx3_reg : signed(8 downto 0);
+	signal pixel_bx4_next : signed(8 downto 0);
+	signal pixel_bx4_reg : signed(8 downto 0);
+
+	-- stage 5: X mult
+	signal rx1_next : signed(17 downto 0);
+	signal rx1_reg : signed(17 downto 0);
+	signal rx2_next : signed(17 downto 0);
+	signal rx2_reg : signed(17 downto 0);
+	signal rx3_next : signed(17 downto 0);
+	signal rx3_reg : signed(17 downto 0);
+	signal rx4_next : signed(17 downto 0);
+	signal rx4_reg : signed(17 downto 0);
+
+	signal gx1_next : signed(17 downto 0);
+	signal gx1_reg : signed(17 downto 0);
+	signal gx2_next : signed(17 downto 0);
+	signal gx2_reg : signed(17 downto 0);
+	signal gx3_next : signed(17 downto 0);
+	signal gx3_reg : signed(17 downto 0);
+	signal gx4_next : signed(17 downto 0);
+	signal gx4_reg : signed(17 downto 0);
+
+	signal bx1_next : signed(17 downto 0);
+	signal bx1_reg : signed(17 downto 0);
+	signal bx2_next : signed(17 downto 0);
+	signal bx2_reg : signed(17 downto 0);
+	signal bx3_next : signed(17 downto 0);
+	signal bx3_reg : signed(17 downto 0);
+	signal bx4_next : signed(17 downto 0);
+	signal bx4_reg : signed(17 downto 0);
+
+	-- stage 6: Pixel output (sum)
+	signal r_reg : std_logic_vector(7 downto 0);
+	signal r_next : std_logic_vector(7 downto 0);
+	signal g_reg : std_logic_vector(7 downto 0);
+	signal g_next : std_logic_vector(7 downto 0);
+	signal b_reg : std_logic_vector(7 downto 0);
+	signal b_next : std_logic_vector(7 downto 0);
+
+BEGIN
+	process(clock,reset_n)
+	begin
+		if (reset_n='0') then
+			-- multi stage 1-5
+			hsync_reg <= (others=>'0');
+			vsync_reg <= (others=>'0');
+			blank_reg <= (others=>'0');
+
+			-- stage 1
+			xacc_reg <= (others=>'0');
+			yacc_reg <= (others=>'0');
+			next_x_delay1_reg <= '0';
+
+			-- stage 2
+			coefx_reg.c1 <= (others=>'0');
+			coefx_reg.c2 <= (others=>'0');
+			coefx_reg.c3 <= (others=>'0');
+			coefx_reg.c4 <= (others=>'0');
+			coefy_reg.c1 <= (others=>'0');
+			coefy_reg.c2 <= (others=>'0');
+			coefy_reg.c3 <= (others=>'0');
+			coefy_reg.c4 <= (others=>'0');
+			next_x_delay2_reg <= '0';
+
+			-- stage 3
+			ry1_reg <= (others=>'0');
+			ry2_reg <= (others=>'0');
+			ry3_reg <= (others=>'0');
+			ry4_reg <= (others=>'0');
+
+			gy1_reg <= (others=>'0');
+			gy2_reg <= (others=>'0');
+			gy3_reg <= (others=>'0');
+			gy4_reg <= (others=>'0');
+
+			by1_reg <= (others=>'0');
+			by2_reg <= (others=>'0');
+			by3_reg <= (others=>'0');
+			by4_reg <= (others=>'0');
+			
+			coefx3_reg.c1 <= (others=>'0');
+			coefx3_reg.c2 <= (others=>'0');
+			coefx3_reg.c3 <= (others=>'0');
+			coefx3_reg.c4 <= (others=>'0');	
+			next_x_delay3_reg <= '0';
+
+			-- stage 4
+			pixel_rx1_reg <= (others=>'0');
+			pixel_gx1_reg <= (others=>'0');
+			pixel_bx1_reg <= (others=>'0');
+
+			pixel_rx2_reg <= (others=>'0');
+			pixel_gx2_reg <= (others=>'0');
+			pixel_bx2_reg <= (others=>'0');
+
+			pixel_rx3_reg <= (others=>'0');
+			pixel_gx3_reg <= (others=>'0');
+			pixel_bx3_reg <= (others=>'0');
+
+			pixel_rx4_reg <= (others=>'0');
+			pixel_gx4_reg <= (others=>'0');
+			pixel_bx4_reg <= (others=>'0');		
+	
+			coefx4_reg.c1 <= (others=>'0');
+			coefx4_reg.c2 <= (others=>'0');
+			coefx4_reg.c3 <= (others=>'0');
+			coefx4_reg.c4 <= (others=>'0');	
+
+			-- stage 5
+			rx1_reg <= (others=>'0');
+			rx2_reg <= (others=>'0');
+			rx3_reg <= (others=>'0');
+			rx4_reg <= (others=>'0');
+
+			gx1_reg <= (others=>'0');
+			gx2_reg <= (others=>'0');
+			gx3_reg <= (others=>'0');
+			gx4_reg <= (others=>'0');
+
+			bx1_reg <= (others=>'0');
+			bx2_reg <= (others=>'0');
+			bx3_reg <= (others=>'0');
+			bx4_reg <= (others=>'0');
+
+			-- stage 6
+			r_reg <= (others=>'0');
+			g_reg <= (others=>'0');
+			b_reg <= (others=>'0');
+		elsif (clock'event and clock='1') then
+			-- multi stage 1-5
+			hsync_reg <= hsync_next;
+			vsync_reg <= vsync_next;
+			blank_reg <= blank_next;			
+			
+			-- stage 1
+			xacc_reg <= xacc_next;
+			yacc_reg <= yacc_next;
+			next_x_delay1_reg <= next_x_delay1_next;
+
+			-- stage 2
+			coefx_reg <= coefx_next;
+			coefy_reg <= coefy_next;
+			next_x_delay2_reg <= next_x_delay2_next;
+
+			-- stage 3
+			ry1_reg <= ry1_next;
+			ry2_reg <= ry2_next;
+			ry3_reg <= ry3_next;
+			ry4_reg <= ry4_next;
+
+			gy1_reg <= gy1_next;
+			gy2_reg <= gy2_next;
+			gy3_reg <= gy3_next;
+			gy4_reg <= gy4_next;
+
+			by1_reg <= by1_next;
+			by2_reg <= by2_next;
+			by3_reg <= by3_next;
+			by4_reg <= by4_next;
+			
+			coefx3_reg <= coefx3_next;			
+			next_x_delay3_reg <= next_x_delay3_next;
+
+			-- stage 4
+			pixel_rx1_reg <= pixel_rx1_next;
+			pixel_gx1_reg <= pixel_gx1_next;
+			pixel_bx1_reg <= pixel_bx1_next;
+
+			pixel_rx2_reg <= pixel_rx2_next;
+			pixel_gx2_reg <= pixel_gx2_next;
+			pixel_bx2_reg <= pixel_bx2_next;
+
+			pixel_rx3_reg <= pixel_rx3_next;
+			pixel_gx3_reg <= pixel_gx3_next;
+			pixel_bx3_reg <= pixel_bx3_next;
+
+			pixel_rx4_reg <= pixel_rx4_next;
+			pixel_gx4_reg <= pixel_gx4_next;
+			pixel_bx4_reg <= pixel_bx4_next;
+			
+			coefx4_reg <= coefx4_next;		
+
+			-- stage 5
+			rx1_reg <= rx1_next;
+			rx2_reg <= rx2_next;
+			rx3_reg <= rx3_next;
+			rx4_reg <= rx4_next;
+
+			gx1_reg <= gx1_next;
+			gx2_reg <= gx2_next;
+			gx3_reg <= gx3_next;
+			gx4_reg <= gx4_next;
+
+			bx1_reg <= bx1_next;
+			bx2_reg <= bx2_next;
+			bx3_reg <= bx3_next;
+			bx4_reg <= bx4_next;
+
+			-- stage 6
+			r_reg <= r_next;
+			g_reg <= g_next;
+			b_reg <= b_next;
+		end if;
+	end process;
+	
+	-- temporary params, until i2c implemented
+	-- 720p
+--	param_xthreshold_next <= to_unsigned(699,10); -- these need to be inputs
+--	param_xdelta_next <= to_unsigned(393,10);
+--	param_ythreshold_next <= to_unsigned(400,9);
+--	param_ydelta_next <= to_unsigned(166,9);
+-- param_ydeltaeach_next <= to_unsigned(166,9);
+--	param_xaddrskip_next <= "10";
+
+	-- 1080i
+--	param_xthreshold_next <= to_unsigned(400,11); -- these need to be inputs
+--	param_xdelta_next <= to_unsigned(300,11);
+--	param_ythreshold_next <= to_unsigned(786,11);
+--	param_ydelta_next <= to_unsigned(218,11);
+--	param_ydeltaeach_next <= to_unsigned(437,11); --interlace, need to skip a line
+--	param_xaddrskip_next <= "01";
+
+
+--	param_xthreshold_next <= to_unsigned(1024,11); -- these need to be inputs
+--	param_xdelta_next <= to_unsigned(768,11);
+--	--param_xdelta_next <= to_unsigned(64,11);
+--	param_ythreshold_next <= to_unsigned(1024,11);
+--	--param_ydelta_next <= to_unsigned(284,11);
+--	param_ydeltaeach_next <= to_unsigned(569,11); --interlace, need to skip a line
+--	param_xaddrskip_next <= "01";
+	
+-- params set from i2c
+	i2cregs : entity work.I2C_regs
+	generic map (
+		SLAVE_ADDR => "0000011", --will we activate this and areascale at once? i.e. do I give it another address?
+		regs => 3,
+		bits => 11
+	)
+	port map (
+		scl => scl,
+		sda => sda,
+		clk => clock,
+		rst => not(reset_n),
+		
+		reg => params			
+	);
+	
+	fixed_xthreshold_reg <= to_unsigned(1024,11);
+	fixed_ythreshold_reg <= to_unsigned(1024,11);	
+	
+	param_xdelta_reg <= unsigned(params(11*1-1 downto 11*0));
+	param_ydeltaeach_reg <= unsigned(params(11*2-1 downto 11*1));
+	param_xaddrskip_reg <= unsigned(params(11*2+2-1 downto 11*2));		
+	
+	-- TODO: how about filter params too?
+	
+--  Delay sync in line with pipeline: multi stage 1-5
+   process(hsync_reg,vsync_reg,blank_reg,hsync_in,vsync_in,blank_in)
+	begin		
+		hsync_next <= hsync_reg(5 downto 1)&hsync_in;
+		vsync_next <= vsync_reg(5 downto 1)&vsync_in;
+		blank_next <= blank_reg(5 downto 1)&blank_in;
+	end process;
+
+-- 	Compute accumulator - pipeline stage 1
+	process(xacc_reg,param_xdelta_reg,fixed_xthreshold_reg,next_y_in)
+	begin
+		next_x <= '0';
+		next_x_delay1_next <= '0';
+		xacc_next <= xacc_reg+param_xdelta_reg;
+		if ((xacc_reg+param_xdelta_reg)>=fixed_xthreshold_reg) then
+			next_x <= '1'; -- when I ask for data, its on p1 in 2 cycles, i.e. pipeline stage 3
+			next_x_delay1_next <= '1';
+			xacc_next <= xacc_reg+param_xdelta_reg-fixed_xthreshold_reg;
+		end if;
+
+		if (next_y_in ='1') then 
+			xacc_next <= (others=>'0');
+		end if;
+	end process;
+
+	process(yacc_reg,param_ydeltaeach_reg,fixed_ythreshold_reg,next_y_in,next_frame_in,field2)
+	begin
+		yacc_next <= yacc_reg;
+		next_y <= '0';
+
+		if (next_y_in='1') then
+			yacc_next <= yacc_reg+param_ydeltaeach_reg; 
+			if ((yacc_reg+param_ydeltaeach_reg)>=fixed_ythreshold_reg) then
+				next_y <= '1';
+				yacc_next <= yacc_reg+param_ydeltaeach_reg-fixed_ythreshold_reg;
+			end if;
+		end if;
+
+		if (next_frame_in='1') then
+			yacc_next <= (others=>'0');
+			if (field2='1') then --slightly lower on interlace field 2
+				yacc_next(9 downto 0) <= fixed_ythreshold_reg(10 downto 1);
+			end if;
+		end if;
+	end process;
+
+--      Coef computation - pipeline stage 2
+	process(
+		xacc_reg,
+		yacc_reg)
+	variable xphase : std_logic_vector(3 downto 0);
+	variable yphase : std_logic_vector(3 downto 0);
+	begin
+		coefx_next.c1 <= (others=>'0');
+		coefx_next.c2 <= (others=>'0');
+		coefx_next.c3 <= (others=>'0');
+		coefx_next.c4 <= (others=>'0');
+		coefy_next.c1 <= (others=>'0');
+		coefy_next.c2 <= (others=>'0');
+		coefy_next.c3 <= (others=>'0');
+		coefy_next.c4 <= (others=>'0');
+
+		xphase := std_logic_vector(xacc_reg(9 downto 6));
+		yphase := std_logic_vector(yacc_reg(9 downto 6));
+
+--		case xphase is
+--		when "0000" =>
+--			coefx_next <= x"7f000000";
+--		when "0001" =>
+--			coefx_next <= x"7f000000";
+--		when "0010" =>
+--			coefx_next <= x"7f000000";
+--		when "0011" =>
+--			coefx_next <= x"7f000000";
+--		when "0100" =>
+--			coefx_next <= x"7f000000";
+--		when "0101" =>
+--			coefx_next <= x"7f000000";
+--		when "0110" =>
+--			coefx_next <= x"7f000000";
+--		when "0111" =>
+--			coefx_next <= x"7f000000";
+--		when "1000" =>
+--		        coefx_next <= x"7f000000";
+--		when "1001" =>
+--		        coefx_next <= x"7f000000";
+--		when "1010" =>
+--		        coefx_next <= x"7f000000";
+--		when "1011" =>
+--		        coefx_next <= x"7f000000";
+--		when "1100" =>
+--		        coefx_next <= x"7f000000";
+--		when "1101" =>
+--		        coefx_next <= x"7f000000";
+--		when "1110" =>
+--		        coefx_next <= x"7f000000";
+--		when "1111" =>
+--			coefx_next <= x"7f000000";
+--		when others=>
+--			coefx_next <= (others=>'0');
+--		end case;
+--
+--		case yphase is
+--		when "0000" =>
+--			coefy_next <= x"7f000000";
+--		when "0001" =>
+--			coefy_next <= x"7f000000";
+--		when "0010" =>
+--			coefy_next <= x"7f000000";
+--		when "0011" =>
+--			coefy_next <= x"7f000000";
+--		when "0100" =>
+--			coefy_next <= x"7f000000";
+--		when "0101" =>
+--			coefy_next <= x"7f000000";
+--		when "0110" =>
+--			coefy_next <= x"7f000000";
+--		when "0111" =>
+--			coefy_next <= x"7f000000";
+--		when "1000" =>
+--		        coefy_next <= x"7f000000";
+--		when "1001" =>
+--		        coefy_next <= x"7f000000";
+--		when "1010" =>
+--		        coefy_next <= x"7f000000";
+--		when "1011" =>
+--		        coefy_next <= x"7f000000";
+--		when "1100" =>
+--		        coefy_next <= x"7f000000";
+--		when "1101" =>
+--		        coefy_next <= x"7f000000";
+--		when "1110" =>
+--		        coefy_next <= x"7f000000";
+--		when "1111" =>
+--			coefy_next <= x"7f000000";
+--		when others=>
+--			coefy_next <= (others=>'0');
+--		end case;
+case xphase is 
+when "0000" =>
+	coefx_next.c1 <= to_signed(-8,9);
+	coefx_next.c2 <= to_signed(147,9);
+	coefx_next.c3 <= to_signed(-8,9);
+	coefx_next.c4 <= to_signed(1,9);
+when "0001" =>
+	coefx_next.c1 <= to_signed(-6,9);
+	coefx_next.c2 <= to_signed(148,9);
+	coefx_next.c3 <= to_signed(-11,9);
+	coefx_next.c4 <= to_signed(1,9);
+when "0010" =>
+	coefx_next.c1 <= to_signed(-3,9);
+	coefx_next.c2 <= to_signed(147,9);
+	coefx_next.c3 <= to_signed(-13,9);
+	coefx_next.c4 <= to_signed(1,9);
+when "0011" =>
+	coefx_next.c1 <= to_signed(-1,9);
+	coefx_next.c2 <= to_signed(145,9);
+	coefx_next.c3 <= to_signed(-13,9);
+	coefx_next.c4 <= to_signed(1,9);
+when "0100" =>
+	coefx_next.c1 <= to_signed(0,9);
+	coefx_next.c2 <= to_signed(141,9);
+	coefx_next.c3 <= to_signed(-10,9);
+	coefx_next.c4 <= to_signed(1,9);
+when "0101" =>
+	coefx_next.c1 <= to_signed(1,9);
+	coefx_next.c2 <= to_signed(133,9);
+	coefx_next.c3 <= to_signed(-3,9);
+	coefx_next.c4 <= to_signed(1,9);
+when "0110" =>
+	coefx_next.c1 <= to_signed(1,9);
+	coefx_next.c2 <= to_signed(118,9);
+	coefx_next.c3 <= to_signed(12,9);
+	coefx_next.c4 <= to_signed(1,9);
+when "0111" =>
+	coefx_next.c1 <= to_signed(1,9);
+	coefx_next.c2 <= to_signed(95,9);
+	coefx_next.c3 <= to_signed(35,9);
+	coefx_next.c4 <= to_signed(1,9);
+when "1000" =>
+	coefx_next.c1 <= to_signed(1,9);
+	coefx_next.c2 <= to_signed(65,9);
+	coefx_next.c3 <= to_signed(65,9);
+	coefx_next.c4 <= to_signed(1,9);
+when "1001" =>
+	coefx_next.c1 <= to_signed(1,9);
+	coefx_next.c2 <= to_signed(35,9);
+	coefx_next.c3 <= to_signed(95,9);
+	coefx_next.c4 <= to_signed(1,9);
+when "1010" =>
+	coefx_next.c1 <= to_signed(1,9);
+	coefx_next.c2 <= to_signed(12,9);
+	coefx_next.c3 <= to_signed(118,9);
+	coefx_next.c4 <= to_signed(1,9);
+when "1011" =>
+	coefx_next.c1 <= to_signed(1,9);
+	coefx_next.c2 <= to_signed(-3,9);
+	coefx_next.c3 <= to_signed(133,9);
+	coefx_next.c4 <= to_signed(1,9);
+when "1100" =>
+	coefx_next.c1 <= to_signed(1,9);
+	coefx_next.c2 <= to_signed(-10,9);
+	coefx_next.c3 <= to_signed(141,9);
+	coefx_next.c4 <= to_signed(0,9);
+when "1101" =>
+	coefx_next.c1 <= to_signed(1,9);
+	coefx_next.c2 <= to_signed(-13,9);
+	coefx_next.c3 <= to_signed(145,9);
+	coefx_next.c4 <= to_signed(-1,9);
+when "1110" =>
+	coefx_next.c1 <= to_signed(1,9);
+	coefx_next.c2 <= to_signed(-13,9);
+	coefx_next.c3 <= to_signed(147,9);
+	coefx_next.c4 <= to_signed(-3,9);
+when "1111" =>
+	coefx_next.c1 <= to_signed(1,9);
+	coefx_next.c2 <= to_signed(-11,9);
+	coefx_next.c3 <= to_signed(148,9);
+	coefx_next.c4 <= to_signed(-6,9);
+when others => 
+	coefx_next.c1 <= (others=>'0');
+	coefx_next.c2 <= (others=>'0');
+	coefx_next.c3 <= (others=>'0');
+	coefx_next.c4 <= (others=>'0');
+end case;
+case yphase is 
+when "0000" =>
+	coefy_next.c1 <= to_signed(-8,9);
+	coefy_next.c2 <= to_signed(147,9);
+	coefy_next.c3 <= to_signed(-8,9);
+	coefy_next.c4 <= to_signed(1,9);
+when "0001" =>
+	coefy_next.c1 <= to_signed(-6,9);
+	coefy_next.c2 <= to_signed(148,9);
+	coefy_next.c3 <= to_signed(-11,9);
+	coefy_next.c4 <= to_signed(1,9);
+when "0010" =>
+	coefy_next.c1 <= to_signed(-3,9);
+	coefy_next.c2 <= to_signed(147,9);
+	coefy_next.c3 <= to_signed(-13,9);
+	coefy_next.c4 <= to_signed(1,9);
+when "0011" =>
+	coefy_next.c1 <= to_signed(-1,9);
+	coefy_next.c2 <= to_signed(145,9);
+	coefy_next.c3 <= to_signed(-13,9);
+	coefy_next.c4 <= to_signed(1,9);
+when "0100" =>
+	coefy_next.c1 <= to_signed(0,9);
+	coefy_next.c2 <= to_signed(141,9);
+	coefy_next.c3 <= to_signed(-10,9);
+	coefy_next.c4 <= to_signed(1,9);
+when "0101" =>
+	coefy_next.c1 <= to_signed(1,9);
+	coefy_next.c2 <= to_signed(133,9);
+	coefy_next.c3 <= to_signed(-3,9);
+	coefy_next.c4 <= to_signed(1,9);
+when "0110" =>
+	coefy_next.c1 <= to_signed(1,9);
+	coefy_next.c2 <= to_signed(118,9);
+	coefy_next.c3 <= to_signed(12,9);
+	coefy_next.c4 <= to_signed(1,9);
+when "0111" =>
+	coefy_next.c1 <= to_signed(1,9);
+	coefy_next.c2 <= to_signed(95,9);
+	coefy_next.c3 <= to_signed(35,9);
+	coefy_next.c4 <= to_signed(1,9);
+when "1000" =>
+	coefy_next.c1 <= to_signed(1,9);
+	coefy_next.c2 <= to_signed(65,9);
+	coefy_next.c3 <= to_signed(65,9);
+	coefy_next.c4 <= to_signed(1,9);
+when "1001" =>
+	coefy_next.c1 <= to_signed(1,9);
+	coefy_next.c2 <= to_signed(35,9);
+	coefy_next.c3 <= to_signed(95,9);
+	coefy_next.c4 <= to_signed(1,9);
+when "1010" =>
+	coefy_next.c1 <= to_signed(1,9);
+	coefy_next.c2 <= to_signed(12,9);
+	coefy_next.c3 <= to_signed(118,9);
+	coefy_next.c4 <= to_signed(1,9);
+when "1011" =>
+	coefy_next.c1 <= to_signed(1,9);
+	coefy_next.c2 <= to_signed(-3,9);
+	coefy_next.c3 <= to_signed(133,9);
+	coefy_next.c4 <= to_signed(1,9);
+when "1100" =>
+	coefy_next.c1 <= to_signed(1,9);
+	coefy_next.c2 <= to_signed(-10,9);
+	coefy_next.c3 <= to_signed(141,9);
+	coefy_next.c4 <= to_signed(0,9);
+when "1101" =>
+	coefy_next.c1 <= to_signed(1,9);
+	coefy_next.c2 <= to_signed(-13,9);
+	coefy_next.c3 <= to_signed(145,9);
+	coefy_next.c4 <= to_signed(-1,9);
+when "1110" =>
+	coefy_next.c1 <= to_signed(1,9);
+	coefy_next.c2 <= to_signed(-13,9);
+	coefy_next.c3 <= to_signed(147,9);
+	coefy_next.c4 <= to_signed(-3,9);
+when "1111" =>
+	coefy_next.c1 <= to_signed(1,9);
+	coefy_next.c2 <= to_signed(-11,9);
+	coefy_next.c3 <= to_signed(148,9);
+	coefy_next.c4 <= to_signed(-6,9);
+when others => 
+	coefy_next.c1 <= (others=>'0');
+	coefy_next.c2 <= (others=>'0');
+	coefy_next.c3 <= (others=>'0');
+	coefy_next.c4 <= (others=>'0');
+end case;
+
+
+	end process;
+
+	next_x_delay2_next <= next_x_delay1_reg;
+	
+--      YMult - pipeline stage 3
+	process(pixels, coefy_reg)
+		variable p1 : t_pixel;
+		variable p2 : t_pixel;
+		variable p3 : t_pixel;
+		variable p4 : t_pixel;
+	begin
+		p1 := pixels(pixel4x4_idx(0,0));
+		p2 := pixels(pixel4x4_idx(0,1));
+		p3 := pixels(pixel4x4_idx(0,2));
+		p4 := pixels(pixel4x4_idx(0,3));
+
+		-- dsp blocks 9x9 multipliers
+		-- 3 per block -> 4 blocks
+		ry1_next <= signed('0'&p1.red)*coefy_reg.c1;
+		ry2_next <= signed('0'&p2.red)*coefy_reg.c2;
+		ry3_next <= signed('0'&p3.red)*coefy_reg.c3;
+		ry4_next <= signed('0'&p4.red)*coefy_reg.c4;
+
+		gy1_next <= signed('0'&p1.green)*coefy_reg.c1;
+		gy2_next <= signed('0'&p2.green)*coefy_reg.c2;
+		gy3_next <= signed('0'&p3.green)*coefy_reg.c3;
+		gy4_next <= signed('0'&p4.green)*coefy_reg.c4;
+
+		by1_next <= signed('0'&p1.blue)*coefy_reg.c1;
+		by2_next <= signed('0'&p2.blue)*coefy_reg.c2;
+		by3_next <= signed('0'&p3.blue)*coefy_reg.c3;
+		by4_next <= signed('0'&p4.blue)*coefy_reg.c4;
+	end process;
+	
+	next_x_delay3_next <= next_x_delay2_reg;
+	coefx3_next <= coefx_reg;
+
+--      X pixels - pipeline stage 4
+	process(
+		pixel_rx1_reg,pixel_rx2_reg,pixel_rx3_reg,pixel_rx4_reg,
+		pixel_gx1_reg,pixel_gx2_reg,pixel_gx3_reg,pixel_gx4_reg,
+		pixel_bx1_reg,pixel_bx2_reg,pixel_bx3_reg,pixel_bx4_reg,
+		ry1_reg,ry2_reg,ry3_reg,ry4_reg,
+		gy1_reg,gy2_reg,gy3_reg,gy4_reg,
+		by1_reg,by2_reg,by3_reg,by4_reg,
+		next_x_delay3_reg
+		)
+		variable ry_sum : signed (17 downto 0);
+		variable gy_sum : signed (17 downto 0);
+		variable by_sum : signed (17 downto 0);
+	begin
+		pixel_rx1_next <= pixel_rx1_reg;
+		pixel_rx2_next <= pixel_rx2_reg;
+		pixel_rx3_next <= pixel_rx3_reg;
+		pixel_rx4_next <= pixel_rx4_reg;
+
+		pixel_gx1_next <= pixel_gx1_reg;
+		pixel_gx2_next <= pixel_gx2_reg;
+		pixel_gx3_next <= pixel_gx3_reg;
+		pixel_gx4_next <= pixel_gx4_reg;
+
+		pixel_bx1_next <= pixel_bx1_reg;
+		pixel_bx2_next <= pixel_bx2_reg;
+		pixel_bx3_next <= pixel_bx3_reg;
+		pixel_bx4_next <= pixel_bx4_reg;
+
+		if (next_x_delay3_reg='1') then
+--		   ry_sum := ry1_reg+ry2_reg+ry3_reg+ry4_reg;			
+--			pixel_rx1_next <= ry_sum(17)&ry_sum(15 downto 8); 
+--			pixel_rx2_next <= pixel_rx1_reg;
+--			pixel_rx3_next <= pixel_rx2_reg;
+--			pixel_rx4_next <= pixel_rx3_reg;
+--
+--			gy_sum := gy1_reg+gy2_reg+gy3_reg+gy4_reg;
+--			pixel_gx1_next <= gy_sum(17)&gy_sum(15 downto 8);
+--			pixel_gx2_next <= pixel_gx1_reg;
+--			pixel_gx3_next <= pixel_gx2_reg;
+--			pixel_gx4_next <= pixel_gx3_reg;
+--
+--			by_sum := by1_reg+by2_reg+by3_reg+by4_reg;
+--			pixel_bx1_next <= by_sum(17)&by_sum(15 downto 8);
+--			pixel_bx2_next <= pixel_bx1_reg;
+--			pixel_bx3_next <= pixel_bx2_reg;
+--			pixel_bx4_next <= pixel_bx3_reg;
+			
+		   ry_sum := ry1_reg+ry2_reg+ry3_reg+ry4_reg;			
+			pixel_rx4_next <= ry_sum(17)&ry_sum(15 downto 8); 
+			pixel_rx3_next <= pixel_rx4_reg;
+			pixel_rx2_next <= pixel_rx3_reg;
+			pixel_rx1_next <= pixel_rx2_reg;
+
+			gy_sum := gy1_reg+gy2_reg+gy3_reg+gy4_reg;
+			pixel_gx4_next <= gy_sum(17)&gy_sum(15 downto 8);
+			pixel_gx3_next <= pixel_gx4_reg;
+			pixel_gx2_next <= pixel_gx3_reg;
+			pixel_gx1_next <= pixel_gx2_reg;
+
+			by_sum := by1_reg+by2_reg+by3_reg+by4_reg;
+			pixel_bx4_next <= by_sum(17)&by_sum(15 downto 8);
+			pixel_bx3_next <= pixel_bx4_reg;
+			pixel_bx2_next <= pixel_bx3_reg;
+			pixel_bx1_next <= pixel_bx2_reg;			
+		end if;
+	end process;
+	
+	coefx4_next <= coefx3_reg;	
+
+--      X mult - pipeline stage 5
+	process(
+		pixel_rx1_reg,pixel_rx2_reg,pixel_rx3_reg,pixel_rx4_reg,
+		pixel_gx1_reg,pixel_gx2_reg,pixel_gx3_reg,pixel_gx4_reg,
+		pixel_bx1_reg,pixel_bx2_reg,pixel_bx3_reg,pixel_bx4_reg,
+	       	coefx4_reg)
+	begin
+		-- dsp blocks 9x9 multipliers
+		-- 3 per block -> 4 blocks
+		rx1_next <= pixel_rx1_reg*coefx4_reg.c1;
+		rx2_next <= pixel_rx2_reg*coefx4_reg.c2;
+		rx3_next <= pixel_rx3_reg*coefx4_reg.c3;
+		rx4_next <= pixel_rx4_reg*coefx4_reg.c4;
+
+		gx1_next <= pixel_gx1_reg*coefx4_reg.c1;
+		gx2_next <= pixel_gx2_reg*coefx4_reg.c2;
+		gx3_next <= pixel_gx3_reg*coefx4_reg.c3;
+		gx4_next <= pixel_gx4_reg*coefx4_reg.c4;
+
+		bx1_next <= pixel_bx1_reg*coefx4_reg.c1;
+		bx2_next <= pixel_bx2_reg*coefx4_reg.c2;
+		bx3_next <= pixel_bx3_reg*coefx4_reg.c3;
+		bx4_next <= pixel_bx4_reg*coefx4_reg.c4;
+	end process;
+
+
+--      Pixel scaling computation - pipeline stage 6
+	-- Compute output
+	-- (p1*A1 + p2*A2 + p3*A3 + p4*A4)/65536
+	process(
+		rx1_reg,rx2_reg,rx3_reg,rx4_reg,
+		gx1_reg,gx2_reg,gx3_reg,gx4_reg,
+		bx1_reg,bx2_reg,bx3_reg,bx4_reg)
+		variable sum_r : signed(17 downto 0);
+		variable sum_g : signed(17 downto 0);
+		variable sum_b : signed(17 downto 0);
+	begin
+		sum_r := (rx1_reg+rx2_reg)+(rx3_reg+rx4_reg);
+		sum_g := (gx1_reg+gx2_reg)+(gx3_reg+gx4_reg);
+		sum_b := (bx1_reg+bx2_reg)+(bx3_reg+bx4_reg);
+
+		if (sum_r(17)='1') then
+			sum_r := (others=>'0');
+		elsif (sum_r(15) or sum_r(14))='1' then
+			sum_r := to_signed(16383,18);
+		end if;
+		if (sum_g(17)='1') then
+			sum_g := (others=>'0');
+		elsif (sum_g(15) or sum_g(14))='1' then
+			sum_g := to_signed(16383,18);
+		end if;
+		if (sum_b(17)='1') then
+			sum_b := (others=>'0');
+		elsif (sum_b(15) or sum_b(14))='1' then
+			sum_b := to_signed(16383,18);
+		end if;
+		r_next <= std_logic_vector(sum_r(13 downto 6));
+		g_next <= std_logic_vector(sum_g(13 downto 6));
+		b_next <= std_logic_vector(sum_b(13 downto 6));
+	end process;
+
+	-- outputnext_x_size
+	r<=r_reg;
+	g<=g_reg;
+	b<=b_reg;
+	hsync<=hsync_reg(6); -- TODO: why 6 and not 5?
+	vsync<=vsync_reg(6);
+	blank<=blank_reg(6); 
+	
+	next_x_size <= std_logic_vector(param_xaddrskip_reg);
+
+END vhdl;
+
+--              h_pixels_across  <= 720 - 1;
+--              h_sync_on <= 732 - 1;
+--              h_sync_off <= 795 - 1;
+--              h_end_count <= 864 - 1;
+--              v_pixels_down <= 576 - 1;
+--              v_sync_on <=  581 - 1;
+--              v_sync_off <= 586 - 1;
+--              v_end_count <=  625 - 1;
+
+--                --PAL
+--                h_pixels_across  <= 1280 - 1;
+--                h_sync_on <= 1720 - 1;
+--                h_sync_off <= 1760 - 1;
+--                h_end_count <= 1980 - 1;
+--                v_pixels_down <= 720 - 1;
+--                v_sync_on <=  725 - 1;
+--                v_sync_off <= 730 - 1;
+--                v_end_count <=  750 - 1;
+
+
+
Index: eclaireXL_ITX/pll_usb.bsf
===================================================================
--- eclaireXL_ITX/pll_usb.bsf	(revision 973)
+++ eclaireXL_ITX/pll_usb.bsf	(revision 974)
@@ -4,7 +4,7 @@
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 2016  Intel Corporation. All rights reserved.
+Copyright (C) 2018  Intel Corporation. All rights reserved.
 Your use of Intel Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -12,12 +12,11 @@
 associated documentation or information are expressly subject 
 to the terms and conditions of the Intel Program License 
 Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other 
-applicable license agreement, including, without limitation, 
-that your use is for the sole purpose of programming logic 
-devices manufactured by Intel and sold by Intel or its 
-authorized distributors.  Please refer to the applicable 
-agreement for further details.
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
 */
 (header "symbol" (version "1.1"))
 (symbol
Index: eclaireXL_ITX/pll_usb_sim/aldec/rivierapro_setup.tcl
===================================================================
--- eclaireXL_ITX/pll_usb_sim/aldec/rivierapro_setup.tcl	(revision 973)
+++ eclaireXL_ITX/pll_usb_sim/aldec/rivierapro_setup.tcl	(revision 974)
@@ -1,5 +1,5 @@
 
-# (C) 2001-2016 Altera Corporation. All rights reserved.
+# (C) 2001-2020 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 16.1 196 linux 2016.12.30.21:53:15
+# ACDS 18.0 614 linux 2020.02.02.21:03:29
 # ----------------------------------------
 # Auto-generated simulation script rivierapro_setup.tcl
 # ----------------------------------------
@@ -47,6 +47,8 @@
 # #
 # # Set any compilation options you require (this is unusual).
 # set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
 # #
 # # Call command to compile the Quartus EDA simulation library.
 # dev_com
@@ -111,12 +113,18 @@
 }
 
 if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/home/markw/fpga/intelFPGA_lite/16.1/quartus/"
+  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/18.0/quartus/"
 }
 
 if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
   set USER_DEFINED_COMPILE_OPTIONS ""
 }
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
 if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
   set USER_DEFINED_ELAB_OPTIONS ""
 }
@@ -170,23 +178,23 @@
 # Compile device library files
 alias dev_com {
   echo "\[exec\] dev_com"
-  eval vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
-  vlog  $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
-  vlog -v2k5 $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v"    -work cyclonev    
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
-  vcom $USER_DEFINED_COMPILE_OPTIONS       "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+  eval vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v"    -work cyclonev    
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
 }
 
 # ----------------------------------------
@@ -193,7 +201,7 @@
 # Compile the design files in correct order
 alias com {
   echo "\[exec\] com"
-  eval  vcom $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_usb.vho"
+  eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_usb.vho"
 }
 
 # ----------------------------------------
@@ -231,37 +239,41 @@
 alias h {
   echo "List Of Command Line Aliases"
   echo
-  echo "file_copy                     -- Copy ROM/RAM files to simulation directory"
+  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
   echo
-  echo "dev_com                       -- Compile device library files"
+  echo "dev_com                                           -- Compile device library files"
   echo
-  echo "com                           -- Compile the design files in correct order"
+  echo "com                                               -- Compile the design files in correct order"
   echo
-  echo "elab                          -- Elaborate top level design"
+  echo "elab                                              -- Elaborate top level design"
   echo
-  echo "elab_debug                    -- Elaborate the top level design with -dbg -O2 option"
+  echo "elab_debug                                        -- Elaborate the top level design with -dbg -O2 option"
   echo
-  echo "ld                            -- Compile all the design files and elaborate the top level design"
+  echo "ld                                                -- Compile all the design files and elaborate the top level design"
   echo
-  echo "ld_debug                      -- Compile all the design files and elaborate the top level design with -dbg -O2"
+  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -dbg -O2"
   echo
   echo 
   echo
   echo "List Of Variables"
   echo
-  echo "TOP_LEVEL_NAME                -- Top level module name."
-  echo "                                 For most designs, this should be overridden"
-  echo "                                 to enable the elab/elab_debug aliases."
+  echo "TOP_LEVEL_NAME                                    -- Top level module name."
+  echo "                                                     For most designs, this should be overridden"
+  echo "                                                     to enable the elab/elab_debug aliases."
   echo
-  echo "SYSTEM_INSTANCE_NAME          -- Instantiated system module name inside top level module."
+  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
   echo
-  echo "QSYS_SIMDIR                   -- Qsys base simulation directory."
+  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
   echo
-  echo "QUARTUS_INSTALL_DIR           -- Quartus installation directory."
+  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
   echo
-  echo "USER_DEFINED_COMPILE_OPTIONS  -- User-defined compile options, added to com/dev_com aliases."
+  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
   echo
-  echo "USER_DEFINED_ELAB_OPTIONS     -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo
+  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
 }
 file_copy
 h
Index: eclaireXL_ITX/pll_usb_sim/synopsys/vcsmx/vcsmx_setup.sh
===================================================================
--- eclaireXL_ITX/pll_usb_sim/synopsys/vcsmx/vcsmx_setup.sh	(revision 973)
+++ eclaireXL_ITX/pll_usb_sim/synopsys/vcsmx/vcsmx_setup.sh	(revision 974)
@@ -1,5 +1,5 @@
 
-# (C) 2001-2016 Altera Corporation. All rights reserved.
+# (C) 2001-2020 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -12,7 +12,7 @@
 # or its authorized distributors. Please refer to the applicable 
 # agreement for further details.
 
-# ACDS 16.1 196 linux 2016.12.30.21:53:15
+# ACDS 18.0 614 linux 2020.02.02.21:03:29
 
 # ----------------------------------------
 # vcsmx - auto-generated simulation script
@@ -55,11 +55,17 @@
 # # simulation libraries and Quartus-generated IP simulation files, and copy
 # # any ROM/RAM initialization files to the simulation directory.
 # #
-# # - If necessary, specify USER_DEFINED_COMPILE_OPTIONS.
+# # - If necessary, specify any compilation options:
+# #   USER_DEFINED_COMPILE_OPTIONS
+# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
 # source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
 # SKIP_ELAB=1 \
 # SKIP_SIM=1 \
 # USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
 # QSYS_SIMDIR=<script generation output directory>
 # #
 # # Compile all design files and testbench files, including the top level.
@@ -101,12 +107,12 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 16.1 196 linux 2016.12.30.21:53:15
+# ACDS 18.0 614 linux 2020.02.02.21:03:29
 # ----------------------------------------
 # initialize variables
 TOP_LEVEL_NAME="pll_usb"
 QSYS_SIMDIR="./../../"
-QUARTUS_INSTALL_DIR="/home/markw/fpga/intelFPGA_lite/16.1/quartus/"
+QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/18.0/quartus/"
 SKIP_FILE_COPY=0
 SKIP_DEV_COM=0
 SKIP_COM=0
@@ -154,29 +160,29 @@
 # ----------------------------------------
 # compile device library files
 if [ $SKIP_DEV_COM -eq 0 ]; then
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
-  vlogan +v2k -sverilog $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
-  vlogan +v2k $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev    
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
-  vhdlan $USER_DEFINED_COMPILE_OPTIONS                "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+  vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev    
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
 fi
 
 # ----------------------------------------
 # compile design files in correct order
 if [ $SKIP_COM -eq 0 ]; then
-  vhdlan -xlrm $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_usb.vho"
+  vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_usb.vho"
 fi
 
 # ----------------------------------------
Index: eclaireXL_ITX/scaler/pixels.vhdl
===================================================================
--- eclaireXL_ITX/scaler/pixels.vhdl	(nonexistent)
+++ eclaireXL_ITX/scaler/pixels.vhdl	(revision 974)
@@ -0,0 +1,48 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+package Pixels is
+
+type t_Pixel is record
+    red   : std_logic_vector(7 downto 0);
+    green : std_logic_vector(7 downto 0);
+    blue  : std_logic_vector(7 downto 0);
+end record t_Pixel;  
+  
+type t_Pixel2x2 is array (0 to 3) of t_Pixel;
+type t_Pixel4x4 is array (0 to (4*4-1)) of t_Pixel;
+
+function pixel_to2x2(v: t_Pixel4x4) return t_Pixel2x2;
+function pixel2x2_idx(i,j : integer) return integer;
+function pixel4x4_idx(i,j : integer) return integer;
+
+end package Pixels;
+
+package body Pixels is
+	function pixel_to2x2(v: t_Pixel4x4) return t_Pixel2x2 is
+		variable res : t_Pixel2x2;
+	begin
+		for i in 0 to 1 loop
+			for j in 0 to 1 loop
+				res(pixel2x2_idx(i,j)) := v(pixel4x4_idx(i,j));
+			end loop;
+		end loop;
+		return res;
+	end pixel_to2x2;
+	
+	function pixel2x2_idx(i,j : integer) return integer is
+		variable res : integer;
+	begin
+		res := i*2+j;
+		return res;
+	end pixel2x2_idx;
+
+	function pixel4x4_idx(i,j : integer) return integer is
+		variable res : integer;
+	begin
+		res := i*4+j;
+		return res;
+	end pixel4x4_idx;	
+	
+end Pixels;
+
Index: eclaireXL_ITX/pll_usb/pll_usb_0002.qip
===================================================================
--- eclaireXL_ITX/pll_usb/pll_usb_0002.qip	(revision 973)
+++ eclaireXL_ITX/pll_usb/pll_usb_0002.qip	(revision 974)
@@ -1,4 +1,4 @@
 set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_usb_0002*|altera_pll:altera_pll_i*|*"
- 
+set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*pll_usb_0002*|altera_pll:altera_pll_i*|*"
 set_instance_assignment -name PLL_AUTO_RESET ON -to "*pll_usb_0002*|altera_pll:altera_pll_i*|*"
 set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_usb_0002*|altera_pll:altera_pll_i*|*"
Index: eclaireXL_ITX/pll_usb.sip
===================================================================
--- eclaireXL_ITX/pll_usb.sip	(revision 973)
+++ eclaireXL_ITX/pll_usb.sip	(revision 974)
@@ -1,5 +1,5 @@
 set_global_assignment -entity "pll_usb" -library "lib_pll_usb" -name IP_TOOL_NAME "altera_pll"
-set_global_assignment -entity "pll_usb" -library "lib_pll_usb" -name IP_TOOL_VERSION "16.1"
+set_global_assignment -entity "pll_usb" -library "lib_pll_usb" -name IP_TOOL_VERSION "18.0"
 set_global_assignment -entity "pll_usb" -library "lib_pll_usb" -name IP_TOOL_ENV "mwpim"
 set_global_assignment -library "lib_pll_usb" -name SPD_FILE [file join $::quartus(sip_path) "pll_usb.spd"]
 
Index: eclaireXL_ITX/pll_usb_sim/mentor/msim_setup.tcl
===================================================================
--- eclaireXL_ITX/pll_usb_sim/mentor/msim_setup.tcl	(revision 973)
+++ eclaireXL_ITX/pll_usb_sim/mentor/msim_setup.tcl	(revision 974)
@@ -1,5 +1,5 @@
 
-# (C) 2001-2016 Altera Corporation. All rights reserved.
+# (C) 2001-2020 Altera Corporation. All rights reserved.
 # Your use of Altera Corporation's design tools, logic functions and 
 # other software and tools, and its AMPP partner logic functions, and 
 # any output files any of the foregoing (including device programming 
@@ -46,6 +46,8 @@
 # #
 # # Set any compilation options you require (this is unusual).
 # set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
 # #
 # # Call command to compile the Quartus EDA simulation library.
 # dev_com
@@ -92,7 +94,7 @@
 # within the Quartus project, and generate a unified
 # script which supports all the Altera IP within the design.
 # ----------------------------------------
-# ACDS 16.1 196 linux 2016.12.30.21:53:15
+# ACDS 18.0 614 linux 2020.02.02.21:03:29
 
 # ----------------------------------------
 # Initialize variables
@@ -111,12 +113,18 @@
 }
 
 if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/home/markw/fpga/intelFPGA_lite/16.1/quartus/"
+  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/18.0/quartus/"
 }
 
 if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
   set USER_DEFINED_COMPILE_OPTIONS ""
 }
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
 if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
   set USER_DEFINED_ELAB_OPTIONS ""
 }
@@ -163,23 +171,23 @@
 alias dev_com {
   echo "\[exec\] dev_com"
   if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
-    eval  vlog -sv $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv"  -work altera_lnsim
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
-    eval  vlog $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v"   -work cyclonev    
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
-    eval  vcom $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+    eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv"  -work altera_lnsim
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v"   -work cyclonev    
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
   }
 }
 
@@ -187,7 +195,7 @@
 # Compile the design files in correct order
 alias com {
   echo "\[exec\] com"
-  eval  vcom $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_usb.vho"
+  eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/pll_usb.vho"
 }
 
 # ----------------------------------------
@@ -225,37 +233,41 @@
 alias h {
   echo "List Of Command Line Aliases"
   echo
-  echo "file_copy                     -- Copy ROM/RAM files to simulation directory"
+  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
   echo
-  echo "dev_com                       -- Compile device library files"
+  echo "dev_com                                           -- Compile device library files"
   echo
-  echo "com                           -- Compile the design files in correct order"
+  echo "com                                               -- Compile the design files in correct order"
   echo
-  echo "elab                          -- Elaborate top level design"
+  echo "elab                                              -- Elaborate top level design"
   echo
-  echo "elab_debug                    -- Elaborate the top level design with novopt option"
+  echo "elab_debug                                        -- Elaborate the top level design with novopt option"
   echo
-  echo "ld                            -- Compile all the design files and elaborate the top level design"
+  echo "ld                                                -- Compile all the design files and elaborate the top level design"
   echo
-  echo "ld_debug                      -- Compile all the design files and elaborate the top level design with -novopt"
+  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -novopt"
   echo
   echo 
   echo
   echo "List Of Variables"
   echo
-  echo "TOP_LEVEL_NAME                -- Top level module name."
-  echo "                                 For most designs, this should be overridden"
-  echo "                                 to enable the elab/elab_debug aliases."
+  echo "TOP_LEVEL_NAME                                    -- Top level module name."
+  echo "                                                     For most designs, this should be overridden"
+  echo "                                                     to enable the elab/elab_debug aliases."
   echo
-  echo "SYSTEM_INSTANCE_NAME          -- Instantiated system module name inside top level module."
+  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
   echo
-  echo "QSYS_SIMDIR                   -- Qsys base simulation directory."
+  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
   echo
-  echo "QUARTUS_INSTALL_DIR           -- Quartus installation directory."
+  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
   echo
-  echo "USER_DEFINED_COMPILE_OPTIONS  -- User-defined compile options, added to com/dev_com aliases."
+  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
   echo
-  echo "USER_DEFINED_ELAB_OPTIONS     -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo
+  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
 }
 file_copy
 h
Index: eclaireXL_ITX/scaler/crtc.vhdl
===================================================================
--- eclaireXL_ITX/scaler/crtc.vhdl	(nonexistent)
+++ eclaireXL_ITX/scaler/crtc.vhdl	(revision 974)
@@ -0,0 +1,420 @@
+---------------------------------------------------------------------------
+-- (c) 2019 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_MISC.all;
+
+ENTITY crtc IS
+PORT 
+( 
+	clk_pixel : in std_logic;
+	reset_n : in std_logic;
+
+	-- inputs
+	resync_start_frame : in std_logic;
+
+	-- outputs
+	hsync : out std_logic;
+	vsync : out std_logic;
+	blank : out std_logic;
+
+	inc_line  : out std_logic;
+	inc_frame : out std_logic;
+	
+	field2 : out std_logic; -- field 2 is lower
+
+	clock_select : out std_logic_vector(2 downto 0);
+	
+	video_id_code : out std_logic_vector(7 downto 0);
+	scaler_select : out std_logic;
+
+	-- to set up params
+	sda : inout std_logic;
+	scl : inout std_logic
+);
+END crtc;
+
+--TODO: start_frame, clock_select and sda/scl
+
+ARCHITECTURE vhdl OF crtc IS
+	-- parameters
+	signal param_h_syncLen_reg      : unsigned(11 downto 0);  --sync right at start
+	signal param_h_preActiveLen_reg  : unsigned(11 downto 0);  --blank after sync
+	signal param_h_activeLen_reg    : unsigned(11 downto 0); --then active
+	signal param_h_postActiveLen_reg : unsigned(11 downto 0); --blank after active
+
+	signal param_v_syncLen_reg      : unsigned(11 downto 0);  --sync right at start
+	signal param_v_preActiveLen_reg  : unsigned(11 downto 0);  --blank after sync
+	signal param_v_activeLen_reg    : unsigned(11 downto 0);  --then active
+	signal param_v_postActiveLen_reg : unsigned(11 downto 0);  --blank after active
+
+	signal param_interlace_reg : std_logic;
+	signal param_interlaceDelayLen_reg : unsigned(11 downto 0); --delay sync by half a len
+
+	signal param_video_id_code_reg : std_logic_vector(7 downto 0); -- CEA 864 id code
+	signal param_scalar_select_reg : std_logic;
+	
+	signal param_clock_select_reg : std_logic_vector(2 downto 0); -- which clock to use
+	
+	signal param_active_reg : std_logic;
+	
+	signal params : std_logic_vector((13*12)-1 downto 0);
+
+	-- state
+	signal h_state_next: std_logic_vector(2 downto 0);
+	signal h_state_reg : std_logic_vector(2 downto 0);
+	signal v_state_next: std_logic_vector(3 downto 0);
+	signal v_state_reg : std_logic_vector(3 downto 0);
+
+	constant H_STATE_IDLE : std_logic_vector(2 downto 0) := "000";
+	constant H_STATE_SYNC : std_logic_vector(2 downto 0) := "001";
+	constant H_STATE_PREBLANK : std_logic_vector(2 downto 0) := "010";
+	constant H_STATE_ACTIVE : std_logic_vector(2 downto 0) := "011";
+	constant H_STATE_POSTBLANK : std_logic_vector(2 downto 0) := "100";
+
+	constant V_STATE_IDLE : std_logic_vector(3 downto 0) := "0000";
+	constant V_STATE_SYNC : std_logic_vector(3 downto 0) := "0001";
+	constant V_STATE_PREBLANK : std_logic_vector(3 downto 0) := "0010";
+	constant V_STATE_ACTIVE : std_logic_vector(3 downto 0) := "0011";
+	constant V_STATE_POSTBLANK : std_logic_vector(3 downto 0) := "0100";
+	constant V_STATE_PRESYNC_FIELD2 : std_logic_vector(3 downto 0) := "0101";
+	constant V_STATE_SYNC_FIELD2 : std_logic_vector(3 downto 0) := "0110";
+	constant V_STATE_POSTSYNC_FIELD2 : std_logic_vector(3 downto 0) := "0111";
+	constant V_STATE_PREBLANK_FIELD2 : std_logic_vector(3 downto 0) := "1000";
+	constant V_STATE_ACTIVE_FIELD2 : std_logic_vector(3 downto 0) := "1001";
+	constant V_STATE_POSTBLANK_FIELD2 : std_logic_vector(3 downto 0) := "1010";
+
+	signal h_delay_next : unsigned(11 downto 0);
+	signal h_delay_reg : unsigned(11 downto 0);
+
+	signal v_delay_next : unsigned(11 downto 0);
+	signal v_delay_reg : unsigned(11 downto 0);
+	signal v_delayh_next : unsigned(11 downto 0);
+	signal v_delayh_reg : unsigned(11 downto 0);
+	
+	signal v_sync_inc : std_logic;
+	
+	signal resync : std_logic;
+	
+	signal h_blank_next : std_logic;
+	signal h_sync_next : std_logic;
+	signal v_blank_next : std_logic;
+	signal v_sync_next : std_logic;
+	signal blank_next : std_logic;
+
+	signal h_blank_reg : std_logic;
+	signal h_sync_reg : std_logic;
+	signal v_blank_reg : std_logic;
+	signal v_sync_reg : std_logic;	
+	signal blank_reg : std_logic;
+	
+BEGIN
+	--registers
+	process(clk_pixel,reset_n)
+	begin
+		if (reset_n='0') then
+			h_state_reg <= H_STATE_IDLE;
+			v_state_reg <= V_STATE_IDLE;
+
+			h_delay_reg <= (others=>'0');
+			v_delay_reg <= (others=>'0');
+			v_delayh_reg <= (others=>'0');
+			
+			h_blank_reg <= '1';
+			h_sync_reg <= '0';
+			v_blank_reg <= '1';
+			v_sync_reg <= '0';
+			blank_reg <= '1';
+		elsif (clk_pixel='1' and clk_pixel'event) then
+			h_state_reg <= h_state_next;
+			v_state_reg <= v_state_next;
+
+			h_delay_reg <= h_delay_next;
+			v_delay_reg <= v_delay_next;
+			v_delayh_reg <= v_delayh_next;
+			
+			h_blank_reg <= h_blank_next;
+			h_sync_reg <= h_sync_next;
+			v_blank_reg <= v_blank_next;
+			v_sync_reg <= v_sync_next;
+			blank_reg <= blank_next;
+		end if;
+	end process;
+	
+	-- parameters from i2c (todo)
+--			-- 720p@50 (temp until we get crtc plumbed to firmware)
+--		param_h_syncLen_next <= to_unsigned(40,12);
+--		param_h_preActiveLen_next <= to_unsigned(220,12);
+--		param_h_activeLen_next <= to_unsigned(1280,12);
+--		param_h_postActiveLen_next <= to_unsigned(440,12);
+--		param_v_syncLen_next <= to_unsigned(5,12);
+--		param_v_preActiveLen_next <= to_unsigned(20,12);
+--		param_v_activeLen_next <= to_unsigned(720,12);
+--		param_v_postActiveLen_next <= to_unsigned(5,12);
+--		param_interlace_next <= '0';
+--		param_interlaceDelayLen_next <= (others=>'0');
+--		param_clock_select_next <= (others=>'0');
+		
+			-- 1080i@50 (temp until we get crtc plumbed to firmware)
+--		param_h_syncLen_next <= to_unsigned(44,12);
+--		param_h_preActiveLen_next <= to_unsigned(148,12);
+--		param_h_activeLen_next <= to_unsigned(1920,12);
+--		param_h_postActiveLen_next <= to_unsigned(528,12);
+--		param_v_syncLen_next <= to_unsigned(5,12);
+--		param_v_preActiveLen_next <= to_unsigned(15,12);
+--		param_v_activeLen_next <= to_unsigned(540,12);
+--		param_v_postActiveLen_next <= to_unsigned(2,12);
+--		param_interlace_next <= '1';
+--		param_interlaceDelayLen_next <= to_unsigned(1320,12);
+--		param_clock_select_next <= (others=>'0');		
+--		param_active_next <= '1';
+
+		
+-- params set from i2c
+	i2cregs : entity work.I2C_regs
+	generic map (
+		SLAVE_ADDR => "0000010",
+		regs => 13,
+		bits => 12
+	)
+	port map (
+		scl => scl,
+		sda => sda,
+		clk => clk_pixel,
+		rst => not(reset_n),
+		
+		reg => params			
+	);
+	param_h_syncLen_reg <= unsigned(params(1*12-1 downto 0*12));
+	param_h_preActiveLen_reg <= unsigned(params(2*12-1 downto 1*12));
+	param_h_activeLen_reg <= unsigned(params(3*12-1 downto 2*12));
+	param_h_postActiveLen_reg <= unsigned(params(4*12-1 downto 3*12));
+	param_v_syncLen_reg <= unsigned(params(5*12-1 downto 4*12));
+	param_v_preActiveLen_reg <= unsigned(params(6*12-1 downto 5*12));
+	param_v_activeLen_reg <= unsigned(params(7*12-1 downto 6*12));
+	param_v_postActiveLen_reg <= unsigned(params(8*12-1 downto 7*12));
+	param_interlace_reg <= params(8*12);
+	param_interlaceDelayLen_reg <= unsigned(params(10*12-1 downto 9*12));
+	param_video_id_code_reg <= params(10*12+8-1 downto 10*12);	
+	param_scalar_select_reg <= params(10*12+9-1);
+	param_clock_select_reg <= params(11*12+3-1 downto 11*12);
+	param_active_reg <= params(12*12);
+	
+	-- state machine
+		-- horizontal
+	process(h_state_reg,h_delay_reg,h_blank_reg,h_sync_reg,
+	   resync_start_frame,
+		param_active_reg,
+		param_h_syncLen_reg,
+		param_h_preActiveLen_reg,
+		param_h_activeLen_reg,
+		param_h_postActiveLen_reg
+	)
+		variable delay_over : std_logic;
+	begin
+		h_state_next <= h_state_reg;
+		h_delay_next <= h_delay_reg;
+		h_blank_next <= h_blank_reg;
+		h_sync_next <= h_sync_reg;
+		
+		v_sync_inc <= '0';
+		inc_line <= '0';		
+
+		h_delay_next <= h_delay_reg - 1;
+
+		delay_over := '0';
+		if (h_delay_reg="00000000001") then
+			delay_over := '1';
+		end if;
+
+		case h_state_reg is
+			when H_STATE_IDLE =>
+				h_blank_next <= '1';
+				h_sync_next <= '1';
+
+				if (param_active_reg='1') then
+					h_state_next <= H_STATE_ACTIVE;
+					h_delay_next <= param_h_activeLen_reg;
+					h_sync_next <= '0';
+					h_blank_next <= '0';
+				end if;
+			when H_STATE_SYNC =>
+				if (delay_over='1') then
+					h_state_next <= H_STATE_PREBLANK;
+					h_delay_next <= param_h_preActiveLen_reg;
+					h_sync_next <= '0';
+				end if;
+			when H_STATE_PREBLANK =>
+				if (delay_over='1') then
+					h_state_next <= H_STATE_ACTIVE;
+					h_delay_next <= param_h_activeLen_reg;
+					h_blank_next <= '0';
+					inc_line <= '1';
+				end if;
+			when H_STATE_ACTIVE =>
+				if (delay_over='1') then
+					h_state_next <= H_STATE_POSTBLANK;
+					h_delay_next <= param_h_postActiveLen_reg;
+					h_blank_next <= '1';					
+				end if;
+			when H_STATE_POSTBLANK =>
+				if (delay_over='1') then
+					h_state_next <= H_STATE_SYNC;
+					h_delay_next <= param_h_syncLen_reg;
+					h_sync_next <= '1';
+					v_sync_inc <= '1';
+				end if;
+			when others =>
+				h_state_next <= H_STATE_IDLE;
+		end case;
+
+		if (param_active_reg='0' or resync_start_frame='1') then
+			h_state_next <= H_STATE_IDLE;
+		end if;
+	end process;
+
+		-- vertical
+	process(v_state_reg,v_delay_reg,v_delayh_reg,v_blank_reg,v_sync_reg,
+		v_sync_inc,
+		resync_start_frame,
+		param_active_reg,
+		param_v_syncLen_reg,
+		param_v_preActiveLen_reg,
+		param_v_activeLen_reg,
+		param_v_postActiveLen_reg,
+		param_interlace_reg,
+		param_interlaceDelayLen_reg		
+	)
+		variable delay_over : std_logic;
+		variable delayh_over : std_logic;
+	begin
+		v_state_next <= v_state_reg;
+		v_delay_next <= v_delay_reg;
+		v_delayh_next <= v_delayh_reg;
+		v_blank_next <= v_blank_reg;
+		v_sync_next <= v_sync_reg;		
+		inc_frame <= '0';
+		field2 <= '0';
+
+		if (v_sync_inc = '1') then
+			v_delay_next <= v_delay_reg - 1;
+		end if;
+		v_delayh_next <= v_delayh_reg - 1;
+
+		delay_over := '0';
+		if (v_delay_reg="0000000001" and v_sync_inc='1') then
+			delay_over := '1';
+		end if;
+		delayh_over := '0';
+		if (v_delayh_reg="00000000001") then
+			delayh_over := '1';
+		end if;
+
+		case v_state_reg is
+			when V_STATE_IDLE =>
+				v_blank_next <= '1';
+				v_sync_next <= '1';		
+
+				if (param_active_reg='1') then
+					v_state_next <= V_STATE_ACTIVE;
+					v_delay_next <= param_v_activeLen_reg;
+					v_sync_next <= '0';
+					v_blank_next <= '0';		
+					inc_frame <= '1';			
+				end if;				
+			when V_STATE_SYNC =>
+				if (delay_over='1') then
+					v_state_next <= V_STATE_PREBLANK;
+					v_delay_next <= param_v_preActiveLen_reg;
+					v_sync_next <= '0';
+				end if;
+			when V_STATE_PREBLANK =>
+				if (delay_over='1') then
+					v_state_next <= V_STATE_ACTIVE;
+					v_delay_next <= param_v_activeLen_reg;
+					v_blank_next <= '0';
+					inc_frame <= '1';
+				end if;
+			when V_STATE_ACTIVE =>
+				if (delay_over='1') then
+					v_state_next <= V_STATE_POSTBLANK;
+					v_delay_next <= param_v_postActiveLen_reg;
+					v_blank_next <= '1';
+				end if;
+			when V_STATE_POSTBLANK =>
+				if (delay_over='1') then
+					if (param_interlace_reg='1') then
+						v_state_next <= V_STATE_PRESYNC_FIELD2;
+						v_delayh_next <= param_interlaceDelayLen_reg;
+					else
+						v_sync_next <= '1';
+						v_state_next <= V_STATE_SYNC;
+						v_delay_next <= param_v_syncLen_reg;
+					end if;
+				end if;
+			when V_STATE_PRESYNC_FIELD2 =>
+				if (delayh_over='1') then
+					v_sync_next <= '1';
+					v_state_next <= V_STATE_SYNC_FIELD2;
+					v_delay_next <= param_v_syncLen_reg;					
+				end if;
+			when V_STATE_SYNC_FIELD2 =>
+				if (delay_over='1') then
+					v_state_next <= V_STATE_POSTSYNC_FIELD2;
+					v_delayh_next <= param_interlaceDelayLen_reg;
+				end if;
+			when V_STATE_POSTSYNC_FIELD2 =>
+				if (delayh_over='1') then
+					v_sync_next <= '0';
+					v_state_next <= V_STATE_PREBLANK_FIELD2;
+					v_delay_next <= param_v_preActiveLen_reg+1;
+				end if;				
+			when V_STATE_PREBLANK_FIELD2 =>
+				if (delay_over='1') then
+					v_state_next <= V_STATE_ACTIVE_FIELD2;
+					v_delay_next <= param_v_activeLen_reg;
+					v_blank_next <= '0';
+					inc_frame <= '1';
+					field2 <= '1';					
+				end if;
+			when V_STATE_ACTIVE_FIELD2 =>
+				if (delay_over='1') then
+					v_state_next <= V_STATE_POSTBLANK_FIELD2;
+					v_delay_next <= param_v_postActiveLen_reg;
+					v_blank_next <= '1';
+				end if;
+			when V_STATE_POSTBLANK_FIELD2 =>
+				if (delay_over='1') then
+					v_sync_next <= '1';
+					v_state_next <= V_STATE_SYNC;
+					v_delay_next <= param_v_syncLen_reg;
+				end if;
+			when others =>
+				v_state_next <= V_STATE_IDLE;
+		end case;
+
+		if (param_active_reg='0' or resync_start_frame='1') then
+			v_state_next <= V_STATE_IDLE;
+		end if;
+	end process;
+	
+	blank_next <= h_blank_next or v_blank_next;
+	
+	-- outputs
+	blank <= blank_reg;
+	hsync <= h_sync_reg;
+	vsync <= v_sync_reg;
+	
+	clock_select <= param_clock_select_reg(2 downto 0);
+	video_id_code <= param_video_id_code_reg;
+	scaler_select <= param_scalar_select_reg;
+
+END vhdl;
Index: eclaireXL_ITX/pll_usb/pll_usb_0002.v
===================================================================
--- eclaireXL_ITX/pll_usb/pll_usb_0002.v	(revision 973)
+++ eclaireXL_ITX/pll_usb/pll_usb_0002.v	(revision 974)
@@ -18,7 +18,7 @@
 );
 
 	altera_pll #(
-		.fractional_vco_multiplier("false"),
+		.fractional_vco_multiplier("true"),
 		.reference_clock_frequency("50.0 MHz"),
 		.operation_mode("normal"),
 		.number_of_clocks(2),
@@ -25,7 +25,7 @@
 		.output_clock_frequency0("48.000000 MHz"),
 		.phase_shift0("0 ps"),
 		.duty_cycle0(50),
-		.output_clock_frequency1("50.000000 MHz"),
+		.output_clock_frequency1("54.000000 MHz"),
 		.phase_shift1("0 ps"),
 		.duty_cycle1(50),
 		.output_clock_frequency2("0 MHz"),
Index: eclaireXL_ITX/pll_usb.vhd
===================================================================
--- eclaireXL_ITX/pll_usb.vhd	(revision 973)
+++ eclaireXL_ITX/pll_usb.vhd	(revision 974)
@@ -1,8 +1,8 @@
--- megafunction wizard: %Altera PLL v16.1%
+-- megafunction wizard: %PLL Intel FPGA IP v18.0%
 -- GENERATION: XML
 -- pll_usb.vhd
 
--- Generated using ACDS version 16.1 196
+-- Generated using ACDS version 18.0 614
 
 library IEEE;
 use IEEE.std_logic_1164.all;
@@ -47,7 +47,7 @@
 --	************************************************************
 --	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --	************************************************************
---	Copyright (C) 1991-2016 Altera Corporation
+--	Copyright (C) 1991-2020 Altera Corporation
 --	Any megafunction design, and related net list (encrypted or decrypted),
 --	support information, device programming or simulation file, and any other
 --	associated documentation or information provided by Altera or a partner
@@ -67,13 +67,13 @@
 --	their respective licensors.  No other licenses, including any licenses
 --	needed under any third party's intellectual property, are provided herein.
 ---->
--- Retrieval info: <instance entity-name="altera_pll" version="16.1" >
+-- Retrieval info: <instance entity-name="altera_pll" version="18.0" >
 -- Retrieval info: 	<generic name="debug_print_output" value="false" />
 -- Retrieval info: 	<generic name="debug_use_rbc_taf_method" value="false" />
 -- Retrieval info: 	<generic name="device_family" value="Cyclone V" />
 -- Retrieval info: 	<generic name="device" value="5CEBA2F17A7" />
 -- Retrieval info: 	<generic name="gui_device_speed_grade" value="2" />
--- Retrieval info: 	<generic name="gui_pll_mode" value="Integer-N PLL" />
+-- Retrieval info: 	<generic name="gui_pll_mode" value="Fractional-N PLL" />
 -- Retrieval info: 	<generic name="gui_reference_clock_frequency" value="50.0" />
 -- Retrieval info: 	<generic name="gui_channel_spacing" value="0.0" />
 -- Retrieval info: 	<generic name="gui_operation_mode" value="normal" />
@@ -96,7 +96,7 @@
 -- Retrieval info: 	<generic name="gui_actual_phase_shift0" value="0" />
 -- Retrieval info: 	<generic name="gui_duty_cycle0" value="50" />
 -- Retrieval info: 	<generic name="gui_cascade_counter1" value="false" />
--- Retrieval info: 	<generic name="gui_output_clock_frequency1" value="50.0" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency1" value="54.0" />
 -- Retrieval info: 	<generic name="gui_divide_factor_c1" value="1" />
 -- Retrieval info: 	<generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
 -- Retrieval info: 	<generic name="gui_ps_units1" value="ps" />
@@ -105,7 +105,7 @@
 -- Retrieval info: 	<generic name="gui_actual_phase_shift1" value="0" />
 -- Retrieval info: 	<generic name="gui_duty_cycle1" value="50" />
 -- Retrieval info: 	<generic name="gui_cascade_counter2" value="false" />
--- Retrieval info: 	<generic name="gui_output_clock_frequency2" value="100.0" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency2" value="0.0" />
 -- Retrieval info: 	<generic name="gui_divide_factor_c2" value="1" />
 -- Retrieval info: 	<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
 -- Retrieval info: 	<generic name="gui_ps_units2" value="ps" />
Index: eclaireXL_ITX/pll_usb_sim/pll_usb.vho
===================================================================
--- eclaireXL_ITX/pll_usb_sim/pll_usb.vho	(revision 973)
+++ eclaireXL_ITX/pll_usb_sim/pll_usb.vho	(revision 974)
@@ -1,8 +1,8 @@
 --IP Functional Simulation Model
---VERSION_BEGIN 16.1 cbx_mgl 2016:10:19:22:10:30:SJ cbx_simgen 2016:10:19:21:26:20:SJ  VERSION_END
+--VERSION_BEGIN 18.0 cbx_mgl 2018:04:18:07:37:08:SJ cbx_simgen 2018:04:18:06:50:44:SJ  VERSION_END
 
 
--- Copyright (C) 2016  Intel Corporation. All rights reserved.
+-- Copyright (C) 2018  Intel Corporation. All rights reserved.
 -- Your use of Intel Corporation's design tools, logic functions 
 -- and other software and tools, and its AMPP partner logic 
 -- functions, and any output files from any of the foregoing 
@@ -10,12 +10,11 @@
 -- associated documentation or information are expressly subject 
 -- to the terms and conditions of the Intel Program License 
 -- Subscription Agreement, the Intel Quartus Prime License Agreement,
--- the Intel MegaCore Function License Agreement, or other 
--- applicable license agreement, including, without limitation, 
--- that your use is for the sole purpose of programming logic 
--- devices manufactured by Intel and sold by Intel or its 
--- authorized distributors.  Please refer to the applicable 
--- agreement for further details.
+-- the Intel FPGA IP License Agreement, or other applicable license
+-- agreement, including, without limitation, that your use is for
+-- the sole purpose of programming logic devices manufactured by
+-- Intel and sold by Intel or its authorized distributors.  Please
+-- refer to the applicable agreement for further details.
 
 -- You may only use these simulation model output files for simulation
 -- purposes and expressly not for synthesis or any other purposes (in which
@@ -221,7 +220,7 @@
 		duty_cycle7 => 50,
 		duty_cycle8 => 50,
 		duty_cycle9 => 50,
-		fractional_vco_multiplier => "false",
+		fractional_vco_multiplier => "true",
 		m_cnt_bypass_en => "false",
 		m_cnt_hi_div => 1,
 		m_cnt_lo_div => 1,
@@ -234,7 +233,7 @@
 		number_of_clocks => 2,
 		operation_mode => "normal",
 		output_clock_frequency0 => "48.000000 MHz",
-		output_clock_frequency1 => "50.000000 MHz",
+		output_clock_frequency1 => "54.000000 MHz",
 		output_clock_frequency10 => "0 MHz",
 		output_clock_frequency11 => "0 MHz",
 		output_clock_frequency12 => "0 MHz",
Index: eclaireXL_ITX/scaler/multiscale.vhd
===================================================================
--- eclaireXL_ITX/scaler/multiscale.vhd	(nonexistent)
+++ eclaireXL_ITX/scaler/multiscale.vhd	(revision 974)
@@ -0,0 +1,209 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+use work.pixels.all;
+
+ENTITY multiscale IS  
+  GENERIC(
+    enable_area : integer := 1;
+	 enable_polyphasic : integer := 1
+  );
+  PORT(
+    clock   : IN     STD_LOGIC;                             --system clock
+    reset_n : IN     STD_LOGIC;                             --asynchronous reset
+
+	 scaler_select : IN STD_LOGIC; -- 0==areascale/1==polyphasic
+	 
+    -- need to know:
+    -- block of 4 pixels (x,y:x+1,y:x,y+1:x+1,y+1)
+    -- relative scale ratios
+    --p1 : in std_logic_vector(23 downto 0); --RGB
+    --p2 : in std_logic_vector(23 downto 0); --RGB
+    --p3 : in std_logic_vector(23 downto 0); --RGB
+    --p4 : in std_logic_vector(23 downto 0); --RGB
+	 
+    pixels : in t_Pixel4x4;
+
+    -- next output line
+    next_y_in : in std_logic;
+    next_frame_in : in std_logic;
+    field2 : in std_logic;
+    
+    -- sync/blank from crtc -> need to be delayed in line with pipeline
+    hsync_in : in std_logic;
+    vsync_in : in std_logic;
+    blank_in : in std_logic; 
+	 
+    -- need to provide control signals:
+    next_x : OUT STD_LOGIC;
+    next_x_size : out std_logic_vector(1 downto 0);
+    next_y : OUT STD_LOGIC;	 
+
+    -- need to output
+    -- current pixel
+    r : out std_logic_vector(7 downto 0);
+    g : out std_logic_vector(7 downto 0);
+    b : out std_logic_vector(7 downto 0);
+    hsync : out std_logic;
+    vsync : out std_logic;
+    blank : out std_logic;
+	 
+    -- to set up params
+    sda : inout std_logic;
+    scl : inout std_logic	 
+  );
+END multiscale;
+
+ARCHITECTURE vhdl OF multiscale IS
+
+		signal poly_red_next : std_logic_vector(7 downto 0);
+		signal poly_green_next : std_logic_vector(7 downto 0);
+		signal poly_blue_next : std_logic_vector(7 downto 0);
+		signal poly_hsync_next : std_logic;
+		signal poly_vsync_next : std_logic;
+		signal poly_blank_next : std_logic;
+		signal poly_next_x : STD_LOGIC;
+		signal poly_next_x_size : std_logic_vector(1 downto 0);
+		signal poly_next_y : STD_LOGIC;	 			
+
+		signal area_red_next : std_logic_vector(7 downto 0);
+		signal area_green_next : std_logic_vector(7 downto 0);
+		signal area_blue_next : std_logic_vector(7 downto 0);
+		signal area_hsync_next : std_logic;
+		signal area_vsync_next : std_logic;
+		signal area_blank_next : std_logic;				
+		signal area_next_x : STD_LOGIC;
+		signal area_next_x_size : std_logic_vector(1 downto 0);
+		signal area_next_y : STD_LOGIC;	 		
+		
+BEGIN
+	
+gen_polyphasic_on : if enable_polyphasic=1 generate
+
+polyphasicscale_impl : entity work.polyphasicscale
+	port map 
+	(
+		CLOCK => CLOCK,
+		RESET_N => reset_n,
+
+		pixels => pixels,
+		next_y_in => next_y_in,      --reset_x
+		next_frame_in => next_frame_in, --reset y
+		next_x => poly_next_x,
+		next_y => poly_next_y,
+		next_x_size => poly_next_x_size,
+		field2 => field2, -- field 2 is half lower
+		
+		hsync_in => hsync_in,
+		vsync_in => vsync_in,
+		blank_in => blank_in,
+
+		r => poly_red_next,
+		g => poly_green_next,
+		b => poly_blue_next,
+		hsync => poly_hsync_next,
+		vsync => poly_vsync_next,
+		blank => poly_blank_next,
+				
+		sda => sda,
+		scl => scl		
+	);
+end generate gen_polyphasic_on;	
+	
+gen_area_on : if enable_area=1 generate	
+areascale_impl : entity work.areascale
+	port map 
+	(
+		CLOCK => CLOCK,
+		RESET_N => reset_n,
+
+		pixels => pixel_to2x2(pixels),
+		next_y_in => next_y_in,      --reset_x
+		next_frame_in => next_frame_in, --reset y
+		next_x => area_next_x,
+		next_y => area_next_y,
+		next_x_size => area_next_x_size,
+		field2 => field2, -- field 2 is half lower
+		
+		hsync_in => hsync_in,
+		vsync_in => vsync_in,
+		blank_in => blank_in,
+
+		r => area_red_next,
+		g => area_green_next,
+		b => area_blue_next,
+		hsync => area_hsync_next,
+		vsync => area_vsync_next,
+		blank => area_blank_next,
+		
+		sda => sda,
+		scl => scl
+	);
+end generate gen_area_on;	
+	
+gen_select_on : if enable_area=1 and enable_polyphasic=1 generate	
+	process(scaler_select,
+		area_red_next,area_green_next,area_blue_next,
+		area_hsync_next,area_vsync_next,area_blank_next,
+		area_next_x,area_next_y,area_next_x_size,
+		poly_red_next,poly_green_next,poly_blue_next,
+		poly_hsync_next,poly_vsync_next,poly_blank_next,
+		poly_next_x,poly_next_y,poly_next_x_size)		
+	begin
+		if (scaler_select='0') then
+			r <= area_red_next;
+			g <= area_green_next;
+			b <= area_blue_next;
+			hsync <= area_hsync_next;
+			vsync <= area_vsync_next;
+			blank <= area_blank_next;		
+			
+			next_x <= area_next_x;
+			next_y <= area_next_y;
+			next_x_size <= area_next_x_size;		
+		else
+			r <= poly_red_next;
+			g <= poly_green_next;
+			b <= poly_blue_next;
+			hsync <= poly_hsync_next;
+			vsync <= poly_vsync_next;
+			blank <= poly_blank_next;		
+			
+			next_x <= poly_next_x;
+			next_y <= poly_next_y;
+			next_x_size <= poly_next_x_size;				
+		end if;
+	end process;
+end generate gen_select_on;
+
+gen_fixed_area : if enable_area=1 and enable_polyphasic=0 generate	
+			r <= area_red_next;
+			g <= area_green_next;
+			b <= area_blue_next;
+			hsync <= area_hsync_next;
+			vsync <= area_vsync_next;
+			blank <= area_blank_next;		
+			
+			next_x <= area_next_x;
+			next_y <= area_next_y;
+			next_x_size <= area_next_x_size;		
+end generate gen_fixed_area;
+
+gen_fixed_poly : if enable_area=0 and enable_polyphasic=1 generate	
+			r <= poly_red_next;
+			g <= poly_green_next;
+			b <= poly_blue_next;
+			hsync <= poly_hsync_next;
+			vsync <= poly_vsync_next;
+			blank <= poly_blank_next;		
+			
+			next_x <= poly_next_x;
+			next_y <= poly_next_y;
+			next_x_size <= poly_next_x_size;		
+end generate gen_fixed_poly;
+
+gen_none : if enable_area=0 and enable_polyphasic=0 generate	
+	-- TODO: nearest neighbour?	
+end generate gen_none;
+
+END vhdl;
