Index: papilioduo/pll/pll/implement/xst.prj
===================================================================
--- papilioduo/pll/pll/implement/xst.prj	(nonexistent)
+++ papilioduo/pll/pll/implement/xst.prj	(revision 325)
@@ -0,0 +1,2 @@
+vhdl work ../../pll.vhd
+vhdl work ../example_design/pll_exdes.vhd
Index: papilioduo/pll/pll/simulation/functional/simulate_isim.bat
===================================================================
--- papilioduo/pll/pll/simulation/functional/simulate_isim.bat	(nonexistent)
+++ papilioduo/pll/pll/simulation/functional/simulate_isim.bat	(revision 325)
@@ -0,0 +1,58 @@
+REM file: simulate_isim.bat
+REM  
+REM  (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM  
+REM  This file contains confidential and proprietary information
+REM  of Xilinx, Inc. and is protected under U.S. and
+REM  international copyright and other intellectual property
+REM  laws.
+REM  
+REM  DISCLAIMER
+REM  This disclaimer is not a license and does not grant any
+REM  rights to the materials distributed herewith. Except as
+REM  otherwise provided in a valid license issued to you by
+REM  Xilinx, and to the maximum extent permitted by applicable
+REM  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM  (2) Xilinx shall not be liable (whether in contract or tort,
+REM  including negligence, or under any other theory of
+REM  liability) for any loss or damage of any kind or nature
+REM  related to, arising under or in connection with these
+REM  materials, including for any direct, or any indirect,
+REM  special, incidental, or consequential loss or damage
+REM  (including loss of data, profits, goodwill, or any type of
+REM  loss or damage suffered as a result of any action brought
+REM  by a third party) even if such damage or loss was
+REM  reasonably foreseeable or Xilinx had been advised of the
+REM  possibility of the same.
+REM  
+REM  CRITICAL APPLICATIONS
+REM  Xilinx products are not designed or intended to be fail-
+REM  safe, or for use in any application requiring fail-safe
+REM  performance, such as life-support or safety devices or
+REM  systems, Class III medical devices, nuclear facilities,
+REM  applications related to the deployment of airbags, or any
+REM  other applications that could lead to death, personal
+REM  injury, or severe property or environmental damage
+REM  (individually and collectively, "Critical
+REM  Applications"). Customer assumes the sole risk and
+REM  liability of any use of Xilinx products in Critical
+REM  Applications, subject only to applicable laws and
+REM  regulations governing limitations on product liability.
+REM  
+REM  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM  PART OF THIS FILE AT ALL TIMES.
+REM  
+
+vhpcomp -work work ..\..\..\pll.vhd
+vhpcomp -work work ..\..\example_design\pll_exdes.vhd
+vhpcomp -work work ..\pll_tb.vhd
+
+REM compile the project
+fuse work.pll_tb  -L unisim -o pll_isim.exe
+
+REM run the simulation script
+.\pll_isim.exe -gui -tclbatch simcmds.tcl
Index: aeon_lite/build.sh
===================================================================
--- aeon_lite/build.sh	(revision 324)
+++ aeon_lite/build.sh	(revision 325)
@@ -48,4 +48,3 @@
 bitgen -intstyle ise -f $name.ut $name.ncd
 
 popd
-cp build/$name.bin core/atari800.bin
Index: chameleon/zpu_rom.vhdl
===================================================================
--- chameleon/zpu_rom.vhdl	(revision 324)
+++ chameleon/zpu_rom.vhdl	(revision 325)
@@ -181,7 +181,7 @@
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@@ -227,8 +227,8 @@
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@@ -554,7 +554,7 @@
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+X"5e80d13d",
+X"fdf40554",
+X"765383e7",
+X"f0527951",
+X"ffa1b13f",
+X"0282b905",
+X"33558159",
+X"7480d72e",
+X"09810680",
+X"c5387752",
+X"7951ffa2",
+X"f53f80d1",
+X"3dfdf005",
+X"5476538f",
+X"3d70537a",
+X"5258ffa2",
+X"ad3f8056",
+X"76762ea2",
+X"38751883",
+X"e7f01733",
+X"71337072",
+X"32703070",
+X"80257030",
+X"7f06811d",
+X"5d5f5151",
+X"51525b55",
+X"db3982ac",
+X"51e4953f",
+X"78802e86",
+X"3880c351",
+X"843980ce",
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+X"cb863fc9",
+X"bb3f83d8",
+X"390282bb",
+X"05330284",
+X"0582ba05",
+X"33718280",
+X"29055955",
+X"80705d59",
+X"80e451e3",
+X"df3fcaa8",
 X"3f80c151",
-X"c9f23f83",
+X"c9e23f83",
 X"ea880879",
 X"2e82d638",
 X"83eaa808",
@@ -3444,7 +3448,7 @@
 X"b238ff18",
 X"70872b83",
 X"ffff8006",
-X"80f8b005",
+X"80f8c005",
 X"83e7f059",
 X"57558180",
 X"55757081",
@@ -3505,12 +3509,12 @@
 X"7780fd29",
 X"fd97d305",
 X"527951ff",
-X"9fe03f80",
+X"9fd03f80",
 X"d13dfdec",
 X"055480fd",
 X"5383e7f0",
 X"527951ff",
-X"9f983f7b",
+X"9f883f7b",
 X"81195956",
 X"7580fc24",
 X"83387858",
@@ -3533,20 +3537,20 @@
 X"2917ff80",
 X"05578180",
 X"59765279",
-X"51ff9eee",
+X"51ff9ede",
 X"3f80d13d",
 X"fdec0554",
 X"785383e7",
 X"f0527951",
-X"ff9ea73f",
-X"7851f6ce",
-X"3fc7b93f",
-X"c5ee3f8b",
+X"ff9e973f",
+X"7851f6c3",
+X"3fc7a93f",
+X"c5de3f8b",
 X"3983e9f0",
 X"08810583",
 X"e9f00c80",
 X"d13d0d04",
-X"f6ef3ffc",
+X"f6e43ffc",
 X"39fc3d0d",
 X"76787184",
 X"2983ea90",
@@ -3654,7 +3658,7 @@
 X"0b8c150c",
 X"87a68033",
 X"7081ff06",
-X"5151dcd7",
+X"5151dcc7",
 X"3f70812a",
 X"81327181",
 X"32718106",
@@ -3863,14 +3867,14 @@
 X"02020202",
 X"02020241",
 X"00060000",
-X"00003aa4",
-X"00003aa8",
-X"00003ab0",
-X"00003abc",
-X"00003ac8",
-X"00003ad4",
-X"00003ae0",
+X"00003ab4",
+X"00003ab8",
+X"00003ac0",
+X"00003acc",
+X"00003ad8",
 X"00003ae4",
+X"00003af0",
+X"00003af4",
 X"72025f07",
 X"f807a900",
 X"8d04038d",
@@ -3974,10 +3978,6 @@
 X"00000000",
 X"00000000",
 X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
-X"00000000",
 X"00000000",
 X"00000000",
 X"00000000",
Index: firmware/sockit/memory.c
===================================================================
--- firmware/sockit/memory.c	(revision 324)
+++ firmware/sockit/memory.c	(revision 325)
@@ -25,8 +25,9 @@
 	zpu_base = (unsigned char *)virtual_base + 0x1000000; 
 	//pokey_regbase = (unsigned char *)virtual_base + 0x1000400;
 
-	struct sched_param param;
-	param.sched_priority = 50;
-	sched_setscheduler(0,SCHED_RR,&param);
+	//struct sched_param param;
+	//param.sched_priority = 50;
+	//sched_setscheduler(0,SCHED_RR,&param);
+	nice(-20);
 }
 
Index: mcc216/zpu_rom.vhdl
===================================================================
--- mcc216/zpu_rom.vhdl	(revision 324)
+++ mcc216/zpu_rom.vhdl	(revision 325)
@@ -181,7 +181,7 @@
 X"00000000",
 X"71fc0608",
 X"0b0b81d3",
-X"98738306",
+X"a8738306",
 X"10100508",
 X"060b0b0b",
 X"88a20400",
@@ -228,7 +228,7 @@
 X"00000000",
 X"00000000",
 X"810b81da",
-X"ac0c5104",
+X"bc0c5104",
 X"00000000",
 X"00000000",
 X"00000000",
@@ -301,7 +301,7 @@
 X"83c08408",
 X"83c08808",
 X"757580f1",
-X"822d5050",
+X"922d5050",
 X"83c08008",
 X"5683c088",
 X"0c83c084",
@@ -310,7 +310,7 @@
 X"c0800883",
 X"c0840883",
 X"c0880875",
-X"7580f0c1",
+X"7580f0d1",
 X"2d505083",
 X"c0800856",
 X"83c0880c",
@@ -554,7 +554,7 @@
 X"5a5a82d0",
 X"5283c2cc",
 X"085180df",
-X"c43f83c0",
+X"d43f83c0",
 X"800857f9",
 X"e13f7952",
 X"83c2d451",
@@ -565,10 +565,10 @@
 X"09810682",
 X"833883c0",
 X"b0080b0b",
-X"81d8a053",
+X"81d8b053",
 X"705256a6",
 X"b63f0b0b",
-X"81d8a052",
+X"81d8b052",
 X"80c01651",
 X"a6a93f75",
 X"bc170c73",
@@ -844,7 +844,7 @@
 X"5affab39",
 X"76982b55",
 X"74802587",
-X"3881d2a8",
+X"3881d2b8",
 X"173357ff",
 X"9f175574",
 X"99268938",
@@ -1040,7 +1040,7 @@
 X"79842a90",
 X"3d335471",
 X"71315356",
-X"5680d0a9",
+X"5680d0b9",
 X"3f83c080",
 X"08820570",
 X"881c0c83",
@@ -1200,11 +1200,11 @@
 X"56537680",
 X"2eb73874",
 X"52ff1651",
-X"80cbaa3f",
+X"80cbba3f",
 X"83c08008",
 X"ff187654",
 X"70535853",
-X"80cb9a3f",
+X"80cbaa3f",
 X"83c08008",
 X"73269638",
 X"74307078",
@@ -1421,8 +1421,8 @@
 X"78902e09",
 X"810680cd",
 X"3802ab05",
-X"3381dab4",
-X"0b81dab4",
+X"3381dac4",
+X"0b81dac4",
 X"33575856",
 X"8c397476",
 X"2e8a3884",
@@ -1468,16 +1468,16 @@
 X"0880c138",
 X"7451e6b1",
 X"3f83c080",
-X"0881d8b0",
+X"0881d8c0",
 X"5383c080",
 X"085253ff",
 X"913f83c0",
 X"8008a138",
-X"81d8b452",
+X"81d8c452",
 X"7251ff82",
 X"3f83c080",
 X"08923881",
-X"d8b85272",
+X"d8c85272",
 X"51fef33f",
 X"83c08008",
 X"802e8338",
@@ -1503,7 +1503,7 @@
 X"c0800833",
 X"953d5654",
 X"73963881",
-X"ddc45274",
+X"ddd45274",
 X"5189903f",
 X"9a397d52",
 X"7851defc",
@@ -1556,11 +1556,11 @@
 X"38800b83",
 X"c7d00c80",
 X"0b83c884",
-X"0c81d8bc",
+X"0c81d8cc",
 X"518d8f3f",
 X"81800b83",
 X"c8840c81",
-X"d8c4518d",
+X"d8d4518d",
 X"813fa80b",
 X"83c7d00c",
 X"76802e80",
@@ -1574,11 +1574,11 @@
 X"56e3b83f",
 X"83c08008",
 X"802e8838",
-X"81d8cc51",
+X"81d8dc51",
 X"8cc83f76",
 X"51e2fa3f",
 X"83c08008",
-X"5281d9d8",
+X"5281d9e8",
 X"518cb73f",
 X"7651e382",
 X"3f83c080",
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Index: mcctv/zpu_rom.vhdl
===================================================================
--- mcctv/zpu_rom.vhdl	(revision 324)
+++ mcctv/zpu_rom.vhdl	(revision 325)
@@ -181,7 +181,7 @@
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Index: mist/zpu_rom.vhdl
===================================================================
--- mist/zpu_rom.vhdl	(revision 324)
+++ mist/zpu_rom.vhdl	(revision 325)
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Index: papilioduo/atari800core_papilioduo.vhd
===================================================================
--- papilioduo/atari800core_papilioduo.vhd	(nonexistent)
+++ papilioduo/atari800core_papilioduo.vhd	(revision 325)
@@ -0,0 +1,589 @@
+---------------------------------------------------------------------------
+-- (c) 2013-2015 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+use ieee.numeric_std.all;
+
+LIBRARY work;
+
+ENTITY atari800core_papilioduo IS 
+	GENERIC
+	(
+		TV : integer := 1;  -- 1 = PAL, 0=NTSC
+		SCANDOUBLE : integer := 0; -- 1 = YES, 0=NO, (+ later scanlines etc)
+		internal_rom : integer := 1 ;
+		internal_ram : integer := 8192;
+		ext_clock : integer := 0
+	);
+	PORT
+	(
+		CLK_32 :  IN  STD_LOGIC; --32MHz - double check TODO
+
+		-- For test bench
+		EXT_CLK : in std_logic_vector(ext_clock downto 1);
+                EXT_SCANDOUBLE_CLK : in std_logic_vector(ext_clock downto 1);
+                EXT_PLL_LOCKED : in std_logic_vector(ext_clock downto 1);
+
+		PS2_CLK1 :  IN  STD_LOGIC;
+		PS2_DAT1 :  IN  STD_LOGIC;
+--NET PS2_DAT1      LOC="P120" | IOSTANDARD=LVTTL;                                # A4
+--NET PS2_CLK1      LOC="P121" | IOSTANDARD=LVTTL;                                # A5
+
+		VGA_VSYNC :  OUT  STD_LOGIC;
+		VGA_HSYNC :  OUT  STD_LOGIC;
+		VGA_BLUE :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_GREEN :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_RED :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+--NET VGA_HSYNC     LOC="P99"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C0
+--NET VGA_VSYNC     LOC="P97"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C1
+--NET VGA_BLUE(0)   LOC="P93"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C2
+--NET VGA_BLUE(1)   LOC="P83"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C5
+--NET VGA_BLUE(2)   LOC="P81"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C6
+--NET VGA_BLUE(3)   LOC="P79"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C7
+--NET VGA_GREEN(0)  LOC="P75"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C8
+--NET VGA_GREEN(1)  LOC="P67"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C9
+--NET VGA_GREEN(2)  LOC="P62"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C10
+--NET VGA_GREEN(3)  LOC="P59"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C11
+--NET VGA_RED(3)    LOC="P57"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C12
+--NET VGA_RED(2)    LOC="P55"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C13
+--NET VGA_RED(1)    LOC="P50"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C14
+--NET VGA_RED(0)    LOC="P47"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C15
+		
+--		JOY1_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		JOYSTICK1_1 : IN STD_LOGIC;
+		JOYSTICK1_2 : IN STD_LOGIC;
+		JOYSTICK1_3 : IN STD_LOGIC;
+		JOYSTICK1_4 : IN STD_LOGIC;
+		JOYSTICK1_5 : IN STD_LOGIC;
+		JOYSTICK1_6 : IN STD_LOGIC;
+		JOYSTICK1_7 : IN STD_LOGIC;
+		JOYSTICK1_9 : IN STD_LOGIC;
+--NET JOYSTICK1_5   LOC="P123" | IOSTANDARD=LVTTL;                                # A6
+--NET JOYSTICK1_9   LOC="P124" | IOSTANDARD=LVTTL;                                # A7
+--NET JOYSTICK1_4   LOC="P126" | IOSTANDARD=LVTTL;                                # A8
+--NET JOYSTICK1_3   LOC="P127" | IOSTANDARD=LVTTL;                                # A9
+--NET JOYSTICK1_7   LOC="P131" | IOSTANDARD=LVTTL;                                # A10
+--NET JOYSTICK1_2   LOC="P132" | IOSTANDARD=LVTTL;                                # A11
+--NET JOYSTICK1_6   LOC="P133" | IOSTANDARD=LVTTL;                                # A12
+--NET JOYSTICK1_1   LOC="P134" | IOSTANDARD=LVTTL;                                # A13
+--		JOY2_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		JOYSTICK2_1 : IN STD_LOGIC;
+		JOYSTICK2_2 : IN STD_LOGIC;
+		JOYSTICK2_3 : IN STD_LOGIC;
+		JOYSTICK2_4 : IN STD_LOGIC;
+		JOYSTICK2_5 : IN STD_LOGIC;
+		JOYSTICK2_6 : IN STD_LOGIC;
+		JOYSTICK2_7 : IN STD_LOGIC;
+		JOYSTICK2_9 : IN STD_LOGIC;
+--NET JOYSTICK2_5   LOC="P98"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D0
+--NET JOYSTICK2_4   LOC="P95"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D1
+--NET JOYSTICK2_3   LOC="P92"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D2
+--NET JOYSTICK2_2   LOC="P87"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D3
+--NET JOYSTICK2_1   LOC="P84"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D4
+--NET JOYSTICK2_6   LOC="P82"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D5
+--NET JOYSTICK2_7   LOC="P80"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D6
+--NET JOYSTICK2_9   LOC="P78"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D7
+		
+		AUDIO1_LEFT : OUT std_logic;
+		AUDIO1_RIGHT : OUT std_logic;
+--NET AUDIO1_LEFT   LOC="P88"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C3
+--NET AUDIO1_RIGHT  LOC="P85"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C4
+
+		SD_MISO :  IN  STD_LOGIC;
+		SD_SCK :  OUT  STD_LOGIC;
+		SD_MOSI :  OUT  STD_LOGIC;
+		SD_nCS :  OUT  STD_LOGIC;
+		SD_CD : IN STD_LOGIC; -- card detect
+
+--NET SD_MISO       LOC="P118" | IOSTANDARD=LVTTL;                                # A2
+--NET SD_CD         LOC="P119" | IOSTANDARD=LVTTL;                                # A3
+--NET SD_MOSI       LOC="P115" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # B0
+--NET SD_SCK        LOC="P114" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # B1
+--NET SD_nCS        LOC="P112" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # B2
+
+
+		SRAM_DATA :  INOUT  STD_LOGIC_VECTOR(7 downto 0);
+		SRAM_ADDR :  OUT  STD_LOGIC_VECTOR(20 downto 0);
+		SRAM_CE :  OUT  STD_LOGIC;
+		SRAM_WE :  OUT  STD_LOGIC;
+		SRAM_OE :  OUT  STD_LOGIC;
+--NET SRAM_DATA(0)  LOC="P14"  | IOSTANDARD=LVTTL;                                # SRAM_DATA0
+--NET SRAM_DATA(1)  LOC="P15"  | IOSTANDARD=LVTTL;                                # SRAM_DATA1
+--NET SRAM_DATA(2)  LOC="P16"  | IOSTANDARD=LVTTL;                                # SRAM_DATA2
+--NET SRAM_DATA(3)  LOC="P17"  | IOSTANDARD=LVTTL;                                # SRAM_DATA3
+--NET SRAM_DATA(4)  LOC="P21"  | IOSTANDARD=LVTTL;                                # SRAM_DATA4
+--NET SRAM_DATA(5)  LOC="P22"  | IOSTANDARD=LVTTL;                                # SRAM_DATA5
+--NET SRAM_DATA(6)  LOC="P23"  | IOSTANDARD=LVTTL;                                # SRAM_DATA6
+--NET SRAM_DATA(7)  LOC="P24"  | IOSTANDARD=LVTTL;                                # SRAM_DATA7
+--NET SRAM_ADDR(0)  LOC="P7"   | IOSTANDARD=LVTTL;                                # SRAM_ADDR0
+--NET SRAM_ADDR(1)  LOC="P8"   | IOSTANDARD=LVTTL;                                # SRAM_ADDR1
+--NET SRAM_ADDR(2)  LOC="P9"   | IOSTANDARD=LVTTL;                                # SRAM_ADDR2
+--NET SRAM_ADDR(3)  LOC="P10"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR3
+--NET SRAM_ADDR(4)  LOC="P11"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR4
+--NET SRAM_ADDR(5)  LOC="P5"   | IOSTANDARD=LVTTL;                                # SRAM_ADDR5
+--NET SRAM_ADDR(6)  LOC="P2"   | IOSTANDARD=LVTTL;                                # SRAM_ADDR6
+--NET SRAM_ADDR(7)  LOC="P1"   | IOSTANDARD=LVTTL;                                # SRAM_ADDR7
+--NET SRAM_ADDR(8)  LOC="P143" | IOSTANDARD=LVTTL;                                # SRAM_ADDR8
+--NET SRAM_ADDR(9)  LOC="P142" | IOSTANDARD=LVTTL;                                # SRAM_ADDR9
+--NET SRAM_ADDR(10) LOC="P43"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR10
+--NET SRAM_ADDR(11) LOC="P41"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR11
+--NET SRAM_ADDR(12) LOC="P40"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR12
+--NET SRAM_ADDR(13) LOC="P35"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR13
+--NET SRAM_ADDR(14) LOC="P34"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR14
+--NET SRAM_ADDR(15) LOC="P27"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR15
+--NET SRAM_ADDR(16) LOC="P29"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR16
+--NET SRAM_ADDR(17) LOC="P33"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR17
+--NET SRAM_ADDR(18) LOC="P32"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR18
+--NET SRAM_ADDR(19) LOC="P44"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR19
+--NET SRAM_ADDR(20) LOC="P30"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR20
+--NET SRAM_CE       LOC="P12"  | IOSTANDARD=LVTTL;                                # SRAM_CE
+--NET SRAM_WE       LOC="P6"   | IOSTANDARD=LVTTL;                                # SRAM_WE
+--NET SRAM_OE       LOC="P26"  | IOSTANDARD=LVTTL;                                # SRAM_OE
+
+
+		ARDUINO_RESET :  OUT  STD_LOGIC;
+		RESET :  IN  STD_LOGIC;
+--NET RESET         LOC="P102" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # B5
+--NET ARDUINO_RESET LOC="P139" | IOSTANDARD=LVTTL;                                # ARDUINO_RESET
+
+
+		--Some LEDS - use one for power(!), one for SIO, others for ???
+		--Could use them to show sd card init, rom loaded or similar
+		LED1 :  OUT  STD_LOGIC;
+		LED2 :  OUT  STD_LOGIC;
+		LED3 :  OUT  STD_LOGIC;
+		LED4 :  OUT  STD_LOGIC
+	
+--NET LED1          LOC="P56"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D12
+--NET LED2          LOC="P51"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D13
+--NET LED3          LOC="P48"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D14
+--NET LED4          LOC="P39"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D15
+	);
+END atari800core_papilioduo;
+
+ARCHITECTURE vhdl OF atari800core_papilioduo IS 
+
+	signal AUDIO_L_PCM : std_logic_vector(15 downto 0);
+	signal AUDIO_R_PCM : std_logic_vector(15 downto 0);
+	
+	signal VIDEO_VS : std_logic;
+	signal VIDEO_HS : std_logic;
+	signal VIDEO_R : std_logic_vector(7 downto 0);
+	signal VIDEO_G : std_logic_vector(7 downto 0);
+	signal VIDEO_B : std_logic_vector(7 downto 0);
+
+	signal VIDEO_BLANK : std_logic;
+	signal VIDEO_BURST : std_logic;
+	signal VIDEO_START_OF_FIELD : std_logic;
+	signal VIDEO_ODD_LINE : std_logic;
+
+	signal PAL : std_logic;
+	
+	signal JOY1_IN_n : std_logic_vector(4 downto 0);
+	signal JOY2_IN_n : std_logic_vector(4 downto 0);
+
+	signal PLL1_LOCKED : std_logic;
+	signal CLK_PLL1 : std_logic;
+	
+	signal RESET_n : std_logic;
+	signal PLL_LOCKED : std_logic;
+	signal CLK : std_logic;
+	signal CLK_SDRAM : std_logic;
+
+	signal SYSTEM_RESET_REQUEST: std_logic;
+
+	-- pokey keyboard
+	SIGNAL KEYBOARD_SCAN : std_logic_vector(5 downto 0);
+	SIGNAL KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
+	
+	-- gtia consol keys
+	SIGNAL CONSOL_START : std_logic;
+	SIGNAL CONSOL_SELECT : std_logic;
+	SIGNAL CONSOL_OPTION : std_logic;
+	SIGNAL FKEYS : std_logic_vector(11 downto 0);
+
+	-- scandoubler
+	signal scandouble_clk : std_logic;
+
+	signal half_scandouble_enable_reg : std_logic;
+	signal half_scandouble_enable_next : std_logic;
+
+	function palette_from_scandouble( scandouble : integer ) return integer is
+	begin
+		if (scandouble = 1) then
+			return 0;
+		else
+			return 1;
+		end if;
+	end palette_from_scandouble;
+	
+	-- dma/virtual drive
+	signal DMA_ADDR_FETCH : std_logic_vector(23 downto 0);
+	signal DMA_WRITE_DATA : std_logic_vector(31 downto 0);
+	signal DMA_FETCH : std_logic;
+	signal DMA_32BIT_WRITE_ENABLE : std_logic;
+	signal DMA_16BIT_WRITE_ENABLE : std_logic;
+	signal DMA_8BIT_WRITE_ENABLE : std_logic;
+	signal DMA_READ_ENABLE : std_logic;
+	signal DMA_MEMORY_READY : std_logic;
+	signal DMA_MEMORY_DATA : std_logic_vector(31 downto 0);
+
+	signal ZPU_ADDR_ROM : std_logic_vector(15 downto 0);
+	signal ZPU_ROM_DATA :  std_logic_vector(31 downto 0);
+
+	signal ZPU_OUT1 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT2 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT3 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT4 : std_logic_vector(31 downto 0);
+	signal ZPU_OUT5 : std_logic_vector(31 downto 0);
+
+	signal zpu_pokey_enable : std_logic;
+	signal zpu_sio_txd : std_logic;
+	signal zpu_sio_rxd : std_logic;
+	signal zpu_sio_command : std_logic;
+
+	-- system control from zpu
+	signal ram_select : std_logic_vector(2 downto 0);
+	signal rom_select : std_logic_vector(5 downto 0);
+	signal reset_atari : std_logic;
+	signal pause_atari : std_logic;
+	SIGNAL speed_6502 : std_logic_vector(5 downto 0);
+	signal emulated_cartridge_select: std_logic_vector(5 downto 0);
+
+	-- turbo freezer!
+	signal freezer_enable : std_logic;
+	signal freezer_activate: std_logic;
+
+	signal PS2_KEYS : STD_LOGIC_VECTOR(511 downto 0);
+	signal PS2_KEYS_NEXT : STD_LOGIC_VECTOR(511 downto 0);
+BEGIN 
+
+ARDUINO_RESET <= '0'; -- hold arduino in reset for now
+SRAM_DATA <= (others => 'Z');
+SRAM_ADDR <= (others => '0');
+SRAM_CE <= '1';
+SRAM_WE <= '1';
+SRAM_OE <= '1';
+
+u_DAC_L : entity work.dac
+port map (
+   CLK_I                      => CLK,
+   RES_N_I                    => RESET_N,
+   DAC_I                      => AUDIO_L_PCM,
+   DAC_O                      => AUDIO1_LEFT );
+
+u_DAC_R : entity work.dac
+port map (
+   CLK_I                      => CLK,
+   RES_N_I                    => RESET_N,
+   DAC_I                      => AUDIO_R_PCM,
+   DAC_O                      => AUDIO1_RIGHT );
+
+
+gen_fake_pll : if ext_clock=1 generate
+	CLK <= EXT_CLK(1);
+	SCANDOUBLE_CLK <= EXT_SCANDOUBLE_CLK(1);
+	PLL_LOCKED <= EXT_PLL_LOCKED(1);
+end generate;
+
+--TODO xilinx version
+gen_real_pll : if ext_clock=0 generate
+--	gen_tv_pal : if tv=1 generate
+--		papilioduo_pll : entity work.pal_pll
+--		PORT MAP(inclk0 => FPGA_CLK,
+--				 c0 => CLK_PLL1,
+--				 locked => PLL1_LOCKED);
+--		papilioduo_pll2 : entity work.pll_downstream_pal
+--		PORT MAP(inclk0 => CLK_PLL1,
+--				 c0 => CLK_SDRAM,
+--				 c1 => CLK,
+--				 c2 => SDRAM_CLK,
+--				 c3 => SVIDEO_DAC_CLK,
+--				 c4 => SCANDOUBLE_CLK,      
+--				 areset => not(PLL1_LOCKED),
+--				 locked => PLL_LOCKED);
+--	end generate;
+--
+--	gen_tv_ntsc : if tv=0 generate
+--		papilioduo_pll : entity work.ntsc_pll
+--		PORT MAP(inclk0 => FPGA_CLK,
+--				 c0 => CLK_PLL1,
+--				 locked => PLL1_LOCKED);
+--		papilioduo_pll2 : entity work.pll_downstream_ntsc
+--		PORT MAP(inclk0 => CLK_PLL1,
+--				 c0 => CLK_SDRAM,
+--				 c1 => CLK,
+--				 c2 => SDRAM_CLK,
+--				 c3 => SVIDEO_DAC_CLK,
+--				 c4 => SCANDOUBLE_CLK,      
+--				 areset => not(PLL1_LOCKED),
+--				 locked => PLL_LOCKED);
+--	end generate;
+
+	u_PLL : entity work.PLL
+	port map (
+	   CLKIN                      => CLK_32,
+	   CLKOUT                     => CLK,
+	   CLKOUT2                    => SCANDOUBLE_CLK,
+	   LOCKED                     => PLL_LOCKED );
+end generate;
+
+reset_n <= PLL_LOCKED;
+JOY1_IN_N <= JOYSTICK1_6&JOYSTICK1_4&JOYSTICK1_3&JOYSTICK1_2&JOYSTICK1_1;
+JOY2_IN_N <= JOYSTICK2_6&JOYSTICK2_4&JOYSTICK2_3&JOYSTICK2_2&JOYSTICK2_1;
+
+--	JOY1_n : IN std_logic_vector(4 downto 0); -- FRLDU, 0=pressed
+
+
+-- PS2 to pokey
+keyboard_map1 : entity work.ps2_to_atari800
+	GENERIC MAP
+	(
+		ps2_enable => 1,
+		direct_enable => 1
+	)
+	PORT MAP
+	( 
+		CLK => clk,
+		RESET_N => reset_n,
+		PS2_CLK => PS2_CLK1,
+		PS2_DAT => PS2_DAT1,
+
+		INPUT => zpu_out4,
+		
+		KEYBOARD_SCAN => KEYBOARD_SCAN,
+		KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
+
+		CONSOL_START => CONSOL_START,
+		CONSOL_SELECT => CONSOL_SELECT,
+		CONSOL_OPTION => CONSOL_OPTION,
+		
+		FKEYS => FKEYS,
+		FREEZER_ACTIVATE => freezer_activate,
+
+		PS2_KEYS_NEXT_OUT => ps2_keys_next,
+		PS2_KEYS => ps2_keys
+	);
+
+PAL <= '1' when TV=1 else '0';
+
+atarixl_simple_sdram1 : entity work.atari800core_simple_sdram
+	GENERIC MAP
+	(
+		cycle_length => 16,
+		internal_rom => internal_rom,
+		internal_ram => internal_ram,
+		video_bits => 8,
+		palette => palette_from_scandouble(scandouble)
+	)
+	PORT MAP
+	(
+		CLK => CLK,
+		--RESET_N => RESET_N and SDRAM_RESET_N and not(SYSTEM_RESET_REQUEST),
+		RESET_N => RESET_N,
+
+		VIDEO_VS => VIDEO_VS,
+		VIDEO_HS => VIDEO_HS,
+		VIDEO_B => VIDEO_B,
+		VIDEO_G => VIDEO_G,
+		VIDEO_R => VIDEO_R,
+		VIDEO_BLANK =>VIDEO_BLANK,
+		VIDEO_BURST =>VIDEO_BURST,
+		VIDEO_START_OF_FIELD =>VIDEO_START_OF_FIELD,
+		VIDEO_ODD_LINE =>VIDEO_ODD_LINE,
+
+		AUDIO_L => AUDIO_L_PCM,
+		AUDIO_R => AUDIO_R_PCM,
+
+		JOY1_n => JOY1_IN_n,
+		JOY2_n => JOY2_IN_n,
+
+		KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
+		KEYBOARD_SCAN => KEYBOARD_SCAN,
+
+		SIO_COMMAND => zpu_sio_command,
+		SIO_RXD => zpu_sio_txd,
+		SIO_TXD => zpu_sio_rxd,
+
+		CONSOL_OPTION => CONSOL_OPTION,
+		CONSOL_SELECT => CONSOL_SELECT,
+		CONSOL_START => CONSOL_START,
+
+-- TODO, connect to SRAM! Handle 32-bit in multiple cycles. How fast is the sram.
+		SDRAM_REQUEST => open,
+		SDRAM_REQUEST_COMPLETE => '1',
+		SDRAM_READ_ENABLE => open,
+		SDRAM_WRITE_ENABLE => open,
+		SDRAM_ADDR => open,
+		SDRAM_DO => (others=>'0'),
+		SDRAM_DI => open,
+		SDRAM_32BIT_WRITE_ENABLE => open,
+		SDRAM_16BIT_WRITE_ENABLE => open,
+		SDRAM_8BIT_WRITE_ENABLE => open,
+		SDRAM_REFRESH => open,
+
+		DMA_FETCH => dma_fetch,
+		DMA_READ_ENABLE => dma_read_enable,
+		DMA_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
+		DMA_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
+		DMA_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
+		DMA_ADDR => dma_addr_fetch,
+		DMA_WRITE_DATA => dma_write_data,
+		MEMORY_READY_DMA => dma_memory_ready,
+		DMA_MEMORY_DATA => dma_memory_data, 
+
+--   		RAM_SELECT => ram_select,
+--    		ROM_SELECT => rom_select,
+--		PAL => PAL,
+--		HALT => pause_atari,
+--		THROTTLE_COUNT_6502 => speed_6502,
+--		emulated_cartridge_select => emulated_cartridge_select,
+--		freezer_enable => freezer_enable,
+--		freezer_activate => freezer_activate
+
+   		RAM_SELECT => (others=>'0'),
+    		ROM_SELECT => "000001",
+		PAL => PAL,
+		HALT => '0',
+		THROTTLE_COUNT_6502 => "000001",
+		emulated_cartridge_select => (others=>'0'),
+		freezer_enable => '0',
+		freezer_activate => '0'
+	);
+
+-- Video options
+	gen_scandouble_off: if scandouble=0 generate
+		VGA_HSYNC <= not(VIDEO_HS xor VIDEO_VS);
+		VGA_VSYNC <= not(VIDEO_VS);
+		VGA_BLUE <= VIDEO_B(7 downto 4);
+		VGA_GREEN <= VIDEO_G(7 downto 4);
+		VGA_RED <= VIDEO_R(7 downto 4);
+	end generate;
+
+	gen_scandouble_on: if scandouble=1 generate
+		process(scandouble_clk,reset_n)
+		begin
+			if (reset_n='0') then
+				half_scandouble_enable_reg <= '0';
+			elsif (scandouble_clk'event and scandouble_clk='1') then
+				half_scandouble_enable_reg <= half_scandouble_enable_next;
+			end if;
+		end process;
+
+		half_scandouble_enable_next <= not(half_scandouble_enable_reg);
+
+		scandoubler1: entity work.scandoubler
+		PORT MAP
+		( 
+			CLK => SCANDOUBLE_CLK,
+		        RESET_N => reset_n,
+			
+			VGA => '1',
+			COMPOSITE_ON_HSYNC => '0', -- TODO
+
+			colour_enable => half_scandouble_enable_reg,
+			doubled_enable => '1',
+			
+			-- GTIA interface
+			pal => PAL,
+			colour_in => VIDEO_B,
+			vsync_in => VIDEO_VS,
+			hsync_in => VIDEO_HS,
+			
+			-- TO TV...
+			R => VGA_RED,
+			G => VGA_GREEN,
+			B => VGA_BLUE,
+			
+			VSYNC => VGA_VSYNC,
+			HSYNC => VGA_HSYNC
+		);
+	end generate;
+
+zpu: entity work.zpucore
+	GENERIC MAP
+	(
+		platform => 1,
+		spi_clock_div => 1, -- 28MHz/2. Max for SD cards is 25MHz...
+		memory => 8192,
+		usb => 0
+	)
+	PORT MAP
+	(
+		-- standard...
+		CLK => CLK,
+		RESET_N => '0', -- RESET_N and sdram_rdy, TODO, allow ZPU to run!
+
+		-- dma bus master (with many waitstates...)
+		ZPU_ADDR_FETCH => dma_addr_fetch,
+		ZPU_DATA_OUT => dma_write_data,
+		ZPU_FETCH => dma_fetch,
+		ZPU_32BIT_WRITE_ENABLE => dma_32bit_write_enable,
+		ZPU_16BIT_WRITE_ENABLE => dma_16bit_write_enable,
+		ZPU_8BIT_WRITE_ENABLE => dma_8bit_write_enable,
+		ZPU_READ_ENABLE => dma_read_enable,
+		ZPU_MEMORY_READY => dma_memory_ready,
+		ZPU_MEMORY_DATA => dma_memory_data, 
+
+		-- rom bus master
+		-- data on next cycle after addr
+		ZPU_ADDR_ROM => zpu_addr_rom,
+		ZPU_ROM_DATA => zpu_rom_data,
+
+		-- spi master
+		-- Too painful to bit bang spi from zpu, so we have a hardware master in here
+		ZPU_SD_DAT0 => SD_MISO,
+		ZPU_SD_CLK => SD_SCK,
+		ZPU_SD_CMD => SD_MOSI,
+		ZPU_SD_DAT3 => SD_nCS,
+
+		-- SIO
+		-- Ditto for speaking to Atari, we have a built in Pokey
+		ZPU_POKEY_ENABLE => zpu_pokey_enable,
+		ZPU_SIO_TXD => zpu_sio_txd,
+		ZPU_SIO_RXD => zpu_sio_rxd,
+		ZPU_SIO_COMMAND => zpu_sio_command,
+
+		-- external control
+		-- switches etc. sector DMA blah blah.
+		ZPU_IN1 => X"000"&
+			"00"&ps2_keys(16#76#)&ps2_keys(16#5A#)&ps2_keys(16#174#)&ps2_keys(16#16B#)&ps2_keys(16#172#)&ps2_keys(16#175#)& -- (esc)FLRDU
+			FKEYS,
+		ZPU_IN2 => X"00000000",
+		ZPU_IN3 => X"00000000",
+		ZPU_IN4 => X"00000000",
+
+		-- ouputs - e.g. Atari system control, halt, throttle, rom select
+		ZPU_OUT1 => zpu_out1,
+		ZPU_OUT2 => zpu_out2, --joy0
+		ZPU_OUT3 => zpu_out3, --joy1
+		ZPU_OUT4 => zpu_out4, --keyboard
+		ZPU_OUT5 => zpu_out5  --analog stick (not supported without USB)
+	);
+
+	pause_atari <= zpu_out1(0);
+	reset_atari <= zpu_out1(1);
+	speed_6502 <= zpu_out1(7 downto 2);
+	ram_select <= zpu_out1(10 downto 8);
+	rom_select <= zpu_out1(16 downto 11);
+	emulated_cartridge_select <= zpu_out1(22 downto 17);
+	freezer_enable <= zpu_out1(25);
+
+zpu_rom1: entity work.zpu_rom
+	port map(
+	        clock => clk,
+	        address => zpu_addr_rom(13 downto 2),
+	        q => zpu_rom_data
+	);
+
+enable_179_clock_div_zpu_pokey : entity work.enable_divider
+	generic map (COUNT=>32) -- cycle_length
+	port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>zpu_pokey_enable);
+
+END vhdl;
Index: papilioduo/build.sh
===================================================================
--- papilioduo/build.sh	(nonexistent)
+++ papilioduo/build.sh	(revision 325)
@@ -0,0 +1,49 @@
+#!/bin/bash
+
+name=papilioduo
+args=$@
+shift
+
+. /home/markw/fpga/xilinx/14.7/ISE_DS/settings64.sh
+
+mkdir -p build
+pushd build
+
+# copy source files
+cp -p ../pll/* .
+cp -p ../../common/a8core/*.vhd .
+cp -p ../../common/a8core/*.vhdl .
+cp -p ../../common/components/*.vhd .
+cp -p ../../common/components/*.vhdl .
+cp -p ../../common/zpu/*.vhd .
+cp -p ../../common/zpu/*.vhdl .
+#rm -f delay_line.vhdl
+cp -p ../*.vhd .
+cp -p ../*.vhdl .
+cp -p ../*.xst .
+
+cp -p ../$name.ucf .
+cp -p ../$name.ut .
+cp -p ../$name.prj .
+
+mkdir -p xst/projnav.tmp/
+
+echo "Starting Synthesis"
+xst -intstyle ise -ifn $name.xst -ofn $name.syr
+
+echo "Starting NGD"
+ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-tqg144-3 $name.ngc $name.ngd
+
+echo "Starting Map..."
+map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -detail -ir off -pr off -lc off -power off -o $name_map.ncd $name.ngd $name.pcf
+
+echo "Starting Place & Route..."
+par -w -intstyle ise -ol high -mt off $name_map.ncd $name.ncd $name.pcf
+
+echo "Starting Timing Analysis..."
+trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml $name.twx $name.ncd -o $name.twr $name.pcf
+
+echo "Starting Bitgen..."
+bitgen -intstyle ise -f $name.ut $name.ncd
+
+popd

Property changes on: papilioduo/build.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: papilioduo/dac.vhd
===================================================================
--- papilioduo/dac.vhd	(nonexistent)
+++ papilioduo/dac.vhd	(revision 325)
@@ -0,0 +1,53 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dac is
+
+  generic (
+    msbi_g : integer := 15
+  );
+  port (
+    clk_i   : in  std_logic;
+    res_n_i : in  std_logic;
+    dac_i   : in  std_logic_vector(msbi_g downto 0);
+    dac_o   : out std_logic
+  );
+
+end dac;
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture rtl of dac is
+
+  signal DACout_q      : std_logic;
+  signal DeltaAdder_s,
+         SigmaAdder_s,
+         SigmaLatch_q,
+         DeltaB_s      : unsigned(msbi_g+2 downto 0);
+
+begin
+
+  DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
+                                        SigmaLatch_q(msbi_g+2);
+  DeltaB_s(msbi_g   downto        0) <= (others => '0');
+
+  DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
+
+  SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
+
+  seq: process (clk_i, res_n_i)
+  begin
+    if res_n_i = '0' then
+      SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
+      DACout_q     <= '0';
+
+    elsif clk_i'event and clk_i = '1' then
+      SigmaLatch_q <= SigmaAdder_s;
+      DACout_q     <= SigmaLatch_q(msbi_g+2);
+    end if;
+  end process seq;
+
+  dac_o <= DACout_q;
+
+end rtl;
Index: papilioduo/papilioduo.prj
===================================================================
--- papilioduo/papilioduo.prj	(nonexistent)
+++ papilioduo/papilioduo.prj	(revision 325)
@@ -0,0 +1,62 @@
+vhdl work "delay_line.vhdl"
+vhdl work "syncreset_enable_divider.vhd"
+vhdl work "synchronizer.vhdl"
+vhdl work "pokey_poly_5.vhdl"
+vhdl work "pokey_poly_4.vhdl"
+vhdl work "pokey_poly_17_9.vhdl"
+vhdl work "pokey_noise_filter.vhdl"
+vhdl work "pokey_keyboard_scanner.vhdl"
+vhdl work "pokey_countdown_timer.vhdl"
+vhdl work "mult_infer.vhdl"
+vhdl work "generic_ram_infer.vhdl"
+vhdl work "cpu_65xx_e.vhd"
+vhdl work "complete_address_decoder.vhdl"
+vhdl work "zpupkg.vhd"
+vhdl work "wide_delay_line.vhdl"
+vhdl work "simple_counter.vhdl"
+vhdl work "reg_file.vhdl"
+vhdl work "pokey_mixer.vhdl"
+vhdl work "pokey.vhdl"
+vhdl work "gtia_priority.vhdl"
+vhdl work "gtia_player.vhdl"
+vhdl work "freezer_logic.vhd"
+vhdl work "enable_divider.vhdl"
+vhdl work "cpu_65xx_a.vhd"
+vhdl work "cart_logic.vhd"
+vhdl work "antic_dma_clock.vhdl"
+vhdl work "antic_counter.vhdl"
+vhdl work "zpu_core.vhd"
+vhdl work "spi_master.vhd"
+vhdl work "sio_device.vhdl"
+vhdl work "shared_enable.vhdl"
+vhdl work "pokey_mixer_mux.vhdl"
+vhdl work "pia.vhdl"
+vhdl work "os_5200.vhdl"
+vhdl work "os8.vhdl"
+vhdl work "os2.vhdl"
+vhdl work "os16_loop.vhdl"
+vhdl work "os16.vhdl"
+vhdl work "irq_glue.vhdl"
+vhdl work "gtia_palette.vhdl"
+vhdl work "gtia.vhdl"
+vhdl work "cpu.vhd"
+vhdl work "covox.vhd"
+vhdl work "basic.vhdl"
+vhdl work "antic.vhdl"
+vhdl work "address_decoder.vhdl"
+vhdl work "zpu_glue.vhdl"
+vhdl work "zpu_config_regs.vhdl"
+vhdl work "scandouble_ram_infer.vhdl"
+vhdl work "ps2_keyboard.vhdl"
+vhdl work "pot_from_signed.vhdl"
+vhdl work "internalromram.vhd"
+vhdl work "atari800core.vhd"
+vhdl work "zpu_rom.vhdl"
+vhdl work "zpucore.vhd"
+vhdl work "sram.vhdl"
+vhdl work "scandoubler.vhdl"
+vhdl work "ps2_to_atari800.vhdl"
+vhdl work "pll.vhd"
+vhdl work "dac.vhd"
+vhdl work "atari800core_simple_sdram.vhd"
+vhdl work "atari800core_papilioduo.vhd"
Index: papilioduo/papilioduo.scr
===================================================================
--- papilioduo/papilioduo.scr	(nonexistent)
+++ papilioduo/papilioduo.scr	(revision 325)
@@ -0,0 +1,10 @@
+run
+-ifn papilioduo.prj
+-ifmt VHDL
+-ofn papilioduo.ngc
+-ofmt NGC
+-p xc6slx9-tqg144
+-opt_mode Area
+-opt_level 1
+-keep_hierarchy yes
+-top atari800core_papilioduo
Index: papilioduo/papilioduo.ucf
===================================================================
--- papilioduo/papilioduo.ucf	(nonexistent)
+++ papilioduo/papilioduo.ucf	(revision 325)
@@ -0,0 +1,107 @@
+# UCF file for the Papilio DUO board
+# Generated by pin_converter, written by Kevin Lindsey
+# https://github.com/thelonious/papilio_pins/tree/development/pin_converter
+
+## Prohibit the automatic placement of pins that are connected to VCC or GND for configuration.
+CONFIG PROHIBIT=P144;
+CONFIG PROHIBIT=P69;
+CONFIG PROHIBIT=P60;
+
+NET CLK_32        LOC="P94"  | IOSTANDARD=LVTTL | PERIOD=31.25ns;               # CLK
+NET RX            LOC="P46"  | IOSTANDARD=LVTTL;                                # RX
+NET TX            LOC="P141" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # TX
+NET ARDUINO_RESET LOC="P139" | IOSTANDARD=LVTTL;                                # ARDUINO_RESET
+NET RS232_RX      LOC="P116" | IOSTANDARD=LVTTL;                                # A0
+NET RS232_TX      LOC="P117" | IOSTANDARD=LVTTL;                                # A1
+NET SD_MISO       LOC="P118" | IOSTANDARD=LVTTL;                                # A2
+NET SD_CD         LOC="P119" | IOSTANDARD=LVTTL;                                # A3
+NET PS2_DAT1      LOC="P120" | IOSTANDARD=LVTTL;                                # A4
+NET PS2_CLK1      LOC="P121" | IOSTANDARD=LVTTL;                                # A5
+NET JOYSTICK1_5   LOC="P123" | IOSTANDARD=LVTTL;                                # A6
+NET JOYSTICK1_9   LOC="P124" | IOSTANDARD=LVTTL;                                # A7
+NET JOYSTICK1_4   LOC="P126" | IOSTANDARD=LVTTL;                                # A8
+NET JOYSTICK1_3   LOC="P127" | IOSTANDARD=LVTTL;                                # A9
+NET JOYSTICK1_7   LOC="P131" | IOSTANDARD=LVTTL;                                # A10
+NET JOYSTICK1_2   LOC="P132" | IOSTANDARD=LVTTL;                                # A11
+NET JOYSTICK1_6   LOC="P133" | IOSTANDARD=LVTTL;                                # A12
+NET JOYSTICK1_1   LOC="P134" | IOSTANDARD=LVTTL;                                # A13
+NET SD_MOSI       LOC="P115" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # B0
+NET SD_SCK        LOC="P114" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # B1
+NET SD_nCS        LOC="P112" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # B2
+NET SW_LEFT       LOC="P111" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # B3
+NET SW_UP         LOC="P105" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # B4
+NET RESET         LOC="P102" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # B5
+NET SW_DOWN       LOC="P101" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # B6
+NET SW_RIGHT      LOC="P100" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # B7
+NET VGA_HSYNC     LOC="P99"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C0
+NET VGA_VSYNC     LOC="P97"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C1
+NET VGA_BLUE(0)   LOC="P93"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C2
+NET AUDIO1_LEFT   LOC="P88"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C3
+NET AUDIO1_RIGHT  LOC="P85"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C4
+NET VGA_BLUE(1)   LOC="P83"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C5
+NET VGA_BLUE(2)   LOC="P81"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C6
+NET VGA_BLUE(3)   LOC="P79"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C7
+NET VGA_GREEN(0)  LOC="P75"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C8
+NET VGA_GREEN(1)  LOC="P67"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C9
+NET VGA_GREEN(2)  LOC="P62"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C10
+NET VGA_GREEN(3)  LOC="P59"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C11
+NET VGA_RED(3)    LOC="P57"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C12
+NET VGA_RED(2)    LOC="P55"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C13
+NET VGA_RED(1)    LOC="P50"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C14
+NET VGA_RED(0)    LOC="P47"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # C15
+NET JOYSTICK2_5   LOC="P98"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D0
+NET JOYSTICK2_4   LOC="P95"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D1
+NET JOYSTICK2_3   LOC="P92"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D2
+NET JOYSTICK2_2   LOC="P87"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D3
+NET JOYSTICK2_1   LOC="P84"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D4
+NET JOYSTICK2_6   LOC="P82"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D5
+NET JOYSTICK2_7   LOC="P80"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D6
+NET JOYSTICK2_9   LOC="P78"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D7
+NET PS2_CLK2      LOC="P74"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D8
+NET PS2_DAT2      LOC="P66"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D9
+NET AUDIO2_RIGHT  LOC="P61"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D10
+NET AUDIO2_LEFT   LOC="P58"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D11
+NET LED1          LOC="P56"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D12
+NET LED2          LOC="P51"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D13
+NET LED3          LOC="P48"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D14
+NET LED4          LOC="P39"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # D15
+NET SRAM_ADDR(0)  LOC="P7"   | IOSTANDARD=LVTTL;                                # SRAM_ADDR0
+NET SRAM_ADDR(1)  LOC="P8"   | IOSTANDARD=LVTTL;                                # SRAM_ADDR1
+NET SRAM_ADDR(2)  LOC="P9"   | IOSTANDARD=LVTTL;                                # SRAM_ADDR2
+NET SRAM_ADDR(3)  LOC="P10"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR3
+NET SRAM_ADDR(4)  LOC="P11"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR4
+NET SRAM_ADDR(5)  LOC="P5"   | IOSTANDARD=LVTTL;                                # SRAM_ADDR5
+NET SRAM_ADDR(6)  LOC="P2"   | IOSTANDARD=LVTTL;                                # SRAM_ADDR6
+NET SRAM_ADDR(7)  LOC="P1"   | IOSTANDARD=LVTTL;                                # SRAM_ADDR7
+NET SRAM_ADDR(8)  LOC="P143" | IOSTANDARD=LVTTL;                                # SRAM_ADDR8
+NET SRAM_ADDR(9)  LOC="P142" | IOSTANDARD=LVTTL;                                # SRAM_ADDR9
+NET SRAM_ADDR(10) LOC="P43"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR10
+NET SRAM_ADDR(11) LOC="P41"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR11
+NET SRAM_ADDR(12) LOC="P40"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR12
+NET SRAM_ADDR(13) LOC="P35"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR13
+NET SRAM_ADDR(14) LOC="P34"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR14
+NET SRAM_ADDR(15) LOC="P27"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR15
+NET SRAM_ADDR(16) LOC="P29"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR16
+NET SRAM_ADDR(17) LOC="P33"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR17
+NET SRAM_ADDR(18) LOC="P32"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR18
+NET SRAM_ADDR(19) LOC="P44"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR19
+NET SRAM_ADDR(20) LOC="P30"  | IOSTANDARD=LVTTL;                                # SRAM_ADDR20
+NET SRAM_DATA(0)  LOC="P14"  | IOSTANDARD=LVTTL;                                # SRAM_DATA0
+NET SRAM_DATA(1)  LOC="P15"  | IOSTANDARD=LVTTL;                                # SRAM_DATA1
+NET SRAM_DATA(2)  LOC="P16"  | IOSTANDARD=LVTTL;                                # SRAM_DATA2
+NET SRAM_DATA(3)  LOC="P17"  | IOSTANDARD=LVTTL;                                # SRAM_DATA3
+NET SRAM_DATA(4)  LOC="P21"  | IOSTANDARD=LVTTL;                                # SRAM_DATA4
+NET SRAM_DATA(5)  LOC="P22"  | IOSTANDARD=LVTTL;                                # SRAM_DATA5
+NET SRAM_DATA(6)  LOC="P23"  | IOSTANDARD=LVTTL;                                # SRAM_DATA6
+NET SRAM_DATA(7)  LOC="P24"  | IOSTANDARD=LVTTL;                                # SRAM_DATA7
+NET SRAM_CE       LOC="P12"  | IOSTANDARD=LVTTL;                                # SRAM_CE
+NET SRAM_WE       LOC="P6"   | IOSTANDARD=LVTTL;                                # SRAM_WE
+NET SRAM_OE       LOC="P26"  | IOSTANDARD=LVTTL;                                # SRAM_OE
+NET JTAG_TMS      LOC="P107" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # JTAG_TMS
+NET JTAG_TCK      LOC="P109" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # JTAG_TCK
+NET JTAG_TDI      LOC="P110" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # JTAG_TDI
+NET JTAG_TDO      LOC="P106" | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # JTAG_TDO
+NET FLASH_CS      LOC="P38"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # FLASH_CS
+NET FLASH_CK      LOC="P70"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # FLASH_CK
+NET FLASH_SI      LOC="P64"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST;          # FLASH_SI
+NET FLASH_SO      LOC="P65"  | IOSTANDARD=LVTTL | DRIVE=8 | SLEW=FAST | PULLUP; # FLASH_SO
Index: papilioduo/papilioduo.ut
===================================================================
--- papilioduo/papilioduo.ut	(nonexistent)
+++ papilioduo/papilioduo.ut	(revision 325)
@@ -0,0 +1,30 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g Reset_on_err:No
+-g ConfigRate:2
+-g ProgPin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g ExtMasterCclk_en:No
+-g SPI_buswidth:1
+-g TIMER_CFG:0xFFFF
+-g multipin_wakeup:No
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:Yes
+-g DriveDone:No
+-g en_sw_gsr:No
+-g drive_awake:No
+-g sw_clk:Startupclk
+-g sw_gwe_cycle:5
+-g sw_gts_cycle:4
Index: papilioduo/papilioduo.xst
===================================================================
--- papilioduo/papilioduo.xst	(nonexistent)
+++ papilioduo/papilioduo.xst	(revision 325)
@@ -0,0 +1,52 @@
+set -tmpdir "xst/projnav.tmp"
+set -xsthdpdir "xst"
+run
+-ifn papilioduo.prj
+-ofn papilioduo
+-ofmt NGC
+-p xc6slx9-3-tqg144
+-top atari800core_papilioduo
+-opt_mode Speed
+-opt_level 1
+-power NO
+-iuc NO
+-keep_hierarchy No
+-netlist_hierarchy As_Optimized
+-rtlview Yes
+-glob_opt AllClockNets
+-read_cores YES
+-write_timing_constraints NO
+-cross_clock_analysis NO
+-hierarchy_separator /
+-bus_delimiter <>
+-case Maintain
+-slice_utilization_ratio 100
+-bram_utilization_ratio 100
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
+-fsm_extract YES -fsm_encoding Auto
+-safe_implementation No
+-fsm_style LUT
+-ram_extract Yes
+-ram_style Auto
+-rom_extract Yes
+-shreg_extract YES
+-rom_style Auto
+-auto_bram_packing NO
+-resource_sharing YES
+-async_to_sync NO
+-shreg_min_size 2
+-use_dsp48 Auto
+-iobuf YES
+-max_fanout 100000
+-bufg 16
+-register_duplication YES
+-register_balancing No
+-optimize_primitives NO
+-use_clock_enable Auto
+-use_sync_set Auto
+-use_sync_reset Auto
+-iob Auto
+-equivalent_register_removal YES
+-slice_utilization_ratio_maxmargin 5
Index: papilioduo/pll/_xmsgs/cg.xmsgs
===================================================================
--- papilioduo/pll/_xmsgs/cg.xmsgs	(nonexistent)
+++ papilioduo/pll/_xmsgs/cg.xmsgs	(revision 325)
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="sim" num="172" delta="old" >Generating IP...
+</msg>
+
+<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;pll&apos; already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+
+<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;pll&apos; already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+
+<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Component clk_wiz_v3_6 does not have a valid model name for VHDL synthesis</arg>
+</msg>
+
+<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
+</msg>
+
+<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
+</msg>
+
+</messages>
+
Index: papilioduo/pll/_xmsgs/pn_parser.xmsgs
===================================================================
--- papilioduo/pll/_xmsgs/pn_parser.xmsgs	(nonexistent)
+++ papilioduo/pll/_xmsgs/pn_parser.xmsgs	(revision 325)
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated   -->
+<!--     by the Xilinx ISE software.  Any direct editing or        -->
+<!--     changes made to this file may result in unpredictable     -->
+<!--     behavior or data corruption.  It is strongly advised that -->
+<!--     users do not edit the contents of this file.              -->
+<!--                                                               -->
+<!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.    -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;D:/Projects/Aeon Lite/cores/Atari_800/src/pll/pll.vhd&quot; into library work</arg>
+</msg>
+
+</messages>
+
Index: papilioduo/pll/coregen.cgp
===================================================================
--- papilioduo/pll/coregen.cgp	(nonexistent)
+++ papilioduo/pll/coregen.cgp	(revision 325)
@@ -0,0 +1,9 @@
+SET busformat = BusFormatAngleBracketNotRipped
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET package = tqg144
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
Index: papilioduo/pll/create_pll.tcl
===================================================================
--- papilioduo/pll/create_pll.tcl	(nonexistent)
+++ papilioduo/pll/create_pll.tcl	(revision 325)
@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator create command
+##
+
+proc findRtfPath { relativePath } {
+   set xilenv ""
+   if { [info exists ::env(XILINX) ] } {
+      if { [info exists ::env(MYXILINX)] } {
+         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+      } else {
+         set xilenv $::env(XILINX)
+      }
+   }
+   foreach path [ split $xilenv $::xilinx::path_sep ] {
+      set fullPath [ file join $path $relativePath ]
+      if { [ file exists $fullPath ] } {
+         return $fullPath
+      }
+   }
+   return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_create "xilinx.com:ip:clk_wiz:3.6" "pll" "Clocking Wizard" "Clocking Wizard (xilinx.com:ip:clk_wiz:3.6) generated by Project Navigator" xc6slx9-3tqg144 VHDL ]
+
+if { $result == 0 } {
+   puts "Core Generator create command completed successfully."
+} elseif { $result == 1 } {
+   puts "Core Generator create command failed."
+} elseif { $result == 3 || $result == 4 } {
+   # convert 'version check' result to real return range, bypassing any messages.
+   set result [ expr $result - 3 ]
+} else {
+   puts "Core Generator create cancelled."
+}
+exit $result
Index: papilioduo/pll/edit_pll.tcl
===================================================================
--- papilioduo/pll/edit_pll.tcl	(nonexistent)
+++ papilioduo/pll/edit_pll.tcl	(revision 325)
@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator edit command
+##
+
+proc findRtfPath { relativePath } {
+   set xilenv ""
+   if { [info exists ::env(XILINX) ] } {
+      if { [info exists ::env(MYXILINX)] } {
+         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+      } else {
+         set xilenv $::env(XILINX)
+      }
+   }
+   foreach path [ split $xilenv $::xilinx::path_sep ] {
+      set fullPath [ file join $path $relativePath ]
+      if { [ file exists $fullPath ] } {
+         return $fullPath
+      }
+   }
+   return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_edit "pll" xc6slx9-3tqg144 VHDL ]
+
+if { $result == 0 } {
+   puts "Core Generator edit command completed successfully."
+} elseif { $result == 1 } {
+   puts "Core Generator edit command failed."
+} elseif { $result == 3 || $result == 4 } {
+   # convert 'version check' result to real return range, bypassing any messages.
+   set result [ expr $result - 3 ]
+} else {
+   puts "Core Generator edit cancelled."
+}
+exit $result
Index: papilioduo/pll/pll/clk_wiz_v3_6_readme.txt
===================================================================
--- papilioduo/pll/pll/clk_wiz_v3_6_readme.txt	(nonexistent)
+++ papilioduo/pll/pll/clk_wiz_v3_6_readme.txt	(revision 325)
@@ -0,0 +1,184 @@
+CHANGE LOG for LogiCORE Clocking Wizard V3.6 
+
+                    Release Date: June 19, 2013
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+   http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+3. NEW FEATURE HISTORY 
+
+
+  3.1 ISE 
+  
+    - Spread Spectrum support for 7 series MMCME2
+
+    - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+      Resolved issue with example design becoming core top in planAhead
+
+      Resolved issue with Virtex6 MMCM instantiation for VHDL project
+      Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+06/19/2013  Xilinx, Inc.  3.6(Rev3)    ISE 14.6 support
+10/16/2012  Xilinx, Inc.  3.6(Rev2)    ISE 14.3 support
+07/25/2012  Xilinx, Inc.  3.6          ISE 14.2 support
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
Index: papilioduo/pll/pll/doc/clk_wiz_v3_6_readme.txt
===================================================================
--- papilioduo/pll/pll/doc/clk_wiz_v3_6_readme.txt	(nonexistent)
+++ papilioduo/pll/pll/doc/clk_wiz_v3_6_readme.txt	(revision 325)
@@ -0,0 +1,184 @@
+CHANGE LOG for LogiCORE Clocking Wizard V3.6 
+
+                    Release Date: June 19, 2013
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+   http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+3. NEW FEATURE HISTORY 
+
+
+  3.1 ISE 
+  
+    - Spread Spectrum support for 7 series MMCME2
+
+    - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+      Resolved issue with example design becoming core top in planAhead
+
+      Resolved issue with Virtex6 MMCM instantiation for VHDL project
+      Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+06/19/2013  Xilinx, Inc.  3.6(Rev3)    ISE 14.6 support
+10/16/2012  Xilinx, Inc.  3.6(Rev2)    ISE 14.3 support
+07/25/2012  Xilinx, Inc.  3.6          ISE 14.2 support
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
Index: papilioduo/pll/pll/doc/clk_wiz_v3_6_vinfo.html
===================================================================
--- papilioduo/pll/pll/doc/clk_wiz_v3_6_vinfo.html	(nonexistent)
+++ papilioduo/pll/pll/doc/clk_wiz_v3_6_vinfo.html	(revision 325)
@@ -0,0 +1,195 @@
+<HTML>
+<HEAD>
+<TITLE>clk_wiz_v3_6_vinfo</TITLE>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
+</HEAD>
+<BODY>
+<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
+CHANGE LOG for LogiCORE Clocking Wizard V3.6 
+
+                    Release Date: June 19, 2013
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
+
+For system requirements:
+
+   <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+   <A HREF="http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/">www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/</A>
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+3. NEW FEATURE HISTORY 
+
+
+  3.1 ISE 
+  
+    - Spread Spectrum support for 7 series MMCME2
+
+    - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+      Resolved issue with example design becoming core top in planAhead
+
+      Resolved issue with Virtex6 MMCM instantiation for VHDL project
+      Please refer to AR 50719 - <A HREF="http://www.xilinx.com/support/answers/50719.htm">www.xilinx.com/support/answers/50719.htm</A>
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+06/19/2013  Xilinx, Inc.  3.6(Rev3)    ISE 14.6 support
+10/16/2012  Xilinx, Inc.  3.6(Rev2)    ISE 14.3 support
+07/25/2012  Xilinx, Inc.  3.6          ISE 14.2 support
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
+</FONT>
+</PRE>
+</BODY>
+</HTML>
Index: papilioduo/pll/pll/doc/pg065_clk_wiz.pdf
===================================================================
Cannot display: file marked as a binary type.
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___________________________________________________________________
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Index: papilioduo/pll/pll/example_design/pll_exdes.ucf
===================================================================
--- papilioduo/pll/pll/example_design/pll_exdes.ucf	(nonexistent)
+++ papilioduo/pll/pll/example_design/pll_exdes.ucf	(revision 325)
@@ -0,0 +1,59 @@
+# file: pll_exdes.ucf
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.000 ns HIGH 50% INPUT_JITTER 200.0ps;
+
+
+# FALSE PATH constraints 
+PIN "COUNTER_RESET" TIG;
+
Index: papilioduo/pll/pll/example_design/pll_exdes.vhd
===================================================================
--- papilioduo/pll/pll/example_design/pll_exdes.vhd	(nonexistent)
+++ papilioduo/pll/pll/example_design/pll_exdes.vhd	(revision 325)
@@ -0,0 +1,198 @@
+-- file: pll_exdes.vhd
+-- 
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+
+------------------------------------------------------------------------------
+-- Clocking wizard example design
+------------------------------------------------------------------------------
+-- This example design instantiates the created clocking network, where each
+--   output clock drives a counter. The high bit of each counter is ported.
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity pll_exdes is
+generic (
+  TCQ               : in time := 100 ps);
+port
+ (-- Clock in ports
+  CLK_IN1           : in  std_logic;
+  -- Reset that only drives logic in example design
+  COUNTER_RESET     : in  std_logic;
+  CLK_OUT           : out std_logic_vector(2 downto 1) ;
+  -- High bits of counters driven by clocks
+  COUNT             : out std_logic_vector(2 downto 1);
+  -- Status and control signals
+  LOCKED            : out std_logic
+ );
+end pll_exdes;
+
+architecture xilinx of pll_exdes is
+
+  -- Parameters for the counters
+  ---------------------------------
+  -- Counter width
+  constant C_W        : integer := 16;
+
+  -- Number of counters
+  constant NUM_C      : integer := 2;
+  -- Array typedef
+  type ctrarr is array (1 to NUM_C) of std_logic_vector(C_W-1 downto 0);
+
+  -- When the clock goes out of lock, reset the counters
+  signal   locked_int : std_logic;
+  signal   reset_int  : std_logic                     := '0';
+  -- Declare the clocks and counters
+  signal   clk        : std_logic_vector(NUM_C downto 1);
+ 
+  signal   clk_int    : std_logic_vector(NUM_C downto 1);
+  signal   clk_n  : std_logic_vector(NUM_C downto 1);
+  signal   counter    : ctrarr := (( others => (others => '0')));
+  signal rst_sync : std_logic_vector(NUM_C downto 1);
+  signal rst_sync_int : std_logic_vector(NUM_C downto 1);
+  signal rst_sync_int1 : std_logic_vector(NUM_C downto 1);
+  signal rst_sync_int2 : std_logic_vector(NUM_C downto 1);
+
+
+component pll is
+port
+ (-- Clock in ports
+  CLKIN           : in     std_logic;
+  -- Clock out ports
+  CLKOUT          : out    std_logic;
+  CLKOUT2          : out    std_logic;
+  -- Status and control signals
+  LOCKED            : out    std_logic
+ );
+end component;
+
+begin
+  -- Alias output to internally used signal
+  LOCKED    <= locked_int;
+
+  -- When the clock goes out of lock, reset the counters
+  reset_int <= (not locked_int) or COUNTER_RESET;
+
+
+  counters_1: for count_gen in 1 to NUM_C generate begin
+ process (clk(count_gen), reset_int) begin
+   if (reset_int = '1') then
+       rst_sync(count_gen) <= '1';
+       rst_sync_int(count_gen) <= '1';
+       rst_sync_int1(count_gen) <= '1';
+       rst_sync_int2(count_gen) <= '1';
+   elsif (clk(count_gen) 'event and clk(count_gen)='1') then
+       rst_sync(count_gen) <= '0';
+       rst_sync_int(count_gen) <= rst_sync(count_gen);
+       rst_sync_int1(count_gen) <= rst_sync_int(count_gen);
+       rst_sync_int2(count_gen) <= rst_sync_int1(count_gen);
+   end if;
+ end process;
+end generate counters_1;
+
+
+  -- Instantiation of the clocking network
+  ----------------------------------------
+  clknetwork : pll
+  port map
+   (-- Clock in ports
+    CLKIN            => CLK_IN1,
+    -- Clock out ports
+    CLKOUT           => clk_int(1),
+    CLKOUT2           => clk_int(2),
+    -- Status and control signals
+    LOCKED             => locked_int);
+
+  gen_outclk_oddr: 
+  for clk_out_pins in 1 to NUM_C generate 
+  begin
+  clk_n(clk_out_pins) <= not clk(clk_out_pins);
+  clkout_oddr : ODDR2
+  port map
+   (Q  => CLK_OUT(clk_out_pins),
+    C0 => clk(clk_out_pins),
+    C1 => clk_n(clk_out_pins),
+    CE => '1',
+    D0 => '1',
+    D1 => '0',
+    R  => '0',
+    S  => '0');
+   end generate;
+
+  -- Connect the output clocks to the design
+  -------------------------------------------
+  clk(1) <= clk_int(1);
+  clk(2) <= clk_int(2);
+
+  -- Output clock sampling
+  -------------------------------------
+  counters: for count_gen in 1 to NUM_C generate begin
+    process (clk(count_gen), rst_sync_int2(count_gen)) begin
+        if (rst_sync_int2(count_gen) = '1') then
+          counter(count_gen) <= (others => '0') after TCQ;
+        elsif (rising_edge (clk(count_gen))) then
+          counter(count_gen) <= counter(count_gen) + 1 after TCQ;
+        end if;
+    end process;
+
+    -- alias the high bit of each counter to the corresponding
+    --   bit in the output bus
+    COUNT(count_gen) <= counter(count_gen)(C_W-1);
+
+  end generate counters;
+
+
+
+end xilinx;
Index: papilioduo/pll/pll/implement/implement.bat
===================================================================
--- papilioduo/pll/pll/implement/implement.bat	(nonexistent)
+++ papilioduo/pll/pll/implement/implement.bat	(revision 325)
@@ -0,0 +1,90 @@
+REM file: implement.bat
+REM 
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM 
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM 
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM 
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM 
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM 
+
+REM -----------------------------------------------------------------------------
+REM  Script to synthesize and implement the RTL provided for the clocking wizard
+REM -----------------------------------------------------------------------------
+
+REM Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+REM Copy unisim_comp.v file to results directory
+copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\
+
+REM Synthesize the Verilog Wrapper Files
+echo 'Synthesizing Clocking Wizard design with XST'
+xst -ifn xst.scr
+move pll_exdes.ngc results\
+
+REM  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\pll_exdes.ucf results\
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -uc pll_exdes.ucf pll_exdes
+
+echo 'Running map'
+map -timing -pr b pll_exdes -o mapped.ncd
+
+echo 'Running par'
+par -w mapped.ncd routed mapped.pcf
+
+echo 'Running trce'
+trce -e 10 routed -o routed mapped.pcf
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level model for the clocking wizard example design'
+netgen -ofmt vhdl -sim -tm pll_exdes -w routed.ncd routed.vhd
+cd ..
+
Index: papilioduo/pll/pll/implement/planAhead_ise.bat
===================================================================
--- papilioduo/pll/pll/implement/planAhead_ise.bat	(nonexistent)
+++ papilioduo/pll/pll/implement/planAhead_ise.bat	(revision 325)
@@ -0,0 +1,58 @@
+REM file: planAhead_ise.bat
+REM 
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM 
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM 
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM 
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM 
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM 
+
+REM-----------------------------------------------------------------------------
+REM Script to synthesize and implement the RTL provided for the clocking wizard
+REM-----------------------------------------------------------------------------
+
+del \f results
+mkdir results
+cd results
+
+planAhead -mode batch -source ..\planAhead_ise.tcl
Index: papilioduo/pll/pll/implement/planAhead_ise.tcl
===================================================================
--- papilioduo/pll/pll/implement/planAhead_ise.tcl	(nonexistent)
+++ papilioduo/pll/pll/implement/planAhead_ise.tcl	(revision 325)
@@ -0,0 +1,78 @@
+# file: planAhead_ise.tcl
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+set projDir [file dirname [info script]]
+set projName pll
+set topName pll_exdes
+set device xc6slx9tqg144-3
+
+create_project $projName $projDir/results/$projName -part $device
+
+set_property design_mode RTL [get_filesets sources_1]
+
+## Source files
+#set verilogSources [glob $srcDir/*.v]
+import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/pll_exdes.vhd
+import_files -fileset [get_filesets sources_1] -force -norecurse ../../../pll.vhd
+
+
+#UCF file
+import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/pll_exdes.ucf
+
+set_property top $topName [get_property srcset [current_run]]
+
+launch_runs -runs synth_1
+wait_on_run synth_1
+
+set_property add_step Bitgen [get_runs impl_1]
+launch_runs -runs impl_1
+wait_on_run impl_1
+
+
+
Index: papilioduo/pll/pll/implement/planAhead_rdn.sh
===================================================================
--- papilioduo/pll/pll/implement/planAhead_rdn.sh	(nonexistent)
+++ papilioduo/pll/pll/implement/planAhead_rdn.sh	(revision 325)
@@ -0,0 +1,57 @@
+#!/bin/sh
+# file: planAhead_rdn.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the XADC wizard
+#-----------------------------------------------------------------------------
+rm -rf results
+mkdir results
+cd results
+planAhead -mode batch -source ../planAhead_rdn.tcl
Index: papilioduo/pll/pll/implement/xst.scr
===================================================================
--- papilioduo/pll/pll/implement/xst.scr	(nonexistent)
+++ papilioduo/pll/pll/implement/xst.scr	(revision 325)
@@ -0,0 +1,9 @@
+run
+-ifmt MIXED
+-top pll_exdes
+-p xc6slx9-tqg144-3
+-ifn xst.prj
+-ofn pll_exdes
+-keep_hierarchy soft 
+-equivalent_register_removal no 
+-max_fanout 65535
Index: papilioduo/pll/pll/simulation/functional/simulate_isim.sh
===================================================================
--- papilioduo/pll/pll/simulation/functional/simulate_isim.sh	(nonexistent)
+++ papilioduo/pll/pll/simulation/functional/simulate_isim.sh	(revision 325)
@@ -0,0 +1,60 @@
+# file: simulate_isim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# nt64
+# create the project
+vhpcomp -work work ../../../pll.vhd
+vhpcomp -work work ../../example_design/pll_exdes.vhd
+vhpcomp -work work ../pll_tb.vhd
+
+# compile the project
+fuse work.pll_tb  -L unisim -o pll_isim.exe
+
+# run the simulation script
+./pll_isim.exe -gui -tclbatch simcmds.tcl
Index: papilioduo/pll/pll/simulation/functional/simulate_mti.sh
===================================================================
--- papilioduo/pll/pll/simulation/functional/simulate_mti.sh	(nonexistent)
+++ papilioduo/pll/pll/simulation/functional/simulate_mti.sh	(revision 325)
@@ -0,0 +1,60 @@
+#/bin/sh
+# file: simulate_mti.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vcom -work work ../../../pll.vhd
+vcom -work work ../../example_design/pll_exdes.vhd
+vcom -work work ../pll_tb.vhd
+
+# run the simulation
+vsim -c -t ps -voptargs="+acc" -L secureip -L unisim work.pll_tb 
Index: papilioduo/pll/pll/simulation/functional/wave.do
===================================================================
--- papilioduo/pll/pll/simulation/functional/wave.do	(nonexistent)
+++ papilioduo/pll/pll/simulation/functional/wave.do	(revision 325)
@@ -0,0 +1,58 @@
+# file: wave.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+add wave -noupdate -divider {Input clocks}
+add wave -noupdate -format Logic /pll_tb/CLK_IN1
+add wave -noupdate -divider {Output clocks}
+add wave -noupdate -format Literal -expand /pll_tb/dut/clk
+add wave -noupdate -divider Status/control
+add wave -noupdate -format Logic /pll_tb/LOCKED
+add wave -noupdate -divider Counters
+add wave -noupdate -format Literal -radix hexadecimal /pll_tb/COUNT
+add wave -noupdate -format Literal -radix hexadecimal -expand /pll_tb/dut/counter
Index: papilioduo/pll/pll/simulation/timing/pll_tb.vhd
===================================================================
--- papilioduo/pll/pll/simulation/timing/pll_tb.vhd	(nonexistent)
+++ papilioduo/pll/pll/simulation/timing/pll_tb.vhd	(revision 325)
@@ -0,0 +1,214 @@
+-- file: pll_tb.vhd
+-- 
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+
+------------------------------------------------------------------------------
+-- Clocking wizard demonstration testbench
+------------------------------------------------------------------------------
+-- This demonstration testbench instantiates the example design for the 
+--   clocking wizard. Input clocks are toggled, which cause the clocking
+--   network to lock and the counters to increment.
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+
+library std;
+use std.textio.all;
+
+library work;
+use work.all;
+
+entity pll_tb is
+end pll_tb;
+
+architecture test of pll_tb is
+
+  -- Clock to Q delay of 100 ps
+  constant TCQ               : time := 100 ps;
+  -- timescale is 1ps
+  constant ONE_NS      : time := 1 ns;
+  -- how many cycles to run
+  constant COUNT_PHASE : integer := 1024 + 1;
+
+
+  -- we'll be using the period in many locations
+  constant PER1        : time := 20.000 ns;
+
+
+  -- Declare the input clock signals
+  signal CLK_IN1       : std_logic := '1';
+  -- The high bits of the sampling counters
+  signal COUNT         : std_logic_vector(2 downto 1);
+  -- Status and control signals
+  signal LOCKED        : std_logic;
+  signal COUNTER_RESET : std_logic := '0';
+  signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
+--  signal defined to stop mti simulation without severity failure in the report
+  signal end_of_sim : std_logic := '0';
+  signal CLK_OUT : std_logic_vector(2 downto 1);
+--Freq Check using the M & D values setting and actual Frequency generated
+
+component pll_exdes
+port
+ (-- Clock in ports
+  CLK_IN1           : in  std_logic;
+  -- Reset that only drives logic in example design
+  COUNTER_RESET     : in  std_logic;
+  CLK_OUT           : out std_logic_vector(2 downto 1) ;
+  -- High bits of counters driven by clocks
+  COUNT             : out std_logic_vector(2 downto 1);
+  -- Status and control signals
+  LOCKED            : out std_logic
+ );
+end component;
+
+begin
+
+  -- Input clock generation
+  --------------------------------------
+  process begin
+    CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
+  end process;
+
+  -- Test sequence
+  process 
+
+    procedure simtimeprint is
+      variable outline : line;
+    begin
+      write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
+      write(outline, NOW/PER1);
+      write(outline, string'(" ns"));
+      writeline(output,outline);
+    end simtimeprint;
+
+    procedure simfreqprint (period : time; clk_num : integer) is
+       variable outputline : LINE;
+       variable str1 : string(1 to 16);
+       variable str2 : integer;
+       variable str3 : string(1 to 2);
+       variable str4 : integer;
+       variable str5 : string(1 to 4);
+    begin
+       str1 := "Freq of CLK_OUT(";
+       str2 :=  clk_num;
+       str3 :=  ") ";
+       str4 :=  1000000 ps/period ;
+       str5 :=  " MHz" ;
+       write(outputline, str1 );
+       write(outputline, str2);
+       write(outputline, str3);
+       write(outputline, str4);
+       write(outputline, str5);
+       writeline(output, outputline);
+    end simfreqprint;
+
+  begin
+   report "Timing checks are not valid" severity note;
+    wait until LOCKED = '1';
+    wait for (PER1*20);
+    COUNTER_RESET <= '1';
+    wait for (PER1*19.5);
+    COUNTER_RESET <= '0';
+    wait for (PER1*1);
+    report "Timing checks are valid" severity note;
+    wait for (PER1*COUNT_PHASE);
+
+
+    simtimeprint;
+    end_of_sim <= '1';
+    wait for 1 ps;
+    report "Simulation Stopped." severity failure;
+    wait;
+  end process;
+
+ process (CLK_IN1)
+    procedure simtimeprint is
+      variable outline : line;
+    begin
+      write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
+      write(outline, NOW/PER1);
+      write(outline, string'(" ns"));
+      writeline(output,outline);
+    end simtimeprint;
+   begin
+     if (CLK_IN1'event and CLK_IN1='1') then
+         timeout_counter <= timeout_counter + '1';
+       if (timeout_counter = "10000000000000") then
+          if (LOCKED /= '1') then
+            simtimeprint;
+            report "NO LOCK signal" severity failure;
+          end if;
+       end if;
+     end if;
+ end process; 
+
+
+  -- Instantiation of the example design containing the clock
+  --    network and sampling counters
+  -----------------------------------------------------------
+  dut : pll_exdes
+  port map
+   (-- Clock in ports
+    CLK_IN1            => CLK_IN1,
+    -- Reset for logic in example design
+    COUNTER_RESET      => COUNTER_RESET,
+    CLK_OUT            => CLK_OUT,
+    -- High bits of the counters
+    COUNT              => COUNT,
+    -- Status and control signals
+    LOCKED             => LOCKED);
+
+-- Freq Check 
+
+end test;
Index: papilioduo/pll/pll/example_design/pll_exdes.xdc
===================================================================
--- papilioduo/pll/pll/example_design/pll_exdes.xdc	(nonexistent)
+++ papilioduo/pll/pll/example_design/pll_exdes.xdc	(revision 325)
@@ -0,0 +1,68 @@
+# file: pll_exdes.xdc
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+create_clock -name CLK_IN1 -period 20.000 [get_ports CLK_IN1]
+set_propagated_clock CLK_IN1
+set_input_jitter CLK_IN1 0.2
+
+# FALSE PATH constraint added on COUNTER_RESET 
+set_false_path -from [get_ports "COUNTER_RESET"]
+
+# Derived clock periods. These are commented out because they are 
+#   automatically propogated by the tools
+# However, if you'd like to use them for module level testing, you 
+#   can copy them into your module level timing checks
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
Index: papilioduo/pll/pll/implement/implement.sh
===================================================================
--- papilioduo/pll/pll/implement/implement.sh	(nonexistent)
+++ papilioduo/pll/pll/implement/implement.sh	(revision 325)
@@ -0,0 +1,91 @@
+#!/bin/sh
+# file: implement.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the clocking wizard
+#-----------------------------------------------------------------------------
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+# Copy unisim_comp.v file to results directory
+cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
+
+# Synthesize the Verilog Wrapper Files
+echo 'Synthesizing Clocking Wizard design with XST'
+xst -ifn xst.scr
+mv pll_exdes.ngc results/
+
+#  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/pll_exdes.ucf results/
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -uc pll_exdes.ucf pll_exdes
+
+echo 'Running map'
+map -timing pll_exdes -o mapped.ncd
+
+echo 'Running par'
+par -w mapped.ncd routed mapped.pcf
+
+echo 'Running trce'
+trce -e 10 routed -o routed mapped.pcf
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level model for the clocking wizard example design'
+netgen -ofmt vhdl -sim -tm pll_exdes -w routed.ncd routed.vhd
+
+cd ..
Index: papilioduo/pll/pll/implement/planAhead_ise.sh
===================================================================
--- papilioduo/pll/pll/implement/planAhead_ise.sh	(nonexistent)
+++ papilioduo/pll/pll/implement/planAhead_ise.sh	(revision 325)
@@ -0,0 +1,59 @@
+#!/bin/sh
+# file: planAhead_ise.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the clocking wizard
+#-----------------------------------------------------------------------------
+
+rm -rf results
+mkdir results
+cd results
+
+planAhead -mode batch -source ../planAhead_ise.tcl
Index: papilioduo/pll/pll/implement/planAhead_rdn.bat
===================================================================
--- papilioduo/pll/pll/implement/planAhead_rdn.bat	(nonexistent)
+++ papilioduo/pll/pll/implement/planAhead_rdn.bat	(revision 325)
@@ -0,0 +1,58 @@
+REM file: planAhead_rdn.sh
+REM 
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM 
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM 
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM 
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM 
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM 
+
+REM-----------------------------------------------------------------------------
+REM Script to synthesize and implement the RTL provided for the XADC wizard
+REM-----------------------------------------------------------------------------
+
+del \f results
+mkdir results
+cd results
+
+planAhead -mode batch -source ..\planAhead_rdn.tcl
Index: papilioduo/pll/pll/implement/planAhead_rdn.tcl
===================================================================
--- papilioduo/pll/pll/implement/planAhead_rdn.tcl	(nonexistent)
+++ papilioduo/pll/pll/implement/planAhead_rdn.tcl	(revision 325)
@@ -0,0 +1,69 @@
+# file : planAhead_rdn.tcl
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+set device xc6slx9tqg144-3
+set projName pll
+set design pll
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module pll_exdes
+set_property top pll_exdes [get_property srcset [current_run]]
+add_files -norecurse {../../../pll.vhd}
+add_files -norecurse {../../example_design/pll_exdes.vhd}
+import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/pll_exdes.xdc}
+synth_design
+opt_design 
+place_design 
+route_design 
+write_sdf -rename_top_module pll_exdes -file routed.sdf 
+write_vhdl -file routed.vhd
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file report.drc
+write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit
Index: papilioduo/pll/pll/simulation/functional/simcmds.tcl
===================================================================
--- papilioduo/pll/pll/simulation/functional/simcmds.tcl	(nonexistent)
+++ papilioduo/pll/pll/simulation/functional/simcmds.tcl	(revision 325)
@@ -0,0 +1,8 @@
+# file: simcmds.tcl
+
+# create the simulation script
+vcd dumpfile isim.vcd
+vcd dumpvars -m /pll_tb -l 0
+wave add /
+run 50000ns
+quit
Index: papilioduo/pll/pll/simulation/functional/simulate_mti.bat
===================================================================
--- papilioduo/pll/pll/simulation/functional/simulate_mti.bat	(nonexistent)
+++ papilioduo/pll/pll/simulation/functional/simulate_mti.bat	(revision 325)
@@ -0,0 +1,60 @@
+REM file: simulate_mti.bat
+REM  
+REM  (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM  
+REM  This file contains confidential and proprietary information
+REM  of Xilinx, Inc. and is protected under U.S. and
+REM  international copyright and other intellectual property
+REM  laws.
+REM  
+REM  DISCLAIMER
+REM  This disclaimer is not a license and does not grant any
+REM  rights to the materials distributed herewith. Except as
+REM  otherwise provided in a valid license issued to you by
+REM  Xilinx, and to the maximum extent permitted by applicable
+REM  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM  (2) Xilinx shall not be liable (whether in contract or tort,
+REM  including negligence, or under any other theory of
+REM  liability) for any loss or damage of any kind or nature
+REM  related to, arising under or in connection with these
+REM  materials, including for any direct, or any indirect,
+REM  special, incidental, or consequential loss or damage
+REM  (including loss of data, profits, goodwill, or any type of
+REM  loss or damage suffered as a result of any action brought
+REM  by a third party) even if such damage or loss was
+REM  reasonably foreseeable or Xilinx had been advised of the
+REM  possibility of the same.
+REM  
+REM  CRITICAL APPLICATIONS
+REM  Xilinx products are not designed or intended to be fail-
+REM  safe, or for use in any application requiring fail-safe
+REM  performance, such as life-support or safety devices or
+REM  systems, Class III medical devices, nuclear facilities,
+REM  applications related to the deployment of airbags, or any
+REM  other applications that could lead to death, personal
+REM  injury, or severe property or environmental damage
+REM  (individually and collectively, "Critical
+REM  Applications"). Customer assumes the sole risk and
+REM  liability of any use of Xilinx products in Critical
+REM  Applications, subject only to applicable laws and
+REM  regulations governing limitations on product liability.
+REM  
+REM  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM  PART OF THIS FILE AT ALL TIMES.
+REM  
+
+REM set up the working directory
+vlib work
+
+REM compile all of the files
+vcom -work work ..\..\..\pll.vhd
+vcom -work work ..\..\example_design\pll_exdes.vhd
+vcom -work work ..\pll_tb.vhd
+
+REM run the simulation
+vsim -c -t ps -voptargs="+acc" -L secureip -L unisim work.pll_tb 
+
Index: papilioduo/pll/pll/simulation/functional/simulate_ncsim.sh
===================================================================
--- papilioduo/pll/pll/simulation/functional/simulate_ncsim.sh	(nonexistent)
+++ papilioduo/pll/pll/simulation/functional/simulate_ncsim.sh	(revision 325)
@@ -0,0 +1,61 @@
+#/bin/sh
+# file: simulate_ncsim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+mkdir work
+
+# compile all of the files
+ncvhdl -v93 -work work ../../../pll.vhd
+ncvhdl -v93 -work work ../../example_design/pll_exdes.vhd
+ncvhdl -v93 -work work ../pll_tb.vhd
+
+# elaborate and run the simulation
+ncelab -work work -access +wc work.pll_tb 
+ncsim -input  "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.pll_tb
Index: papilioduo/pll/pll/simulation/functional/wave.sv
===================================================================
--- papilioduo/pll/pll/simulation/functional/wave.sv	(nonexistent)
+++ papilioduo/pll/pll/simulation/functional/wave.sv	(revision 325)
@@ -0,0 +1,119 @@
+# file: wave.sv
+# 
+# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# Get the windows set up
+#
+if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} {
+    window geometry "Design Browser 1" 1054x819+536+322
+}
+window target "Design Browser 1" on
+browser using {Design Browser 1}
+browser set \
+    -scope nc::pll_tb
+browser yview see nc::pll_tb
+browser timecontrol set -lock 0
+
+if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} {
+    window geometry "Waveform 1" 1010x600+0+541
+}
+window target "Waveform 1" on
+waveform using {Waveform 1}
+waveform sidebar visibility partial
+waveform set \
+    -primarycursor TimeA \
+    -signalnames name \
+    -signalwidth 175 \
+    -units ns \
+    -valuewidth 75
+cursor set -using TimeA -time 0
+waveform baseline set -time 0
+waveform xview limits 0 20000n
+
+#
+# Define signal groups
+#
+catch {group new -name {Output clocks} -overlay 0}
+catch {group new -name {Status/control} -overlay 0}
+catch {group new -name {Counters} -overlay 0}
+
+set id [waveform add -signals [list {nc::pll_tb.CLK_IN1}]]
+
+group using {Output clocks}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+    {pll_tb.dut.clk[1]} \
+    {pll_tb.dut.clk[2]} 
+group using {Counters}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+    {pll_tb.dut.counter[1]} \
+    {pll_tb.dut.counter[2]} 
+group using {Status/control}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+   {nc::pll_tb.LOCKED}
+
+
+set id [waveform add -signals [list {nc::pll_tb.COUNT} ]]
+
+set id [waveform add -signals [list {nc::pll_tb.test_phase} ]]
+waveform format $id -radix %a
+
+set groupId [waveform add -groups {{Input clocks}}]
+set groupId [waveform add -groups {{Output clocks}}]
+set groupId [waveform add -groups {{Status/control}}]
+set groupId [waveform add -groups {{Counters}}]
Index: papilioduo/pll/pll/simulation/timing/sdf_cmd_file
===================================================================
--- papilioduo/pll/pll/simulation/timing/sdf_cmd_file	(nonexistent)
+++ papilioduo/pll/pll/simulation/timing/sdf_cmd_file	(revision 325)
@@ -0,0 +1,2 @@
+COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X",
+SCOPE = :dut;
Index: papilioduo/pll/pll/simulation/functional/simulate_mti.do
===================================================================
--- papilioduo/pll/pll/simulation/functional/simulate_mti.do	(nonexistent)
+++ papilioduo/pll/pll/simulation/functional/simulate_mti.do	(revision 325)
@@ -0,0 +1,65 @@
+# file: simulate_mti.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vcom -work work ../../../pll.vhd
+vcom -work work ../../example_design/pll_exdes.vhd
+vcom -work work ../pll_tb.vhd
+
+# run the simulation
+vsim  -t ps -voptargs="+acc" -L unisim work.pll_tb 
+do wave.do
+when {end_of_sim} {echo "End of Simulation"; stop} 
+log pll_tb/dut/counter
+log -r /*
+run 50000ns
Index: papilioduo/pll/pll/simulation/functional/simulate_vcs.sh
===================================================================
--- papilioduo/pll/pll/simulation/functional/simulate_vcs.sh	(nonexistent)
+++ papilioduo/pll/pll/simulation/functional/simulate_vcs.sh	(revision 325)
@@ -0,0 +1,70 @@
+#!/bin/sh
+# file: simulate_vcs.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# remove old files
+rm -rf simv* csrc DVEfiles AN.DB 
+
+# compile all of the files
+# Note that -sverilog is not strictly required- You can
+#   remove the -sverilog if you change the type of the
+#   localparam for the periods in the testbench file to 
+#   [63:0] from time
+vhdlan -xlrm ../../../pll.vhd \
+      ../../example_design/pll_exdes.vhd \
+      ../pll_tb.vhd
+
+# prepare the simulation 
+vcs +vcs+lic+wait -xlrm -debug pll_tb
+
+# run the simulation
+./simv -xlrm -ucli -i ucli_commands.key
+
+# launch the viewer
+#dve -vpd vcdplus.vpd -session vcs_session.tcl
Index: papilioduo/pll/pll/simulation/pll_tb.vhd
===================================================================
--- papilioduo/pll/pll/simulation/pll_tb.vhd	(nonexistent)
+++ papilioduo/pll/pll/simulation/pll_tb.vhd	(revision 325)
@@ -0,0 +1,191 @@
+-- file: pll_tb.vhd
+-- 
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+
+------------------------------------------------------------------------------
+-- Clocking wizard demonstration testbench
+------------------------------------------------------------------------------
+-- This demonstration testbench instantiates the example design for the 
+--   clocking wizard. Input clocks are toggled, which cause the clocking
+--   network to lock and the counters to increment.
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+
+library std;
+use std.textio.all;
+
+library work;
+use work.all;
+
+entity pll_tb is
+end pll_tb;
+
+architecture test of pll_tb is
+
+  -- Clock to Q delay of 100 ps
+  constant TCQ               : time := 100 ps;
+  -- timescale is 1ps
+  constant ONE_NS      : time := 1 ns;
+  -- how many cycles to run
+  constant COUNT_PHASE : integer := 1024 + 1;
+
+
+  -- we'll be using the period in many locations
+  constant PER1        : time := 20.000 ns;
+
+
+  -- Declare the input clock signals
+  signal CLK_IN1       : std_logic := '1';
+  -- The high bits of the sampling counters
+  signal COUNT         : std_logic_vector(2 downto 1);
+  -- Status and control signals
+  signal LOCKED        : std_logic;
+  signal COUNTER_RESET : std_logic := '0';
+--  signal defined to stop mti simulation without severity failure in the report
+  signal end_of_sim : std_logic := '0';
+  signal CLK_OUT : std_logic_vector(2 downto 1);
+--Freq Check using the M & D values setting and actual Frequency generated
+
+component pll_exdes
+generic (
+  TCQ               : in time := 100 ps);
+port
+ (-- Clock in ports
+  CLK_IN1           : in  std_logic;
+  -- Reset that only drives logic in example design
+  COUNTER_RESET     : in  std_logic;
+  CLK_OUT           : out std_logic_vector(2 downto 1) ;
+  -- High bits of counters driven by clocks
+  COUNT             : out std_logic_vector(2 downto 1);
+  -- Status and control signals
+  LOCKED            : out std_logic
+ );
+end component;
+
+begin
+
+  -- Input clock generation
+  --------------------------------------
+  process begin
+    CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
+  end process;
+
+  -- Test sequence
+  process 
+
+    procedure simtimeprint is
+      variable outline : line;
+    begin
+      write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
+      write(outline, NOW/PER1);
+      write(outline, string'(" ns"));
+      writeline(output,outline);
+    end simtimeprint;
+
+    procedure simfreqprint (period : time; clk_num : integer) is
+       variable outputline : LINE;
+       variable str1 : string(1 to 16);
+       variable str2 : integer;
+       variable str3 : string(1 to 2);
+       variable str4 : integer;
+       variable str5 : string(1 to 4);
+    begin
+       str1 := "Freq of CLK_OUT(";
+       str2 :=  clk_num;
+       str3 :=  ") ";
+       str4 :=  1000000 ps/period ;
+       str5 :=  " MHz" ;
+       write(outputline, str1 );
+       write(outputline, str2);
+       write(outputline, str3);
+       write(outputline, str4);
+       write(outputline, str5);
+       writeline(output, outputline);
+    end simfreqprint;
+
+  begin
+    wait until LOCKED = '1';
+    COUNTER_RESET <= '1';
+    wait for (PER1*20);
+    COUNTER_RESET <= '0';
+    wait for (PER1*COUNT_PHASE);
+
+
+    simtimeprint;
+    end_of_sim <= '1';
+    wait for 1 ps;
+    report "Simulation Stopped." severity failure;
+    wait;
+  end process;
+
+  -- Instantiation of the example design containing the clock
+  --    network and sampling counters
+  -----------------------------------------------------------
+  dut : pll_exdes
+  generic map (
+    TCQ                => TCQ)
+  port map
+   (-- Clock in ports
+    CLK_IN1            => CLK_IN1,
+    -- Reset for logic in example design
+    COUNTER_RESET      => COUNTER_RESET,
+    CLK_OUT            => CLK_OUT,
+    -- High bits of the counters
+    COUNT              => COUNT,
+    -- Status and control signals
+    LOCKED             => LOCKED);
+
+-- Freq Check 
+
+end test;
Index: papilioduo/pll/pll/simulation/timing/simcmds.tcl
===================================================================
--- papilioduo/pll/pll/simulation/timing/simcmds.tcl	(nonexistent)
+++ papilioduo/pll/pll/simulation/timing/simcmds.tcl	(revision 325)
@@ -0,0 +1,9 @@
+# file: simcmds.tcl
+
+# create the simulation script
+vcd dumpfile isim.vcd
+vcd dumpvars -m /pll_tb -l 0
+wave add /
+run 50000ns
+quit
+
Index: papilioduo/pll/pll/simulation/timing/simulate_mti.do
===================================================================
--- papilioduo/pll/pll/simulation/timing/simulate_mti.do	(nonexistent)
+++ papilioduo/pll/pll/simulation/timing/simulate_mti.do	(revision 325)
@@ -0,0 +1,65 @@
+# file: simulate_mti.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vcom -work work ../../implement/results/routed.vhd
+vcom -work work pll_tb.vhd
+
+# run the simulation
+vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprim -sdfmax pll_tb/dut=../../implement/results/routed.sdf +no_notifier work.pll_tb 
+when {end_of_sim} {echo "End of Simulation"; stop} 
+#do wave.do
+#log -r /*
+run 50000ns
+
+
Index: papilioduo/pll/pll/simulation/timing/ucli_commands.key
===================================================================
--- papilioduo/pll/pll/simulation/timing/ucli_commands.key	(nonexistent)
+++ papilioduo/pll/pll/simulation/timing/ucli_commands.key	(revision 325)
@@ -0,0 +1,3 @@
+
+run 50000ns
+quit
Index: papilioduo/pll/pll/simulation/timing/simulate_mti.bat
===================================================================
--- papilioduo/pll/pll/simulation/timing/simulate_mti.bat	(nonexistent)
+++ papilioduo/pll/pll/simulation/timing/simulate_mti.bat	(revision 325)
@@ -0,0 +1,58 @@
+REM file: simulate_mti.bat
+REM  
+REM  (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM  
+REM  This file contains confidential and proprietary information
+REM  of Xilinx, Inc. and is protected under U.S. and
+REM  international copyright and other intellectual property
+REM  laws.
+REM  
+REM  DISCLAIMER
+REM  This disclaimer is not a license and does not grant any
+REM  rights to the materials distributed herewith. Except as
+REM  otherwise provided in a valid license issued to you by
+REM  Xilinx, and to the maximum extent permitted by applicable
+REM  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM  (2) Xilinx shall not be liable (whether in contract or tort,
+REM  including negligence, or under any other theory of
+REM  liability) for any loss or damage of any kind or nature
+REM  related to, arising under or in connection with these
+REM  materials, including for any direct, or any indirect,
+REM  special, incidental, or consequential loss or damage
+REM  (including loss of data, profits, goodwill, or any type of
+REM  loss or damage suffered as a result of any action brought
+REM  by a third party) even if such damage or loss was
+REM  reasonably foreseeable or Xilinx had been advised of the
+REM  possibility of the same.
+REM  
+REM  CRITICAL APPLICATIONS
+REM  Xilinx products are not designed or intended to be fail-
+REM  safe, or for use in any application requiring fail-safe
+REM  performance, such as life-support or safety devices or
+REM  systems, Class III medical devices, nuclear facilities,
+REM  applications related to the deployment of airbags, or any
+REM  other applications that could lead to death, personal
+REM  injury, or severe property or environmental damage
+REM  (individually and collectively, "Critical
+REM  Applications"). Customer assumes the sole risk and
+REM  liability of any use of Xilinx products in Critical
+REM  Applications, subject only to applicable laws and
+REM  regulations governing limitations on product liability.
+REM  
+REM  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM  PART OF THIS FILE AT ALL TIMES.
+REM  
+# set up the working directory
+set work work
+vlib work
+
+REM compile all of the files
+vcom -work work ..\..\implement\results\routed.vhd
+vcom -work work pll_tb.vhd
+
+REM run the simulation
+vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprim -sdfmax pll_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.pll_tb 
Index: papilioduo/pll/pll/simulation/timing/simulate_vcs.sh
===================================================================
--- papilioduo/pll/pll/simulation/timing/simulate_vcs.sh	(nonexistent)
+++ papilioduo/pll/pll/simulation/timing/simulate_vcs.sh	(revision 325)
@@ -0,0 +1,70 @@
+#!/bin/sh
+# file: simulate_vcs.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+
+# remove old files
+rm -rf simv* csrc DVEfiles AN.DB 
+
+# compile all of the files
+# Note that -sverilog is not strictly required- You can
+#   remove the -sverilog if you change the type of the
+#   localparam for the periods in the testbench file to 
+#   [63:0] from time
+vhdlan -xlrm ../../implement/results/routed.vhd \
+      pll_tb.vhd
+
+# prepare the simulation 
+vcs +vcs+lic+wait -xlrm -sdf max:pll_exdes:../../implement/results/routed.sdf -debug pll_tb.vhd ../../implement/results/routed.vhd
+
+# run the simulation
+./simv -xlrm -ucli -i ucli_commands.key
+
+# launch the viewer
+#dve -vpd vcdplus.vpd -session vcs_session.tcl
Index: papilioduo/pll/pll.asy
===================================================================
--- papilioduo/pll/pll.asy	(nonexistent)
+++ papilioduo/pll/pll.asy	(revision 325)
@@ -0,0 +1,21 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 pll
+RECTANGLE Normal 32 32 576 1088
+LINE Normal 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName clk_in1
+PINATTR Polarity IN
+LINE Normal 608 80 576 80
+PIN 608 80 RIGHT 36
+PINATTR PinName clk_out1
+PINATTR Polarity OUT
+LINE Normal 608 176 576 176
+PIN 608 176 RIGHT 36
+PINATTR PinName clk_out2
+PINATTR Polarity OUT
+LINE Normal 608 976 576 976
+PIN 608 976 RIGHT 36
+PINATTR PinName locked
+PINATTR Polarity OUT
+
Index: papilioduo/pll/pll.ucf
===================================================================
--- papilioduo/pll/pll.ucf	(nonexistent)
+++ papilioduo/pll/pll.ucf	(revision 325)
@@ -0,0 +1,58 @@
+# file: pll.ucf
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.000 ns HIGH 50% INPUT_JITTER 200.0ps;
+
+
+# FALSE PATH constraints 
+
Index: papilioduo/pll/pll.xdc
===================================================================
--- papilioduo/pll/pll.xdc	(nonexistent)
+++ papilioduo/pll/pll.xdc	(revision 325)
@@ -0,0 +1,66 @@
+# file: pll.xdc
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+create_clock -name CLK_IN1 -period 20.000 [get_ports CLK_IN1]
+set_propagated_clock CLK_IN1
+set_input_jitter CLK_IN1 0.2
+
+
+# Derived clock periods. These are commented out because they are 
+#   automatically propogated by the tools
+# However, if you'd like to use them for module level testing, you 
+#   can copy them into your module level timing checks
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
Index: papilioduo/sram.vhdl
===================================================================
--- papilioduo/sram.vhdl	(nonexistent)
+++ papilioduo/sram.vhdl	(revision 325)
@@ -0,0 +1,104 @@
+---------------------------------------------------------------------------
+-- (c) 2013,2015 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY sram IS
+PORT 
+( 
+	ADDRESS : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
+	DIN : IN STD_LOGIC_vector(7 downto 0);
+	WREN : IN STD_LOGIC;
+	
+	clk : in std_logic;
+	reset_n : in std_logic;
+	
+	request : in std_logic;
+	
+	-- SRAM interface
+	SRAM_ADDR: OUT STD_LOGIC_VECTOR(17 downto 0);
+	SRAM_CE_N: OUT STD_LOGIC;
+	SRAM_OE_N: OUT STD_LOGIC;
+	SRAM_WE_N: OUT STD_LOGIC;
+
+	SRAM_LB_N: OUT STD_LOGIC;
+	SRAM_UB_N: OUT STD_LOGIC;
+	
+	SRAM_DQ: INOUT STD_LOGIC_VECTOR(7 downto 0);
+	
+	-- Provide data to system
+	DOUT : OUT STD_LOGIC_VECTOR(15 downto 0);
+	complete : out std_logic
+);
+
+END sram;
+
+-- TODO, implement 32-bit accesses in two cycles
+
+-- first cycle, capture inputs
+-- second cycle, sram access
+ARCHITECTURE slow OF sram IS
+	signal oe_n_next : std_logic;
+	signal oe_n_reg : std_logic;
+	
+	signal we_n_next : std_logic;
+	signal we_n_reg : std_logic;	
+	
+	signal data_next : std_logic_vector(7 downto 0);
+	signal data_reg : std_logic_vector(7 downto 0);
+	
+	signal request_next : std_logic;
+	signal request_reg : std_logic;
+BEGIN
+	-- registers
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			oe_n_reg <= '1';
+			we_n_reg <= '1';
+			data_reg <= (others=>'0');
+			request_reg <= '0';
+		elsif (clk'event and clk='1') then
+			oe_n_reg <= oe_n_next;
+			we_n_reg <= we_n_next;
+			data_reg <= data_next;
+			request_reg <= request_next;
+		end if;
+	end process;
+
+	-- next state
+	process(din,wren,request,request_reg)
+	begin		
+		data_next <= din;
+		request_next <= '0';
+		
+		oe_n_next <= '0';
+		we_n_next <= '1';
+		
+		if (request = '1') then
+			-- on second cycle do write - address/data stable by now guaranteed (normal timequest...)
+			oe_n_next <= wren;
+			we_n_next <= not(wren);		
+			request_next <= '1';
+		end if;
+	end process;
+	
+	-- output
+	SRAM_ADDR <= address;
+	SRAM_CE_N <= '0';
+	SRAM_OE_N <= oe_n_reg;
+	SRAM_WE_N <= we_n_reg;
+	SRAM_DQ <= data_reg when we_n_reg = '0' else (others=>'Z');
+
+	DOUT <= SRAM_DQ;
+			
+	complete <= request_reg;		
+		
+	--GPIO <= (others=>'0');
+END slow;
+
Index: papilioduo/pll/pll/simulation/timing/simulate_isim.sh
===================================================================
--- papilioduo/pll/pll/simulation/timing/simulate_isim.sh	(nonexistent)
+++ papilioduo/pll/pll/simulation/timing/simulate_isim.sh	(revision 325)
@@ -0,0 +1,61 @@
+# file: simulate_isim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# create the project
+vhpcomp -work work ../../implement/results/routed.vhd
+vhpcomp -work work pll_tb.vhd
+
+# compile the project
+fuse work.pll_tb  -L secureip -L simprim -o pll_isim.exe
+
+# run the simulation script
+./pll_isim.exe -tclbatch simcmds.tcl -sdfmax /pll_tb/dut=../../implement/results/routed.sdf
+
+# run the simulation script
+#./pll_isim.exe -gui -tclbatch simcmds.tcl
Index: papilioduo/pll/pll/simulation/timing/simulate_ncsim.sh
===================================================================
--- papilioduo/pll/pll/simulation/timing/simulate_ncsim.sh	(nonexistent)
+++ papilioduo/pll/pll/simulation/timing/simulate_ncsim.sh	(revision 325)
@@ -0,0 +1,63 @@
+#!/bin/sh
+# file: simulate_ncsim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+mkdir work
+
+# compile all of the files
+ncvhdl -v93 -work work ../../implement/results/routed.vhd
+ncvhdl -v93 -work work pll_tb.vhd
+
+# elaborate and run the simulation
+ncsdfc ../../implement/results/routed.sdf
+
+ncelab -work work -access +wc -pulse_r 10 -nonotifier work.pll_tb -sdf_cmd_file sdf_cmd_file
+ncsim -input  "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.pll_tb
+
Index: papilioduo/pll/pll/simulation/timing/wave.do
===================================================================
--- papilioduo/pll/pll/simulation/timing/wave.do	(nonexistent)
+++ papilioduo/pll/pll/simulation/timing/wave.do	(revision 325)
@@ -0,0 +1,74 @@
+# file: wave.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider {Input clocks}
+add wave -noupdate /pll_tb/clk_in1
+add wave -noupdate -divider {Output clocks}
+add wave -noupdate /pll_tb/clk_in1
+add wave -noupdate /pll_tb/count
+add wave -noupdate /pll_tb/counter_reset
+add wave -noupdate /pll_tb/locked
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {3223025 ps} 0}
+configure wave -namecolwidth 238
+configure wave -valuecolwidth 107
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
Index: papilioduo/pll/pll.sym
===================================================================
--- papilioduo/pll/pll.sym	(nonexistent)
+++ papilioduo/pll/pll.sym	(revision 325)
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="pll">
+    <symboltype>BLOCK</symboltype>
+    <timestamp>2014-7-23T19:14:8</timestamp>
+    <pin polarity="Input" x="0" y="80" name="clk_in1" />
+    <pin polarity="Output" x="608" y="80" name="clk_out1" />
+    <pin polarity="Output" x="608" y="176" name="clk_out2" />
+    <pin polarity="Output" x="608" y="976" name="locked" />
+    <graph>
+        <text style="fontsize:40;fontname:Arial" x="32" y="32">pll</text>
+        <rect width="544" x="32" y="32" height="1056" />
+        <line x2="32" y1="80" y2="80" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin clk_in1" />
+        <line x2="576" y1="80" y2="80" x1="608" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="80" type="pin clk_out1" />
+        <line x2="576" y1="176" y2="176" x1="608" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="176" type="pin clk_out2" />
+        <line x2="576" y1="976" y2="976" x1="608" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="976" type="pin locked" />
+    </graph>
+</symbol>
Index: papilioduo/pll/pll.xco
===================================================================
--- papilioduo/pll/pll.xco	(nonexistent)
+++ papilioduo/pll/pll.xco	(revision 325)
@@ -0,0 +1,269 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Wed Jul 23 19:13:47 2014
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:clk_wiz:3.6
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
+# END Select
+# BEGIN Parameters
+CSET calc_done=DONE
+CSET clk_in_sel_port=CLK_IN_SEL
+CSET clk_out1_port=CLKOUT
+CSET clk_out1_use_fine_ps_gui=false
+CSET clk_out2_port=CLKOUT2
+CSET clk_out2_use_fine_ps_gui=false
+CSET clk_out3_port=CLK_OUT3
+CSET clk_out3_use_fine_ps_gui=false
+CSET clk_out4_port=CLK_OUT4
+CSET clk_out4_use_fine_ps_gui=false
+CSET clk_out5_port=CLK_OUT5
+CSET clk_out5_use_fine_ps_gui=false
+CSET clk_out6_port=CLK_OUT6
+CSET clk_out6_use_fine_ps_gui=false
+CSET clk_out7_port=CLK_OUT7
+CSET clk_out7_use_fine_ps_gui=false
+CSET clk_valid_port=CLK_VALID
+CSET clkfb_in_n_port=CLKFB_IN_N
+CSET clkfb_in_p_port=CLKFB_IN_P
+CSET clkfb_in_port=CLKFB_IN
+CSET clkfb_in_signaling=SINGLE
+CSET clkfb_out_n_port=CLKFB_OUT_N
+CSET clkfb_out_p_port=CLKFB_OUT_P
+CSET clkfb_out_port=CLKFB_OUT
+CSET clkfb_stopped_port=CLKFB_STOPPED
+CSET clkin1_jitter_ps=200.0
+CSET clkin1_ui_jitter=0.010
+CSET clkin2_jitter_ps=100.0
+CSET clkin2_ui_jitter=0.010
+CSET clkout1_drives=BUFG
+CSET clkout1_requested_duty_cycle=50.000
+CSET clkout1_requested_out_freq=28.64
+CSET clkout1_requested_phase=0.000
+CSET clkout2_drives=BUFG
+CSET clkout2_requested_duty_cycle=50.000
+CSET clkout2_requested_out_freq=57.28
+CSET clkout2_requested_phase=0.000
+CSET clkout2_used=true
+CSET clkout3_drives=BUFG
+CSET clkout3_requested_duty_cycle=50.000
+CSET clkout3_requested_out_freq=100.000
+CSET clkout3_requested_phase=0.000
+CSET clkout3_used=false
+CSET clkout4_drives=BUFG
+CSET clkout4_requested_duty_cycle=50.000
+CSET clkout4_requested_out_freq=100.000
+CSET clkout4_requested_phase=0.000
+CSET clkout4_used=false
+CSET clkout5_drives=BUFG
+CSET clkout5_requested_duty_cycle=50.000
+CSET clkout5_requested_out_freq=100.000
+CSET clkout5_requested_phase=0.000
+CSET clkout5_used=false
+CSET clkout6_drives=BUFG
+CSET clkout6_requested_duty_cycle=50.000
+CSET clkout6_requested_out_freq=100.000
+CSET clkout6_requested_phase=0.000
+CSET clkout6_used=false
+CSET clkout7_drives=BUFG
+CSET clkout7_requested_duty_cycle=50.000
+CSET clkout7_requested_out_freq=100.000
+CSET clkout7_requested_phase=0.000
+CSET clkout7_used=false
+CSET clock_mgr_type=AUTO
+CSET component_name=pll
+CSET daddr_port=DADDR
+CSET dclk_port=DCLK
+CSET dcm_clk_feedback=1X
+CSET dcm_clk_out1_port=CLKFX
+CSET dcm_clk_out2_port=CLK0
+CSET dcm_clk_out3_port=CLK0
+CSET dcm_clk_out4_port=CLK0
+CSET dcm_clk_out5_port=CLK0
+CSET dcm_clk_out6_port=CLK0
+CSET dcm_clkdv_divide=2.0
+CSET dcm_clkfx_divide=25
+CSET dcm_clkfx_multiply=14
+CSET dcm_clkgen_clk_out1_port=CLKFX
+CSET dcm_clkgen_clk_out2_port=CLKFX
+CSET dcm_clkgen_clk_out3_port=CLKFX
+CSET dcm_clkgen_clkfx_divide=1
+CSET dcm_clkgen_clkfx_md_max=0.000
+CSET dcm_clkgen_clkfx_multiply=4
+CSET dcm_clkgen_clkfxdv_divide=2
+CSET dcm_clkgen_clkin_period=10.000
+CSET dcm_clkgen_notes=None
+CSET dcm_clkgen_spread_spectrum=NONE
+CSET dcm_clkgen_startup_wait=false
+CSET dcm_clkin_divide_by_2=false
+CSET dcm_clkin_period=20.000
+CSET dcm_clkout_phase_shift=NONE
+CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
+CSET dcm_notes=None
+CSET dcm_phase_shift=0
+CSET dcm_pll_cascade=NONE
+CSET dcm_startup_wait=false
+CSET den_port=DEN
+CSET din_port=DIN
+CSET dout_port=DOUT
+CSET drdy_port=DRDY
+CSET dwe_port=DWE
+CSET feedback_source=FDBK_AUTO
+CSET in_freq_units=Units_MHz
+CSET in_jitter_units=Units_UI
+CSET input_clk_stopped_port=INPUT_CLK_STOPPED
+CSET jitter_options=UI
+CSET jitter_sel=No_Jitter
+CSET locked_port=LOCKED
+CSET mmcm_bandwidth=OPTIMIZED
+CSET mmcm_clkfbout_mult_f=4.000
+CSET mmcm_clkfbout_phase=0.000
+CSET mmcm_clkfbout_use_fine_ps=false
+CSET mmcm_clkin1_period=10.000
+CSET mmcm_clkin2_period=10.000
+CSET mmcm_clkout0_divide_f=4.000
+CSET mmcm_clkout0_duty_cycle=0.500
+CSET mmcm_clkout0_phase=0.000
+CSET mmcm_clkout0_use_fine_ps=false
+CSET mmcm_clkout1_divide=1
+CSET mmcm_clkout1_duty_cycle=0.500
+CSET mmcm_clkout1_phase=0.000
+CSET mmcm_clkout1_use_fine_ps=false
+CSET mmcm_clkout2_divide=1
+CSET mmcm_clkout2_duty_cycle=0.500
+CSET mmcm_clkout2_phase=0.000
+CSET mmcm_clkout2_use_fine_ps=false
+CSET mmcm_clkout3_divide=1
+CSET mmcm_clkout3_duty_cycle=0.500
+CSET mmcm_clkout3_phase=0.000
+CSET mmcm_clkout3_use_fine_ps=false
+CSET mmcm_clkout4_cascade=false
+CSET mmcm_clkout4_divide=1
+CSET mmcm_clkout4_duty_cycle=0.500
+CSET mmcm_clkout4_phase=0.000
+CSET mmcm_clkout4_use_fine_ps=false
+CSET mmcm_clkout5_divide=1
+CSET mmcm_clkout5_duty_cycle=0.500
+CSET mmcm_clkout5_phase=0.000
+CSET mmcm_clkout5_use_fine_ps=false
+CSET mmcm_clkout6_divide=1
+CSET mmcm_clkout6_duty_cycle=0.500
+CSET mmcm_clkout6_phase=0.000
+CSET mmcm_clkout6_use_fine_ps=false
+CSET mmcm_clock_hold=false
+CSET mmcm_compensation=ZHOLD
+CSET mmcm_divclk_divide=1
+CSET mmcm_notes=None
+CSET mmcm_ref_jitter1=0.010
+CSET mmcm_ref_jitter2=0.010
+CSET mmcm_startup_wait=false
+CSET num_out_clks=2
+CSET override_dcm=false
+CSET override_dcm_clkgen=false
+CSET override_mmcm=false
+CSET override_pll=false
+CSET platform=nt64
+CSET pll_bandwidth=OPTIMIZED
+CSET pll_clk_feedback=CLKFBOUT
+CSET pll_clkfbout_mult=39
+CSET pll_clkfbout_phase=0.000
+CSET pll_clkin_period=20.000
+CSET pll_clkout0_divide=34
+CSET pll_clkout0_duty_cycle=0.500
+CSET pll_clkout0_phase=0.000
+CSET pll_clkout1_divide=17
+CSET pll_clkout1_duty_cycle=0.500
+CSET pll_clkout1_phase=0.000
+CSET pll_clkout2_divide=1
+CSET pll_clkout2_duty_cycle=0.500
+CSET pll_clkout2_phase=0.000
+CSET pll_clkout3_divide=1
+CSET pll_clkout3_duty_cycle=0.500
+CSET pll_clkout3_phase=0.000
+CSET pll_clkout4_divide=1
+CSET pll_clkout4_duty_cycle=0.500
+CSET pll_clkout4_phase=0.000
+CSET pll_clkout5_divide=1
+CSET pll_clkout5_duty_cycle=0.500
+CSET pll_clkout5_phase=0.000
+CSET pll_compensation=SYSTEM_SYNCHRONOUS
+CSET pll_divclk_divide=2
+CSET pll_notes=None
+CSET pll_ref_jitter=0.010
+CSET power_down_port=POWER_DOWN
+CSET prim_in_freq=50
+CSET prim_in_jitter=0.010
+CSET prim_source=Single_ended_clock_capable_pin
+CSET primary_port=CLKIN
+CSET primitive=MMCM
+CSET primtype_sel=PLL_BASE
+CSET psclk_port=PSCLK
+CSET psdone_port=PSDONE
+CSET psen_port=PSEN
+CSET psincdec_port=PSINCDEC
+CSET relative_inclk=REL_PRIMARY
+CSET reset_port=RESET
+CSET secondary_in_freq=100.000
+CSET secondary_in_jitter=0.010
+CSET secondary_port=CLK_IN2
+CSET secondary_source=Single_ended_clock_capable_pin
+CSET ss_mod_freq=250
+CSET ss_mode=CENTER_HIGH
+CSET status_port=STATUS
+CSET summary_strings=empty
+CSET use_clk_valid=false
+CSET use_clkfb_stopped=false
+CSET use_dyn_phase_shift=false
+CSET use_dyn_reconfig=false
+CSET use_freeze=false
+CSET use_freq_synth=true
+CSET use_inclk_stopped=false
+CSET use_inclk_switchover=false
+CSET use_locked=true
+CSET use_max_i_jitter=false
+CSET use_min_o_jitter=false
+CSET use_min_power=false
+CSET use_phase_alignment=true
+CSET use_power_down=false
+CSET use_reset=false
+CSET use_spread_spectrum=false
+CSET use_spread_spectrum_1=false
+CSET use_status=false
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-05-10T12:44:55Z
+# END Extra information
+GENERATE
+# CRC: 51445c78
Index: papilioduo/pll/pll_xmdf.tcl
===================================================================
--- papilioduo/pll/pll_xmdf.tcl	(nonexistent)
+++ papilioduo/pll/pll_xmdf.tcl	(revision 325)
@@ -0,0 +1,128 @@
+# The package naming convention is <core_name>_xmdf
+package provide pll_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::pll_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::pll_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name pll
+}
+# ::pll_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::pll_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/clk_wiz_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/doc/clk_wiz_ds709.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/doc/clk_wiz_gsg521.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/implement/implement.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/implement/implement.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/implement/xst.prj
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/implement/xst.scr
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/pll_tb.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/functional/simcmds.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/functional/simulate_isim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/functional/simulate_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/functional/simulate_ncsim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/functional/wave.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/functional/wave.sv
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll.ejp
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll.vho
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module pll
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
Index: papilioduo/pll/pll/simulation/timing/simulate_mti.sh
===================================================================
--- papilioduo/pll/pll/simulation/timing/simulate_mti.sh	(nonexistent)
+++ papilioduo/pll/pll/simulation/timing/simulate_mti.sh	(revision 325)
@@ -0,0 +1,60 @@
+#/bin/sh
+# file: simulate_mti.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vcom -work work ../../implement/results/routed.vhd
+vcom -work work pll_tb.vhd
+
+# run the simulation
+vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprim -sdfmax pll_tb/dut=../../implement/results/routed.sdf +no_notifier work.pll_tb 
Index: papilioduo/pll/pll/simulation/timing/vcs_session.tcl
===================================================================
--- papilioduo/pll/pll/simulation/timing/vcs_session.tcl	(nonexistent)
+++ papilioduo/pll/pll/simulation/timing/vcs_session.tcl	(revision 325)
@@ -0,0 +1 @@
+gui_open_window Wave
Index: papilioduo/pll/pll.ncf
===================================================================
--- papilioduo/pll/pll.ncf	(nonexistent)
+++ papilioduo/pll/pll.ncf	(revision 325)
@@ -0,0 +1,59 @@
+# file: pll.ucf
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.000 ns HIGH 50% INPUT_JITTER 200.0ps;
+
+
+# FALSE PATH constraints 
+
+
Index: papilioduo/pll/pll.vho
===================================================================
--- papilioduo/pll/pll.vho	(nonexistent)
+++ papilioduo/pll/pll.vho	(revision 325)
@@ -0,0 +1,93 @@
+-- 
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+-- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+------------------------------------------------------------------------------
+-- CLK_OUT1____28.676______0.000______50.0______292.034____257.452
+-- CLK_OUT2____57.353______0.000______50.0______239.345____257.452
+--
+------------------------------------------------------------------------------
+-- "Input Clock   Freq (MHz)    Input Jitter (UI)"
+------------------------------------------------------------------------------
+-- __primary______________50____________0.010
+
+
+-- The following code must appear in the VHDL architecture header:
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component pll
+port
+ (-- Clock in ports
+  CLKIN           : in     std_logic;
+  -- Clock out ports
+  CLKOUT          : out    std_logic;
+  CLKOUT2          : out    std_logic;
+  -- Status and control signals
+  LOCKED            : out    std_logic
+ );
+end component;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : pll
+  port map
+   (-- Clock in ports
+    CLKIN => CLKIN,
+    -- Clock out ports
+    CLKOUT => CLKOUT,
+    CLKOUT2 => CLKOUT2,
+    -- Status and control signals
+    LOCKED => LOCKED);
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
Index: papilioduo/pll/pll_flist.txt
===================================================================
--- papilioduo/pll/pll_flist.txt	(nonexistent)
+++ papilioduo/pll/pll_flist.txt	(revision 325)
@@ -0,0 +1,53 @@
+# Output products list for <pll>
+_xmsgs\pn_parser.xmsgs
+pll.asy
+pll.gise
+pll.sym
+pll.ucf
+pll.vhd
+pll.vho
+pll.xco
+pll.xdc
+pll.xise
+pll\clk_wiz_v3_6_readme.txt
+pll\doc\clk_wiz_v3_6_readme.txt
+pll\doc\clk_wiz_v3_6_vinfo.html
+pll\doc\pg065_clk_wiz.pdf
+pll\example_design\pll_exdes.ucf
+pll\example_design\pll_exdes.vhd
+pll\example_design\pll_exdes.xdc
+pll\implement\implement.bat
+pll\implement\implement.sh
+pll\implement\planAhead_ise.bat
+pll\implement\planAhead_ise.sh
+pll\implement\planAhead_ise.tcl
+pll\implement\planAhead_rdn.bat
+pll\implement\planAhead_rdn.sh
+pll\implement\planAhead_rdn.tcl
+pll\implement\xst.prj
+pll\implement\xst.scr
+pll\simulation\functional\simcmds.tcl
+pll\simulation\functional\simulate_isim.bat
+pll\simulation\functional\simulate_isim.sh
+pll\simulation\functional\simulate_mti.bat
+pll\simulation\functional\simulate_mti.do
+pll\simulation\functional\simulate_mti.sh
+pll\simulation\functional\simulate_ncsim.sh
+pll\simulation\functional\simulate_vcs.sh
+pll\simulation\functional\wave.do
+pll\simulation\functional\wave.sv
+pll\simulation\pll_tb.vhd
+pll\simulation\timing\pll_tb.vhd
+pll\simulation\timing\sdf_cmd_file
+pll\simulation\timing\simcmds.tcl
+pll\simulation\timing\simulate_isim.sh
+pll\simulation\timing\simulate_mti.bat
+pll\simulation\timing\simulate_mti.do
+pll\simulation\timing\simulate_mti.sh
+pll\simulation\timing\simulate_ncsim.sh
+pll\simulation\timing\simulate_vcs.sh
+pll\simulation\timing\ucli_commands.key
+pll\simulation\timing\vcs_session.tcl
+pll\simulation\timing\wave.do
+pll_flist.txt
+pll_xmdf.tcl
Index: papilioduo/pll/pll.gise
===================================================================
--- papilioduo/pll/pll.gise	(nonexistent)
+++ papilioduo/pll/pll.gise	(revision 325)
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="pll.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="pll.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VHO" xil_pn:name="pll.vho" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
Index: papilioduo/pll/pll.vhd
===================================================================
--- papilioduo/pll/pll.vhd	(nonexistent)
+++ papilioduo/pll/pll.vhd	(revision 325)
@@ -0,0 +1,172 @@
+-- file: pll.vhd
+-- 
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+-- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+------------------------------------------------------------------------------
+-- CLK_OUT1____28.676______0.000______50.0______292.034____257.452
+-- CLK_OUT2____57.353______0.000______50.0______239.345____257.452
+--
+------------------------------------------------------------------------------
+-- "Input Clock   Freq (MHz)    Input Jitter (UI)"
+------------------------------------------------------------------------------
+-- __primary______________50____________0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity pll is
+port
+ (-- Clock in ports
+  CLKIN           : in     std_logic;
+  -- Clock out ports
+  CLKOUT          : out    std_logic;
+  CLKOUT2          : out    std_logic;
+  -- Status and control signals
+  LOCKED            : out    std_logic
+ );
+end pll;
+
+architecture xilinx of pll is
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of xilinx : architecture is "pll,clk_wiz_v3_6,{component_name=pll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=20.000,clkin2_period=20.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
+  -- Input clock buffering / unused connectors
+  signal clkin1      : std_logic;
+  -- Output clock buffering / unused connectors
+  signal clkfbout         : std_logic;
+  signal clkfbout_buf     : std_logic;
+  signal clkout0          : std_logic;
+  signal clkout1          : std_logic;
+  signal clkout2_unused   : std_logic;
+  signal clkout3_unused   : std_logic;
+  signal clkout4_unused   : std_logic;
+  signal clkout5_unused   : std_logic;
+  -- Unused status signals
+
+begin
+
+
+  -- Input buffering
+  --------------------------------------
+  clkin1_buf : IBUFG
+  port map
+   (O => clkin1,
+    I => CLKIN);
+
+
+  -- Clocking primitive
+  --------------------------------------
+  -- Instantiation of the PLL primitive
+  --    * Unused inputs are tied off
+  --    * Unused outputs are labeled unused
+
+  pll_base_inst : PLL_BASE
+  generic map
+   (BANDWIDTH            => "OPTIMIZED",
+    CLK_FEEDBACK         => "CLKFBOUT",
+    COMPENSATION         => "SYSTEM_SYNCHRONOUS",
+    DIVCLK_DIVIDE        => 2,
+    CLKFBOUT_MULT        => 39,
+    CLKFBOUT_PHASE       => 0.000,
+    CLKOUT0_DIVIDE       => 34,
+    CLKOUT0_PHASE        => 0.000,
+    CLKOUT0_DUTY_CYCLE   => 0.500,
+    CLKOUT1_DIVIDE       => 17,
+    CLKOUT1_PHASE        => 0.000,
+    CLKOUT1_DUTY_CYCLE   => 0.500,
+    CLKIN_PERIOD         => 20.000,
+    REF_JITTER           => 0.010)
+  port map
+    -- Output clocks
+   (CLKFBOUT            => clkfbout,
+    CLKOUT0             => clkout0,
+    CLKOUT1             => clkout1,
+    CLKOUT2             => clkout2_unused,
+    CLKOUT3             => clkout3_unused,
+    CLKOUT4             => clkout4_unused,
+    CLKOUT5             => clkout5_unused,
+    -- Status and control signals
+    LOCKED              => LOCKED,
+    RST                 => '0',
+    -- Input clock control
+    CLKFBIN             => clkfbout_buf,
+    CLKIN               => clkin1);
+
+  -- Output buffering
+  -------------------------------------
+  clkf_buf : BUFG
+  port map
+   (O => clkfbout_buf,
+    I => clkfbout);
+
+
+  clkout1_buf : BUFG
+  port map
+   (O   => CLKOUT,
+    I   => clkout0);
+
+
+
+  clkout2_buf : BUFG
+  port map
+   (O   => CLKOUT2,
+    I   => clkout1);
+
+end xilinx;
Index: papilioduo/pll/pll.xise
===================================================================
--- papilioduo/pll/pll.xise	(nonexistent)
+++ papilioduo/pll/pll.xise	(revision 325)
@@ -0,0 +1,74 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="pll.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="pll.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|pll|xilinx" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="pll.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/pll" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="pll" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-07-23T21:14:11" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="81FEB3840ACE4C7C9F4657A3E975FFC2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings>
+    <binding xil_pn:location="/pll" xil_pn:name="pll.ucf"/>
+  </bindings>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
Index: papilioduo/zpu_rom.vhdl
===================================================================
--- papilioduo/zpu_rom.vhdl	(nonexistent)
+++ papilioduo/zpu_rom.vhdl	(revision 325)
@@ -0,0 +1,4130 @@
+
+--
+--ROMsUsingBlockRAMResources.
+--VHDLcodeforaROMwithregisteredoutput(template2)
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity zpu_rom is
+port(
+        clock:in std_logic;
+        address:in std_logic_vector(11 downto 0);
+        q:out std_logic_vector(31 downto 0)
+);
+end zpu_rom;
+
+architecture syn of zpu_rom is
+        type rom_type is array(0 to 4095) of std_logic_vector(31 downto 0);
+        signal ROM:rom_type:=
+(
+	X"0b0b0b89",
+X"ad040b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"72830609",
+X"81058205",
+X"832b2a83",
+X"ffff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"83ffff73",
+X"83060981",
+X"05820583",
+X"2b2b0906",
+X"7383ffff",
+X"0b0b0b0b",
+X"83a70400",
+X"72098105",
+X"72057373",
+X"09060906",
+X"73097306",
+X"070a8106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"72722473",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71737109",
+X"71068106",
+X"30720a10",
+X"0a720a10",
+X"0a31050a",
+X"81065151",
+X"53510400",
+X"00000000",
+X"72722673",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"bc040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"720a722b",
+X"0a535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72729f06",
+X"0981050b",
+X"0b0b889f",
+X"05040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72722aff",
+X"739f062a",
+X"0974090a",
+X"8106ff05",
+X"06075351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71715351",
+X"020d0406",
+X"73830609",
+X"81058205",
+X"832b0b2b",
+X"0772fc06",
+X"0c515104",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a810653",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a098106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71098105",
+X"52040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72720981",
+X"05055351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72097206",
+X"73730906",
+X"07535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fc0608",
+X"72830609",
+X"81058305",
+X"1010102a",
+X"81ff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fc0608",
+X"0b0b80f2",
+X"80738306",
+X"10100508",
+X"060b0b0b",
+X"88a20400",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"ff040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"d8040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72097081",
+X"0509060a",
+X"8106ff05",
+X"70547106",
+X"73097274",
+X"05ff0506",
+X"07515151",
+X"04000000",
+X"72097081",
+X"0509060a",
+X"098106ff",
+X"05705471",
+X"06730972",
+X"7405ff05",
+X"06075151",
+X"51040000",
+X"05ff0504",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"810b80f5",
+X"b40c5104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00007181",
+X"05520400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000284",
+X"05721010",
+X"05520400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00007171",
+X"05ff0571",
+X"5351020d",
+X"04000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"10101010",
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+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000"
+
+);
+        signal rdata:std_logic_vector(31 downto 0);
+begin
+        rdata<=ROM(conv_integer(address));
+
+        process(clock)
+        begin
+                if(clock'event and clock='1')then
+                	q<=rdata;
+                end if;
+        end process;
+end syn;
