Index: sockit/pll_pal_sim/cadence/ncsim_setup.sh
===================================================================
--- sockit/pll_pal_sim/cadence/ncsim_setup.sh	(nonexistent)
+++ sockit/pll_pal_sim/cadence/ncsim_setup.sh	(revision 302)
@@ -0,0 +1,107 @@
+
+# (C) 2001-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 14.0 200 linux 2014.12.14.13:40:56
+
+# ----------------------------------------
+# ncsim - auto-generated simulation script
+
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="pll_pal"
+QSYS_SIMDIR="./../"
+QUARTUS_INSTALL_DIR="/home/markw/fpga/altera/14.0/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for 
+# overwriting variables. An example usage:
+#   sh <simulator>_setup.sh SKIP_ELAB=1 SKIP_SIM=1
+for expression in "$@"; do
+  eval $expression
+  if [ $? -ne 0 ]; then
+    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+    exit $?
+  fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
+  :
+else
+  :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera/
+mkdir -p ./libraries/lpm/
+mkdir -p ./libraries/sgate/
+mkdir -p ./libraries/altera_mf/
+mkdir -p ./libraries/altera_lnsim/
+mkdir -p ./libraries/cyclonev/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+  ncvlog -sv  "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+  ncvlog      "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v"  -work cyclonev    
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+  ncvhdl -v93 "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+  ncvhdl -v93 "$QSYS_SIMDIR/pll_pal.vho"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+  ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+  eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
+fi

Property changes on: sockit/pll_pal_sim/cadence/ncsim_setup.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sockit/pll_pal_sim/synopsys/vcsmx/synopsys_sim.setup
===================================================================
--- sockit/pll_pal_sim/synopsys/vcsmx/synopsys_sim.setup	(nonexistent)
+++ sockit/pll_pal_sim/synopsys/vcsmx/synopsys_sim.setup	(revision 302)
@@ -0,0 +1,11 @@
+
+WORK > DEFAULT
+DEFAULT:      ./libraries/work/        
+work:         ./libraries/work/        
+altera:       ./libraries/altera/      
+lpm:          ./libraries/lpm/         
+sgate:        ./libraries/sgate/       
+altera_mf:    ./libraries/altera_mf/   
+altera_lnsim: ./libraries/altera_lnsim/
+cyclonev:     ./libraries/cyclonev/    
+LIBRARY_SCAN = TRUE
Index: sockit/pll_pal.cmp
===================================================================
--- sockit/pll_pal.cmp	(nonexistent)
+++ sockit/pll_pal.cmp	(revision 302)
@@ -0,0 +1,9 @@
+	component pll_pal is
+		port (
+			refclk   : in  std_logic := 'X'; -- clk
+			rst      : in  std_logic := 'X'; -- reset
+			outclk_0 : out std_logic;        -- clk
+			locked   : out std_logic         -- export
+		);
+	end component pll_pal;
+
Index: sockit/pll_pal.qip
===================================================================
--- sockit/pll_pal.qip	(nonexistent)
+++ sockit/pll_pal.qip	(revision 302)
@@ -0,0 +1,339 @@
+set_global_assignment -entity "pll_pal" -library "pll_pal" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_pal" -library "pll_pal" -name IP_TOOL_VERSION "14.0"
+set_global_assignment -entity "pll_pal" -library "pll_pal" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "pll_pal" -name MISC_FILE [file join $::quartus(qip_path) "pll_pal.cmp"]
+set_global_assignment -entity "pll_pal" -library "pll_pal" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V"
+set_global_assignment -entity "pll_pal" -library "pll_pal" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -entity "pll_pal" -library "pll_pal" -name IP_QSYS_MODE "UNKNOWN"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -entity "pll_pal" -library "pll_pal" -name IP_COMPONENT_NAME "cGxsX3BhbA=="
+set_global_assignment -entity "pll_pal" -library "pll_pal" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_pal" -library "pll_pal" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_pal" -library "pll_pal" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_pal" -library "pll_pal" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll_pal" -library "pll_pal" -name IP_COMPONENT_VERSION "MTQuMA=="
+set_global_assignment -entity "pll_pal" -library "pll_pal" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_NAME "cGxsX3BhbF8wMDAy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_DISPLAY_NAME "QWx0ZXJhIFBMTA=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_AUTHOR "QWx0ZXJhIENvcnBvcmF0aW9u"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_VERSION "MTQuMA=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_DESCRIPTION "QWx0ZXJhIFBoYXNlLUxvY2tlZCBMb29wIChBTFRFUkFfUExMKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::VW5rbm93bg==::ZGV2aWNl"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RldmljZV9zcGVlZF9ncmFkZQ==::OA==::RGV2aWNlIFNwZWVkIEdyYWRl"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::SW50ZWdlci1OIFBMTA==::UExMIE1vZGU="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::ZmFsc2U=::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NTAuMA==::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NTAuMCBNSHo=::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::MQ==::TnVtYmVyIE9mIENsb2Nrcw=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::MQ==::bnVtYmVyX29mX2Nsb2Nrcw=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::NTYuNzUwMzI=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MjI3::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::MjAw::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::NTYuNzUwMDAwIE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MCBwcw==::cGhhc2Vfc2hpZnQx"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::MCBwcw==::cGhhc2Vfc2hpZnQz"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::MCBwcw==::cGhhc2Vfc2hpZnQ0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T2Zm::UExMIEF1dG8gUmVzZXQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::MTE0LDExMyw1LDUsZmFsc2UsZmFsc2UsdHJ1ZSxmYWxzZSwxMCwxMCwxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwxLDIwLDE0MDAwLDExMzUuMCBNSHosMSxnY2xrLGdsYixmYl8xLHBoX211eF9jbGssZmFsc2U=::UGFyYW1ldGVyIFZhbHVlcw=="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw="
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_COMPONENT_PARAMETER "QVVUT19SRUZDTEtfQ0xPQ0tfUkFURQ==::LTE=::QXV0byBDTE9DS19SQVRF"
+
+set_global_assignment -library "pll_pal" -name VHDL_FILE [file join $::quartus(qip_path) "pll_pal.vhd"]
+set_global_assignment -library "pll_pal" -name VERILOG_FILE [file join $::quartus(qip_path) "pll_pal/pll_pal_0002.v"]
+set_global_assignment -library "pll_pal" -name QIP_FILE [file join $::quartus(qip_path) "pll_pal/pll_pal_0002.qip"]
+
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_TOOL_VERSION "14.0"
+set_global_assignment -entity "pll_pal_0002" -library "pll_pal" -name IP_TOOL_ENV "mwpim"
Index: sockit/pll_pal.spd
===================================================================
--- sockit/pll_pal.spd	(nonexistent)
+++ sockit/pll_pal.spd	(revision 302)
@@ -0,0 +1,6 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<simPackage>
+ <file path="pll_pal_sim/pll_pal.vho" type="VHDL" />
+ <topLevel name="pll_pal" />
+ <deviceFamily name="cyclonev" />
+</simPackage>
Index: sockit/pll_pal_sim/aldec/rivierapro_setup.tcl
===================================================================
--- sockit/pll_pal_sim/aldec/rivierapro_setup.tcl	(nonexistent)
+++ sockit/pll_pal_sim/aldec/rivierapro_setup.tcl	(revision 302)
@@ -0,0 +1,177 @@
+
+# (C) 2001-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 14.0 200 linux 2014.12.14.13:40:56
+
+# ----------------------------------------
+# Auto-generated simulation script
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] { 
+  set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
+  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] { 
+  set TOP_LEVEL_NAME "pll_pal"
+}
+
+if ![info exists QSYS_SIMDIR] { 
+  set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] { 
+  set QUARTUS_INSTALL_DIR "/home/markw/fpga/altera/14.0/quartus/"
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+set Aldec "Riviera"
+if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
+  set Aldec "Active"
+}
+
+if { [ string match "Active" $Aldec ] } {
+  scripterconf -tcl
+  createdesign "$TOP_LEVEL_NAME"  "."
+  opendesign "$TOP_LEVEL_NAME"
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+  echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib      ./libraries     
+ensure_lib      ./libraries/work
+vmap       work ./libraries/work
+ensure_lib              ./libraries/altera      
+vmap       altera       ./libraries/altera      
+ensure_lib              ./libraries/lpm         
+vmap       lpm          ./libraries/lpm         
+ensure_lib              ./libraries/sgate       
+vmap       sgate        ./libraries/sgate       
+ensure_lib              ./libraries/altera_mf   
+vmap       altera_mf    ./libraries/altera_mf   
+ensure_lib              ./libraries/altera_lnsim
+vmap       altera_lnsim ./libraries/altera_lnsim
+ensure_lib              ./libraries/cyclonev    
+vmap       cyclonev     ./libraries/cyclonev    
+
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+  echo "\[exec\] dev_com"
+  vcom  "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+  vcom  "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+  vcom  "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+  vcom  "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+  vcom  "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+  vcom  "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+  vcom  "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+  vcom  "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+  vcom  "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+  vcom  "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+  vcom  "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+  vcom  "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+  vlog  "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
+  vcom  "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+  vlog  "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v"    -work cyclonev    
+  vcom  "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+  vcom  "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+  echo "\[exec\] com"
+  vcom "$QSYS_SIMDIR/pll_pal.vho"
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+  echo "\[exec\] elab"
+  eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -dbg -O2 option
+alias elab_debug {
+  echo "\[exec\] elab_debug"
+  eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+  dev_com
+  com
+  elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -dbg -O2
+alias ld_debug "
+  dev_com
+  com
+  elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+  echo "List Of Command Line Aliases"
+  echo
+  echo "file_copy                     -- Copy ROM/RAM files to simulation directory"
+  echo
+  echo "dev_com                       -- Compile device library files"
+  echo
+  echo "com                           -- Compile the design files in correct order"
+  echo
+  echo "elab                          -- Elaborate top level design"
+  echo
+  echo "elab_debug                    -- Elaborate the top level design with -dbg -O2 option"
+  echo
+  echo "ld                            -- Compile all the design files and elaborate the top level design"
+  echo
+  echo "ld_debug                      -- Compile all the design files and elaborate the top level design with -dbg -O2"
+  echo
+  echo 
+  echo
+  echo "List Of Variables"
+  echo
+  echo "TOP_LEVEL_NAME                -- Top level module name."
+  echo
+  echo "SYSTEM_INSTANCE_NAME          -- Instantiated system module name inside top level module."
+  echo
+  echo "QSYS_SIMDIR                   -- Qsys base simulation directory."
+  echo
+  echo "QUARTUS_INSTALL_DIR           -- Quartus installation directory."
+}
+file_copy
+h
Index: sockit/pll_pal_sim/cadence/hdl.var
===================================================================
--- sockit/pll_pal_sim/cadence/hdl.var	(nonexistent)
+++ sockit/pll_pal_sim/cadence/hdl.var	(revision 302)
@@ -0,0 +1,2 @@
+
+DEFINE WORK work
Index: sockit/pll_pal_sim/pll_pal.vho
===================================================================
--- sockit/pll_pal_sim/pll_pal.vho	(nonexistent)
+++ sockit/pll_pal_sim/pll_pal.vho	(revision 302)
@@ -0,0 +1,306 @@
+--IP Functional Simulation Model
+--VERSION_BEGIN 14.0 cbx_mgl 2014:06:05:10:17:12:SJ cbx_simgen 2014:06:05:09:45:41:SJ  VERSION_END
+
+
+-- Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, the Altera Quartus II License Agreement,
+-- the Altera MegaCore Function License Agreement, or other 
+-- applicable license agreement, including, without limitation, 
+-- that your use is for the sole purpose of programming logic 
+-- devices manufactured by Altera and sold by Altera or its 
+-- authorized distributors.  Please refer to the applicable 
+-- agreement for further details.
+
+-- You may only use these simulation model output files for simulation
+-- purposes and expressly not for synthesis or any other purposes (in which
+-- event Altera disclaims all warranties of any kind).
+
+
+--synopsys translate_off
+
+ LIBRARY altera_lnsim;
+ USE altera_lnsim.altera_lnsim_components.all;
+
+--synthesis_resources = altera_pll 1 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  pll_pal IS 
+	 PORT 
+	 ( 
+		 locked	:	OUT  STD_LOGIC;
+		 outclk_0	:	OUT  STD_LOGIC;
+		 refclk	:	IN  STD_LOGIC;
+		 rst	:	IN  STD_LOGIC
+	 ); 
+ END pll_pal;
+
+ ARCHITECTURE RTL OF pll_pal IS
+
+	 ATTRIBUTE synthesis_clearbox : natural;
+	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 1;
+	 SIGNAL  wire_gnd	:	STD_LOGIC;
+	 SIGNAL  wire_pll_pal_altera_pll_altera_pll_i_639_locked	:	STD_LOGIC;
+	 SIGNAL  wire_pll_pal_altera_pll_altera_pll_i_639_outclk	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+ BEGIN
+
+	wire_gnd <= '0';
+	locked <= wire_pll_pal_altera_pll_altera_pll_i_639_locked;
+	outclk_0 <= wire_pll_pal_altera_pll_altera_pll_i_639_outclk(0);
+	pll_pal_altera_pll_altera_pll_i_639 :  altera_pll
+	  GENERIC MAP (
+		c_cnt_bypass_en0 => "false",
+		c_cnt_bypass_en1 => "false",
+		c_cnt_bypass_en10 => "false",
+		c_cnt_bypass_en11 => "false",
+		c_cnt_bypass_en12 => "false",
+		c_cnt_bypass_en13 => "false",
+		c_cnt_bypass_en14 => "false",
+		c_cnt_bypass_en15 => "false",
+		c_cnt_bypass_en16 => "false",
+		c_cnt_bypass_en17 => "false",
+		c_cnt_bypass_en2 => "false",
+		c_cnt_bypass_en3 => "false",
+		c_cnt_bypass_en4 => "false",
+		c_cnt_bypass_en5 => "false",
+		c_cnt_bypass_en6 => "false",
+		c_cnt_bypass_en7 => "false",
+		c_cnt_bypass_en8 => "false",
+		c_cnt_bypass_en9 => "false",
+		c_cnt_hi_div0 => 1,
+		c_cnt_hi_div1 => 1,
+		c_cnt_hi_div10 => 1,
+		c_cnt_hi_div11 => 1,
+		c_cnt_hi_div12 => 1,
+		c_cnt_hi_div13 => 1,
+		c_cnt_hi_div14 => 1,
+		c_cnt_hi_div15 => 1,
+		c_cnt_hi_div16 => 1,
+		c_cnt_hi_div17 => 1,
+		c_cnt_hi_div2 => 1,
+		c_cnt_hi_div3 => 1,
+		c_cnt_hi_div4 => 1,
+		c_cnt_hi_div5 => 1,
+		c_cnt_hi_div6 => 1,
+		c_cnt_hi_div7 => 1,
+		c_cnt_hi_div8 => 1,
+		c_cnt_hi_div9 => 1,
+		c_cnt_in_src0 => "ph_mux_clk",
+		c_cnt_in_src1 => "ph_mux_clk",
+		c_cnt_in_src10 => "ph_mux_clk",
+		c_cnt_in_src11 => "ph_mux_clk",
+		c_cnt_in_src12 => "ph_mux_clk",
+		c_cnt_in_src13 => "ph_mux_clk",
+		c_cnt_in_src14 => "ph_mux_clk",
+		c_cnt_in_src15 => "ph_mux_clk",
+		c_cnt_in_src16 => "ph_mux_clk",
+		c_cnt_in_src17 => "ph_mux_clk",
+		c_cnt_in_src2 => "ph_mux_clk",
+		c_cnt_in_src3 => "ph_mux_clk",
+		c_cnt_in_src4 => "ph_mux_clk",
+		c_cnt_in_src5 => "ph_mux_clk",
+		c_cnt_in_src6 => "ph_mux_clk",
+		c_cnt_in_src7 => "ph_mux_clk",
+		c_cnt_in_src8 => "ph_mux_clk",
+		c_cnt_in_src9 => "ph_mux_clk",
+		c_cnt_lo_div0 => 1,
+		c_cnt_lo_div1 => 1,
+		c_cnt_lo_div10 => 1,
+		c_cnt_lo_div11 => 1,
+		c_cnt_lo_div12 => 1,
+		c_cnt_lo_div13 => 1,
+		c_cnt_lo_div14 => 1,
+		c_cnt_lo_div15 => 1,
+		c_cnt_lo_div16 => 1,
+		c_cnt_lo_div17 => 1,
+		c_cnt_lo_div2 => 1,
+		c_cnt_lo_div3 => 1,
+		c_cnt_lo_div4 => 1,
+		c_cnt_lo_div5 => 1,
+		c_cnt_lo_div6 => 1,
+		c_cnt_lo_div7 => 1,
+		c_cnt_lo_div8 => 1,
+		c_cnt_lo_div9 => 1,
+		c_cnt_odd_div_duty_en0 => "false",
+		c_cnt_odd_div_duty_en1 => "false",
+		c_cnt_odd_div_duty_en10 => "false",
+		c_cnt_odd_div_duty_en11 => "false",
+		c_cnt_odd_div_duty_en12 => "false",
+		c_cnt_odd_div_duty_en13 => "false",
+		c_cnt_odd_div_duty_en14 => "false",
+		c_cnt_odd_div_duty_en15 => "false",
+		c_cnt_odd_div_duty_en16 => "false",
+		c_cnt_odd_div_duty_en17 => "false",
+		c_cnt_odd_div_duty_en2 => "false",
+		c_cnt_odd_div_duty_en3 => "false",
+		c_cnt_odd_div_duty_en4 => "false",
+		c_cnt_odd_div_duty_en5 => "false",
+		c_cnt_odd_div_duty_en6 => "false",
+		c_cnt_odd_div_duty_en7 => "false",
+		c_cnt_odd_div_duty_en8 => "false",
+		c_cnt_odd_div_duty_en9 => "false",
+		c_cnt_ph_mux_prst0 => 0,
+		c_cnt_ph_mux_prst1 => 0,
+		c_cnt_ph_mux_prst10 => 0,
+		c_cnt_ph_mux_prst11 => 0,
+		c_cnt_ph_mux_prst12 => 0,
+		c_cnt_ph_mux_prst13 => 0,
+		c_cnt_ph_mux_prst14 => 0,
+		c_cnt_ph_mux_prst15 => 0,
+		c_cnt_ph_mux_prst16 => 0,
+		c_cnt_ph_mux_prst17 => 0,
+		c_cnt_ph_mux_prst2 => 0,
+		c_cnt_ph_mux_prst3 => 0,
+		c_cnt_ph_mux_prst4 => 0,
+		c_cnt_ph_mux_prst5 => 0,
+		c_cnt_ph_mux_prst6 => 0,
+		c_cnt_ph_mux_prst7 => 0,
+		c_cnt_ph_mux_prst8 => 0,
+		c_cnt_ph_mux_prst9 => 0,
+		c_cnt_prst0 => 1,
+		c_cnt_prst1 => 1,
+		c_cnt_prst10 => 1,
+		c_cnt_prst11 => 1,
+		c_cnt_prst12 => 1,
+		c_cnt_prst13 => 1,
+		c_cnt_prst14 => 1,
+		c_cnt_prst15 => 1,
+		c_cnt_prst16 => 1,
+		c_cnt_prst17 => 1,
+		c_cnt_prst2 => 1,
+		c_cnt_prst3 => 1,
+		c_cnt_prst4 => 1,
+		c_cnt_prst5 => 1,
+		c_cnt_prst6 => 1,
+		c_cnt_prst7 => 1,
+		c_cnt_prst8 => 1,
+		c_cnt_prst9 => 1,
+		clock_name_0 => "UNUSED",
+		clock_name_1 => "UNUSED",
+		clock_name_2 => "UNUSED",
+		clock_name_3 => "UNUSED",
+		clock_name_4 => "UNUSED",
+		clock_name_5 => "UNUSED",
+		clock_name_6 => "UNUSED",
+		clock_name_7 => "UNUSED",
+		clock_name_8 => "UNUSED",
+		clock_name_global_0 => "false",
+		clock_name_global_1 => "false",
+		clock_name_global_2 => "false",
+		clock_name_global_3 => "false",
+		clock_name_global_4 => "false",
+		clock_name_global_5 => "false",
+		clock_name_global_6 => "false",
+		clock_name_global_7 => "false",
+		clock_name_global_8 => "false",
+		data_rate => 0,
+		deserialization_factor => 4,
+		duty_cycle0 => 50,
+		duty_cycle1 => 50,
+		duty_cycle10 => 50,
+		duty_cycle11 => 50,
+		duty_cycle12 => 50,
+		duty_cycle13 => 50,
+		duty_cycle14 => 50,
+		duty_cycle15 => 50,
+		duty_cycle16 => 50,
+		duty_cycle17 => 50,
+		duty_cycle2 => 50,
+		duty_cycle3 => 50,
+		duty_cycle4 => 50,
+		duty_cycle5 => 50,
+		duty_cycle6 => 50,
+		duty_cycle7 => 50,
+		duty_cycle8 => 50,
+		duty_cycle9 => 50,
+		fractional_vco_multiplier => "false",
+		m_cnt_bypass_en => "false",
+		m_cnt_hi_div => 1,
+		m_cnt_lo_div => 1,
+		m_cnt_odd_div_duty_en => "false",
+		mimic_fbclk_type => "gclk",
+		n_cnt_bypass_en => "false",
+		n_cnt_hi_div => 1,
+		n_cnt_lo_div => 1,
+		n_cnt_odd_div_duty_en => "false",
+		number_of_clocks => 1,
+		operation_mode => "normal",
+		output_clock_frequency0 => "56.750000 MHz",
+		output_clock_frequency1 => "0 MHz",
+		output_clock_frequency10 => "0 MHz",
+		output_clock_frequency11 => "0 MHz",
+		output_clock_frequency12 => "0 MHz",
+		output_clock_frequency13 => "0 MHz",
+		output_clock_frequency14 => "0 MHz",
+		output_clock_frequency15 => "0 MHz",
+		output_clock_frequency16 => "0 MHz",
+		output_clock_frequency17 => "0 MHz",
+		output_clock_frequency2 => "0 MHz",
+		output_clock_frequency3 => "0 MHz",
+		output_clock_frequency4 => "0 MHz",
+		output_clock_frequency5 => "0 MHz",
+		output_clock_frequency6 => "0 MHz",
+		output_clock_frequency7 => "0 MHz",
+		output_clock_frequency8 => "0 MHz",
+		output_clock_frequency9 => "0 MHz",
+		phase_shift0 => "0 ps",
+		phase_shift1 => "0 ps",
+		phase_shift10 => "0 ps",
+		phase_shift11 => "0 ps",
+		phase_shift12 => "0 ps",
+		phase_shift13 => "0 ps",
+		phase_shift14 => "0 ps",
+		phase_shift15 => "0 ps",
+		phase_shift16 => "0 ps",
+		phase_shift17 => "0 ps",
+		phase_shift2 => "0 ps",
+		phase_shift3 => "0 ps",
+		phase_shift4 => "0 ps",
+		phase_shift5 => "0 ps",
+		phase_shift6 => "0 ps",
+		phase_shift7 => "0 ps",
+		phase_shift8 => "0 ps",
+		phase_shift9 => "0 ps",
+		pll_auto_clk_sw_en => "false",
+		pll_bwctrl => 0,
+		pll_clk_loss_sw_en => "false",
+		pll_clk_sw_dly => 0,
+		pll_clkin_0_src => "clk_0",
+		pll_clkin_1_src => "clk_0",
+		pll_cp_current => 0,
+		pll_dsm_out_sel => "1st_order",
+		pll_extclk_0_cnt_src => "pll_extclk_cnt_src_vss",
+		pll_extclk_1_cnt_src => "pll_extclk_cnt_src_vss",
+		pll_fbclk_mux_1 => "glb",
+		pll_fbclk_mux_2 => "fb_1",
+		pll_fractional_cout => 24,
+		pll_fractional_division => 1,
+		pll_m_cnt_in_src => "ph_mux_clk",
+		pll_manu_clk_sw_en => "false",
+		pll_output_clk_frequency => "0 MHz",
+		pll_slf_rst => "false",
+		pll_subtype => "General",
+		pll_type => "General",
+		pll_vco_div => 1,
+		pll_vcoph_div => 1,
+		refclk1_frequency => "0 MHz",
+		reference_clock_frequency => "50.0 MHz",
+		sim_additional_refclk_cycles_to_lock => 0
+	  )
+	  PORT MAP ( 
+		fbclk => wire_gnd,
+		locked => wire_pll_pal_altera_pll_altera_pll_i_639_locked,
+		outclk => wire_pll_pal_altera_pll_altera_pll_i_639_outclk,
+		refclk => refclk,
+		rst => rst
+	  );
+
+ END RTL; --pll_pal
+--synopsys translate_on
+--VALID FILE
Index: sockit/pll_pal_sim.f
===================================================================
--- sockit/pll_pal_sim.f	(nonexistent)
+++ sockit/pll_pal_sim.f	(revision 302)
@@ -0,0 +1 @@
+pll_pal_sim/pll_pal.vho
Index: aeon_lite/Aeon.prj
===================================================================
--- aeon_lite/Aeon.prj	(revision 301)
+++ aeon_lite/Aeon.prj	(revision 302)
@@ -43,6 +43,7 @@
 covox.vhd
 ps2_keyboard.vhdl
 ps2_to_atari800.vhdl
+pot_from_signed.vhdl
 atari800core.vhd
 atari800core_simple_sdram.vhd
 dac.vhd
@@ -53,6 +54,7 @@
 scandouble_ram_infer.vhdl
 scandoubler.vhdl
 spi_master.vhd
+sio_device.vhdl
 zpupkg.vhd
 zpu_config_regs.vhdl
 zpu_glue.vhdl
Index: aeon_lite/Aeon.scr
===================================================================
--- aeon_lite/Aeon.scr	(revision 301)
+++ aeon_lite/Aeon.scr	(revision 302)
@@ -3,7 +3,7 @@
 -ifmt VHDL
 -ofn Aeon.ngc
 -ofmt NGC
--p xc6slx9
+-p xc6slx9-tqg144
 -opt_mode Area
 -opt_level 1
 -keep_hierarchy yes
Index: aeon_lite/Aeon.ucf
===================================================================
--- aeon_lite/Aeon.ucf	(revision 301)
+++ aeon_lite/Aeon.ucf	(revision 302)
@@ -35,7 +35,6 @@
 #NET "COMM_RDY"    LOC = P39   |  IOSTANDARD = LVTTL;
 
 # SD-Card & SPI-Flash
-NET "SD_MOSI"     LOC = P41   |  IOSTANDARD = LVTTL;
 NET "SD_MISO"     LOC = P38   |  IOSTANDARD = LVTTL;
 NET "SD_SCK"      LOC = P40   |  IOSTANDARD = LVTTL;
 NET "SD_CS"       LOC = P44   |  IOSTANDARD = LVTTL;
Index: aeon_lite/atari.vhd
===================================================================
--- aeon_lite/atari.vhd	(revision 301)
+++ aeon_lite/atari.vhd	(revision 302)
@@ -48,7 +48,6 @@
    JOY_DATA0      : in    std_logic;
    JOY_DATA1      : in    std_logic;
    
-   SD_MOSI        : out   std_logic;
    SD_MISO        : in    std_logic;
    SD_SCK         : out   std_logic;
    SD_CS          : out   std_logic; 
@@ -322,7 +321,7 @@
 
    ZPU_SD_DAT0                => SD_MISO,
    ZPU_SD_CLK                 => SD_SCK,
-   ZPU_SD_CMD                 => SD_MOSI,
+   ZPU_SD_CMD                 => open,
    ZPU_SD_DAT3                => SD_CS,
 
    ZPU_POKEY_ENABLE           => ZPU_POKEY_ENABLE,
Index: common/antic.wcfg
===================================================================
--- common/antic.wcfg	(revision 301)
+++ common/antic.wcfg	(revision 302)
@@ -18,7 +18,7 @@
          </top_modules>
       </db_ref>
    </db_ref_list>
-   <WVObjectSize size="36" />
+   <WVObjectSize size="48" />
    <wave_markers>
       <marker time="517213670600" label="" />
    </wave_markers>
@@ -180,4 +180,54 @@
       <obj_property name="ElementShortName">data_in</obj_property>
       <obj_property name="ObjectShortName">data_in</obj_property>
    </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/dma_fetch_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">dma_fetch_reg</obj_property>
+      <obj_property name="ObjectShortName">dma_fetch_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/dma_cache_ready_reg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">dma_cache_ready_reg</obj_property>
+      <obj_property name="ObjectShortName">dma_cache_ready_reg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/load_display_shift_from_memory" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">load_display_shift_from_memory</obj_property>
+      <obj_property name="ObjectShortName">load_display_shift_from_memory</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/dma_cache_next" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">dma_cache_next[7:0]</obj_property>
+      <obj_property name="ObjectShortName">dma_cache_next[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/dma_cache_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">dma_cache_reg[7:0]</obj_property>
+      <obj_property name="ObjectShortName">dma_cache_reg[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/dma_fetch_destination_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">dma_fetch_destination_reg[2:0]</obj_property>
+      <obj_property name="ObjectShortName">dma_fetch_destination_reg[2:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/dma_fetch_destination_next" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">dma_fetch_destination_next[2:0]</obj_property>
+      <obj_property name="ObjectShortName">dma_fetch_destination_next[2:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/antic_dma_clock1/playfield_start" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">playfield_start</obj_property>
+      <obj_property name="ObjectShortName">playfield_start</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/antic_dma_clock1/dma_shiftreg_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">dma_shiftreg_reg[7:0]</obj_property>
+      <obj_property name="ObjectShortName">dma_shiftreg_reg[7:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/antic_dma_clock1/enable_dma" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">enable_dma</obj_property>
+      <obj_property name="ObjectShortName">enable_dma</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/playfield_dma_start_shiftreg_next" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">playfield_dma_start_shiftreg_next[4:0]</obj_property>
+      <obj_property name="ObjectShortName">playfield_dma_start_shiftreg_next[4:0]</obj_property>
+   </wvobject>
+   <wvobject fp_name="/antic_tb/antic1/playfield_dma_start_shiftreg_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">playfield_dma_start_shiftreg_reg[4:0]</obj_property>
+      <obj_property name="ObjectShortName">playfield_dma_start_shiftreg_reg[4:0]</obj_property>
+   </wvobject>
 </wave_config>
Index: common/tb_antic/antic_tb.vhd
===================================================================
--- common/tb_antic/antic_tb.vhd	(revision 301)
+++ common/tb_antic/antic_tb.vhd	(revision 302)
@@ -85,7 +85,7 @@
 	wait until cpu_shared_enable = '1';
 	cpu_wr_en <= '1';
 	cpu_addr <= x"d400";
-	cpu_data_in <= x"22";
+	cpu_data_in <= x"62";
 	wait until cpu_shared_enable = '0';
 	cpu_wr_en <= '0';
 
@@ -147,7 +147,7 @@
 --		fetch_data(15):= x"a5"; -- char6 data
 --		fetch_data(16):= x"12"; -- char8
 
-		fetch_data(0) := x"48";
+		fetch_data(0) := x"42";
 		fetch_data(1) := x"00";
 		fetch_data(2) := x"07";
 		fetch_data(3) := x"ff"; -- char1
Index: mcc216_5200/build.sh
===================================================================
--- mcc216_5200/build.sh	(revision 301)
+++ mcc216_5200/build.sh	(revision 302)
@@ -64,27 +64,27 @@
 	print "Building $variant\n";
 
 	my $dir = "build_$variant";
-	`rm -rf $dir`;
-	mkdir $dir;
-	`cp atari5200core_mcc.vhd $dir`;
-	`cp *pll*.* $dir`;
-	`cp sdram_ctrl_3_ports.v $dir`;
-	`cp zpu_rom.vhdl $dir`;
-	`cp atari5200core.sdc $dir`;
-	`mkdir $dir/common`;
-	`mkdir $dir/common/a8core`;
-	`mkdir $dir/common/components`;
-	`mkdir $dir/common/zpu`;
-	`mkdir $dir/svideo`;
-	`cp ../common/a8core/* ./$dir/common/a8core`;
-	`cp ../common/components/* ./$dir/common/components`;
-	mkdir "./$dir/common/components/usbhostslave";
-	`cp ../common/components/usbhostslave/trunk/RTL/*/*.v ./$dir/common/components/usbhostslave`;
-	`cp ../common/zpu/* ./$dir/common/zpu`;
-	`cp ./svideo/* ./$dir/svideo`;
+#	`rm -rf $dir`;
+#	mkdir $dir;
+#	`cp atari5200core_mcc.vhd $dir`;
+#	`cp *pll*.* $dir`;
+#	`cp sdram_ctrl_3_ports.v $dir`;
+#	`cp zpu_rom.vhdl $dir`;
+#	`cp atari5200core.sdc $dir`;
+#	`mkdir $dir/common`;
+#	`mkdir $dir/common/a8core`;
+#	`mkdir $dir/common/components`;
+#	`mkdir $dir/common/zpu`;
+#	`mkdir $dir/svideo`;
+#	`cp ../common/a8core/* ./$dir/common/a8core`;
+#	`cp ../common/components/* ./$dir/common/components`;
+#	mkdir "./$dir/common/components/usbhostslave";
+#	`cp ../common/components/usbhostslave/trunk/RTL/*/*.v ./$dir/common/components/usbhostslave`;
+#	`cp ../common/zpu/* ./$dir/common/zpu`;
+#	`cp ./svideo/* ./$dir/svideo`;
 
 	chdir $dir;
-	`../makeqsf ../atari5200core.qsf ./svideo ./common/a8core ./common/components ./common/zpu ./common/components/usbhostslave`;
+#	`../makeqsf ../atari5200core.qsf ./svideo ./common/a8core ./common/components ./common/zpu ./common/components/usbhostslave`;
 
 	foreach my $key (sort keys %{$variants{$variant}})
 	{
@@ -92,7 +92,7 @@
 		`echo set_parameter -name $key $val >> atari5200core.qsf`;
 	}
 
-	`quartus_sh --flow compile atari5200core > build.log 2> build.err`;
+#	`quartus_sh --flow compile atari5200core > build.log 2> build.err`;
 
 	`quartus_cpf --convert ../output_file.cof`;
 	my $vga = 1;
Index: mcc216_5200/output_file.cof
===================================================================
--- mcc216_5200/output_file.cof	(revision 301)
+++ mcc216_5200/output_file.cof	(revision 302)
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
 <cof>
 	<eprom_name>CFI_128Mb</eprom_name>
-	<output_filename>output_files/atari800core.rbf</output_filename>
+	<output_filename>output_files/atari5200core.rbf</output_filename>
 	<n_pages>1</n_pages>
 	<width>1</width>
 	<mode>0</mode>
@@ -9,7 +9,7 @@
 		<user_name>Page_0</user_name>
 		<page_flags>1</page_flags>
 		<bit0>
-			<sof_filename>output_files/atari800core.sof<compress_bitstream>1</compress_bitstream></sof_filename>
+			<sof_filename>output_files/atari5200core.sof<compress_bitstream>1</compress_bitstream></sof_filename>
 		</bit0>
 	</sof_data>
 	<version>5</version>
Index: sockit/altiobuf.cmp
===================================================================
--- sockit/altiobuf.cmp	(nonexistent)
+++ sockit/altiobuf.cmp	(revision 302)
@@ -0,0 +1,27 @@
+--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, the Altera Quartus II License Agreement,
+--the Altera MegaCore Function License Agreement, or other 
+--applicable license agreement, including, without limitation, 
+--that your use is for the sole purpose of programming logic 
+--devices manufactured by Altera and sold by Altera or its 
+--authorized distributors.  Please refer to the applicable 
+--agreement for further details.
+
+
+component altiobuf
+	PORT
+	(
+		datain		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		oe		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		oe_b		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		dataio		: INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+		dataio_b		: INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+		dataout		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+end component;
Index: sockit/altiobuf.qip
===================================================================
--- sockit/altiobuf.qip	(nonexistent)
+++ sockit/altiobuf.qip	(revision 302)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTIOBUF"
+set_global_assignment -name IP_TOOL_VERSION "14.0"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altiobuf.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altiobuf.cmp"]
Index: sockit/altiobuf.vhd
===================================================================
--- sockit/altiobuf.vhd	(nonexistent)
+++ sockit/altiobuf.vhd	(revision 302)
@@ -0,0 +1,279 @@
+-- megafunction wizard: %ALTIOBUF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altiobuf_bidir 
+
+-- ============================================================
+-- File Name: altiobuf.vhd
+-- Megafunction Name(s):
+-- 			altiobuf_bidir
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 14.0.0 Build 200 06/17/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, the Altera Quartus II License Agreement,
+--the Altera MegaCore Function License Agreement, or other 
+--applicable license agreement, including, without limitation, 
+--that your use is for the sole purpose of programming logic 
+--devices manufactured by Altera and sold by Altera or its 
+--authorized distributors.  Please refer to the applicable 
+--agreement for further details.
+
+
+--altiobuf_bidir CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=4 OPEN_DRAIN_OUTPUT="FALSE" USE_DIFFERENTIAL_MODE="TRUE" USE_DYNAMIC_TERMINATION_CONTROL="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataio dataio_b dataout oe oe_b
+--VERSION_BEGIN 14.0 cbx_altiobuf_bidir 2014:06:05:09:45:41:SJ cbx_mgl 2014:06:05:10:17:12:SJ cbx_stratixiii 2014:06:05:09:45:41:SJ cbx_stratixv 2014:06:05:09:45:41:SJ  VERSION_END
+
+ LIBRARY cyclonev;
+ USE cyclonev.all;
+
+--synthesis_resources = cyclonev_io_ibuf 4 cyclonev_io_obuf 8 cyclonev_pseudo_diff_out 4 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  altiobuf_iobuf_bidir_lup IS 
+	 PORT 
+	 ( 
+		 datain	:	IN  STD_LOGIC_VECTOR (3 DOWNTO 0);
+		 dataio	:	INOUT  STD_LOGIC_VECTOR (3 DOWNTO 0);
+		 dataio_b	:	INOUT  STD_LOGIC_VECTOR (3 DOWNTO 0);
+		 dataout	:	OUT  STD_LOGIC_VECTOR (3 DOWNTO 0);
+		 oe	:	IN  STD_LOGIC_VECTOR (3 DOWNTO 0);
+		 oe_b	:	IN  STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1')
+	 ); 
+ END altiobuf_iobuf_bidir_lup;
+
+ ARCHITECTURE RTL OF altiobuf_iobuf_bidir_lup IS
+
+	 SIGNAL  wire_ibufa_i	:	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 SIGNAL  wire_ibufa_ibar	:	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 SIGNAL  wire_ibufa_o	:	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 SIGNAL  wire_obuf_ba_o	:	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 SIGNAL  wire_obuf_ba_oe	:	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 SIGNAL  wire_obufa_o	:	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 SIGNAL  wire_obufa_oe	:	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 SIGNAL  wire_pseudo_diffa_w_lg_oebout3w	:	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 SIGNAL  wire_pseudo_diffa_w_lg_oeout2w	:	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 SIGNAL  wire_pseudo_diffa_i	:	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 SIGNAL  wire_pseudo_diffa_o	:	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 SIGNAL  wire_pseudo_diffa_obar	:	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 SIGNAL  wire_pseudo_diffa_oebout	:	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 SIGNAL  wire_pseudo_diffa_oein	:	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 SIGNAL  wire_pseudo_diffa_oeout	:	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 SIGNAL  wire_w_lg_oe1w	:	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 COMPONENT  cyclonev_io_ibuf
+	 GENERIC 
+	 (
+		bus_hold	:	STRING := "false";
+		differential_mode	:	STRING := "false";
+		simulate_z_as	:	STRING := "z";
+		lpm_type	:	STRING := "cyclonev_io_ibuf"
+	 );
+	 PORT
+	 ( 
+		dynamicterminationcontrol	:	IN STD_LOGIC := '0';
+		i	:	IN STD_LOGIC := '0';
+		ibar	:	IN STD_LOGIC := '0';
+		o	:	OUT STD_LOGIC
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  cyclonev_io_obuf
+	 GENERIC 
+	 (
+		bus_hold	:	STRING := "false";
+		open_drain_output	:	STRING := "false";
+		shift_series_termination_control	:	STRING := "false";
+		lpm_type	:	STRING := "cyclonev_io_obuf"
+	 );
+	 PORT
+	 ( 
+		dynamicterminationcontrol	:	IN STD_LOGIC := '0';
+		i	:	IN STD_LOGIC := '0';
+		o	:	OUT STD_LOGIC;
+		obar	:	OUT STD_LOGIC;
+		oe	:	IN STD_LOGIC := '1';
+		parallelterminationcontrol	:	IN STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
+		seriesterminationcontrol	:	IN STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0')
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  cyclonev_pseudo_diff_out
+	 PORT
+	 ( 
+		dtc	:	OUT STD_LOGIC;
+		dtcbar	:	OUT STD_LOGIC;
+		dtcin	:	IN STD_LOGIC := '0';
+		i	:	IN STD_LOGIC := '0';
+		o	:	OUT STD_LOGIC;
+		obar	:	OUT STD_LOGIC;
+		oebout	:	OUT STD_LOGIC;
+		oein	:	IN STD_LOGIC := '0';
+		oeout	:	OUT STD_LOGIC
+	 ); 
+	 END COMPONENT;
+ BEGIN
+
+	loop0 : FOR i IN 0 TO 3 GENERATE 
+		wire_w_lg_oe1w(i) <= NOT oe(i);
+	END GENERATE loop0;
+	dataio <= wire_obufa_o;
+	dataio_b <= wire_obuf_ba_o;
+	dataout <= wire_ibufa_o;
+	wire_ibufa_i <= dataio;
+	wire_ibufa_ibar <= dataio_b;
+	loop1 : FOR i IN 0 TO 3 GENERATE 
+	  ibufa :  cyclonev_io_ibuf
+	  GENERIC MAP (
+		bus_hold => "false",
+		differential_mode => "true"
+	  )
+	  PORT MAP ( 
+		i => wire_ibufa_i(i),
+		ibar => wire_ibufa_ibar(i),
+		o => wire_ibufa_o(i)
+	  );
+	END GENERATE loop1;
+	wire_obuf_ba_oe <= wire_pseudo_diffa_w_lg_oebout3w;
+	loop2 : FOR i IN 0 TO 3 GENERATE 
+	  obuf_ba :  cyclonev_io_obuf
+	  GENERIC MAP (
+		bus_hold => "false",
+		open_drain_output => "false"
+	  )
+	  PORT MAP ( 
+		i => wire_pseudo_diffa_obar(i),
+		o => wire_obuf_ba_o(i),
+		oe => wire_obuf_ba_oe(i)
+	  );
+	END GENERATE loop2;
+	wire_obufa_oe <= wire_pseudo_diffa_w_lg_oeout2w;
+	loop3 : FOR i IN 0 TO 3 GENERATE 
+	  obufa :  cyclonev_io_obuf
+	  GENERIC MAP (
+		bus_hold => "false",
+		open_drain_output => "false"
+	  )
+	  PORT MAP ( 
+		i => wire_pseudo_diffa_o(i),
+		o => wire_obufa_o(i),
+		oe => wire_obufa_oe(i)
+	  );
+	END GENERATE loop3;
+	loop4 : FOR i IN 0 TO 3 GENERATE 
+		wire_pseudo_diffa_w_lg_oebout3w(i) <= NOT wire_pseudo_diffa_oebout(i);
+	END GENERATE loop4;
+	loop5 : FOR i IN 0 TO 3 GENERATE 
+		wire_pseudo_diffa_w_lg_oeout2w(i) <= NOT wire_pseudo_diffa_oeout(i);
+	END GENERATE loop5;
+	wire_pseudo_diffa_i <= datain;
+	wire_pseudo_diffa_oein <= wire_w_lg_oe1w;
+	loop6 : FOR i IN 0 TO 3 GENERATE 
+	  pseudo_diffa :  cyclonev_pseudo_diff_out
+	  PORT MAP ( 
+		i => wire_pseudo_diffa_i(i),
+		o => wire_pseudo_diffa_o(i),
+		obar => wire_pseudo_diffa_obar(i),
+		oebout => wire_pseudo_diffa_oebout(i),
+		oein => wire_pseudo_diffa_oein(i),
+		oeout => wire_pseudo_diffa_oeout(i)
+	  );
+	END GENERATE loop6;
+
+ END RTL; --altiobuf_iobuf_bidir_lup
+--VALID FILE
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY altiobuf IS
+	PORT
+	(
+		datain		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		oe		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		oe_b		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		dataio		: INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+		dataio_b		: INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+		dataout		: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+END altiobuf;
+
+
+ARCHITECTURE RTL OF altiobuf IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (3 DOWNTO 0);
+
+
+
+	COMPONENT altiobuf_iobuf_bidir_lup
+	PORT (
+			datain	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+			oe	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+			oe_b	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+			dataout	: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+			dataio	: INOUT STD_LOGIC_VECTOR (3 DOWNTO 0);
+			dataio_b	: INOUT STD_LOGIC_VECTOR (3 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	dataout    <= sub_wire0(3 DOWNTO 0);
+
+	altiobuf_iobuf_bidir_lup_component : altiobuf_iobuf_bidir_lup
+	PORT MAP (
+		datain => datain,
+		oe => oe,
+		oe_b => oe_b,
+		dataout => sub_wire0,
+		dataio => dataio,
+		dataio_b => dataio_b
+	);
+
+
+
+END RTL;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+-- Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
+-- Retrieval info: CONSTANT: left_shift_series_termination_control STRING "FALSE"
+-- Retrieval info: CONSTANT: number_of_channels NUMERIC "4"
+-- Retrieval info: CONSTANT: open_drain_output STRING "FALSE"
+-- Retrieval info: CONSTANT: use_differential_mode STRING "TRUE"
+-- Retrieval info: CONSTANT: use_dynamic_termination_control STRING "FALSE"
+-- Retrieval info: CONSTANT: use_termination_control STRING "FALSE"
+-- Retrieval info: USED_PORT: datain 0 0 4 0 INPUT NODEFVAL "datain[3..0]"
+-- Retrieval info: USED_PORT: dataio 0 0 4 0 BIDIR NODEFVAL "dataio[3..0]"
+-- Retrieval info: USED_PORT: dataio_b 0 0 4 0 BIDIR NODEFVAL "dataio_b[3..0]"
+-- Retrieval info: USED_PORT: dataout 0 0 4 0 OUTPUT NODEFVAL "dataout[3..0]"
+-- Retrieval info: USED_PORT: oe 0 0 4 0 INPUT NODEFVAL "oe[3..0]"
+-- Retrieval info: USED_PORT: oe_b 0 0 4 0 INPUT NODEFVAL "oe_b[3..0]"
+-- Retrieval info: CONNECT: @datain 0 0 4 0 datain 0 0 4 0
+-- Retrieval info: CONNECT: @oe 0 0 4 0 oe 0 0 4 0
+-- Retrieval info: CONNECT: @oe_b 0 0 4 0 oe_b 0 0 4 0
+-- Retrieval info: CONNECT: dataio 0 0 4 0 @dataio 0 0 4 0
+-- Retrieval info: CONNECT: dataio_b 0 0 4 0 @dataio_b 0 0 4 0
+-- Retrieval info: CONNECT: dataout 0 0 4 0 @dataout 0 0 4 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: sockit/altiobufo.cmp
===================================================================
--- sockit/altiobufo.cmp	(nonexistent)
+++ sockit/altiobufo.cmp	(revision 302)
@@ -0,0 +1,26 @@
+--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, the Altera Quartus II License Agreement,
+--the Altera MegaCore Function License Agreement, or other 
+--applicable license agreement, including, without limitation, 
+--that your use is for the sole purpose of programming logic 
+--devices manufactured by Altera and sold by Altera or its 
+--authorized distributors.  Please refer to the applicable 
+--agreement for further details.
+
+
+component altiobufo
+	PORT
+	(
+		datain		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+		oe		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+		oe_b		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+		dataout		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
+		dataout_b		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
+	);
+end component;
Index: sockit/altiobufo.qip
===================================================================
--- sockit/altiobufo.qip	(nonexistent)
+++ sockit/altiobufo.qip	(revision 302)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTIOBUF"
+set_global_assignment -name IP_TOOL_VERSION "14.0"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altiobufo.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altiobufo.cmp"]
Index: sockit/altiobufo.vhd
===================================================================
--- sockit/altiobufo.vhd	(nonexistent)
+++ sockit/altiobufo.vhd	(revision 302)
@@ -0,0 +1,230 @@
+-- megafunction wizard: %ALTIOBUF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altiobuf_out 
+
+-- ============================================================
+-- File Name: altiobufo.vhd
+-- Megafunction Name(s):
+-- 			altiobuf_out
+--
+-- Simulation Library Files(s):
+-- 			cyclonev
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 14.0.0 Build 200 06/17/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, the Altera Quartus II License Agreement,
+--the Altera MegaCore Function License Agreement, or other 
+--applicable license agreement, including, without limitation, 
+--that your use is for the sole purpose of programming logic 
+--devices manufactured by Altera and sold by Altera or its 
+--authorized distributors.  Please refer to the applicable 
+--agreement for further details.
+
+
+--altiobuf_out CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" LEFT_SHIFT_SERIES_TERMINATION_CONTROL="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="TRUE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b oe oe_b
+--VERSION_BEGIN 14.0 cbx_altiobuf_out 2014:06:05:09:45:41:SJ cbx_mgl 2014:06:05:10:17:12:SJ cbx_stratixiii 2014:06:05:09:45:41:SJ cbx_stratixv 2014:06:05:09:45:41:SJ  VERSION_END
+
+ LIBRARY cyclonev;
+ USE cyclonev.all;
+
+--synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  altiobufo_iobuf_out_h5u IS 
+	 PORT 
+	 ( 
+		 datain	:	IN  STD_LOGIC_VECTOR (0 DOWNTO 0);
+		 dataout	:	OUT  STD_LOGIC_VECTOR (0 DOWNTO 0);
+		 dataout_b	:	OUT  STD_LOGIC_VECTOR (0 DOWNTO 0);
+		 oe	:	IN  STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '1');
+		 oe_b	:	IN  STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '1')
+	 ); 
+ END altiobufo_iobuf_out_h5u;
+
+ ARCHITECTURE RTL OF altiobufo_iobuf_out_h5u IS
+
+	 SIGNAL  wire_obuf_ba_o	:	STD_LOGIC;
+	 SIGNAL  wire_obuf_ba_oe	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pseudo_diffa_w_lg_oebout3w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_obufa_o	:	STD_LOGIC;
+	 SIGNAL  wire_obufa_oe	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pseudo_diffa_w_lg_oeout2w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pseudo_diffa_o	:	STD_LOGIC;
+	 SIGNAL  wire_pseudo_diffa_obar	:	STD_LOGIC;
+	 SIGNAL  wire_pseudo_diffa_oebout	:	STD_LOGIC;
+	 SIGNAL  wire_pseudo_diffa_oein	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_oe_w1w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_pseudo_diffa_oeout	:	STD_LOGIC;
+	 SIGNAL  oe_w :	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 COMPONENT  cyclonev_io_obuf
+	 GENERIC 
+	 (
+		bus_hold	:	STRING := "false";
+		open_drain_output	:	STRING := "false";
+		shift_series_termination_control	:	STRING := "false";
+		lpm_type	:	STRING := "cyclonev_io_obuf"
+	 );
+	 PORT
+	 ( 
+		dynamicterminationcontrol	:	IN STD_LOGIC := '0';
+		i	:	IN STD_LOGIC := '0';
+		o	:	OUT STD_LOGIC;
+		obar	:	OUT STD_LOGIC;
+		oe	:	IN STD_LOGIC := '1';
+		parallelterminationcontrol	:	IN STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
+		seriesterminationcontrol	:	IN STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0')
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  cyclonev_pseudo_diff_out
+	 PORT
+	 ( 
+		dtc	:	OUT STD_LOGIC;
+		dtcbar	:	OUT STD_LOGIC;
+		dtcin	:	IN STD_LOGIC := '0';
+		i	:	IN STD_LOGIC := '0';
+		o	:	OUT STD_LOGIC;
+		obar	:	OUT STD_LOGIC;
+		oebout	:	OUT STD_LOGIC;
+		oein	:	IN STD_LOGIC := '0';
+		oeout	:	OUT STD_LOGIC
+	 ); 
+	 END COMPONENT;
+ BEGIN
+
+	dataout(0) <= wire_obufa_o;
+	dataout_b(0) <= wire_obuf_ba_o;
+	oe_w <= oe;
+	wire_obuf_ba_oe <= wire_pseudo_diffa_w_lg_oebout3w;
+	wire_pseudo_diffa_w_lg_oebout3w(0) <= NOT wire_pseudo_diffa_oebout;
+	obuf_ba :  cyclonev_io_obuf
+	  GENERIC MAP (
+		bus_hold => "false",
+		open_drain_output => "false"
+	  )
+	  PORT MAP ( 
+		i => wire_pseudo_diffa_obar,
+		o => wire_obuf_ba_o,
+		oe => wire_obuf_ba_oe(0)
+	  );
+	wire_obufa_oe <= wire_pseudo_diffa_w_lg_oeout2w;
+	wire_pseudo_diffa_w_lg_oeout2w(0) <= NOT wire_pseudo_diffa_oeout;
+	obufa :  cyclonev_io_obuf
+	  GENERIC MAP (
+		bus_hold => "false",
+		open_drain_output => "false"
+	  )
+	  PORT MAP ( 
+		i => wire_pseudo_diffa_o,
+		o => wire_obufa_o,
+		oe => wire_obufa_oe(0)
+	  );
+	wire_pseudo_diffa_oein <= wire_w_lg_oe_w1w;
+	wire_w_lg_oe_w1w(0) <= NOT oe_w(0);
+	pseudo_diffa :  cyclonev_pseudo_diff_out
+	  PORT MAP ( 
+		i => datain(0),
+		o => wire_pseudo_diffa_o,
+		obar => wire_pseudo_diffa_obar,
+		oebout => wire_pseudo_diffa_oebout,
+		oein => wire_pseudo_diffa_oein(0),
+		oeout => wire_pseudo_diffa_oeout
+	  );
+
+ END RTL; --altiobufo_iobuf_out_h5u
+--VALID FILE
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY altiobufo IS
+	PORT
+	(
+		datain		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+		oe		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+		oe_b		: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+		dataout		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
+		dataout_b		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
+	);
+END altiobufo;
+
+
+ARCHITECTURE RTL OF altiobufo IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altiobufo_iobuf_out_h5u
+	PORT (
+			datain	: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+			oe	: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+			oe_b	: IN STD_LOGIC_VECTOR (0 DOWNTO 0);
+			dataout	: OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
+			dataout_b	: OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	dataout    <= sub_wire0(0 DOWNTO 0);
+	dataout_b    <= sub_wire1(0 DOWNTO 0);
+
+	altiobufo_iobuf_out_h5u_component : altiobufo_iobuf_out_h5u
+	PORT MAP (
+		datain => datain,
+		oe => oe,
+		oe_b => oe_b,
+		dataout => sub_wire0,
+		dataout_b => sub_wire1
+	);
+
+
+
+END RTL;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
+-- Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
+-- Retrieval info: CONSTANT: left_shift_series_termination_control STRING "FALSE"
+-- Retrieval info: CONSTANT: number_of_channels NUMERIC "1"
+-- Retrieval info: CONSTANT: open_drain_output STRING "FALSE"
+-- Retrieval info: CONSTANT: pseudo_differential_mode STRING "TRUE"
+-- Retrieval info: CONSTANT: use_differential_mode STRING "TRUE"
+-- Retrieval info: CONSTANT: use_oe STRING "TRUE"
+-- Retrieval info: CONSTANT: use_termination_control STRING "FALSE"
+-- Retrieval info: USED_PORT: datain 0 0 1 0 INPUT NODEFVAL "datain[0..0]"
+-- Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
+-- Retrieval info: USED_PORT: dataout_b 0 0 1 0 OUTPUT NODEFVAL "dataout_b[0..0]"
+-- Retrieval info: USED_PORT: oe 0 0 1 0 INPUT NODEFVAL "oe[0..0]"
+-- Retrieval info: USED_PORT: oe_b 0 0 1 0 INPUT NODEFVAL "oe_b[0..0]"
+-- Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 1 0
+-- Retrieval info: CONNECT: @oe 0 0 1 0 oe 0 0 1 0
+-- Retrieval info: CONNECT: @oe_b 0 0 1 0 oe_b 0 0 1 0
+-- Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
+-- Retrieval info: CONNECT: dataout_b 0 0 1 0 @dataout_b 0 0 1 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobufo.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobufo.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobufo.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobufo.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobufo_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: cyclonev
Index: sockit/atari800core.htm
===================================================================
--- sockit/atari800core.htm	(nonexistent)
+++ sockit/atari800core.htm	(revision 302)
@@ -0,0 +1,1460 @@
+<html>
+<body>
+<h1 align="center">Cylone V SoC FPGA Board Configuration</h1>
+<br />
+<br />
+<h2 align="left">Pin Assignments:</h2>
+<ul>
+<a href="#CLOCK"><li>CLOCK</li></a>
+<br />
+<a href="#LED"><li>LED</li></a>
+<br />
+<a href="#KEY"><li>KEY</li></a>
+<br />
+<a href="#SW"><li>SW</li></a>
+<br />
+<a href="#Si5338"><li>Si5338</li></a>
+<br />
+<a href="#Temperature"><li>Temperature</li></a>
+<br />
+<a href="#VGA"><li>VGA</li></a>
+<br />
+<a href="#Audio"><li>Audio</li></a>
+<br />
+<a href="#I2C for Audio "><li>I2C for Audio </li></a>
+<br />
+<a href="#SDRAM"><li>SDRAM</li></a>
+<br />
+<a href="#HSMC"><li>HSMC</li></a>
+<br />
+</ul>
+<br />
+<br />
+<br />
+<h2 align="left">Pin Assignment Table:</h2>
+<h2><a name="CLOCK"></a></h2><table border="3">
+<caption  align="left">CLOCK</caption>
+<br />
+<br />
+<tr>
+   <th align="left" bgcolor="Khaki">Name</th>
+   <th align="left" bgcolor="Khaki">Location</th>
+   <th align="left" bgcolor="Khaki">Direction</th>
+   <th align="left" bgcolor="Khaki">Standard</th>
+</tr>
+<tr>
+   <td align="left">OSC_50_B3B</td>
+   <td align="left">AF14</td>
+   <td align="left">input </td>
+   <td align="left">1.5 V</td>
+</tr>
+<tr>
+   <td align="left">OSC_50_B4A</td>
+   <td align="left">AA16</td>
+   <td align="left">input </td>
+   <td align="left">1.5 V</td>
+</tr>
+<tr>
+   <td align="left">OSC_50_B5B</td>
+   <td align="left">Y26</td>
+   <td align="left">input </td>
+   <td align="left">2.5 V</td>
+</tr>
+<tr>
+   <td align="left">OSC_50_B8A</td>
+   <td align="left">K14</td>
+   <td align="left">input </td>
+   <td align="left">2.5 V</td>
+</tr>
+</table>
+<h2><a name="LED"></a></h2><table border="3">
+<caption  align="left">LED</caption>
+<br />
+<br />
+<tr>
+   <th align="left" bgcolor="Khaki">Name</th>
+   <th align="left" bgcolor="Khaki">Location</th>
+   <th align="left" bgcolor="Khaki">Direction</th>
+   <th align="left" bgcolor="Khaki">Standard</th>
+</tr>
+<tr>
+   <td align="left">LED[0]</td>
+   <td align="left">AF10</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">LED[1]</td>
+   <td align="left">AD10</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">LED[2]</td>
+   <td align="left">AE11</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">LED[3]</td>
+   <td align="left">AD7</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+</table>
+<h2><a name="KEY"></a></h2><table border="3">
+<caption  align="left">KEY</caption>
+<br />
+<br />
+<tr>
+   <th align="left" bgcolor="Khaki">Name</th>
+   <th align="left" bgcolor="Khaki">Location</th>
+   <th align="left" bgcolor="Khaki">Direction</th>
+   <th align="left" bgcolor="Khaki">Standard</th>
+</tr>
+<tr>
+   <td align="left">KEY[0]</td>
+   <td align="left">AE9</td>
+   <td align="left">input </td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">KEY[1]</td>
+   <td align="left">AE12</td>
+   <td align="left">input </td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">KEY[2]</td>
+   <td align="left">AD9</td>
+   <td align="left">input </td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">KEY[3]</td>
+   <td align="left">AD11</td>
+   <td align="left">input </td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">RESET_n</td>
+   <td align="left">AD27</td>
+   <td align="left">input </td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+</table>
+<h2><a name="SW"></a></h2><table border="3">
+<caption  align="left">SW</caption>
+<br />
+<br />
+<tr>
+   <th align="left" bgcolor="Khaki">Name</th>
+   <th align="left" bgcolor="Khaki">Location</th>
+   <th align="left" bgcolor="Khaki">Direction</th>
+   <th align="left" bgcolor="Khaki">Standard</th>
+</tr>
+<tr>
+   <td align="left">SW[0]</td>
+   <td align="left">W25</td>
+   <td align="left">input </td>
+   <td align="left">2.5 V</td>
+</tr>
+<tr>
+   <td align="left">SW[1]</td>
+   <td align="left">V25</td>
+   <td align="left">input </td>
+   <td align="left">2.5 V</td>
+</tr>
+<tr>
+   <td align="left">SW[2]</td>
+   <td align="left">AC28</td>
+   <td align="left">input </td>
+   <td align="left">2.5 V</td>
+</tr>
+<tr>
+   <td align="left">SW[3]</td>
+   <td align="left">AC29</td>
+   <td align="left">input </td>
+   <td align="left">2.5 V</td>
+</tr>
+</table>
+<h2><a name="Si5338"></a></h2><table border="3">
+<caption  align="left">Si5338</caption>
+<br />
+<br />
+<tr>
+   <th align="left" bgcolor="Khaki">Name</th>
+   <th align="left" bgcolor="Khaki">Location</th>
+   <th align="left" bgcolor="Khaki">Direction</th>
+   <th align="left" bgcolor="Khaki">Standard</th>
+</tr>
+<tr>
+   <td align="left">SI5338_SCL</td>
+   <td align="left">AE26</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">SI5338_SDA</td>
+   <td align="left">AJ29</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+</table>
+<h2><a name="Temperature"></a></h2><table border="3">
+<caption  align="left">Temperature</caption>
+<br />
+<br />
+<tr>
+   <th align="left" bgcolor="Khaki">Name</th>
+   <th align="left" bgcolor="Khaki">Location</th>
+   <th align="left" bgcolor="Khaki">Direction</th>
+   <th align="left" bgcolor="Khaki">Standard</th>
+</tr>
+<tr>
+   <td align="left">TEMP_CS_n</td>
+   <td align="left">AF8</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">TEMP_DIN</td>
+   <td align="left">AG7</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">TEMP_DOUT</td>
+   <td align="left">AG1</td>
+   <td align="left">input </td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">TEMP_SCLK</td>
+   <td align="left">AF9</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+</table>
+<h2><a name="VGA"></a></h2><table border="3">
+<caption  align="left">VGA</caption>
+<br />
+<br />
+<tr>
+   <th align="left" bgcolor="Khaki">Name</th>
+   <th align="left" bgcolor="Khaki">Location</th>
+   <th align="left" bgcolor="Khaki">Direction</th>
+   <th align="left" bgcolor="Khaki">Standard</th>
+</tr>
+<tr>
+   <td align="left">VGA_HS</td>
+   <td align="left">AD12</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_VS</td>
+   <td align="left">AC12</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_SYNC_n</td>
+   <td align="left">AG2</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_CLK</td>
+   <td align="left">W20</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_BLANK_n</td>
+   <td align="left">AH3</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_R[0]</td>
+   <td align="left">AG5</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_R[1]</td>
+   <td align="left">AA12</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_R[2]</td>
+   <td align="left">AB12</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_R[3]</td>
+   <td align="left">AF6</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_R[4]</td>
+   <td align="left">AG6</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_R[5]</td>
+   <td align="left">AJ2</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_R[6]</td>
+   <td align="left">AH5</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_R[7]</td>
+   <td align="left">AJ1</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_G[0]</td>
+   <td align="left">Y21</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_G[1]</td>
+   <td align="left">AA25</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_G[2]</td>
+   <td align="left">AB26</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_G[3]</td>
+   <td align="left">AB22</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_G[4]</td>
+   <td align="left">AB23</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_G[5]</td>
+   <td align="left">AA24</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_G[6]</td>
+   <td align="left">AB25</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_G[7]</td>
+   <td align="left">AE27</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_B[0]</td>
+   <td align="left">AE28</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_B[1]</td>
+   <td align="left">Y23</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_B[2]</td>
+   <td align="left">Y24</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_B[3]</td>
+   <td align="left">AG28</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_B[4]</td>
+   <td align="left">AF28</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_B[5]</td>
+   <td align="left">V23</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_B[6]</td>
+   <td align="left">W24</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">VGA_B[7]</td>
+   <td align="left">AF29</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+</table>
+<h2><a name="Audio"></a></h2><table border="3">
+<caption  align="left">Audio</caption>
+<br />
+<br />
+<tr>
+   <th align="left" bgcolor="Khaki">Name</th>
+   <th align="left" bgcolor="Khaki">Location</th>
+   <th align="left" bgcolor="Khaki">Direction</th>
+   <th align="left" bgcolor="Khaki">Standard</th>
+</tr>
+<tr>
+   <td align="left">AUD_ADCLRCK</td>
+   <td align="left">AG30</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">AUD_ADCDAT</td>
+   <td align="left">AC27</td>
+   <td align="left">input </td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">AUD_DACLRCK</td>
+   <td align="left">AH4</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">AUD_DACDAT</td>
+   <td align="left">AG3</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">AUD_XCK</td>
+   <td align="left">AC9</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">AUD_BCLK</td>
+   <td align="left">AE7</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">AUD_MUTE</td>
+   <td align="left">AD26</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+</table>
+<h2><a name="I2C for Audio "></a></h2><table border="3">
+<caption  align="left">I2C for Audio </caption>
+<br />
+<br />
+<tr>
+   <th align="left" bgcolor="Khaki">Name</th>
+   <th align="left" bgcolor="Khaki">Location</th>
+   <th align="left" bgcolor="Khaki">Direction</th>
+   <th align="left" bgcolor="Khaki">Standard</th>
+</tr>
+<tr>
+   <td align="left">AUD_I2C_SCLK</td>
+   <td align="left">AH30</td>
+   <td align="left">output</td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+<tr>
+   <td align="left">AUD_I2C_SDAT</td>
+   <td align="left">AF30</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+</tr>
+</table>
+<h2><a name="SDRAM"></a></h2><table border="3">
+<caption  align="left">SDRAM</caption>
+<br />
+<br />
+<tr>
+   <th align="left" bgcolor="Khaki">Name</th>
+   <th align="left" bgcolor="Khaki">Location</th>
+   <th align="left" bgcolor="Khaki">Direction</th>
+   <th align="left" bgcolor="Khaki">Standard</th>
+</tr>
+<tr>
+   <td align="left">DDR3_CK_p</td>
+   <td align="left">AA14</td>
+   <td align="left">output</td>
+   <td align="left">Differential 1.5-V SSTL Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_CK_n</td>
+   <td align="left">AA15</td>
+   <td align="left">output</td>
+   <td align="left">Differential 1.5-V SSTL Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQS_p[0]</td>
+   <td align="left">V16</td>
+   <td align="left">inout </td>
+   <td align="left">Differential 1.5-V SSTL Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQS_n[0]</td>
+   <td align="left">W16</td>
+   <td align="left">inout </td>
+   <td align="left">Differential 1.5-V SSTL Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQS_p[1]</td>
+   <td align="left">V17</td>
+   <td align="left">inout </td>
+   <td align="left">Differential 1.5-V SSTL Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQS_n[1]</td>
+   <td align="left">W17</td>
+   <td align="left">inout </td>
+   <td align="left">Differential 1.5-V SSTL Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQS_p[2]</td>
+   <td align="left">Y17</td>
+   <td align="left">inout </td>
+   <td align="left">Differential 1.5-V SSTL Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQS_n[2]</td>
+   <td align="left">AA18</td>
+   <td align="left">inout </td>
+   <td align="left">Differential 1.5-V SSTL Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQS_p[3]</td>
+   <td align="left">AC20</td>
+   <td align="left">inout </td>
+   <td align="left">Differential 1.5-V SSTL Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQS_n[3]</td>
+   <td align="left">AD19</td>
+   <td align="left">inout </td>
+   <td align="left">Differential 1.5-V SSTL Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_CKE</td>
+   <td align="left">AJ21</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_CS_n</td>
+   <td align="left">AB15</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_RESET_n</td>
+   <td align="left">AK21</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_WE_n</td>
+   <td align="left">AJ6</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_RAS_n</td>
+   <td align="left">AH8</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_CAS_n</td>
+   <td align="left">AH7</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_BA[0]</td>
+   <td align="left">AH10</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_BA[1]</td>
+   <td align="left">AJ11</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_BA[2]</td>
+   <td align="left">AK11</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DM[0]</td>
+   <td align="left">AH17</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DM[1]</td>
+   <td align="left">AG23</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DM[2]</td>
+   <td align="left">AK23</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DM[3]</td>
+   <td align="left">AJ27</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_ODT</td>
+   <td align="left">AE16</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_RZQ</td>
+   <td align="left">AG17</td>
+   <td align="left">input </td>
+   <td align="left">1.5 V</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[0]</td>
+   <td align="left">AF18</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[1]</td>
+   <td align="left">AE17</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[2]</td>
+   <td align="left">AG16</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[3]</td>
+   <td align="left">AF16</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[4]</td>
+   <td align="left">AH20</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[5]</td>
+   <td align="left">AG21</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[6]</td>
+   <td align="left">AJ16</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[7]</td>
+   <td align="left">AH18</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[8]</td>
+   <td align="left">AK18</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[9]</td>
+   <td align="left">AJ17</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[10]</td>
+   <td align="left">AG18</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[11]</td>
+   <td align="left">AK19</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[12]</td>
+   <td align="left">AG20</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[13]</td>
+   <td align="left">AF19</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[14]</td>
+   <td align="left">AJ20</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[15]</td>
+   <td align="left">AH24</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[16]</td>
+   <td align="left">AE19</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[17]</td>
+   <td align="left">AE18</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[18]</td>
+   <td align="left">AG22</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[19]</td>
+   <td align="left">AK22</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[20]</td>
+   <td align="left">AF21</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[21]</td>
+   <td align="left">AF20</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[22]</td>
+   <td align="left">AH23</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[23]</td>
+   <td align="left">AK24</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[24]</td>
+   <td align="left">AF24</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[25]</td>
+   <td align="left">AF23</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[26]</td>
+   <td align="left">AJ24</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[27]</td>
+   <td align="left">AK26</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[28]</td>
+   <td align="left">AE23</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[29]</td>
+   <td align="left">AE22</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[30]</td>
+   <td align="left">AG25</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_DQ[31]</td>
+   <td align="left">AK27</td>
+   <td align="left">inout </td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_A[0]</td>
+   <td align="left">AJ14</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_A[1]</td>
+   <td align="left">AK14</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_A[2]</td>
+   <td align="left">AH12</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_A[3]</td>
+   <td align="left">AJ12</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_A[4]</td>
+   <td align="left">AG15</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_A[5]</td>
+   <td align="left">AH15</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_A[6]</td>
+   <td align="left">AK12</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_A[7]</td>
+   <td align="left">AK13</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_A[8]</td>
+   <td align="left">AH13</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_A[9]</td>
+   <td align="left">AH14</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_A[10]</td>
+   <td align="left">AJ9</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_A[11]</td>
+   <td align="left">AK9</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_A[12]</td>
+   <td align="left">AK7</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_A[13]</td>
+   <td align="left">AK8</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+<tr>
+   <td align="left">DDR3_A[14]</td>
+   <td align="left">AG12</td>
+   <td align="left">output</td>
+   <td align="left">SSTL-15 Class I</td>
+</tr>
+</table>
+<h2><a name="HSMC"></a></h2><table border="3">
+<caption  align="left">HSMC connect to HTG - HSMC to PIO Adaptor</caption>
+<br />
+<br />
+<tr>
+   <th align="left" bgcolor="Khaki">Name</th>
+   <th align="left" bgcolor="Khaki">Location</th>
+   <th align="left" bgcolor="Khaki">Direction</th>
+   <th align="left" bgcolor="Khaki">Standard</th>
+   <th align="left" bgcolor="Khaki">HSMC Pin Index</th>
+</tr>
+<tr>
+   <td align="left">GPIO1_35</td>
+   <td align="left">A9</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">47</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_31</td>
+   <td align="left">G12</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">48</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_33</td>
+   <td align="left">A8</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">49</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_29</td>
+   <td align="left">G11</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">50</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_34</td>
+   <td align="left">E8</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">53</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_27</td>
+   <td align="left">K12</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">54</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_32</td>
+   <td align="left">D7</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">55</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_25</td>
+   <td align="left">J12</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">56</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_30</td>
+   <td align="left">G7</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">59</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_23</td>
+   <td align="left">G10</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">60</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_28</td>
+   <td align="left">F6</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">61</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_21</td>
+   <td align="left">F10</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">62</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_26</td>
+   <td align="left">D6</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">65</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_19</td>
+   <td align="left">J10</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">66</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_24</td>
+   <td align="left">C5</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">67</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_17</td>
+   <td align="left">J9</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">68</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_22</td>
+   <td align="left">D5</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">71</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_15</td>
+   <td align="left">K7</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">72</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_20</td>
+   <td align="left">C4</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">73</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_13</td>
+   <td align="left">K8</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">74</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_14</td>
+   <td align="left">E3</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">77</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_11</td>
+   <td align="left">J7</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">78</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_12</td>
+   <td align="left">E2</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">79</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_9</td>
+   <td align="left">H7</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">80</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_10</td>
+   <td align="left">E4</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">83</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_7</td>
+   <td align="left">H8</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">84</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_8</td>
+   <td align="left">D4</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">85</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_5</td>
+   <td align="left">G8</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">86</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_6</td>
+   <td align="left">C3</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">89</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_3</td>
+   <td align="left">F9</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">90</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_4</td>
+   <td align="left">B3</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">91</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_1</td>
+   <td align="left">F8</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">92</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_18</td>
+   <td align="left">E7</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">95</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_2</td>
+   <td align="left">AA26</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">96</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_16</td>
+   <td align="left">E6</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">97</td>
+</tr>
+<tr>
+   <td align="left">GPIO1_0</td>
+   <td align="left">AB27</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">98</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_35</td>
+   <td align="left">D2</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">107</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_31</td>
+   <td align="left">B6</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">108</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_33</td>
+   <td align="left">C2</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">109</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_29</td>
+   <td align="left">B5</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">110</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_34</td>
+   <td align="left">B2</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">113</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_27</td>
+   <td align="left">E9</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">114</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_32</td>
+   <td align="left">B1</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">115</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_25</td>
+   <td align="left">D9</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">116</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_30</td>
+   <td align="left">A4</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">119</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_23</td>
+   <td align="left">E12</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">120</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_28</td>
+   <td align="left">A3</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">121</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_21</td>
+   <td align="left">D12</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">122</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_26</td>
+   <td align="left">A6</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">125</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_19</td>
+   <td align="left">D11</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">126</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_24</td>
+   <td align="left">A5</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">127</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_17</td>
+   <td align="left">D10</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">128</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_22</td>
+   <td align="left">C7</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">131</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_15</td>
+   <td align="left">C13</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">132</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_20</td>
+   <td align="left">B7</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">133</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_13</td>
+   <td align="left">B12</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">134</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_14</td>
+   <td align="left">C8</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">137</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_11</td>
+   <td align="left">F13</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">138</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_12</td>
+   <td align="left">B8</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">139</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_9</td>
+   <td align="left">E13</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">140</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_10</td>
+   <td align="left">C12</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">143</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_7</td>
+   <td align="left">H14</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">144</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_8</td>
+   <td align="left">B11</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">145</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_5</td>
+   <td align="left">G13</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">146</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_6</td>
+   <td align="left">B13</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">149</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_3</td>
+   <td align="left">F15</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">150</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_4</td>
+   <td align="left">A13</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">151</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_1</td>
+   <td align="left">F14</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">152</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_18</td>
+   <td align="left">A11</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">155</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_2</td>
+   <td align="left">H15</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">156</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_16</td>
+   <td align="left">A10</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">157</td>
+</tr>
+<tr>
+   <td align="left">GPIO0_0</td>
+   <td align="left">G15</td>
+   <td align="left">inout </td>
+   <td align="left">3.3-V LVTTL</td>
+   <td align="left">158</td>
+</tr>
+</table>
+</html>
+</body>
Index: sockit/atari800core.qpf
===================================================================
--- sockit/atari800core.qpf	(nonexistent)
+++ sockit/atari800core.qpf	(revision 302)
@@ -0,0 +1,6 @@
+DATE = "13:37:44 December 14, 2014"
+QUARTUS_VERSION = "13.1"
+
+# Revisions
+
+PROJECT_REVISION = "atari800core"
Index: sockit/atari800core.qsf
===================================================================
--- sockit/atari800core.qsf	(nonexistent)
+++ sockit/atari800core.qsf	(revision 302)
@@ -0,0 +1,481 @@
+#============================================================
+# Build by Terasic System Builder
+#============================================================
+
+set_global_assignment -name FAMILY "Cyclone V"
+set_global_assignment -name DEVICE 5CSXFC6D6F31C8ES
+set_global_assignment -name TOP_LEVEL_ENTITY "atari800core_sockit"
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.1"
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:37:44 DECEMBER 14,2014"
+set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 896
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8_H6
+set_global_assignment -name SDC_FILE atari800core.SDC
+
+#============================================================
+# CLOCK
+#============================================================
+set_location_assignment PIN_AF14 -to OSC_50_B3B
+set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B3B
+set_location_assignment PIN_AA16 -to OSC_50_B4A
+set_instance_assignment -name IO_STANDARD "1.5 V" -to OSC_50_B4A
+set_location_assignment PIN_Y26 -to OSC_50_B5B
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_B5B
+set_location_assignment PIN_K14 -to OSC_50_B8A
+set_instance_assignment -name IO_STANDARD "2.5 V" -to OSC_50_B8A
+
+#============================================================
+# LED
+#============================================================
+set_location_assignment PIN_AF10 -to LED[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
+set_location_assignment PIN_AD10 -to LED[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
+set_location_assignment PIN_AE11 -to LED[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
+set_location_assignment PIN_AD7 -to LED[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
+
+#============================================================
+# KEY
+#============================================================
+set_location_assignment PIN_AE9 -to KEY[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
+set_location_assignment PIN_AE12 -to KEY[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
+set_location_assignment PIN_AD9 -to KEY[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2]
+set_location_assignment PIN_AD11 -to KEY[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3]
+set_location_assignment PIN_AD27 -to RESET_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to RESET_n
+
+#============================================================
+# SW
+#============================================================
+set_location_assignment PIN_W25 -to SW[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[0]
+set_location_assignment PIN_V25 -to SW[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[1]
+set_location_assignment PIN_AC28 -to SW[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[2]
+set_location_assignment PIN_AC29 -to SW[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to SW[3]
+
+#============================================================
+# Si5338
+#============================================================
+set_location_assignment PIN_AE26 -to SI5338_SCL
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SI5338_SCL
+set_location_assignment PIN_AJ29 -to SI5338_SDA
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SI5338_SDA
+
+#============================================================
+# Temperature
+#============================================================
+set_location_assignment PIN_AF8 -to TEMP_CS_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_CS_n
+set_location_assignment PIN_AG7 -to TEMP_DIN
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_DIN
+set_location_assignment PIN_AG1 -to TEMP_DOUT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_DOUT
+set_location_assignment PIN_AF9 -to TEMP_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TEMP_SCLK
+
+#============================================================
+# VGA
+#============================================================
+set_location_assignment PIN_AD12 -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS
+set_location_assignment PIN_AC12 -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS
+set_location_assignment PIN_AG2 -to VGA_SYNC_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_n
+set_location_assignment PIN_W20 -to VGA_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK
+set_location_assignment PIN_AH3 -to VGA_BLANK_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_n
+set_location_assignment PIN_AG5 -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0]
+set_location_assignment PIN_AA12 -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1]
+set_location_assignment PIN_AB12 -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2]
+set_location_assignment PIN_AF6 -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3]
+set_location_assignment PIN_AG6 -to VGA_R[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4]
+set_location_assignment PIN_AJ2 -to VGA_R[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5]
+set_location_assignment PIN_AH5 -to VGA_R[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6]
+set_location_assignment PIN_AJ1 -to VGA_R[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7]
+set_location_assignment PIN_Y21 -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0]
+set_location_assignment PIN_AA25 -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1]
+set_location_assignment PIN_AB26 -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2]
+set_location_assignment PIN_AB22 -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3]
+set_location_assignment PIN_AB23 -to VGA_G[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4]
+set_location_assignment PIN_AA24 -to VGA_G[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5]
+set_location_assignment PIN_AB25 -to VGA_G[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6]
+set_location_assignment PIN_AE27 -to VGA_G[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7]
+set_location_assignment PIN_AE28 -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0]
+set_location_assignment PIN_Y23 -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1]
+set_location_assignment PIN_Y24 -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2]
+set_location_assignment PIN_AG28 -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3]
+set_location_assignment PIN_AF28 -to VGA_B[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4]
+set_location_assignment PIN_V23 -to VGA_B[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5]
+set_location_assignment PIN_W24 -to VGA_B[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6]
+set_location_assignment PIN_AF29 -to VGA_B[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7]
+
+#============================================================
+# Audio
+#============================================================
+set_location_assignment PIN_AG30 -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK
+set_location_assignment PIN_AC27 -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT
+set_location_assignment PIN_AH4 -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK
+set_location_assignment PIN_AG3 -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT
+set_location_assignment PIN_AC9 -to AUD_XCK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK
+set_location_assignment PIN_AE7 -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK
+set_location_assignment PIN_AD26 -to AUD_MUTE
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_MUTE
+
+#============================================================
+# I2C for Audio 
+#============================================================
+set_location_assignment PIN_AH30 -to AUD_I2C_SCLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_I2C_SCLK
+set_location_assignment PIN_AF30 -to AUD_I2C_SDAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_I2C_SDAT
+
+#============================================================
+# SDRAM
+#============================================================
+set_location_assignment PIN_AA14 -to DDR3_CK_p
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to DDR3_CK_p
+set_location_assignment PIN_AA15 -to DDR3_CK_n
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to DDR3_CK_n
+set_location_assignment PIN_V16 -to DDR3_DQS_p[0]
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to DDR3_DQS_p[0]
+set_location_assignment PIN_W16 -to DDR3_DQS_n[0]
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to DDR3_DQS_n[0]
+set_location_assignment PIN_V17 -to DDR3_DQS_p[1]
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to DDR3_DQS_p[1]
+set_location_assignment PIN_W17 -to DDR3_DQS_n[1]
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to DDR3_DQS_n[1]
+set_location_assignment PIN_Y17 -to DDR3_DQS_p[2]
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to DDR3_DQS_p[2]
+set_location_assignment PIN_AA18 -to DDR3_DQS_n[2]
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to DDR3_DQS_n[2]
+set_location_assignment PIN_AC20 -to DDR3_DQS_p[3]
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to DDR3_DQS_p[3]
+set_location_assignment PIN_AD19 -to DDR3_DQS_n[3]
+set_instance_assignment -name IO_STANDARD "Differential 1.5-V SSTL Class I" -to DDR3_DQS_n[3]
+set_location_assignment PIN_AJ21 -to DDR3_CKE
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_CKE
+set_location_assignment PIN_AB15 -to DDR3_CS_n
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_CS_n
+set_location_assignment PIN_AK21 -to DDR3_RESET_n
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_RESET_n
+set_location_assignment PIN_AJ6 -to DDR3_WE_n
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_WE_n
+set_location_assignment PIN_AH8 -to DDR3_RAS_n
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_RAS_n
+set_location_assignment PIN_AH7 -to DDR3_CAS_n
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_CAS_n
+set_location_assignment PIN_AH10 -to DDR3_BA[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_BA[0]
+set_location_assignment PIN_AJ11 -to DDR3_BA[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_BA[1]
+set_location_assignment PIN_AK11 -to DDR3_BA[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_BA[2]
+set_location_assignment PIN_AH17 -to DDR3_DM[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DM[0]
+set_location_assignment PIN_AG23 -to DDR3_DM[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DM[1]
+set_location_assignment PIN_AK23 -to DDR3_DM[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DM[2]
+set_location_assignment PIN_AJ27 -to DDR3_DM[3]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DM[3]
+set_location_assignment PIN_AE16 -to DDR3_ODT
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_ODT
+set_location_assignment PIN_AG17 -to DDR3_RZQ
+set_instance_assignment -name IO_STANDARD "1.5 V" -to DDR3_RZQ
+set_location_assignment PIN_AF18 -to DDR3_DQ[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[0]
+set_location_assignment PIN_AE17 -to DDR3_DQ[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[1]
+set_location_assignment PIN_AG16 -to DDR3_DQ[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[2]
+set_location_assignment PIN_AF16 -to DDR3_DQ[3]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[3]
+set_location_assignment PIN_AH20 -to DDR3_DQ[4]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[4]
+set_location_assignment PIN_AG21 -to DDR3_DQ[5]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[5]
+set_location_assignment PIN_AJ16 -to DDR3_DQ[6]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[6]
+set_location_assignment PIN_AH18 -to DDR3_DQ[7]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[7]
+set_location_assignment PIN_AK18 -to DDR3_DQ[8]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[8]
+set_location_assignment PIN_AJ17 -to DDR3_DQ[9]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[9]
+set_location_assignment PIN_AG18 -to DDR3_DQ[10]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[10]
+set_location_assignment PIN_AK19 -to DDR3_DQ[11]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[11]
+set_location_assignment PIN_AG20 -to DDR3_DQ[12]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[12]
+set_location_assignment PIN_AF19 -to DDR3_DQ[13]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[13]
+set_location_assignment PIN_AJ20 -to DDR3_DQ[14]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[14]
+set_location_assignment PIN_AH24 -to DDR3_DQ[15]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[15]
+set_location_assignment PIN_AE19 -to DDR3_DQ[16]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[16]
+set_location_assignment PIN_AE18 -to DDR3_DQ[17]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[17]
+set_location_assignment PIN_AG22 -to DDR3_DQ[18]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[18]
+set_location_assignment PIN_AK22 -to DDR3_DQ[19]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[19]
+set_location_assignment PIN_AF21 -to DDR3_DQ[20]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[20]
+set_location_assignment PIN_AF20 -to DDR3_DQ[21]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[21]
+set_location_assignment PIN_AH23 -to DDR3_DQ[22]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[22]
+set_location_assignment PIN_AK24 -to DDR3_DQ[23]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[23]
+set_location_assignment PIN_AF24 -to DDR3_DQ[24]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[24]
+set_location_assignment PIN_AF23 -to DDR3_DQ[25]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[25]
+set_location_assignment PIN_AJ24 -to DDR3_DQ[26]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[26]
+set_location_assignment PIN_AK26 -to DDR3_DQ[27]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[27]
+set_location_assignment PIN_AE23 -to DDR3_DQ[28]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[28]
+set_location_assignment PIN_AE22 -to DDR3_DQ[29]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[29]
+set_location_assignment PIN_AG25 -to DDR3_DQ[30]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[30]
+set_location_assignment PIN_AK27 -to DDR3_DQ[31]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_DQ[31]
+set_location_assignment PIN_AJ14 -to DDR3_A[0]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_A[0]
+set_location_assignment PIN_AK14 -to DDR3_A[1]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_A[1]
+set_location_assignment PIN_AH12 -to DDR3_A[2]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_A[2]
+set_location_assignment PIN_AJ12 -to DDR3_A[3]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_A[3]
+set_location_assignment PIN_AG15 -to DDR3_A[4]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_A[4]
+set_location_assignment PIN_AH15 -to DDR3_A[5]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_A[5]
+set_location_assignment PIN_AK12 -to DDR3_A[6]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_A[6]
+set_location_assignment PIN_AK13 -to DDR3_A[7]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_A[7]
+set_location_assignment PIN_AH13 -to DDR3_A[8]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_A[8]
+set_location_assignment PIN_AH14 -to DDR3_A[9]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_A[9]
+set_location_assignment PIN_AJ9 -to DDR3_A[10]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_A[10]
+set_location_assignment PIN_AK9 -to DDR3_A[11]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_A[11]
+set_location_assignment PIN_AK7 -to DDR3_A[12]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_A[12]
+set_location_assignment PIN_AK8 -to DDR3_A[13]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_A[13]
+set_location_assignment PIN_AG12 -to DDR3_A[14]
+set_instance_assignment -name IO_STANDARD "SSTL-15 Class I" -to DDR3_A[14]
+
+#============================================================
+# HSMC, HSMC connect to HTG - HSMC to PIO Adaptor
+#============================================================
+set_location_assignment PIN_A9 -to GPIO1_35
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_35
+set_location_assignment PIN_G12 -to GPIO1_31
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_31
+set_location_assignment PIN_A8 -to GPIO1_33
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_33
+set_location_assignment PIN_G11 -to GPIO1_29
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_29
+set_location_assignment PIN_E8 -to GPIO1_34
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_34
+set_location_assignment PIN_K12 -to GPIO1_27
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_27
+set_location_assignment PIN_D7 -to GPIO1_32
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_32
+set_location_assignment PIN_J12 -to GPIO1_25
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_25
+set_location_assignment PIN_G7 -to GPIO1_30
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_30
+set_location_assignment PIN_G10 -to GPIO1_23
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_23
+set_location_assignment PIN_F6 -to GPIO1_28
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_28
+set_location_assignment PIN_F10 -to GPIO1_21
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_21
+set_location_assignment PIN_D6 -to GPIO1_26
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_26
+set_location_assignment PIN_J10 -to GPIO1_19
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_19
+set_location_assignment PIN_C5 -to GPIO1_24
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_24
+set_location_assignment PIN_J9 -to GPIO1_17
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_17
+set_location_assignment PIN_D5 -to GPIO1_22
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_22
+set_location_assignment PIN_K7 -to GPIO1_15
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_15
+set_location_assignment PIN_C4 -to GPIO1_20
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_20
+set_location_assignment PIN_K8 -to GPIO1_13
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_13
+set_location_assignment PIN_E3 -to GPIO1_14
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_14
+set_location_assignment PIN_J7 -to GPIO1_11
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_11
+set_location_assignment PIN_E2 -to GPIO1_12
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_12
+set_location_assignment PIN_H7 -to GPIO1_9
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_9
+set_location_assignment PIN_E4 -to GPIO1_10
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_10
+set_location_assignment PIN_H8 -to GPIO1_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_7
+set_location_assignment PIN_D4 -to GPIO1_8
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_8
+set_location_assignment PIN_G8 -to GPIO1_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_5
+set_location_assignment PIN_C3 -to GPIO1_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_6
+set_location_assignment PIN_F9 -to GPIO1_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_3
+set_location_assignment PIN_B3 -to GPIO1_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_4
+set_location_assignment PIN_F8 -to GPIO1_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_1
+set_location_assignment PIN_E7 -to GPIO1_18
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_18
+set_location_assignment PIN_AA26 -to GPIO1_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_2
+set_location_assignment PIN_E6 -to GPIO1_16
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_16
+set_location_assignment PIN_AB27 -to GPIO1_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO1_0
+set_location_assignment PIN_D2 -to GPIO0_35
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_35
+set_location_assignment PIN_B6 -to GPIO0_31
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_31
+set_location_assignment PIN_C2 -to GPIO0_33
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_33
+set_location_assignment PIN_B5 -to GPIO0_29
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_29
+set_location_assignment PIN_B2 -to GPIO0_34
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_34
+set_location_assignment PIN_E9 -to GPIO0_27
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_27
+set_location_assignment PIN_B1 -to GPIO0_32
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_32
+set_location_assignment PIN_D9 -to GPIO0_25
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_25
+set_location_assignment PIN_A4 -to GPIO0_30
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_30
+set_location_assignment PIN_E12 -to GPIO0_23
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_23
+set_location_assignment PIN_A3 -to GPIO0_28
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_28
+set_location_assignment PIN_D12 -to GPIO0_21
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_21
+set_location_assignment PIN_A6 -to GPIO0_26
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_26
+set_location_assignment PIN_D11 -to GPIO0_19
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_19
+set_location_assignment PIN_A5 -to GPIO0_24
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_24
+set_location_assignment PIN_D10 -to GPIO0_17
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_17
+set_location_assignment PIN_C7 -to GPIO0_22
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_22
+set_location_assignment PIN_C13 -to GPIO0_15
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_15
+set_location_assignment PIN_B7 -to GPIO0_20
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_20
+set_location_assignment PIN_B12 -to GPIO0_13
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_13
+set_location_assignment PIN_C8 -to GPIO0_14
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_14
+set_location_assignment PIN_F13 -to GPIO0_11
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_11
+set_location_assignment PIN_B8 -to GPIO0_12
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_12
+set_location_assignment PIN_E13 -to GPIO0_9
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_9
+set_location_assignment PIN_C12 -to GPIO0_10
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_10
+set_location_assignment PIN_H14 -to GPIO0_7
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_7
+set_location_assignment PIN_B11 -to GPIO0_8
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_8
+set_location_assignment PIN_G13 -to GPIO0_5
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_5
+set_location_assignment PIN_B13 -to GPIO0_6
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_6
+set_location_assignment PIN_F15 -to GPIO0_3
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_3
+set_location_assignment PIN_A13 -to GPIO0_4
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_4
+set_location_assignment PIN_F14 -to GPIO0_1
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_1
+set_location_assignment PIN_A11 -to GPIO0_18
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_18
+set_location_assignment PIN_H15 -to GPIO0_2
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_2
+set_location_assignment PIN_A10 -to GPIO0_16
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_16
+set_location_assignment PIN_G15 -to GPIO0_0
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO0_0
+
+#============================================================
+# End of pin assignments by Terasic System Builder
+#============================================================
+
+set_global_assignment -name QIP_FILE pll_pal.qip
+set_global_assignment -name SIP_FILE pll_pal.sip
+set_global_assignment -name VHDL_FILE pll_pal.vhd
+set_global_assignment -name QIP_FILE altiobuf.qip
+set_global_assignment -name QIP_FILE altiobufo.qip
+set_global_assignment -name VHDL_FILE altiobuf.vhd
+set_global_assignment -name VHDL_FILE altiobufo.vhd
+set_global_assignment -name VHDL_FILE atari800core_sockit.vhdl
Index: sockit/atari800core.sdc
===================================================================
--- sockit/atari800core.sdc	(nonexistent)
+++ sockit/atari800core.sdc	(revision 302)
@@ -0,0 +1,87 @@
+#**************************************************************
+# This .sdc file is created by Terasic Tool.
+# Users are recommended to modify this file to match users logic.
+#**************************************************************
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+create_clock -period 20 [get_ports OSC_50_B3B]
+create_clock -period 20 [get_ports OSC_50_B4A]
+create_clock -period 20 [get_ports OSC_50_B5B]
+create_clock -period 20 [get_ports OSC_50_B8A]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+derive_pll_clocks
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+derive_clock_uncertainty
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Load
+#**************************************************************
+
+
+
Index: sockit/atari800core_sockit.vhdl
===================================================================
--- sockit/atari800core_sockit.vhdl	(nonexistent)
+++ sockit/atari800core_sockit.vhdl	(revision 302)
@@ -0,0 +1,271 @@
+---------------------------------------------------------------------------
+-- (c) 2014 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+LIBRARY work;
+
+ENTITY atari800core_sockit IS
+        PORT
+        (
+	--//////////// CLOCK //////////
+	OSC_50_B3B : in std_logic;
+	OSC_50_B4A : in std_logic;
+	OSC_50_B5B : in std_logic;
+	OSC_50_B8A : in std_logic;
+
+	--//////////// LED //////////
+	LED : out std_logic_vector(3 downto 0);
+
+	--//////////// KEY //////////
+	KEY : in std_logic_vector(3 downto 0);
+	RESET_n : in std_logic;
+
+	--//////////// SW //////////
+	SW : in std_logic_vector(3 downto 0);
+
+	--//////////// Si5338 //////////
+	SI5338_SCL : out std_logic;
+	SI5338_SDA : inout std_logic;
+
+	--//////////// Temperature //////////
+	TEMP_CS_n : out std_logic;
+	TEMP_DIN : out std_logic;
+	TEMP_DOUT : in std_logic;
+	TEMP_SCLK : out std_logic;
+
+	--//////////// VGA //////////
+	VGA_B : out std_logic_vector(7 downto 0);
+	VGA_BLANK_n : out std_logic;
+	VGA_CLK : out std_logic;
+	VGA_G : out std_logic_vector(7 downto 0);
+	VGA_HS : out std_logic;
+	VGA_R : out std_logic_vector(7 downto 0);
+	VGA_SYNC_n : out std_logic;
+	VGA_VS : out std_logic;
+
+	--//////////// Audio //////////
+	AUD_ADCDAT : inout std_logic;
+	AUD_ADCLRCK : inout std_logic;
+	AUD_BCLK : inout std_logic;
+	AUD_DACDAT : out std_logic;
+	AUD_DACLRCK : inout std_logic;
+	AUD_MUTE : out std_logic;
+	AUD_XCK : out std_logic;
+
+	--//////////// I2C for Audio  //////////
+	AUD_I2C_SCLK : out std_logic;
+	AUD_I2C_SDAT : inout std_logic;
+
+	--//////////// SDRAM //////////
+	DDR3_A : out std_logic_vector(14 downto 0);
+	DDR3_BA : out std_logic_vector(2 downto 0);
+	DDR3_CAS_n : out std_logic;
+	DDR3_CK_n : out std_logic;
+	DDR3_CK_p : out std_logic;
+	DDR3_CKE : out std_logic;
+	DDR3_CS_n : out std_logic;
+	DDR3_DM : out std_logic_vector(3 downto 0);
+	DDR3_DQ : inout std_logic_vector(31 downto 0);
+	DDR3_DQS_n : inout std_logic_vector(3 downto 0);
+	DDR3_DQS_p : inout std_logic_vector(3 downto 0);
+	DDR3_ODT : out std_logic;
+	DDR3_RAS_n : out std_logic;
+	DDR3_RESET_n : out std_logic;
+	DDR3_RZQ : in std_logic;
+	DDR3_WE_n : out std_logic;
+
+	--//////////// HSMC : in std_logic; HSMC connect to HTG - HSMC to PIO Adaptor //////////
+	GPIO0 : inout std_logic_vector(35 downto 0);
+	GPIO1 : inout std_logic_vector(35 downto 0)
+	);
+END atari800core_sockit;
+
+ARCHITECTURE vhdl OF atari800core_sockit IS 
+	function vectorize(s: std_logic) return std_logic_vector is
+	variable v: std_logic_vector(0 downto 0);
+	begin
+		v(0) := s;
+		return v;
+	end;
+
+-- PLL
+signal CLK : std_logic;
+signal PLL_LOCKED : std_logic;
+
+-- VGA
+signal VGA_HS_RAW : std_logic;
+signal VGA_VS_RAW : std_logic;
+signal VGA_BLANK : std_logic;
+BEGIN
+	-- safe defaults
+	LED <= "1010";
+
+	SI5338_SCL <= 'Z';
+	SI5338_SDA <= 'Z';
+
+	TEMP_CS_n <= '1';
+	TEMP_DIN <= 'Z';
+	TEMP_SCLK <= 'Z';
+
+	AUD_ADCDAT <= 'Z';
+	AUD_ADCLRCK <= 'Z';
+	AUD_BCLK <= 'Z';
+	AUD_DACDAT <= '0';
+	AUD_DACLRCK <= 'Z';
+	AUD_MUTE <= '0';
+	AUD_XCK <= '0';
+
+	AUD_I2C_SCLK <= '0';
+	AUD_I2C_SDAT <= 'Z';
+
+	-- Hmmm, ddr3 controller? I thought it had a hard controller...
+	DDR3_A <= (others=>'0');
+	DDR3_BA <= (others=>'0');
+	DDR3_CAS_n <= '1';
+	--DDR3_CK_n <= '0';
+	--DDR3_CK_p <= '1';
+	DDR3_CKE <= '0';
+	DDR3_CS_n <= '1';
+	DDR3_DM <= (others=>'Z');
+	DDR3_DQ <= (others=>'Z');
+	--DDR3_DQS_n <= (others=>'0');
+	--DDR3_DQS_p <= (others=>'1');
+	DDR3_ODT <= 'Z';
+	DDR3_RAS_n <= '1';
+	DDR3_RESET_n <= '1';
+	DDR3_WE_n <= '1';
+
+iobuf1: ENTITY  work.altiobuf_iobuf_bidir_lup
+	 PORT  MAP
+	 ( 
+		 datain	=> "0000",
+		 dataio	=> DDR3_DQS_p,
+		 dataio_b => DDR3_DQS_n,
+		 dataout => open,
+		 oe=> "1111",
+		 oe_b=> "1111"
+	 ); 
+
+iobuf2: ENTITY  work.altiobufo_iobuf_out_h5u
+	 PORT MAP
+	 ( 
+		 datain	=> "0",
+		 dataout(0) => DDR3_CK_p,
+		 dataout_b(0) => DDR3_CK_n,
+		 oe	=> "0",
+		 oe_b	=> "0"
+	 ); 
+
+	GPIO0 <= (others=>'Z');
+	GPIO1 <= (others=>'Z');
+
+	-- pll
+pll : entity work.pll_pal
+	PORT MAP(refclk => OSC_50_B3B,
+	rst => not(reset_n),
+	outclk_0 => CLK,
+	locked => PLL_LOCKED);
+
+	-- vga
+	VGA_HS <= not(VGA_HS_RAW xor VGA_VS_RAW);
+	VGA_VS <= not(VGA_VS_RAW);
+	VGA_SYNC_N <= not(VGA_HS_RAW xor VGA_VS_RAW);
+	VGA_BLANK_N <= NOT(VGA_BLANK);
+	VGA_CLK <= CLK;
+
+	-- Atari 800 core... With internal ROM/RAM.
+atari800core1 : ENTITY work.atari800core_simple_sdram
+	GENERIC MAP
+	(
+		cycle_length => 32,
+
+		video_bits => 8,
+		palette => 1,
+	
+		internal_rom => 1,
+		internal_ram => 65536
+	)
+	PORT MAP
+	(
+		CLK => CLK,
+		RESET_N => PLL_LOCKED,
+
+		-- VIDEO OUT - PAL/NTSC, original Atari timings approx (may be higher res)
+		VIDEO_VS => VGA_VS_RAW,
+		VIDEO_HS => VGA_HS_RAW,
+		VIDEO_B => VGA_B,
+		VIDEO_G => VGA_G,
+		VIDEO_R => VGA_R,
+			-- These ones are probably only needed for e.g. svideo
+		VIDEO_BLANK => VGA_BLANK,
+		VIDEO_BURST => open,
+		VIDEO_START_OF_FIELD => open,
+		VIDEO_ODD_LINE => open,
+
+		-- AUDIO OUT - Pokey/GTIA 1-bit and Covox all mixed
+		-- TODO - choose stereo/mono pokey
+		AUDIO_L => open,
+		AUDIO_R => open,
+
+		-- JOYSTICK
+		JOY1_n => (others=>'0'),
+		JOY2_n => (others=>'0'),
+
+		-- Pokey keyboard matrix
+		-- Standard component available to connect this to PS2
+		KEYBOARD_RESPONSE => "11",
+		KEYBOARD_SCAN => open,
+
+		-- SIO
+		SIO_COMMAND => open,
+		SIO_RXD => '1',
+		SIO_TXD => open,
+
+		-- GTIA consol
+		CONSOL_OPTION => '0',
+		CONSOL_SELECT => '0',
+		CONSOL_START => '0',
+
+		SDRAM_REQUEST => open,
+		SDRAM_REQUEST_COMPLETE => '1',
+		SDRAM_READ_ENABLE => open,
+		SDRAM_WRITE_ENABLE => open,
+		SDRAM_ADDR => open,
+		SDRAM_DO => (others=>'0'),
+		SDRAM_DI => open,
+		SDRAM_32BIT_WRITE_ENABLE => open,
+		SDRAM_16BIT_WRITE_ENABLE => open,
+		SDRAM_8BIT_WRITE_ENABLE => open,
+		SDRAM_REFRESH => open,
+
+		DMA_FETCH => '0',
+		DMA_READ_ENABLE => '0',
+		DMA_32BIT_WRITE_ENABLE => '0',
+		DMA_16BIT_WRITE_ENABLE => '0',
+		DMA_8BIT_WRITE_ENABLE => '0',
+		DMA_ADDR => (others=>'0'),
+		DMA_WRITE_DATA => (others=>'0'),
+		MEMORY_READY_DMA => open,
+		DMA_MEMORY_DATA => open,
+
+		-- Special config params
+   		RAM_SELECT => (others=>'0'), -- 64K,128K,320KB Compy, 320KB Rambo, 576K Compy, 576K Rambo, 1088K, 4MB
+    		ROM_SELECT => "000001",
+		PAL => '1',
+		HALT => '0',
+		THROTTLE_COUNT_6502 => "000001",
+		emulated_cartridge_select => (others=>'0'),
+		freezer_enable => '0',
+		freezer_activate => '0'
+	);
+
+END vhdl;
+
Index: sockit/build.log
===================================================================
--- sockit/build.log	(nonexistent)
+++ sockit/build.log	(revision 302)
@@ -0,0 +1,1088 @@
+cp: omitting directory ‘../common/components/usbhostslave’
+cp: omitting directory ‘../common/zpu/sim’
+cp: omitting directory ‘../common/zpu/tb’
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Shell
+    Info: Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
+    Info: Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+    Info: Your use of Altera Corporation's design tools, logic functions 
+    Info: and other software and tools, and its AMPP partner logic 
+    Info: functions, and any output files from any of the foregoing 
+    Info: (including device programming or simulation files), and any 
+    Info: associated documentation or information are expressly subject 
+    Info: to the terms and conditions of the Altera Program License 
+    Info: Subscription Agreement, the Altera Quartus II License Agreement,
+    Info: the Altera MegaCore Function License Agreement, or other 
+    Info: applicable license agreement, including, without limitation, 
+    Info: that your use is for the sole purpose of programming logic 
+    Info: devices manufactured by Altera and sold by Altera or its 
+    Info: authorized distributors.  Please refer to the applicable 
+    Info: agreement for further details.
+    Info: Processing started: Sun Dec 14 20:17:06 2014
+Info: Command: quartus_sh --flow compile atari800core
+Info: Quartus(args): compile atari800core
+Info: Project Name = /home/markw/fpga/svn/repo/trunk/atari_800xl/sockit/build/atari800core
+Info: Revision Name = atari800core
+Info (125068): Revision "atari800core" was previously opened in Quartus II software version 13.1. Created Quartus II Default Settings File /home/markw/fpga/svn/repo/trunk/atari_800xl/sockit/build/atari800core_assignment_defaults.qdf, which contains the default assignment setting information from Quartus II software version 13.1.
+Info (125069): Default assignment values were changed in the current version of the Quartus II software -- changes to default assignments values are contained in file /home/markw/fpga/altera/14.0/quartus/linux64/assignment_defaults.qdf
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Analysis & Synthesis
+    Info: Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
+    Info: Processing started: Sun Dec 14 20:17:11 2014
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off atari800core -c atari800core
+Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
+Info (12021): Found 2 design units, including 1 entities, in source file pll_pal.vhd
+    Info (12022): Found design unit 1: pll_pal-rtl
+    Info (12023): Found entity 1: pll_pal
+Info (12021): Found 1 design units, including 1 entities, in source file pll_pal/pll_pal_0002.v
+    Info (12023): Found entity 1: pll_pal_0002
+Info (12021): Found 4 design units, including 2 entities, in source file altiobuf.vhd
+    Info (12022): Found design unit 1: altiobuf_iobuf_bidir_lup-RTL
+    Info (12022): Found design unit 2: altiobuf-RTL
+    Info (12023): Found entity 1: altiobuf_iobuf_bidir_lup
+    Info (12023): Found entity 2: altiobuf
+Info (12021): Found 4 design units, including 2 entities, in source file altiobufo.vhd
+    Info (12022): Found design unit 1: altiobufo_iobuf_out_h5u-RTL
+    Info (12022): Found design unit 2: altiobufo-RTL
+    Info (12023): Found entity 1: altiobufo_iobuf_out_h5u
+    Info (12023): Found entity 2: altiobufo
+Info (12021): Found 2 design units, including 1 entities, in source file atari800core_sockit.vhdl
+    Info (12022): Found design unit 1: atari800core_sockit-vhdl
+    Info (12023): Found entity 1: atari800core_sockit
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/atari5200core.vhd
+    Info (12022): Found design unit 1: atari5200core-bdf_type
+    Info (12023): Found entity 1: atari5200core
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/atari5200core_simplesdram.vhd
+    Info (12022): Found design unit 1: atari5200core_simplesdram-vhdl
+    Info (12023): Found entity 1: atari5200core_simplesdram
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/atari800core.vhd
+    Info (12022): Found design unit 1: atari800core-bdf_type
+    Info (12023): Found entity 1: atari800core
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/atari800core_helloworld.vhd
+    Info (12022): Found design unit 1: atari800core_helloworld-vhdl
+    Info (12023): Found entity 1: atari800core_helloworld
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/atari800core_simple_sdram.vhd
+    Info (12022): Found design unit 1: atari800core_simple_sdram-vhdl
+    Info (12023): Found entity 1: atari800core_simple_sdram
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/cart_logic.vhd
+    Info (12022): Found design unit 1: CartLogic-vhdl
+    Info (12023): Found entity 1: CartLogic
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/covox.vhd
+    Info (12022): Found design unit 1: covox-vhdl
+    Info (12023): Found entity 1: covox
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/cpu.vhd
+    Info (12022): Found design unit 1: cpu-vhdl
+    Info (12023): Found entity 1: cpu
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/cpu_6510.vhd
+    Info (12022): Found design unit 1: cpu_6510-rtl
+    Info (12023): Found entity 1: cpu_6510
+Info (12021): Found 1 design units, including 0 entities, in source file common/a8core/cpu_65xx_a.vhd
+    Info (12022): Found design unit 1: cpu_65xx-rtl
+Info (12021): Found 1 design units, including 1 entities, in source file common/a8core/cpu_65xx_e.vhd
+    Info (12023): Found entity 1: cpu_65xx
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/freezer_logic.vhd
+    Info (12022): Found design unit 1: FreezerLogic-RTL
+    Info (12023): Found entity 1: FreezerLogic
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/internalromram.vhd
+    Info (12022): Found design unit 1: internalromram-vhdl
+    Info (12023): Found entity 1: internalromram
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/timing6502.vhd
+    Info (12022): Found design unit 1: timing6502-vhdl
+    Info (12023): Found entity 1: timing6502
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/address_decoder.vhdl
+    Info (12022): Found design unit 1: address_decoder-vhdl
+    Info (12023): Found entity 1: address_decoder
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/antic.vhdl
+    Info (12022): Found design unit 1: antic-vhdl
+    Info (12023): Found entity 1: antic
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/antic_counter.vhdl
+    Info (12022): Found design unit 1: antic_counter-vhdl
+    Info (12023): Found entity 1: antic_counter
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/antic_dma_clock.vhdl
+    Info (12022): Found design unit 1: antic_dma_clock-vhdl
+    Info (12023): Found entity 1: antic_dma_clock
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/basic.vhdl
+    Info (12022): Found design unit 1: basic-syn
+    Info (12023): Found entity 1: basic
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/enable_divider.vhdl
+    Info (12022): Found design unit 1: enable_divider-vhdl
+    Info (12023): Found entity 1: enable_divider
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/gtia.vhdl
+    Info (12022): Found design unit 1: gtia-vhdl
+    Info (12023): Found entity 1: gtia
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/gtia_palette.vhdl
+    Info (12022): Found design unit 1: gtia_palette-vhdl
+    Info (12023): Found entity 1: gtia_palette
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/gtia_player.vhdl
+    Info (12022): Found design unit 1: gtia_player-vhdl
+    Info (12023): Found entity 1: gtia_player
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/gtia_priority.vhdl
+    Info (12022): Found design unit 1: gtia_priority-vhdl
+    Info (12023): Found entity 1: gtia_priority
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/irq_glue.vhdl
+    Info (12022): Found design unit 1: irq_glue-vhdl
+    Info (12023): Found entity 1: irq_glue
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/os16.vhdl
+    Info (12022): Found design unit 1: os16-syn
+    Info (12023): Found entity 1: os16
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/os16_loop.vhdl
+    Info (12022): Found design unit 1: os16_loop-syn
+    Info (12023): Found entity 1: os16_loop
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/os2.vhdl
+    Info (12022): Found design unit 1: os2-syn
+    Info (12023): Found entity 1: os2
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/os8.vhdl
+    Info (12022): Found design unit 1: os8-syn
+    Info (12023): Found entity 1: os8
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/os_5200.vhdl
+    Info (12022): Found design unit 1: os_5200-syn
+    Info (12023): Found entity 1: os_5200
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/pia.vhdl
+    Info (12022): Found design unit 1: pia-vhdl
+    Info (12023): Found entity 1: pia
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/pokey.vhdl
+    Info (12022): Found design unit 1: pokey-vhdl
+    Info (12023): Found entity 1: pokey
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/pokey_countdown_timer.vhdl
+    Info (12022): Found design unit 1: pokey_countdown_timer-vhdl
+    Info (12023): Found entity 1: pokey_countdown_timer
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/pokey_keyboard_scanner.vhdl
+    Info (12022): Found design unit 1: pokey_keyboard_scanner-vhdl
+    Info (12023): Found entity 1: pokey_keyboard_scanner
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/pokey_mixer.vhdl
+    Info (12022): Found design unit 1: pokey_mixer-vhdl
+    Info (12023): Found entity 1: pokey_mixer
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/pokey_mixer_mux.vhdl
+    Info (12022): Found design unit 1: pokey_mixer_mux-vhdl
+    Info (12023): Found entity 1: pokey_mixer_mux
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/pokey_noise_filter.vhdl
+    Info (12022): Found design unit 1: pokey_noise_filter-vhdl
+    Info (12023): Found entity 1: pokey_noise_filter
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/pokey_poly_17_9.vhdl
+    Info (12022): Found design unit 1: pokey_poly_17_9-vhdl
+    Info (12023): Found entity 1: pokey_poly_17_9
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/pokey_poly_4.vhdl
+    Info (12022): Found design unit 1: pokey_poly_4-vhdl
+    Info (12023): Found entity 1: pokey_poly_4
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/pokey_poly_5.vhdl
+    Info (12022): Found design unit 1: pokey_poly_5-vhdl
+    Info (12023): Found entity 1: pokey_poly_5
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/pot_from_signed.vhdl
+    Info (12022): Found design unit 1: pot_from_signed-vhdl
+    Info (12023): Found entity 1: pot_from_signed
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/ps2_to_atari5200.vhdl
+    Info (12022): Found design unit 1: ps2_to_atari5200-vhdl
+    Info (12023): Found entity 1: ps2_to_atari5200
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/ps2_to_atari800.vhdl
+    Info (12022): Found design unit 1: ps2_to_atari800-vhdl
+    Info (12023): Found entity 1: ps2_to_atari800
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/reg_file.vhdl
+    Info (12022): Found design unit 1: reg_file-vhdl
+    Info (12023): Found entity 1: reg_file
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/shared_enable.vhdl
+    Info (12022): Found design unit 1: shared_enable-vhdl
+    Info (12023): Found entity 1: shared_enable
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/simple_counter.vhdl
+    Info (12022): Found design unit 1: simple_counter-vhdl
+    Info (12023): Found entity 1: simple_counter
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/sio_device.vhdl
+    Info (12022): Found design unit 1: sio_device-vhdl
+    Info (12023): Found entity 1: sio_device
+Info (12021): Found 2 design units, including 1 entities, in source file common/a8core/wide_delay_line.vhdl
+    Info (12022): Found design unit 1: wide_delay_line-vhdl
+    Info (12023): Found entity 1: wide_delay_line
+Info (12021): Found 1 design units, including 1 entities, in source file common/components/hq_dac.v
+    Info (12023): Found entity 1: hq_dac
+Info (12021): Found 2 design units, including 1 entities, in source file common/components/spi_master.vhd
+    Info (12022): Found design unit 1: spi_master-logic
+    Info (12023): Found entity 1: spi_master
+Info (12021): Found 2 design units, including 1 entities, in source file common/components/syncreset_enable_divider.vhd
+    Info (12022): Found design unit 1: syncreset_enable_divider-vhdl
+    Info (12023): Found entity 1: syncreset_enable_divider
+Info (12021): Found 2 design units, including 1 entities, in source file common/components/complete_address_decoder.vhdl
+    Info (12022): Found design unit 1: complete_address_decoder-tree
+    Info (12023): Found entity 1: complete_address_decoder
+Info (12021): Found 2 design units, including 1 entities, in source file common/components/delay_line.vhdl
+    Info (12022): Found design unit 1: delay_line-vhdl
+    Info (12023): Found entity 1: delay_line
+Info (12021): Found 2 design units, including 1 entities, in source file common/components/generic_ram_infer.vhdl
+    Info (12022): Found design unit 1: generic_ram_infer-rtl
+    Info (12023): Found entity 1: generic_ram_infer
+Info (12021): Found 2 design units, including 1 entities, in source file common/components/ps2_keyboard.vhdl
+    Info (12022): Found design unit 1: ps2_keyboard-vhdl
+    Info (12023): Found entity 1: ps2_keyboard
+Info (12021): Found 2 design units, including 1 entities, in source file common/components/scandouble_ram_infer.vhdl
+    Info (12022): Found design unit 1: scandouble_ram_infer-rtl
+    Info (12023): Found entity 1: scandouble_ram_infer
+Info (12021): Found 2 design units, including 1 entities, in source file common/components/scandoubler.vhdl
+    Info (12022): Found design unit 1: scandoubler-vhdl
+    Info (12023): Found entity 1: scandoubler
+Info (12021): Found 2 design units, including 1 entities, in source file common/components/sdram_statemachine.vhdl
+    Info (12022): Found design unit 1: sdram_statemachine-vhdl
+    Info (12023): Found entity 1: sdram_statemachine
+Info (12021): Found 2 design units, including 1 entities, in source file common/components/synchronizer.vhdl
+    Info (12022): Found design unit 1: synchronizer-vhdl
+    Info (12023): Found entity 1: synchronizer
+Info (12021): Found 2 design units, including 1 entities, in source file common/zpu/zpu_core.vhd
+    Info (12022): Found design unit 1: ZPUMediumCore-Behave
+    Info (12023): Found entity 1: ZPUMediumCore
+Info (12021): Found 2 design units, including 1 entities, in source file common/zpu/zpucore.vhd
+    Info (12022): Found design unit 1: zpucore-vhdl
+    Info (12023): Found entity 1: zpucore
+Info (12021): Found 2 design units, including 0 entities, in source file common/zpu/zpupkg.vhd
+    Info (12022): Found design unit 1: zpupkg
+    Info (12022): Found design unit 2: UART
+Info (12021): Found 2 design units, including 1 entities, in source file common/zpu/zpu_config_regs.vhdl
+    Info (12022): Found design unit 1: zpu_config_regs-vhdl
+    Info (12023): Found entity 1: zpu_config_regs
+Info (12021): Found 2 design units, including 1 entities, in source file common/zpu/zpu_glue.vhdl
+    Info (12022): Found design unit 1: zpu_glue-sticky
+    Info (12023): Found entity 1: zpu_glue
+Info (12127): Elaborating entity "atari800core_sockit" for the top level hierarchy
+Info (12128): Elaborating entity "altiobuf_iobuf_bidir_lup" for hierarchy "altiobuf_iobuf_bidir_lup:iobuf1"
+Info (12128): Elaborating entity "altiobufo_iobuf_out_h5u" for hierarchy "altiobufo_iobuf_out_h5u:iobuf2"
+Info (12128): Elaborating entity "pll_pal" for hierarchy "pll_pal:pll"
+Info (12128): Elaborating entity "pll_pal_0002" for hierarchy "pll_pal:pll|pll_pal_0002:pll_pal_inst"
+Info (12128): Elaborating entity "altera_pll" for hierarchy "pll_pal:pll|pll_pal_0002:pll_pal_inst|altera_pll:altera_pll_i"
+Info (10008): Verilog HDL or VHDL information: EDA Netlist Writer cannot regroup multidimensional array "wire_to_nowhere_64" into its bus
+Info (12130): Elaborated megafunction instantiation "pll_pal:pll|pll_pal_0002:pll_pal_inst|altera_pll:altera_pll_i"
+Info (12133): Instantiated megafunction "pll_pal:pll|pll_pal_0002:pll_pal_inst|altera_pll:altera_pll_i" with the following parameter:
+    Info (12134): Parameter "fractional_vco_multiplier" = "false"
+    Info (12134): Parameter "reference_clock_frequency" = "50.0 MHz"
+    Info (12134): Parameter "operation_mode" = "normal"
+    Info (12134): Parameter "number_of_clocks" = "1"
+    Info (12134): Parameter "output_clock_frequency0" = "56.750000 MHz"
+    Info (12134): Parameter "phase_shift0" = "0 ps"
+    Info (12134): Parameter "duty_cycle0" = "50"
+    Info (12134): Parameter "output_clock_frequency1" = "0 MHz"
+    Info (12134): Parameter "phase_shift1" = "0 ps"
+    Info (12134): Parameter "duty_cycle1" = "50"
+    Info (12134): Parameter "output_clock_frequency2" = "0 MHz"
+    Info (12134): Parameter "phase_shift2" = "0 ps"
+    Info (12134): Parameter "duty_cycle2" = "50"
+    Info (12134): Parameter "output_clock_frequency3" = "0 MHz"
+    Info (12134): Parameter "phase_shift3" = "0 ps"
+    Info (12134): Parameter "duty_cycle3" = "50"
+    Info (12134): Parameter "output_clock_frequency4" = "0 MHz"
+    Info (12134): Parameter "phase_shift4" = "0 ps"
+    Info (12134): Parameter "duty_cycle4" = "50"
+    Info (12134): Parameter "output_clock_frequency5" = "0 MHz"
+    Info (12134): Parameter "phase_shift5" = "0 ps"
+    Info (12134): Parameter "duty_cycle5" = "50"
+    Info (12134): Parameter "output_clock_frequency6" = "0 MHz"
+    Info (12134): Parameter "phase_shift6" = "0 ps"
+    Info (12134): Parameter "duty_cycle6" = "50"
+    Info (12134): Parameter "output_clock_frequency7" = "0 MHz"
+    Info (12134): Parameter "phase_shift7" = "0 ps"
+    Info (12134): Parameter "duty_cycle7" = "50"
+    Info (12134): Parameter "output_clock_frequency8" = "0 MHz"
+    Info (12134): Parameter "phase_shift8" = "0 ps"
+    Info (12134): Parameter "duty_cycle8" = "50"
+    Info (12134): Parameter "output_clock_frequency9" = "0 MHz"
+    Info (12134): Parameter "phase_shift9" = "0 ps"
+    Info (12134): Parameter "duty_cycle9" = "50"
+    Info (12134): Parameter "output_clock_frequency10" = "0 MHz"
+    Info (12134): Parameter "phase_shift10" = "0 ps"
+    Info (12134): Parameter "duty_cycle10" = "50"
+    Info (12134): Parameter "output_clock_frequency11" = "0 MHz"
+    Info (12134): Parameter "phase_shift11" = "0 ps"
+    Info (12134): Parameter "duty_cycle11" = "50"
+    Info (12134): Parameter "output_clock_frequency12" = "0 MHz"
+    Info (12134): Parameter "phase_shift12" = "0 ps"
+    Info (12134): Parameter "duty_cycle12" = "50"
+    Info (12134): Parameter "output_clock_frequency13" = "0 MHz"
+    Info (12134): Parameter "phase_shift13" = "0 ps"
+    Info (12134): Parameter "duty_cycle13" = "50"
+    Info (12134): Parameter "output_clock_frequency14" = "0 MHz"
+    Info (12134): Parameter "phase_shift14" = "0 ps"
+    Info (12134): Parameter "duty_cycle14" = "50"
+    Info (12134): Parameter "output_clock_frequency15" = "0 MHz"
+    Info (12134): Parameter "phase_shift15" = "0 ps"
+    Info (12134): Parameter "duty_cycle15" = "50"
+    Info (12134): Parameter "output_clock_frequency16" = "0 MHz"
+    Info (12134): Parameter "phase_shift16" = "0 ps"
+    Info (12134): Parameter "duty_cycle16" = "50"
+    Info (12134): Parameter "output_clock_frequency17" = "0 MHz"
+    Info (12134): Parameter "phase_shift17" = "0 ps"
+    Info (12134): Parameter "duty_cycle17" = "50"
+    Info (12134): Parameter "pll_type" = "General"
+    Info (12134): Parameter "pll_subtype" = "General"
+Info (12128): Elaborating entity "atari800core_simple_sdram" for hierarchy "atari800core_simple_sdram:atari800core1"
+Warning (10873): Using initial value X (don't care) for net "RAM_DO[15..8]" at atari800core_simple_sdram.vhd(181)
+Info (12128): Elaborating entity "pot_from_signed" for hierarchy "atari800core_simple_sdram:atari800core1|pot_from_signed:pot0"
+Info (12128): Elaborating entity "enable_divider" for hierarchy "atari800core_simple_sdram:atari800core1|pot_from_signed:pot0|enable_divider:enable_179_clock_div"
+Info (12128): Elaborating entity "enable_divider" for hierarchy "atari800core_simple_sdram:atari800core1|pot_from_signed:pot0|enable_divider:pot_clock_div"
+Info (12128): Elaborating entity "internalromram" for hierarchy "atari800core_simple_sdram:atari800core1|internalromram:internalromram1"
+Info (12128): Elaborating entity "os16" for hierarchy "atari800core_simple_sdram:atari800core1|internalromram:internalromram1|os16:\gen_internal_os:rom16a"
+Info (12128): Elaborating entity "basic" for hierarchy "atari800core_simple_sdram:atari800core1|internalromram:internalromram1|basic:\gen_internal_os:basic1"
+Info (12128): Elaborating entity "generic_ram_infer" for hierarchy "atari800core_simple_sdram:atari800core1|internalromram:internalromram1|generic_ram_infer:\gen_internal_ram:ramint1"
+Info (12128): Elaborating entity "atari800core" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl"
+Warning (10036): Verilog HDL or VHDL warning at atari800core.vhd(204): object "hcount_temp" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at atari800core.vhd(205): object "vcount_temp" assigned a value but never read
+Info (12128): Elaborating entity "shared_enable" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|shared_enable:enables"
+Info (12128): Elaborating entity "delay_line" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|shared_enable:enables|delay_line:delay_line_phase"
+Info (12128): Elaborating entity "cpu" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|cpu:cpu6502"
+Warning (10036): Verilog HDL or VHDL warning at cpu.vhd(64): object "debugOpcode" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at cpu.vhd(65): object "debugPc" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at cpu.vhd(66): object "debugA" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at cpu.vhd(67): object "debugX" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at cpu.vhd(68): object "debugY" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at cpu.vhd(69): object "debugS" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at cpu.vhd(81): object "CPU_ENABLE_RESET" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at cpu.vhd(82): object "not_rdy" assigned a value but never read
+Info (12128): Elaborating entity "cpu_65xx" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter"
+Info (12128): Elaborating entity "antic" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|antic:antic1"
+Warning (10036): Verilog HDL or VHDL warning at antic.vhdl(222): object "playfield_dma_start" assigned a value but never read
+Info (12128): Elaborating entity "antic_counter" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_memory_scan"
+Info (12128): Elaborating entity "antic_counter" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_display_list"
+Info (12128): Elaborating entity "simple_counter" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer"
+Info (12128): Elaborating entity "simple_counter" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_row_count"
+Info (12128): Elaborating entity "wide_delay_line" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|antic:antic1|wide_delay_line:nmien_delay"
+Info (12128): Elaborating entity "antic_dma_clock" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|antic:antic1|antic_dma_clock:antic_dma_clock1"
+Info (12128): Elaborating entity "reg_file" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1"
+Info (12128): Elaborating entity "complete_address_decoder" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|complete_address_decoder:complete_address_decoder1"
+Info (12128): Elaborating entity "wide_delay_line" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay"
+Info (12128): Elaborating entity "wide_delay_line" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay"
+Info (12128): Elaborating entity "complete_address_decoder" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|antic:antic1|complete_address_decoder:decode_addr1"
+Info (12128): Elaborating entity "delay_line" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|antic:antic1|delay_line:wsync_delay"
+Info (12128): Elaborating entity "pokey_mixer_mux" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both"
+Info (12128): Elaborating entity "pokey_mixer" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|pokey_mixer_mux:pokey_mixer_both|pokey_mixer:shared_pokey_mixer"
+Info (12128): Elaborating entity "pokey" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|pokey:pokey2"
+Info (12128): Elaborating entity "pokey_countdown_timer" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0"
+Info (12128): Elaborating entity "delay_line" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay"
+Info (12128): Elaborating entity "pokey_noise_filter" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|pokey:pokey2|pokey_noise_filter:pokey_noise_filter0"
+Info (12128): Elaborating entity "syncreset_enable_divider" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|pokey:pokey2|syncreset_enable_divider:enable_64_div"
+Info (12128): Elaborating entity "syncreset_enable_divider" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|pokey:pokey2|syncreset_enable_divider:enable_15_div"
+Info (12128): Elaborating entity "pokey_poly_17_9" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|pokey:pokey2|pokey_poly_17_9:poly_17_19_lfsr"
+Info (12128): Elaborating entity "pokey_poly_5" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|pokey:pokey2|pokey_poly_5:poly_5_lfsr"
+Info (12128): Elaborating entity "pokey_poly_4" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|pokey:pokey2|pokey_poly_4:poly_4_lfsr"
+Info (12128): Elaborating entity "delay_line" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|pokey:pokey2|delay_line:serout_clock_delay"
+Info (12128): Elaborating entity "synchronizer" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|pokey:pokey2|synchronizer:sio_in1_synchronizer"
+Info (12128): Elaborating entity "pokey_keyboard_scanner" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|pokey:pokey2|pokey_keyboard_scanner:pokey_keyboard_scanner1"
+Info (12128): Elaborating entity "pia" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|pia:pia1"
+Warning (10036): Verilog HDL or VHDL warning at pia.vhdl(103): object "write_ora" assigned a value but never read
+Info (12128): Elaborating entity "complete_address_decoder" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|pia:pia1|complete_address_decoder:decode_addr1"
+Info (12128): Elaborating entity "address_decoder" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|address_decoder:mmu1"
+Warning (10036): Verilog HDL or VHDL warning at address_decoder.vhdl(214): object "emu_cart_s4_n_out" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at address_decoder.vhdl(215): object "emu_cart_s5_n_out" assigned a value but never read
+Info (12128): Elaborating entity "CartLogic" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|address_decoder:mmu1|CartLogic:emu_cart"
+Info (12128): Elaborating entity "FreezerLogic" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer"
+Info (12128): Elaborating entity "generic_ram_infer" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|address_decoder:mmu1|FreezerLogic:freezer|generic_ram_infer:freezer_bram"
+Info (12128): Elaborating entity "gtia" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|gtia:gtia1"
+Info (12128): Elaborating entity "complete_address_decoder" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|gtia:gtia1|complete_address_decoder:decode_addr1"
+Info (12128): Elaborating entity "delay_line" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|gtia:gtia1|delay_line:hsync_delay"
+Info (12128): Elaborating entity "delay_line" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|gtia:gtia1|delay_line:burst_delay"
+Info (12128): Elaborating entity "gtia_player" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|gtia:gtia1|gtia_player:player0"
+Info (12128): Elaborating entity "gtia_priority" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|gtia:gtia1|gtia_priority:priority_rules"
+Info (12128): Elaborating entity "wide_delay_line" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:prior_short_delay"
+Info (12128): Elaborating entity "wide_delay_line" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:prior_long_delay"
+Info (12128): Elaborating entity "wide_delay_line" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:prior_longer_delay"
+Info (12128): Elaborating entity "wide_delay_line" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:colbk_delay"
+Info (12128): Elaborating entity "wide_delay_line" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposp0_delay"
+Info (12128): Elaborating entity "wide_delay_line" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay"
+Info (12128): Elaborating entity "gtia_palette" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|gtia_palette:\gen_palette_on:palette4"
+Info (12128): Elaborating entity "irq_glue" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|irq_glue:irq_glue1"
+Info (12128): Elaborating entity "reg_file" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|reg_file:pokey1_mirror"
+Info (12128): Elaborating entity "reg_file" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|reg_file:gtia_mirror"
+Info (12128): Elaborating entity "covox" for hierarchy "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|covox:covox1"
+Info (286030): Timing-Driven Synthesis is running
+Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
+    Warning (13049): Converted tri-state buffer "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|pokey:pokey1|SIO_CLOCK~synth" feeding internal logic into a wire
+    Warning (13049): Converted tri-state buffer "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|pokey:pokey2|SIO_CLOCK~synth" feeding internal logic into a wire
+Info (19000): Inferred 8 megafunctions from design logic
+    Info (276029): Inferred altsyncram megafunction from the following design logic: "atari800core_simple_sdram:atari800core1|internalromram:internalromram1|generic_ram_infer:\gen_internal_ram:ramint1|ram_block_rtl_0" 
+        Info (286033): Parameter OPERATION_MODE set to SINGLE_PORT
+        Info (286033): Parameter WIDTH_A set to 8
+        Info (286033): Parameter WIDTHAD_A set to 16
+        Info (286033): Parameter NUMWORDS_A set to 65536
+        Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED
+        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
+        Info (286033): Parameter OUTDATA_ACLR_A set to NONE
+        Info (286033): Parameter INDATA_ACLR_A set to NONE
+        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
+    Info (276029): Inferred altsyncram megafunction from the following design logic: "atari800core_simple_sdram:atari800core1|internalromram:internalromram1|basic:\gen_internal_os:basic1|ROM_rtl_0" 
+        Info (286033): Parameter OPERATION_MODE set to ROM
+        Info (286033): Parameter WIDTH_A set to 8
+        Info (286033): Parameter WIDTHAD_A set to 13
+        Info (286033): Parameter NUMWORDS_A set to 8192
+        Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED
+        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
+        Info (286033): Parameter OUTDATA_ACLR_A set to NONE
+        Info (286033): Parameter INDATA_ACLR_A set to NONE
+        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
+        Info (286033): Parameter INIT_FILE set to db/atari800core.ram0_basic_6451119.hdl.mif
+    Info (276029): Inferred altsyncram megafunction from the following design logic: "atari800core_simple_sdram:atari800core1|internalromram:internalromram1|os16:\gen_internal_os:rom16a|ROM_rtl_0" 
+        Info (286033): Parameter OPERATION_MODE set to ROM
+        Info (286033): Parameter WIDTH_A set to 8
+        Info (286033): Parameter WIDTHAD_A set to 14
+        Info (286033): Parameter NUMWORDS_A set to 16384
+        Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED
+        Info (286033): Parameter ADDRESS_ACLR_A set to NONE
+        Info (286033): Parameter OUTDATA_ACLR_A set to NONE
+        Info (286033): Parameter INDATA_ACLR_A set to NONE
+        Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
+        Info (286033): Parameter INIT_FILE set to db/atari800core.ram0_os16_3be07a.hdl.mif
+    Info (276031): Inferred altsyncram megafunction from the following design logic: "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Mux54_rtl_0"
+        Info (286033): Parameter OPERATION_MODE set to ROM
+        Info (286033): Parameter WIDTH_A set to 1
+        Info (286033): Parameter WIDTHAD_A set to 8
+        Info (286033): Parameter NUMWORDS_A set to 256
+        Info (286033): Parameter OUTDATA_REG_A set to UNREGISTERED
+        Info (286033): Parameter RAM_BLOCK_TYPE set to AUTO
+        Info (286033): Parameter INIT_FILE set to atari800core.atari800core_sockit0.rtl.mif
+    Info (276034): Inferred altshift_taps megafunction from the following design logic: "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg_rtl_0"
+        Info (286033): Parameter NUMBER_OF_TAPS set to 1
+        Info (286033): Parameter TAP_DISTANCE set to 64
+        Info (286033): Parameter WIDTH set to 7
+        Info (286033): Parameter POWER_UP_STATE set to DONT_CARE
+    Info (276034): Inferred altshift_taps megafunction from the following design logic: "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg_rtl_0"
+        Info (286033): Parameter NUMBER_OF_TAPS set to 1
+        Info (286033): Parameter TAP_DISTANCE set to 32
+        Info (286033): Parameter WIDTH set to 6
+        Info (286033): Parameter POWER_UP_STATE set to DONT_CARE
+    Info (276034): Inferred altshift_taps megafunction from the following design logic: "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg_rtl_0"
+        Info (286033): Parameter NUMBER_OF_TAPS set to 1
+        Info (286033): Parameter TAP_DISTANCE set to 5
+        Info (286033): Parameter WIDTH set to 64
+        Info (286033): Parameter POWER_UP_STATE set to DONT_CARE
+    Info (276034): Inferred altshift_taps megafunction from the following design logic: "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg_rtl_0"
+        Info (286033): Parameter NUMBER_OF_TAPS set to 1
+        Info (286033): Parameter TAP_DISTANCE set to 4
+        Info (286033): Parameter WIDTH set to 16
+        Info (286033): Parameter POWER_UP_STATE set to DONT_CARE
+Info (12130): Elaborated megafunction instantiation "atari800core_simple_sdram:atari800core1|internalromram:internalromram1|generic_ram_infer:\gen_internal_ram:ramint1|altsyncram:ram_block_rtl_0"
+Info (12133): Instantiated megafunction "atari800core_simple_sdram:atari800core1|internalromram:internalromram1|generic_ram_infer:\gen_internal_ram:ramint1|altsyncram:ram_block_rtl_0" with the following parameter:
+    Info (12134): Parameter "OPERATION_MODE" = "SINGLE_PORT"
+    Info (12134): Parameter "WIDTH_A" = "8"
+    Info (12134): Parameter "WIDTHAD_A" = "16"
+    Info (12134): Parameter "NUMWORDS_A" = "65536"
+    Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED"
+    Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
+    Info (12134): Parameter "OUTDATA_ACLR_A" = "NONE"
+    Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
+    Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_apa1.tdf
+    Info (12023): Found entity 1: altsyncram_apa1
+Info (12021): Found 1 design units, including 1 entities, in source file db/decode_dla.tdf
+    Info (12023): Found entity 1: decode_dla
+Info (12021): Found 1 design units, including 1 entities, in source file db/decode_61a.tdf
+    Info (12023): Found entity 1: decode_61a
+Info (12021): Found 1 design units, including 1 entities, in source file db/mux_tfb.tdf
+    Info (12023): Found entity 1: mux_tfb
+Info (12130): Elaborated megafunction instantiation "atari800core_simple_sdram:atari800core1|internalromram:internalromram1|basic:\gen_internal_os:basic1|altsyncram:ROM_rtl_0"
+Info (12133): Instantiated megafunction "atari800core_simple_sdram:atari800core1|internalromram:internalromram1|basic:\gen_internal_os:basic1|altsyncram:ROM_rtl_0" with the following parameter:
+    Info (12134): Parameter "OPERATION_MODE" = "ROM"
+    Info (12134): Parameter "WIDTH_A" = "8"
+    Info (12134): Parameter "WIDTHAD_A" = "13"
+    Info (12134): Parameter "NUMWORDS_A" = "8192"
+    Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED"
+    Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
+    Info (12134): Parameter "OUTDATA_ACLR_A" = "NONE"
+    Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
+    Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
+    Info (12134): Parameter "INIT_FILE" = "db/atari800core.ram0_basic_6451119.hdl.mif"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_o5d1.tdf
+    Info (12023): Found entity 1: altsyncram_o5d1
+Info (12130): Elaborated megafunction instantiation "atari800core_simple_sdram:atari800core1|internalromram:internalromram1|os16:\gen_internal_os:rom16a|altsyncram:ROM_rtl_0"
+Info (12133): Instantiated megafunction "atari800core_simple_sdram:atari800core1|internalromram:internalromram1|os16:\gen_internal_os:rom16a|altsyncram:ROM_rtl_0" with the following parameter:
+    Info (12134): Parameter "OPERATION_MODE" = "ROM"
+    Info (12134): Parameter "WIDTH_A" = "8"
+    Info (12134): Parameter "WIDTHAD_A" = "14"
+    Info (12134): Parameter "NUMWORDS_A" = "16384"
+    Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED"
+    Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
+    Info (12134): Parameter "OUTDATA_ACLR_A" = "NONE"
+    Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
+    Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
+    Info (12134): Parameter "INIT_FILE" = "db/atari800core.ram0_os16_3be07a.hdl.mif"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_94d1.tdf
+    Info (12023): Found entity 1: altsyncram_94d1
+Info (12021): Found 1 design units, including 1 entities, in source file db/decode_u0a.tdf
+    Info (12023): Found entity 1: decode_u0a
+Info (12021): Found 1 design units, including 1 entities, in source file db/mux_lfb.tdf
+    Info (12023): Found entity 1: mux_lfb
+Info (12130): Elaborated megafunction instantiation "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|altsyncram:Mux54_rtl_0"
+Info (12133): Instantiated megafunction "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|altsyncram:Mux54_rtl_0" with the following parameter:
+    Info (12134): Parameter "OPERATION_MODE" = "ROM"
+    Info (12134): Parameter "WIDTH_A" = "1"
+    Info (12134): Parameter "WIDTHAD_A" = "8"
+    Info (12134): Parameter "NUMWORDS_A" = "256"
+    Info (12134): Parameter "OUTDATA_REG_A" = "UNREGISTERED"
+    Info (12134): Parameter "RAM_BLOCK_TYPE" = "AUTO"
+    Info (12134): Parameter "INIT_FILE" = "atari800core.atari800core_sockit0.rtl.mif"
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_v081.tdf
+    Info (12023): Found entity 1: altsyncram_v081
+Info (12130): Elaborated megafunction instantiation "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0"
+Info (12133): Instantiated megafunction "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|altshift_taps:shift_reg_rtl_0" with the following parameter:
+    Info (12134): Parameter "NUMBER_OF_TAPS" = "1"
+    Info (12134): Parameter "TAP_DISTANCE" = "64"
+    Info (12134): Parameter "WIDTH" = "7"
+    Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE"
+Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_6dv.tdf
+    Info (12023): Found entity 1: shift_taps_6dv
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_7gc1.tdf
+    Info (12023): Found entity 1: altsyncram_7gc1
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_jjf.tdf
+    Info (12023): Found entity 1: cntr_jjf
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_73h.tdf
+    Info (12023): Found entity 1: cntr_73h
+Info (12130): Elaborated megafunction instantiation "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0"
+Info (12133): Instantiated megafunction "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|altshift_taps:shift_reg_rtl_0" with the following parameter:
+    Info (12134): Parameter "NUMBER_OF_TAPS" = "1"
+    Info (12134): Parameter "TAP_DISTANCE" = "32"
+    Info (12134): Parameter "WIDTH" = "6"
+    Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE"
+Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_0dv.tdf
+    Info (12023): Found entity 1: shift_taps_0dv
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_pfc1.tdf
+    Info (12023): Found entity 1: altsyncram_pfc1
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_djf.tdf
+    Info (12023): Found entity 1: cntr_djf
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_13h.tdf
+    Info (12023): Found entity 1: cntr_13h
+Info (12130): Elaborated megafunction instantiation "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|altshift_taps:shift_reg_rtl_0"
+Info (12133): Instantiated megafunction "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|altshift_taps:shift_reg_rtl_0" with the following parameter:
+    Info (12134): Parameter "NUMBER_OF_TAPS" = "1"
+    Info (12134): Parameter "TAP_DISTANCE" = "5"
+    Info (12134): Parameter "WIDTH" = "64"
+    Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE"
+Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_huv.tdf
+    Info (12023): Found entity 1: shift_taps_huv
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_tfc1.tdf
+    Info (12023): Found entity 1: altsyncram_tfc1
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_rhf.tdf
+    Info (12023): Found entity 1: cntr_rhf
+Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_b9c.tdf
+    Info (12023): Found entity 1: cmpr_b9c
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_e1h.tdf
+    Info (12023): Found entity 1: cntr_e1h
+Info (12130): Elaborated megafunction instantiation "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0"
+Info (12133): Instantiated megafunction "atari800core_simple_sdram:atari800core1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|altshift_taps:shift_reg_rtl_0" with the following parameter:
+    Info (12134): Parameter "NUMBER_OF_TAPS" = "1"
+    Info (12134): Parameter "TAP_DISTANCE" = "4"
+    Info (12134): Parameter "WIDTH" = "16"
+    Info (12134): Parameter "POWER_UP_STATE" = "DONT_CARE"
+Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_duv.tdf
+    Info (12023): Found entity 1: shift_taps_duv
+Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_jfc1.tdf
+    Info (12023): Found entity 1: altsyncram_jfc1
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_phf.tdf
+    Info (12023): Found entity 1: cntr_phf
+Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_d1h.tdf
+    Info (12023): Found entity 1: cntr_d1h
+Warning (12241): 3 hierarchies have connectivity warnings - see the Connectivity Checks report folder
+Warning (13024): Output pins are stuck at VCC or GND
+    Warning (13410): Pin "LED[0]" is stuck at GND
+    Warning (13410): Pin "LED[1]" is stuck at VCC
+    Warning (13410): Pin "LED[2]" is stuck at GND
+    Warning (13410): Pin "LED[3]" is stuck at VCC
+    Warning (13410): Pin "TEMP_CS_n" is stuck at VCC
+    Warning (13410): Pin "AUD_DACDAT" is stuck at GND
+    Warning (13410): Pin "AUD_MUTE" is stuck at GND
+    Warning (13410): Pin "AUD_XCK" is stuck at GND
+    Warning (13410): Pin "AUD_I2C_SCLK" is stuck at GND
+    Warning (13410): Pin "DDR3_A[0]" is stuck at GND
+    Warning (13410): Pin "DDR3_A[1]" is stuck at GND
+    Warning (13410): Pin "DDR3_A[2]" is stuck at GND
+    Warning (13410): Pin "DDR3_A[3]" is stuck at GND
+    Warning (13410): Pin "DDR3_A[4]" is stuck at GND
+    Warning (13410): Pin "DDR3_A[5]" is stuck at GND
+    Warning (13410): Pin "DDR3_A[6]" is stuck at GND
+    Warning (13410): Pin "DDR3_A[7]" is stuck at GND
+    Warning (13410): Pin "DDR3_A[8]" is stuck at GND
+    Warning (13410): Pin "DDR3_A[9]" is stuck at GND
+    Warning (13410): Pin "DDR3_A[10]" is stuck at GND
+    Warning (13410): Pin "DDR3_A[11]" is stuck at GND
+    Warning (13410): Pin "DDR3_A[12]" is stuck at GND
+    Warning (13410): Pin "DDR3_A[13]" is stuck at GND
+    Warning (13410): Pin "DDR3_A[14]" is stuck at GND
+    Warning (13410): Pin "DDR3_BA[0]" is stuck at GND
+    Warning (13410): Pin "DDR3_BA[1]" is stuck at GND
+    Warning (13410): Pin "DDR3_BA[2]" is stuck at GND
+    Warning (13410): Pin "DDR3_CAS_n" is stuck at VCC
+    Warning (13410): Pin "DDR3_CKE" is stuck at GND
+    Warning (13410): Pin "DDR3_CS_n" is stuck at VCC
+    Warning (13410): Pin "DDR3_RAS_n" is stuck at VCC
+    Warning (13410): Pin "DDR3_RESET_n" is stuck at VCC
+    Warning (13410): Pin "DDR3_WE_n" is stuck at VCC
+Info (17049): 54 registers lost all their fanouts during netlist optimizations.
+Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
+    Info (16011): Adding 7 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
+Warning (21074): Design contains 13 input pin(s) that do not drive logic
+    Warning (15610): No output dependent on input pin "OSC_50_B4A"
+    Warning (15610): No output dependent on input pin "OSC_50_B5B"
+    Warning (15610): No output dependent on input pin "OSC_50_B8A"
+    Warning (15610): No output dependent on input pin "KEY[0]"
+    Warning (15610): No output dependent on input pin "KEY[1]"
+    Warning (15610): No output dependent on input pin "KEY[2]"
+    Warning (15610): No output dependent on input pin "KEY[3]"
+    Warning (15610): No output dependent on input pin "SW[0]"
+    Warning (15610): No output dependent on input pin "SW[1]"
+    Warning (15610): No output dependent on input pin "SW[2]"
+    Warning (15610): No output dependent on input pin "SW[3]"
+    Warning (15610): No output dependent on input pin "TEMP_DOUT"
+    Warning (15610): No output dependent on input pin "DDR3_RZQ"
+Info (21057): Implemented 4437 device resources after synthesis - the final resource count might be different
+    Info (21058): Implemented 15 input pins
+    Info (21059): Implemented 72 output pins
+    Info (21060): Implemented 118 bidirectional pins
+    Info (21061): Implemented 4044 logic cells
+    Info (21064): Implemented 182 RAM segments
+    Info (21065): Implemented 1 PLLs
+Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 67 warnings
+    Info: Peak virtual memory: 1045 megabytes
+    Info: Processing ended: Sun Dec 14 20:18:17 2014
+    Info: Elapsed time: 00:01:06
+    Info: Total CPU time (on all processors): 00:01:06
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Fitter
+    Info: Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
+    Info: Processing started: Sun Dec 14 20:18:24 2014
+Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off atari800core -c atari800core
+Info: qfit2_default_script.tcl version: #1
+Info: Project  = atari800core
+Info: Revision = atari800core
+Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
+Info (119006): Selected device 5CSXFC6D6F31C8ES for design "atari800core"
+Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
+Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
+Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
+Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
+Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
+Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
+Critical Warning (169085): No exact pin location assignment(s) for 72 pins of 205 total pins. For the list of the pins please refer to the Input Pins, Output Pins, and Bidir Pins tables in the Fitter report and look for the user pins whose location is assigned by Fitter.
+Info (184020): Starting Fitter periphery placement operations
+Warning (177007): PLL(s) placed in location FRACTIONALPLL_X0_Y15_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks
+    Info (177008): PLL pll_pal:pll|pll_pal_0002:pll_pal_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL
+Info (11178): Promoted 1 clock (1 global)
+    Info (11162): pll_pal:pll|pll_pal_0002:pll_pal_inst|altera_pll:altera_pll_i|outclk_wire[0]~CLKENA0 with 2383 fanout uses global clock CLKCTRL_G7
+Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:26
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'atari800core.SDC'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332144): No user constrained generated clocks found in the design
+Info (332144): No user constrained base clocks found in the design
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
+    Info (332098): Cell: pll|pll_pal_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk
+    Info (332098): Cell: pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk
+    Info (332098): Cell: pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT  from: clkin[0]  to: clkout
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
+Info (176233): Starting register packing
+Info (176235): Finished register packing
+    Extra Info (176219): No registers were packed into other blocks
+Warning (15705): Ignored locations or region assignments to the following nodes
+    Warning (15706): Node "GPIO0_0" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_1" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_10" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_11" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_12" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_13" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_14" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_15" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_16" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_17" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_18" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_19" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_2" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_20" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_21" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_22" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_23" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_24" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_25" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_26" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_27" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_28" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_29" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_3" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_30" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_31" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_32" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_33" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_34" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_35" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_4" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_5" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_6" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_7" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_8" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO0_9" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_0" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_1" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_10" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_11" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_12" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_13" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_14" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_15" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_16" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_17" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_18" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_19" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_2" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_20" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_21" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_22" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_23" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_24" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_25" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_26" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_27" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_28" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_29" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_3" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_30" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_31" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_32" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_33" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_34" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_35" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_4" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_5" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_6" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_7" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_8" is assigned to location or region, but does not exist in design
+    Warning (15706): Node "GPIO1_9" is assigned to location or region, but does not exist in design
+Info (11798): Fitter preparation operations ending: elapsed time is 00:00:49
+Info (170189): Fitter placement preparation operations beginning
+Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:03
+Info (170191): Fitter placement operations beginning
+Info (170137): Fitter placement was successful
+Info (170192): Fitter placement operations ending: elapsed time is 00:00:11
+Info (170193): Fitter routing operations beginning
+Info (170195): Router estimated average interconnect usage is 2% of the available device resources
+    Info (170196): Router estimated peak interconnect usage is 27% of the available device resources in the region that extends from location X33_Y23 to location X44_Y34
+Info (170194): Fitter routing operations ending: elapsed time is 00:00:10
+Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
+    Info (170201): Optimizations that may affect the design's routability were skipped
+    Info (170200): Optimizations that may affect the design's timing were skipped
+Info (11888): Total time spent on timing analysis during the Fitter is 6.29 seconds.
+Info (334003): Started post-fitting delay annotation
+Warning (334000): Timing characteristics of device 5CSXFC6D6F31C8ES are preliminary
+Info (334004): Delay annotation completed successfully
+Info (334003): Started post-fitting delay annotation
+Warning (334000): Timing characteristics of device 5CSXFC6D6F31C8ES are preliminary
+Info (334004): Delay annotation completed successfully
+Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:33
+Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
+Warning (169064): Following 110 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results
+    Info (169065): Pin SI5338_SDA has a permanently disabled output enable
+    Info (169065): Pin AUD_ADCDAT has a permanently disabled output enable
+    Info (169065): Pin AUD_ADCLRCK has a permanently disabled output enable
+    Info (169065): Pin AUD_BCLK has a permanently disabled output enable
+    Info (169065): Pin AUD_DACLRCK has a permanently disabled output enable
+    Info (169065): Pin AUD_I2C_SDAT has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[0] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[1] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[2] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[3] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[4] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[5] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[6] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[7] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[8] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[9] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[10] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[11] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[12] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[13] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[14] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[15] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[16] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[17] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[18] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[19] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[20] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[21] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[22] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[23] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[24] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[25] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[26] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[27] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[28] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[29] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[30] has a permanently disabled output enable
+    Info (169065): Pin DDR3_DQ[31] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[0] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[1] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[2] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[3] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[4] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[5] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[6] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[7] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[8] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[9] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[10] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[11] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[12] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[13] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[14] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[15] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[16] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[17] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[18] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[19] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[20] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[21] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[22] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[23] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[24] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[25] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[26] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[27] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[28] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[29] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[30] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[31] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[32] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[33] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[34] has a permanently disabled output enable
+    Info (169065): Pin GPIO0[35] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[0] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[1] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[2] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[3] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[4] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[5] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[6] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[7] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[8] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[9] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[10] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[11] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[12] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[13] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[14] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[15] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[16] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[17] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[18] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[19] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[20] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[21] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[22] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[23] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[24] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[25] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[26] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[27] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[28] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[29] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[30] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[31] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[32] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[33] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[34] has a permanently disabled output enable
+    Info (169065): Pin GPIO1[35] has a permanently disabled output enable
+Warning (169069): Following 39 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
+    Info (169070): Pin DDR3_CKE has GND driving its datain port
+    Info (169070): Pin DDR3_DM[0] has VCC driving its datain port
+    Info (169070): Pin DDR3_DM[1] has VCC driving its datain port
+    Info (169070): Pin DDR3_DM[2] has VCC driving its datain port
+    Info (169070): Pin DDR3_DM[3] has VCC driving its datain port
+    Info (169070): Pin DDR3_ODT has VCC driving its datain port
+    Info (169070): Pin DDR3_RESET_n has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[0] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[1] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[2] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[3] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[4] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[5] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[6] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[7] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[8] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[9] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[10] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[11] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[12] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[13] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[14] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[15] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[16] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[17] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[18] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[19] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[20] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[21] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[22] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[23] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[24] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[25] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[26] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[27] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[28] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[29] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[30] has VCC driving its datain port
+    Info (169070): Pin DDR3_DQ[31] has VCC driving its datain port
+Info (144001): Generated suppressed messages file /home/markw/fpga/svn/repo/trunk/atari_800xl/sockit/build/atari800core.fit.smsg
+Info: Quartus II 64-Bit Fitter was successful. 0 errors, 83 warnings
+    Info: Peak virtual memory: 1999 megabytes
+    Info: Processing ended: Sun Dec 14 20:20:48 2014
+    Info: Elapsed time: 00:02:24
+    Info: Total CPU time (on all processors): 00:03:03
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit Assembler
+    Info: Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
+    Info: Processing started: Sun Dec 14 20:20:56 2014
+Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off atari800core -c atari800core
+Info (115030): Assembler is generating device programming files
+Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings
+    Info: Peak virtual memory: 919 megabytes
+    Info: Processing ended: Sun Dec 14 20:21:11 2014
+    Info: Elapsed time: 00:00:15
+    Info: Total CPU time (on all processors): 00:00:14
+Info (293026): Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER
+Info: *******************************************************************
+Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer
+    Info: Version 14.0.0 Build 200 06/17/2014 SJ Web Edition
+    Info: Processing started: Sun Dec 14 20:21:18 2014
+Info: Command: quartus_sta atari800core -c atari800core
+Info: qsta_default_script.tcl version: #1
+Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
+Info (21076): High junction temperature operating condition is not set. Assuming a default value of '85'.
+Info (21076): Low junction temperature operating condition is not set. Assuming a default value of '0'.
+Critical Warning (332012): Synopsys Design Constraints File file not found: 'atari800core.SDC'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
+Info (332142): No user constrained generated clocks found in the design. Calling "derive_pll_clocks -create_base_clocks"
+Info (332110): Deriving PLL clocks
+    Info (332110): create_clock -period 20.000 -waveform {0.000 10.000} -name OSC_50_B3B OSC_50_B3B
+    Info (332110): create_generated_clock -source {pll|pll_pal_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|refclkin} -divide_by 10 -multiply_by 227 -duty_cycle 50.00 -name {pll|pll_pal_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]} {pll|pll_pal_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}
+    Info (332110): create_generated_clock -source {pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|vco0ph[0]} -divide_by 20 -duty_cycle 50.00 -name {pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk} {pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
+Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
+Info (332096): The command derive_clocks did not find any clocks to derive.  No clocks were created or changed.
+Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
+    Info (332098): Cell: pll|pll_pal_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk
+    Info (332098): Cell: pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk
+    Info (332098): Cell: pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT  from: clkin[0]  to: clkout
+Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
+Info: Analyzing Slow 1100mV 85C Model
+Info (332146): Worst-case setup slack is 2.614
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     2.614               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+Info (332146): Worst-case hold slack is 0.528
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.528               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+Info (332146): Worst-case recovery slack is 14.562
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    14.562               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+Info (332146): Worst-case removal slack is 0.922
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.922               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+Info (332146): Worst-case minimum pulse width slack is 0.440
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.440               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] 
+    Info (332119):     7.180               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+    Info (332119):     9.802               0.000 OSC_50_B3B 
+Info: Analyzing Slow 1100mV 0C Model
+Info (334003): Started post-fitting delay annotation
+Warning (334000): Timing characteristics of device 5CSXFC6D6F31C8ES are preliminary
+Info (334004): Delay annotation completed successfully
+Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
+    Info (332098): Cell: pll|pll_pal_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk
+    Info (332098): Cell: pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk
+    Info (332098): Cell: pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT  from: clkin[0]  to: clkout
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332146): Worst-case setup slack is 2.704
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     2.704               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+Info (332146): Worst-case hold slack is 0.555
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.555               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+Info (332146): Worst-case recovery slack is 14.710
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    14.710               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+Info (332146): Worst-case removal slack is 0.791
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.791               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+Info (332146): Worst-case minimum pulse width slack is 0.440
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.440               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] 
+    Info (332119):     7.131               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+    Info (332119):     9.797               0.000 OSC_50_B3B 
+Info: Analyzing Fast 1100mV 85C Model
+Info (334003): Started post-fitting delay annotation
+Warning (334000): Timing characteristics of device 5CSXFC6D6F31C8ES are preliminary
+Info (334004): Delay annotation completed successfully
+Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
+    Info (332098): Cell: pll|pll_pal_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk
+    Info (332098): Cell: pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk
+    Info (332098): Cell: pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT  from: clkin[0]  to: clkout
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332146): Worst-case setup slack is 10.143
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    10.143               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+Info (332146): Worst-case hold slack is 0.179
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.179               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+Info (332146): Worst-case recovery slack is 15.826
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    15.826               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+Info (332146): Worst-case removal slack is 0.358
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.358               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+Info (332146): Worst-case minimum pulse width slack is 0.440
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.440               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] 
+    Info (332119):     7.695               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+    Info (332119):     9.903               0.000 OSC_50_B3B 
+Info: Analyzing Fast 1100mV 0C Model
+Info (332097): The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network.
+    Info (332098): Cell: pll|pll_pal_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL  from: refclkin  to: fbclk
+    Info (332098): Cell: pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER  from: vco0ph[0]  to: divclk
+    Info (332098): Cell: pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_REFCLK_SELECT  from: clkin[0]  to: clkout
+Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
+Info (332146): Worst-case setup slack is 10.899
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    10.899               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+Info (332146): Worst-case hold slack is 0.171
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.171               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+Info (332146): Worst-case recovery slack is 16.012
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):    16.012               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+Info (332146): Worst-case removal slack is 0.287
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.287               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+Info (332146): Worst-case minimum pulse width slack is 0.440
+    Info (332119):     Slack       End Point TNS Clock 
+    Info (332119): ========= =================== =====================
+    Info (332119):     0.440               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] 
+    Info (332119):     7.694               0.000 pll|pll_pal_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk 
+    Info (332119):     9.908               0.000 OSC_50_B3B 
+Info (332102): Design is not fully constrained for setup requirements
+Info (332102): Design is not fully constrained for hold requirements
+Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings
+    Info: Peak virtual memory: 1292 megabytes
+    Info: Processing ended: Sun Dec 14 20:21:54 2014
+    Info: Elapsed time: 00:00:36
+    Info: Total CPU time (on all processors): 00:00:51
+Info (293000): Quartus II Full Compilation was successful. 0 errors, 153 warnings
+Info (23030): Evaluation of Tcl script /home/markw/fpga/altera/14.0/quartus/common/tcl/internal/qsh_flow.tcl was successful
+Info: Quartus II 64-Bit Shell was successful. 0 errors, 153 warnings
+    Info: Peak virtual memory: 294 megabytes
+    Info: Processing ended: Sun Dec 14 20:21:59 2014
+    Info: Elapsed time: 00:04:53
+    Info: Total CPU time (on all processors): 00:05:31
Index: sockit/build.sh
===================================================================
--- sockit/build.sh	(nonexistent)
+++ sockit/build.sh	(revision 302)
@@ -0,0 +1,22 @@
+rm -rf build
+mkdir build
+cp atari800core_sockit.vhdl build
+cp altiobuf.* build
+cp altiobufo.* build
+cp pll_pal.* build
+cp -r pll_pal build
+cp -r pll_pal_sim build
+cp atari800core.sdc build
+
+mkdir build/common
+mkdir build/common/a8core
+mkdir build/common/components
+mkdir build/common/zpu
+cp ../common/a8core/* ./build/common/a8core
+cp ../common/components/* ./build/common/components
+cp ../common/zpu/* ./build/common/zpu
+
+cd build
+../makeqsf ../atari800core.qsf ./common/a8core ./common/components ./common/zpu
+
+quartus_sh --flow compile atari800core

Property changes on: sockit/build.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sockit/makeqsf
===================================================================
--- sockit/makeqsf	(nonexistent)
+++ sockit/makeqsf	(revision 302)
@@ -0,0 +1,40 @@
+#!/usr/bin/perl -w
+use strict;
+
+my $qsf_in = shift @ARGV;
+my $qsf_out = $qsf_in;
+$qsf_out =~ s/.*\///;
+
+open (QSF_IN,$qsf_in) or die "Failed to open $qsf_in";
+my @qsf_base = <QSF_IN>;
+close (QSF_IN);
+
+open (QSF_OUT,">$qsf_out") or die "Failed to open $qsf_out";
+print QSF_OUT @qsf_base;
+print QSF_OUT "\n";
+
+foreach (@ARGV)
+{
+	my @vhdl = glob ("$_/*.vhd");
+	push @vhdl, glob ("$_/*.vhdl");
+	my @verilog = glob ("$_/*.v");
+	my @qip = glob ("$_/*.qip");
+
+	foreach (@verilog)
+	{
+		print QSF_OUT "set_global_assignment -name VERILOG_FILE $_\n";
+	}
+
+	foreach (@vhdl)
+	{
+		print QSF_OUT "set_global_assignment -name VHDL_FILE $_\n";
+	}
+
+	foreach (@qip)
+	{
+		print QSF_OUT "set_global_assignment -name QIP_FILE $_\n";
+	}
+}
+
+close (QSF_OUT);
+

Property changes on: sockit/makeqsf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: sockit/pll_pal/pll_pal_0002.qip
===================================================================
--- sockit/pll_pal/pll_pal_0002.qip	(nonexistent)
+++ sockit/pll_pal/pll_pal_0002.qip	(revision 302)
@@ -0,0 +1,4 @@
+set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*pll_pal_0002*|altera_pll:altera_pll_i*|*"
+ 
+set_instance_assignment -name PLL_AUTO_RESET OFF -to "*pll_pal_0002*|altera_pll:altera_pll_i*|*"
+set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*pll_pal_0002*|altera_pll:altera_pll_i*|*"
Index: sockit/pll_pal/pll_pal_0002.v
===================================================================
--- sockit/pll_pal/pll_pal_0002.v	(nonexistent)
+++ sockit/pll_pal/pll_pal_0002.v	(revision 302)
@@ -0,0 +1,87 @@
+`timescale 1ns/10ps
+module  pll_pal_0002(
+
+	// interface 'refclk'
+	input wire refclk,
+
+	// interface 'reset'
+	input wire rst,
+
+	// interface 'outclk0'
+	output wire outclk_0,
+
+	// interface 'locked'
+	output wire locked
+);
+
+	altera_pll #(
+		.fractional_vco_multiplier("false"),
+		.reference_clock_frequency("50.0 MHz"),
+		.operation_mode("normal"),
+		.number_of_clocks(1),
+		.output_clock_frequency0("56.750000 MHz"),
+		.phase_shift0("0 ps"),
+		.duty_cycle0(50),
+		.output_clock_frequency1("0 MHz"),
+		.phase_shift1("0 ps"),
+		.duty_cycle1(50),
+		.output_clock_frequency2("0 MHz"),
+		.phase_shift2("0 ps"),
+		.duty_cycle2(50),
+		.output_clock_frequency3("0 MHz"),
+		.phase_shift3("0 ps"),
+		.duty_cycle3(50),
+		.output_clock_frequency4("0 MHz"),
+		.phase_shift4("0 ps"),
+		.duty_cycle4(50),
+		.output_clock_frequency5("0 MHz"),
+		.phase_shift5("0 ps"),
+		.duty_cycle5(50),
+		.output_clock_frequency6("0 MHz"),
+		.phase_shift6("0 ps"),
+		.duty_cycle6(50),
+		.output_clock_frequency7("0 MHz"),
+		.phase_shift7("0 ps"),
+		.duty_cycle7(50),
+		.output_clock_frequency8("0 MHz"),
+		.phase_shift8("0 ps"),
+		.duty_cycle8(50),
+		.output_clock_frequency9("0 MHz"),
+		.phase_shift9("0 ps"),
+		.duty_cycle9(50),
+		.output_clock_frequency10("0 MHz"),
+		.phase_shift10("0 ps"),
+		.duty_cycle10(50),
+		.output_clock_frequency11("0 MHz"),
+		.phase_shift11("0 ps"),
+		.duty_cycle11(50),
+		.output_clock_frequency12("0 MHz"),
+		.phase_shift12("0 ps"),
+		.duty_cycle12(50),
+		.output_clock_frequency13("0 MHz"),
+		.phase_shift13("0 ps"),
+		.duty_cycle13(50),
+		.output_clock_frequency14("0 MHz"),
+		.phase_shift14("0 ps"),
+		.duty_cycle14(50),
+		.output_clock_frequency15("0 MHz"),
+		.phase_shift15("0 ps"),
+		.duty_cycle15(50),
+		.output_clock_frequency16("0 MHz"),
+		.phase_shift16("0 ps"),
+		.duty_cycle16(50),
+		.output_clock_frequency17("0 MHz"),
+		.phase_shift17("0 ps"),
+		.duty_cycle17(50),
+		.pll_type("General"),
+		.pll_subtype("General")
+	) altera_pll_i (
+		.rst	(rst),
+		.outclk	({outclk_0}),
+		.locked	(locked),
+		.fboutclk	( ),
+		.fbclk	(1'b0),
+		.refclk	(refclk)
+	);
+endmodule
+
Index: sockit/pll_pal.bsf
===================================================================
--- sockit/pll_pal.bsf	(nonexistent)
+++ sockit/pll_pal.bsf	(revision 302)
@@ -0,0 +1,82 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus II License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 160 144)
+	(text "pll_pal" (rect 62 -1 85 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 128 20 140)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
+		(text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 48 72)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8)))
+		(text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 48 112)(line_width 1))
+	)
+	(port
+		(pt 160 72)
+		(output)
+		(text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8)))
+		(text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8)))
+		(line (pt 160 72)(pt 112 72)(line_width 1))
+	)
+	(port
+		(pt 160 112)
+		(output)
+		(text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8)))
+		(text "locked" (rect 127 101 163 112)(font "Arial" (font_size 8)))
+		(line (pt 160 112)(pt 112 112)(line_width 1))
+	)
+	(drawing
+		(text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0)))
+		(text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0)))
+		(text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0)))
+		(text "locked" (rect 113 83 262 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 82 107 200 224)(font "Arial" (color 0 0 0)))
+		(text " altera_pll " (rect 118 128 308 266)(font "Arial" ))
+		(line (pt 48 32)(pt 112 32)(line_width 1))
+		(line (pt 112 32)(pt 112 128)(line_width 1))
+		(line (pt 48 128)(pt 112 128)(line_width 1))
+		(line (pt 48 32)(pt 48 128)(line_width 1))
+		(line (pt 49 52)(pt 49 76)(line_width 1))
+		(line (pt 50 52)(pt 50 76)(line_width 1))
+		(line (pt 49 92)(pt 49 116)(line_width 1))
+		(line (pt 50 92)(pt 50 116)(line_width 1))
+		(line (pt 111 52)(pt 111 76)(line_width 1))
+		(line (pt 110 52)(pt 110 76)(line_width 1))
+		(line (pt 111 92)(pt 111 116)(line_width 1))
+		(line (pt 110 92)(pt 110 116)(line_width 1))
+		(line (pt 0 0)(pt 160 0)(line_width 1))
+		(line (pt 160 0)(pt 160 144)(line_width 1))
+		(line (pt 0 144)(pt 160 144)(line_width 1))
+		(line (pt 0 0)(pt 0 144)(line_width 1))
+	)
+)
Index: sockit/pll_pal.ppf
===================================================================
--- sockit/pll_pal.ppf	(nonexistent)
+++ sockit/pll_pal.ppf	(revision 302)
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<pinplan
+ variation_name="pll_pal"
+ megafunction_name="ALTERA_PLL"
+ intended_family="Cyclone V"
+ specifies="all_ports">
+ <global>
+  <pin name="refclk" direction="input" scope="external" />
+  <pin name="rst" direction="input" scope="external" />
+  <pin name="outclk_0" direction="output" scope="external" />
+  <pin name="locked" direction="output" scope="external" />
+ </global>
+</pinplan>
Index: sockit/pll_pal.sip
===================================================================
--- sockit/pll_pal.sip	(nonexistent)
+++ sockit/pll_pal.sip	(revision 302)
@@ -0,0 +1,6 @@
+set_global_assignment -entity "pll_pal" -library "lib_pll_pal" -name IP_TOOL_NAME "altera_pll"
+set_global_assignment -entity "pll_pal" -library "lib_pll_pal" -name IP_TOOL_VERSION "14.0"
+set_global_assignment -entity "pll_pal" -library "lib_pll_pal" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "lib_pll_pal" -name SPD_FILE [file join $::quartus(sip_path) "pll_pal.spd"]
+
+set_global_assignment -library "lib_pll_pal" -name MISC_FILE [file join $::quartus(sip_path) "pll_pal_sim/pll_pal.vho"]
Index: sockit/pll_pal.vhd
===================================================================
--- sockit/pll_pal.vhd	(nonexistent)
+++ sockit/pll_pal.vhd	(revision 302)
@@ -0,0 +1,273 @@
+-- megafunction wizard: %Altera PLL v14.0%
+-- GENERATION: XML
+-- pll_pal.vhd
+
+-- Generated using ACDS version 14.0 200 at 2014.12.14.13:40:40
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity pll_pal is
+	port (
+		refclk   : in  std_logic := '0'; --  refclk.clk
+		rst      : in  std_logic := '0'; --   reset.reset
+		outclk_0 : out std_logic;        -- outclk0.clk
+		locked   : out std_logic         --  locked.export
+	);
+end entity pll_pal;
+
+architecture rtl of pll_pal is
+	component pll_pal_0002 is
+		port (
+			refclk   : in  std_logic := 'X'; -- clk
+			rst      : in  std_logic := 'X'; -- reset
+			outclk_0 : out std_logic;        -- clk
+			locked   : out std_logic         -- export
+		);
+	end component pll_pal_0002;
+
+begin
+
+	pll_pal_inst : component pll_pal_0002
+		port map (
+			refclk   => refclk,   --  refclk.clk
+			rst      => rst,      --   reset.reset
+			outclk_0 => outclk_0, -- outclk0.clk
+			locked   => locked    --  locked.export
+		);
+
+end architecture rtl; -- of pll_pal
+-- Retrieval info: <?xml version="1.0"?>
+--<!--
+--	Generated by Altera MegaWizard Launcher Utility version 1.0
+--	************************************************************
+--	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--	************************************************************
+--	Copyright (C) 1991-2014 Altera Corporation
+--	Any megafunction design, and related net list (encrypted or decrypted),
+--	support information, device programming or simulation file, and any other
+--	associated documentation or information provided by Altera or a partner
+--	under Altera's Megafunction Partnership Program may be used only to
+--	program PLD devices (but not masked PLD devices) from Altera.  Any other
+--	use of such megafunction design, net list, support information, device
+--	programming or simulation file, or any other related documentation or
+--	information is prohibited for any other purpose, including, but not
+--	limited to modification, reverse engineering, de-compiling, or use with
+--	any other silicon devices, unless such use is explicitly licensed under
+--	a separate agreement with Altera or a megafunction partner.  Title to
+--	the intellectual property, including patents, copyrights, trademarks,
+--	trade secrets, or maskworks, embodied in any such megafunction design,
+--	net list, support information, device programming or simulation file, or
+--	any other related documentation or information provided by Altera or a
+--	megafunction partner, remains with Altera, the megafunction partner, or
+--	their respective licensors.  No other licenses, including any licenses
+--	needed under any third party's intellectual property, are provided herein.
+---->
+-- Retrieval info: <instance entity-name="altera_pll" version="14.0" >
+-- Retrieval info: 	<generic name="debug_print_output" value="false" />
+-- Retrieval info: 	<generic name="debug_use_rbc_taf_method" value="false" />
+-- Retrieval info: 	<generic name="device_family" value="Cyclone V" />
+-- Retrieval info: 	<generic name="device" value="Unknown" />
+-- Retrieval info: 	<generic name="gui_device_speed_grade" value="8" />
+-- Retrieval info: 	<generic name="gui_pll_mode" value="Integer-N PLL" />
+-- Retrieval info: 	<generic name="gui_reference_clock_frequency" value="50.0" />
+-- Retrieval info: 	<generic name="gui_channel_spacing" value="0.0" />
+-- Retrieval info: 	<generic name="gui_operation_mode" value="normal" />
+-- Retrieval info: 	<generic name="gui_feedback_clock" value="Global Clock" />
+-- Retrieval info: 	<generic name="gui_fractional_cout" value="32" />
+-- Retrieval info: 	<generic name="gui_dsm_out_sel" value="1st_order" />
+-- Retrieval info: 	<generic name="gui_use_locked" value="true" />
+-- Retrieval info: 	<generic name="gui_en_adv_params" value="false" />
+-- Retrieval info: 	<generic name="gui_number_of_clocks" value="1" />
+-- Retrieval info: 	<generic name="gui_multiply_factor" value="1" />
+-- Retrieval info: 	<generic name="gui_frac_multiply_factor" value="1" />
+-- Retrieval info: 	<generic name="gui_divide_factor_n" value="1" />
+-- Retrieval info: 	<generic name="gui_cascade_counter0" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency0" value="56.75032" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c0" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units0" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift0" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg0" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift0" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle0" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter1" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency1" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c1" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units1" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift1" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg1" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift1" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle1" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter2" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency2" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c2" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units2" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift2" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg2" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift2" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle2" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter3" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency3" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c3" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units3" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift3" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg3" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift3" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle3" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter4" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency4" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c4" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units4" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift4" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg4" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift4" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle4" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter5" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency5" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c5" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units5" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift5" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg5" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift5" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle5" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter6" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency6" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c6" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units6" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift6" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg6" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift6" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle6" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter7" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency7" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c7" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units7" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift7" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg7" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift7" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle7" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter8" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency8" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c8" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units8" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift8" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg8" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift8" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle8" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter9" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency9" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c9" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units9" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift9" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg9" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift9" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle9" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter10" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency10" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c10" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units10" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift10" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg10" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift10" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle10" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter11" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency11" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c11" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units11" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift11" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg11" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift11" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle11" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter12" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency12" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c12" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units12" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift12" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg12" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift12" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle12" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter13" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency13" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c13" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units13" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift13" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg13" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift13" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle13" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter14" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency14" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c14" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units14" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift14" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg14" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift14" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle14" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter15" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency15" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c15" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units15" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift15" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg15" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift15" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle15" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter16" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency16" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c16" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units16" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift16" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg16" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift16" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle16" value="50" />
+-- Retrieval info: 	<generic name="gui_cascade_counter17" value="false" />
+-- Retrieval info: 	<generic name="gui_output_clock_frequency17" value="100.0" />
+-- Retrieval info: 	<generic name="gui_divide_factor_c17" value="1" />
+-- Retrieval info: 	<generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
+-- Retrieval info: 	<generic name="gui_ps_units17" value="ps" />
+-- Retrieval info: 	<generic name="gui_phase_shift17" value="0" />
+-- Retrieval info: 	<generic name="gui_phase_shift_deg17" value="0.0" />
+-- Retrieval info: 	<generic name="gui_actual_phase_shift17" value="0" />
+-- Retrieval info: 	<generic name="gui_duty_cycle17" value="50" />
+-- Retrieval info: 	<generic name="gui_pll_auto_reset" value="Off" />
+-- Retrieval info: 	<generic name="gui_pll_bandwidth_preset" value="Auto" />
+-- Retrieval info: 	<generic name="gui_en_reconf" value="false" />
+-- Retrieval info: 	<generic name="gui_en_dps_ports" value="false" />
+-- Retrieval info: 	<generic name="gui_en_phout_ports" value="false" />
+-- Retrieval info: 	<generic name="gui_phout_division" value="1" />
+-- Retrieval info: 	<generic name="gui_en_lvds_ports" value="false" />
+-- Retrieval info: 	<generic name="gui_mif_generate" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_mif_dps" value="false" />
+-- Retrieval info: 	<generic name="gui_dps_cntr" value="C0" />
+-- Retrieval info: 	<generic name="gui_dps_num" value="1" />
+-- Retrieval info: 	<generic name="gui_dps_dir" value="Positive" />
+-- Retrieval info: 	<generic name="gui_refclk_switch" value="false" />
+-- Retrieval info: 	<generic name="gui_refclk1_frequency" value="100.0" />
+-- Retrieval info: 	<generic name="gui_switchover_mode" value="Automatic Switchover" />
+-- Retrieval info: 	<generic name="gui_switchover_delay" value="0" />
+-- Retrieval info: 	<generic name="gui_active_clk" value="false" />
+-- Retrieval info: 	<generic name="gui_clk_bad" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_cascade_out" value="false" />
+-- Retrieval info: 	<generic name="gui_cascade_outclk_index" value="0" />
+-- Retrieval info: 	<generic name="gui_enable_cascade_in" value="false" />
+-- Retrieval info: 	<generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
+-- Retrieval info: 	<generic name="AUTO_REFCLK_CLOCK_RATE" value="-1" />
+-- Retrieval info: </instance>
+-- IPFS_FILES : pll_pal.vho
+-- RELATED_FILES: pll_pal.vhd, pll_pal_0002.v
Index: sockit/pll_pal_sim/cadence/cds.lib
===================================================================
--- sockit/pll_pal_sim/cadence/cds.lib	(nonexistent)
+++ sockit/pll_pal_sim/cadence/cds.lib	(revision 302)
@@ -0,0 +1,17 @@
+
+DEFINE std            $CDS_ROOT/tools/inca/files/STD/           
+DEFINE synopsys       $CDS_ROOT/tools/inca/files/SYNOPSYS/      
+DEFINE ieee           $CDS_ROOT/tools/inca/files/IEEE/          
+DEFINE ambit          $CDS_ROOT/tools/inca/files/AMBIT/         
+DEFINE vital_memory   $CDS_ROOT/tools/inca/files/VITAL_MEMORY/  
+DEFINE ncutils        $CDS_ROOT/tools/inca/files/NCUTILS/       
+DEFINE ncinternal     $CDS_ROOT/tools/inca/files/NCINTERNAL/    
+DEFINE ncmodels       $CDS_ROOT/tools/inca/files/NCMODELS/      
+DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work           ./libraries/work/                         
+DEFINE altera         ./libraries/altera/                       
+DEFINE lpm            ./libraries/lpm/                          
+DEFINE sgate          ./libraries/sgate/                        
+DEFINE altera_mf      ./libraries/altera_mf/                    
+DEFINE altera_lnsim   ./libraries/altera_lnsim/                 
+DEFINE cyclonev       ./libraries/cyclonev/                     
Index: sockit/pll_pal_sim/mentor/msim_setup.tcl
===================================================================
--- sockit/pll_pal_sim/mentor/msim_setup.tcl	(nonexistent)
+++ sockit/pll_pal_sim/mentor/msim_setup.tcl	(revision 302)
@@ -0,0 +1,171 @@
+
+# (C) 2001-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 14.0 200 linux 2014.12.14.13:40:56
+
+# ----------------------------------------
+# Auto-generated simulation script
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] { 
+  set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
+  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] { 
+  set TOP_LEVEL_NAME "pll_pal"
+}
+
+if ![info exists QSYS_SIMDIR] { 
+  set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] { 
+  set QUARTUS_INSTALL_DIR "/home/markw/fpga/altera/14.0/quartus/"
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+  echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib          ./libraries/     
+ensure_lib          ./libraries/work/
+vmap       work     ./libraries/work/
+vmap       work_lib ./libraries/work/
+if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+  ensure_lib              ./libraries/altera/      
+  vmap       altera       ./libraries/altera/      
+  ensure_lib              ./libraries/lpm/         
+  vmap       lpm          ./libraries/lpm/         
+  ensure_lib              ./libraries/sgate/       
+  vmap       sgate        ./libraries/sgate/       
+  ensure_lib              ./libraries/altera_mf/   
+  vmap       altera_mf    ./libraries/altera_mf/   
+  ensure_lib              ./libraries/altera_lnsim/
+  vmap       altera_lnsim ./libraries/altera_lnsim/
+  ensure_lib              ./libraries/cyclonev/    
+  vmap       cyclonev     ./libraries/cyclonev/    
+}
+
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+  echo "\[exec\] dev_com"
+  if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+    vlog -sv "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv"  -work altera_lnsim
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+    vlog     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v"   -work cyclonev    
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+    vcom     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+  }
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+  echo "\[exec\] com"
+  vcom "$QSYS_SIMDIR/pll_pal.vho"
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+  echo "\[exec\] elab"
+  eval vsim -t ps $ELAB_OPTIONS -L work -L work_lib -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with novopt option
+alias elab_debug {
+  echo "\[exec\] elab_debug"
+  eval vsim -novopt -t ps $ELAB_OPTIONS -L work -L work_lib -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cyclonev $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+  dev_com
+  com
+  elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -novopt
+alias ld_debug "
+  dev_com
+  com
+  elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+  echo "List Of Command Line Aliases"
+  echo
+  echo "file_copy                     -- Copy ROM/RAM files to simulation directory"
+  echo
+  echo "dev_com                       -- Compile device library files"
+  echo
+  echo "com                           -- Compile the design files in correct order"
+  echo
+  echo "elab                          -- Elaborate top level design"
+  echo
+  echo "elab_debug                    -- Elaborate the top level design with novopt option"
+  echo
+  echo "ld                            -- Compile all the design files and elaborate the top level design"
+  echo
+  echo "ld_debug                      -- Compile all the design files and elaborate the top level design with -novopt"
+  echo
+  echo 
+  echo
+  echo "List Of Variables"
+  echo
+  echo "TOP_LEVEL_NAME                -- Top level module name."
+  echo
+  echo "SYSTEM_INSTANCE_NAME          -- Instantiated system module name inside top level module."
+  echo
+  echo "QSYS_SIMDIR                   -- Qsys base simulation directory."
+  echo
+  echo "QUARTUS_INSTALL_DIR           -- Quartus installation directory."
+}
+file_copy
+h
Index: sockit/pll_pal_sim/synopsys/vcsmx/vcsmx_setup.sh
===================================================================
--- sockit/pll_pal_sim/synopsys/vcsmx/vcsmx_setup.sh	(nonexistent)
+++ sockit/pll_pal_sim/synopsys/vcsmx/vcsmx_setup.sh	(revision 302)
@@ -0,0 +1,107 @@
+
+# (C) 2001-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 14.0 200 linux 2014.12.14.13:40:56
+
+# ----------------------------------------
+# vcsmx - auto-generated simulation script
+
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="pll_pal"
+QSYS_SIMDIR="./../../"
+QUARTUS_INSTALL_DIR="/home/markw/fpga/altera/14.0/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for 
+# overwriting variables. An example usage:
+#   sh <simulator>_setup.sh SKIP_ELAB=1 SKIP_SIM=1
+for expression in "$@"; do
+  eval $expression
+  if [ $? -ne 0 ]; then
+    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+    exit $?
+  fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `vcs -platform` != *"amd64"* ]]; then
+  :
+else
+  :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/altera/
+mkdir -p ./libraries/lpm/
+mkdir -p ./libraries/sgate/
+mkdir -p ./libraries/altera_mf/
+mkdir -p ./libraries/altera_lnsim/
+mkdir -p ./libraries/cyclonev/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera      
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera      
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera      
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera      
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera      
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera      
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm         
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm         
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate       
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate       
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf   
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf   
+  vlogan +v2k -sverilog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim
+  vlogan +v2k           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev    
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.vhd"               -work cyclonev    
+  vhdlan                "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_components.vhd"          -work cyclonev    
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+  vhdlan -xlrm "$QSYS_SIMDIR/pll_pal.vho"
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+  vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+  ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
+fi

Property changes on: sockit/pll_pal_sim/synopsys/vcsmx/vcsmx_setup.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
