Index: de1/zpu_config_regs.vhdl
===================================================================
--- de1/zpu_config_regs.vhdl	(revision 23)
+++ de1/zpu_config_regs.vhdl	(nonexistent)
@@ -1,501 +0,0 @@
----------------------------------------------------------------------------
--- (c) 2013 mark watson
--- I am happy for anyone to use this for non-commercial use.
--- If my vhdl files are used commercially or otherwise sold,
--- please contact me for explicit permission at scrameta (gmail).
--- This applies for source and binary form and derived works.
----------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-ENTITY zpu_config_regs IS
-PORT 
-( 
-	CLK : IN STD_LOGIC;
-	
-	ENABLE_179 : in std_logic;
-	
-	ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
-	CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-	WR_EN : IN STD_LOGIC;
-	
-	-- SWITCHES
-	SWITCH : in std_logic_vector(9 downto 0); -- already synchronized
-	KEY : in std_logic_vector(3 downto 0); -- already synchronized
-	
-	-- LEDS
-	LEDG : out std_logic_vector(7 downto 0);
-	LEDR : out std_logic_vector(9 downto 0);
-	
-	-- SDCARD
-	SDCARD_CLK : out std_logic;
-	SDCARD_CMD : out std_logic;
-	SDCARD_DAT : in std_logic;
-	SDCARD_DAT3 : out std_logic;
-	
-	-- ATARI interface (in future we can also turbo load by directly hitting memory...)
-	SIO_DATA_IN  : out std_logic;
-	SIO_COMMAND_OUT : in std_logic;
-	SIO_DATA_OUT : in std_logic;
-	
-	-- CPU interface
-	DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-	PAUSE_ZPU : out std_logic;
-	
-	-- SYSTEM CONFIG SETTINGS (legacy from switches - hardcoded to start with, then much fancier)
-	PAL : OUT STD_LOGIC;
-	USE_SDRAM : OUT STD_LOGIC;
-	RAM_SELECT : OUT STD_LOGIC_VECTOR(1 downto 0);
-	VGA : OUT STD_LOGIC;
-	COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
-	GPIO_ENABLE : OUT STD_LOGIC;
-	ROM_SELECT : out stD_logic_vector(1 downto 0);
-
-	-- system reset/halt
-	PLL_LOCKED : IN STD_LOGIC; -- pll locked
-	REQUEST_RESET_ZPU : in std_logic; -- from keyboard (f12 to start with)
-	
-	RESET_6502 : OUT STD_LOGIC; -- i.e. cpu reset - 6502
-	RESET_ZPU : OUT STD_LOGIC; -- i.e. cpu reset - zpu
-	RESET_N : OUT STD_LOGIC; -- i.e. reset line on flip flops
-	
-	PAUSE_6502 : out std_logic;
-	
-	THROTTLE_COUNT_6502 : out std_logic_vector(5 downto 0);
-	
-	ZPU_HEX : out std_logic_vector(15 downto 0)
-
---	-- synchronize async inputs
---	locked_synchronizer : synchronizer
---		port map (clk=>clk, raw=>LOCKED, sync=>LOCKED_REG);
-	
-);
-END zpu_config_regs;
-
-ARCHITECTURE vhdl OF zpu_config_regs IS
-	COMPONENT complete_address_decoder IS
-	generic (width : natural := 4);
-	PORT 
-	( 
-		addr_in : in std_logic_vector(width-1 downto 0);			
-		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
-	);
-	END component;
-	
-	COMPONENT spi_master IS
-	  GENERIC(
-		 slaves  : INTEGER := 4;  --number of spi slaves
-		 d_width : INTEGER := 2); --data bus width
-	  PORT(
-		 clock   : IN     STD_LOGIC;                             --system clock
-		 reset_n : IN     STD_LOGIC;                             --asynchronous reset
-		 enable  : IN     STD_LOGIC;                             --initiate transaction
-		 cpol    : IN     STD_LOGIC;                             --spi clock polarity
-		 cpha    : IN     STD_LOGIC;                             --spi clock phase
-		 cont    : IN     STD_LOGIC;                             --continuous mode command
-		 clk_div : IN     INTEGER;                               --system clock cycles per 1/2 period of sclk
-		 addr    : IN     INTEGER;                               --address of slave
-		 tx_data : IN     STD_LOGIC_VECTOR(d_width-1 DOWNTO 0);  --data to transmit
-		 miso    : IN     STD_LOGIC;                             --master in, slave out
-		 sclk    : BUFFER STD_LOGIC;                             --spi clock
-		 ss_n    : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0);   --slave select
-		 mosi    : OUT    STD_LOGIC;                             --master out, slave in
-		 busy    : OUT    STD_LOGIC;                             --busy / data ready signal
-		 rx_data : OUT    STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
-	END component;	
-	
-
-	component pokey IS
-	PORT 
-	( 
-		CLK : IN STD_LOGIC;
-		--ENABLE_179 :in std_logic;
-		CPU_MEMORY_READY :in std_logic;
-		ANTIC_MEMORY_READY :in std_logic;
-		ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		WR_EN : IN STD_LOGIC;
-		
-		RESET_N : IN STD_LOGIC;
-		
-		-- keyboard interface
-		keyboard_scan : out std_logic_vector(5 downto 0);
-		keyboard_response : in std_logic_vector(1 downto 0);
-		
-		-- pots - go high as capacitor charges
-		POT_IN : in std_logic_vector(7 downto 0);
-		
-		-- sio interface
-		SIO_IN1 : IN std_logic;
-		SIO_IN2 : IN std_logic;
-		SIO_IN3 : IN std_logic;
-		
-		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-		
-		CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
-		CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
-		CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
-		CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
-		
-		IRQ_N_OUT : OUT std_logic;
-		
-		SIO_OUT1 : OUT std_logic;
-		SIO_OUT2 : OUT std_logic;
-		SIO_OUT3 : OUT std_logic;
-		
-		SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
-		
-		POT_RESET : out std_logic
-	);
-	END component;	
-	
-	function vectorize(s: std_logic) return std_logic_vector is
-	variable v: std_logic_vector(0 downto 0);
-	begin
-		v(0) := s;
-		return v;
-	end;
-	
-	signal addr_decoded : std_logic_vector(15 downto 0);	
-	
-	signal config_6502_next : std_logic_vector(7 downto 0);
-	signal config_6502_reg : std_logic_vector(7 downto 0);
-	signal ram_select_next : std_logic_vector(1 downto 0);
-	signal ram_select_reg : std_logic_vector(1 downto 0);
-	signal rom_select_next : std_logic_vector(1 downto 0);
-	signal rom_select_reg : std_logic_vector(1 downto 0);
-	signal gpio_enable_next : std_logic;
-	signal gpio_enable_reg : std_logic;
-	
-	signal pause_next : std_logic_vector(31 downto 0);
-	signal pause_reg : std_logic_vector(31 downto 0);
-	signal paused_next : std_logic;
-	signal paused_reg : std_logic;
-	
-	signal ledg_next : std_logic_vector(7 downto 0);
-	signal ledg_reg : std_logic_vector(7 downto 0);
-
-	signal ledr_next : std_logic_vector(9 downto 0);
-	signal ledr_reg : std_logic_vector(9 downto 0);
-	
-	signal reset_n_next : std_logic;
-	signal reset_n_reg : std_logic;
-	
-	signal reset_6502_cpu_next : std_logic;
-	signal reset_6502_cpu_reg : std_logic;
-	
-	signal reset_zpu_next : std_logic;
-	signal reset_zpu_reg : std_logic;	
-	
-	signal spi_miso : std_logic;
-	signal spi_mosi : std_logic;
-	signal spi_busy : std_logic;	
-	signal spi_enable : std_logic;
-	signal spi_chip_select : std_logic_vector(0 downto 0);
-	signal spi_clk_out : std_logic;
-	
-	signal spi_tx_data : std_logic_vector(7 downto 0);
-	signal spi_rx_data : std_logic_vector(7 downto 0);
-	
-	signal spi_addr_next : std_logic;
-	signal spi_addr_reg : std_logic;
-	signal spi_speed_next : std_logic_vector(7 downto 0);
-	signal spi_speed_reg : std_logic_vector(7 downto 0);
-
-	signal zpu_hex_next : std_logic_vector(15 downto 0);
-	signal zpu_hex_reg : std_logic_vector(15 downto 0);
-	
-	signal pokey_data_out : std_logic_vector(7 downto 0);
-begin
-	-- register
-	process(clk,pll_locked)
-	begin
-		if (clk'event and clk='1') then	
-			if (pll_locked = '0') then
-				config_6502_reg <= "1"&"0"&"011111"; -- reset_6502, halt_6502, run_every 32 cycles
-				rom_select_reg <= "01";
-				ram_select_reg <= "10";
-				gpio_enable_reg <= '0';
-				pause_reg <= (others=>'0');
-				paused_reg <= '0';
-				ledg_reg <= (others=>'0');
-				ledr_reg <= (others=>'0');
-				
-				spi_addr_reg <= '1';
-				spi_speed_reg <= X"80";
-				
-				zpu_hex_reg <= X"b007";
-				
-				reset_n_reg <= '0';			
-				reset_zpu_reg <= '1';
-				reset_6502_cpu_reg <= '1';											
-			else
-				config_6502_reg <= config_6502_next;
-				rom_select_reg <= rom_select_next;
-				ram_select_reg <= ram_select_next;
-				gpio_enable_reg <= gpio_enable_next;			
-				pause_reg <= pause_next;
-				paused_reg <= paused_next;
-				ledg_reg <= ledg_next;
-				ledr_reg <= ledr_next;
-				
-				spi_addr_reg <= spi_addr_next;
-				spi_speed_reg <= spi_speed_next;
-	
-				zpu_hex_reg <= zpu_hex_next;
-	
-				reset_n_reg <= reset_n_next;			
-				reset_zpu_reg <= reset_zpu_next;
-				reset_6502_cpu_reg <= reset_6502_cpu_next;							
-			end if;
-		end if;
-	end process;
-
-	-- decode address
-	decode_addr1 : complete_address_decoder
-		generic map(width=>4)
-		port map (addr_in=>addr(3 downto 0), addr_decoded=>addr_decoded);
-
-	-- spi - for sd card access without bit banging...
-	-- 200KHz to start with - probably fine for 8-bit, can up it later after init
-	spi_master1 : spi_master
-		generic map(slaves=>1,d_width=>8)
-		port map (clock=>clk,reset_n=>pll_locked,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>to_integer(unsigned(spi_speed_reg)),addr=>to_integer(unsigned(vectorize(spi_addr_reg))),
-		          tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk_out,ss_n=>spi_chip_select,mosi=>spi_mosi,
-					 rx_data=>spi_rx_data,busy=>spi_busy);
-					 
-	-- spi-programming model:
-	-- reg for write/read
-	-- data (send/receive)
-	-- busy
-	-- speed - 0=400KHz, 1=10MHz? Start with 400KHz then atari800core...
-	-- chip select
-	
-	-- uart - another Pokey! Running at atari frequency.
-	uart1 : pokey
-		port map (clk=>clk,CPU_MEMORY_READY=>enable_179,ANTIC_MEMORY_READY=>enable_179,addr=>addr(3 downto 0),data_in=>cpu_data_in(7 downto 0),wr_en=>addr(4) and wr_en, 
-		reset_n=>pll_locked,keyboard_response=>"11",pot_in=>X"00",
-		sio_in1=>sio_data_out,sio_in2=>'1',sio_in3=>'1', -- TODO, pokey dir...
-		data_out=>pokey_data_out, 
-		sio_out1=>sio_data_in);
-
-	-- hardware regs for ZPU
-	--
-	-- KEYS -> all for ZPU. SWITCHES -> all for ZPU
-	-- i.e. zpu must control: rom/ram select, turbo, 6502 reset, scandoubler, rom wait states, pal/ntsc, gpio enable, sdram vs sram
-	-- these need storing somewhere...
-	-- TODO - volume output from here
-	-- TODO - hex digits register
-	-- TODO - if we take over antic we need to point antic to alternative RAM!
-	-- TODO - if we take over antic we need to point it back at the original display list... e.g. freeze, store state, restore state...
-	-- TODO - reset pokey and pia interrupts too?
-	--
-	-- virtual joystick button -> keyboard (windows key?)
-	-- reset -> keyboard -> f12 -> zpu reset. Then zpu controls 6502 reset.
-	--
-	-- important todo -> speed up clearing ram. e.g. 32-bit sram write. Only clear bit we need to.
-	--
-	-- STEP 1 -> joystick -> keyboard (DONE)
-	-- STEP 2 -> hardcode switch inputs to 65XE, PAL, non scandoubled  (DONE)
-	-- STEP 3 -> 6502 reset (DONE))/turbo under zpu control (DONE)
-	-- STEP 4 -> zpu starts 6502 on key1 (DONE)
-	-- STEP 5 -> simple OSD! ok, just make antic display mode 2 on reset with hello world, joystick to select... (CLOSE)
-	--
-	-- CONFIG_ATARI: 
-	-- 	R/W: 0-5: run every n cycles (0-63), 6: pause, 7: reset 
-	--    R/W(8-11 bits) - XX 00=64k,01=128K,10=320K Compy,11=320K Rambo
-	--    R/W(12-15 bits) - XX 00=XL, 01=XL turbo, 10=OS B/debugger, 11=OS B turbo
-	--	   R/W(16-20 bits) - XXXG= G:0=GPIO_OFF,1=GPIO_ON(ISH!)
-	-- PAUSE (DONE) -- W: 0-31:wait for n cycles
-	-- SWITCH (DONE)
-	--		R: 0-9 - switches
-	-- KEY (DONE)
-	--    R: 0-3 - keys
-	-- LEDG (DONE) 
-	--    R/W: 0-9
-	-- LEDR (DONE) 
-	--    R/W: 0-9
-	-- SPI_DATA (DONE) 
-	--		W - write data (starts transmission)
-	--		R - read data (wait for complete first)
-	-- SPI_STATE/SPI_CTRL (DONE) 
-	--    R: 0=busy
-	--    W: 0=select_n, speed
-	-- SIO
-	--    R: 0=CMD
-	-- FPGA board (DONE) 
-	--    R(32 bits) 0=DE1
-	-- HEX digits
-	--    W(16 bits)
-	
-	-- TODO, ROM select, RAM select etc etc
-	-- TODO firmware with OSD!
-				
-	-- Writes to registers
-	process(cpu_data_in,wr_en,addr,addr_decoded, ledg_reg, ledr_reg, pause_reg, config_6502_reg, rom_select_reg, ram_select_reg, gpio_enable_reg, spi_speed_reg, spi_addr_reg, zpu_hex_reg)
-	begin
-		config_6502_next <= config_6502_reg;
-		rom_select_next <= rom_select_reg;
-		ram_select_next <= ram_select_reg;
-		gpio_enable_next <= gpio_enable_reg;
-		pause_next <= pause_reg;
-		ledg_next <= ledg_reg;
-		ledr_next <= ledr_reg;
-		
-		spi_speed_next <= spi_speed_reg;
-		spi_addr_next <= spi_addr_reg;
-		spi_tx_data <= (others=>'0');
-		spi_enable <= '0';
-		
-		zpu_hex_next <= zpu_hex_reg;
-		
-		paused_next <= '0';
-		if (not(pause_reg = X"00000000")) then
-			pause_next <= std_LOGIC_VECTOR(unsigned(pause_reg)-to_unsigned(1,32));
-			paused_next <= '1';
-		end if;
-	
-		if (wr_en = '1' and addr(4) = '0') then
-			if(addr_decoded(0) = '1') then
-				config_6502_next <= cpu_data_in(7 downto 0);
-				ram_select_next <= cpu_DATA_IN(9 downto 8);
-				rom_select_next <= cpu_DATA_IN(13 downto 12);
-				gpio_enable_next <= cpu_DATA_IN(16);
-			end if;	
-			
-			if(addr_decoded(1) = '1') then
-				pause_next <= cpu_data_in;
-				paused_next <= '1';
-			end if;				
-
-			if(addr_decoded(4) = '1') then
-				ledg_next <= cpu_data_in(7 downto 0);
-			end if;	
-			
-			if(addr_decoded(5) = '1') then
-				ledr_next <= cpu_data_in(9 downto 0);
-			end if;	
-
-			if(addr_decoded(6) = '1') then
-				-- TODO, check overrun?
-				spi_tx_data <= cpu_data_in(7 downto 0);
-				spi_enable <= '1';
-			end if;	
-
-			if(addr_decoded(7) = '1') then
-				spi_addr_next <= cpu_data_in(0);
-				if (cpu_data_in(1) = '1') then
-					spi_speed_next <= X"80"; -- slow, for init
-				else
-					spi_speed_next <= X"04"; -- turbo!
-				end if;
-			end if;	
-
-			if(addr_decoded(10) = '1') then
-				zpu_hex_next <= cpu_data_in(15 downto 0);
-			end if;	
-			
-		end if;
-	end process;
-	
-	-- Read from registers
-	process(addr,addr_decoded, ledg_reg, ledr_reg, SWITCH, KEY, SIO_COMMAND_OUT, spi_rx_data, spi_busy, pokey_data_out, zpu_hex_reg, config_6502_reg, ram_select_reg, rom_select_reg, gpio_enable_reg)
-	begin
-		data_out <= (others=>'0');
-
-		if (addr(4) = '0') then
-			if (addr_decoded(0) = '1') then
-				data_out(7 downto 0) <= config_6502_reg;
-				data_out(9 downto 8) <= ram_select_reg;
-				data_out(13 downto 12) <= rom_select_reg;
-				data_out(16) <= gpio_enable_reg;
-			end if;
-			
-			if (addr_decoded(2) = '1') then
-				data_out(9 downto 0) <= SWITCH;
-			end if;		
-			
-			if (addr_decoded(3) = '1') then
-				data_out(3 downto 0) <= KEY;
-			end if;		
-			
-			if (addr_decoded(4) = '1') then
-				data_out(7 downto 0) <= ledg_reg;
-			end if;
-
-			if (addr_decoded(5) = '1') then
-				data_out(9 downto 0) <= ledr_reg;
-			end if;
-
-			if (addr_decoded(6) = '1') then
-				data_out(7 downto 0) <= spi_rx_data;
-			end if;
-
-			if (addr_decoded(7) = '1') then
-				data_out(0) <= spi_busy;
-			end if;		
-
-			if(addr_decoded(8) = '1') then
-				data_out(0) <= sio_command_OUT;
-			end if;	
-			
-			if (addr_decoded(9) = '1') then
-				data_out <= X"00000000"; -- DE1!
-				--data_out <= X"00000001"; -- DE2!
-				--data_out <= X"00000002"; -- SOCKIT!
-				--data_out <= X"00000003"; -- REPLAY!
-				--data_out <= X"00000004"; -- MMC!		
-			end if;
-			
-			if (addr_decoded(10) = '1') then
-				data_out(15 downto 0) <= zpu_hex_reg;
-			end if;			
-		else
-			data_out(7 downto 0) <= pokey_data_out;
-		end if;
-	end process;	
-	
-	process(request_reset_zpu, config_6502_next, config_6502_reg)
-	begin
-		reset_n_next <= '1';
-		reset_zpu_next <= '0';
-		reset_6502_cpu_next <= config_6502_reg(7);
-		
-		if (request_reset_zpu = '1') then
-			reset_n_next <= '0';
-			reset_zpu_next <= '1';
-			reset_6502_cpu_next <= '1';
-		end if;
-	end process;
-	
-	-- outputs
-	PAUSE_ZPU <= paused_reg;
-	LEDG <= ledg_reg;
-	LEDR <= ledr_reg;
-	
-	SDCARD_CLK <= spi_clk_out;
-	SDCARD_CMD <= spi_mosi;
-	spi_miso <= SDCARD_DAT; -- INPUT!! XXX
-	SDCARD_DAT3 <= spi_chip_select(0);
-	
-	PAL <= switch(6);
-	USE_SDRAM <= switch(7); -- should not be all or nothing. can mix for higher ram settings...
-	RAM_SELECT <= ram_select_reg;
-	VGA <= switch(9);
-	COMPOSITE_ON_HSYNC <= switch(8);
-	GPIO_ENABLE <= gpio_enable_reg; -- enable gpio - FIXME - esp carts!
-	ROM_SELECT <= rom_select_reg;
-	
-	reset_n <= reset_n_reg; -- system reset or pll not locked
-	reset_zpu <= reset_zpu_reg; -- system_reset or pll not locked
-	reset_6502 <= reset_6502_cpu_reg; -- zpu software controlled
-	
-	pause_6502 <= config_6502_reg(6); -- zpu software controlled
-	
-	throttle_count_6502 <= config_6502_reg(5 downto 0); -- zpu software controlled	
-	
-	zpu_hex <= zpu_hex_reg;
-end vhdl;
-
-
Index: de1/atari800core.vhd
===================================================================
--- de1/atari800core.vhd	(revision 23)
+++ de1/atari800core.vhd	(nonexistent)
@@ -1,1461 +0,0 @@
--- Copyright (C) 1991-2012 Altera Corporation
--- Your use of Altera Corporation's design tools, logic functions 
--- and other software and tools, and its AMPP partner logic 
--- functions, and any output files from any of the foregoing 
--- (including device programming or simulation files), and any 
--- associated documentation or information are expressly subject 
--- to the terms and conditions of the Altera Program License 
--- Subscription Agreement, Altera MegaCore Function License 
--- Agreement, or other applicable license agreement, including, 
--- without limitation, that your use is for the sole purpose of 
--- programming logic devices manufactured by Altera and sold by 
--- Altera or its authorized distributors.  Please refer to the 
--- applicable agreement for further details.
-
--- PROGRAM		"Quartus II 64-Bit"
--- VERSION		"Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Web Edition"
--- CREATED		"Tue Dec 31 22:21:48 2013"
-
-LIBRARY ieee;
-USE ieee.std_logic_1164.all; 
-
-LIBRARY work;
-
-ENTITY atari800core IS 
-	PORT
-	(
-		CLOCK_50 :  IN  STD_LOGIC;
-		AUD_BCLK :  IN  STD_LOGIC;
-		AUD_DACLRCK :  IN  STD_LOGIC;
-		PS2_CLK :  IN  STD_LOGIC;
-		PS2_DAT :  IN  STD_LOGIC;
-		UART_RXD :  IN  STD_LOGIC;
-		SD_DATA :  IN  STD_LOGIC;
-		I2C_SCLK :  INOUT  STD_LOGIC;
-		I2C_SDAT :  INOUT  STD_LOGIC;
-		DRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
-		FL_DQ :  IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
-		GPIO_0 :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
-		GPIO_1 :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
-		KEY :  IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
-		SRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
-		SW :  IN  STD_LOGIC_VECTOR(9 DOWNTO 0);
-		AUD_XCK :  OUT  STD_LOGIC;
-		AUD_DACDAT :  OUT  STD_LOGIC;
-		VGA_VS :  OUT  STD_LOGIC;
-		VGA_HS :  OUT  STD_LOGIC;
-		FL_OE_N :  OUT  STD_LOGIC;
-		FL_WE_N :  OUT  STD_LOGIC;
-		FL_RST_N :  OUT  STD_LOGIC;
-		SRAM_CE_N :  OUT  STD_LOGIC;
-		SRAM_OE_N :  OUT  STD_LOGIC;
-		SRAM_WE_N :  OUT  STD_LOGIC;
-		SRAM_LB_N :  OUT  STD_LOGIC;
-		SRAM_UB_N :  OUT  STD_LOGIC;
-		UART_TXD :  OUT  STD_LOGIC;
-		DRAM_BA_0 :  OUT  STD_LOGIC;
-		DRAM_BA_1 :  OUT  STD_LOGIC;
-		DRAM_CS_N :  OUT  STD_LOGIC;
-		DRAM_RAS_N :  OUT  STD_LOGIC;
-		DRAM_CAS_N :  OUT  STD_LOGIC;
-		DRAM_WE_N :  OUT  STD_LOGIC;
-		DRAM_LDQM :  OUT  STD_LOGIC;
-		DRAM_UDQM :  OUT  STD_LOGIC;
-		DRAM_CLK :  OUT  STD_LOGIC;
-		DRAM_CKE :  OUT  STD_LOGIC;
-		SD_CLK :  OUT  STD_LOGIC;
-		SD_CMD :  OUT  STD_LOGIC;
-		SD_THREE :  OUT  STD_LOGIC;
-		DRAM_ADDR :  OUT  STD_LOGIC_VECTOR(11 DOWNTO 0);
-		FL_ADDR :  OUT  STD_LOGIC_VECTOR(21 DOWNTO 0);
-		HEX0 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
-		HEX1 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
-		HEX2 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
-		HEX3 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
-		LEDG :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
-		LEDR :  OUT  STD_LOGIC_VECTOR(9 DOWNTO 0);
-		SRAM_ADDR :  OUT  STD_LOGIC_VECTOR(17 DOWNTO 0);
-		VGA_B :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
-		VGA_G :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
-		VGA_R :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0)
-	);
-END atari800core;
-
-ARCHITECTURE bdf_type OF atari800core IS 
-
-COMPONENT cpu
-	PORT(CLK : IN STD_LOGIC;
-		 RESET : IN STD_LOGIC;
-		 ENABLE : IN STD_LOGIC;
-		 IRQ_n : IN STD_LOGIC;
-		 NMI_n : IN STD_LOGIC;
-		 MEMORY_READY : IN STD_LOGIC;
-		 THROTTLE : IN STD_LOGIC;
-		 RDY : IN STD_LOGIC;
-		 DI : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 R_W_n : OUT STD_LOGIC;
-		 CPU_FETCH : OUT STD_LOGIC;
-		 A : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
-		 DO : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT hexdecoder
-	PORT(CLK : IN STD_LOGIC;
-		 NUMBER : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 DIGIT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT sram
-	PORT(WREN : IN STD_LOGIC;
-		 clk : IN STD_LOGIC;
-		 reset_n : IN STD_LOGIC;
-		 request : IN STD_LOGIC;
-		 width_16bit : IN STD_LOGIC;
-		 ADDRESS : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
-		 DIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-		 SRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
-		 SRAM_CE_N : OUT STD_LOGIC;
-		 SRAM_OE_N : OUT STD_LOGIC;
-		 SRAM_WE_N : OUT STD_LOGIC;
-		 SRAM_LB_N : OUT STD_LOGIC;
-		 SRAM_UB_N : OUT STD_LOGIC;
-		 complete : OUT STD_LOGIC;
-		 DOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
-		 SRAM_ADDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT antic
-	PORT(CLK : IN STD_LOGIC;
-		 WR_EN : IN STD_LOGIC;
-		 RESET_N : IN STD_LOGIC;
-		 MEMORY_READY_ANTIC : IN STD_LOGIC;
-		 MEMORY_READY_CPU : IN STD_LOGIC;
-		 ANTIC_ENABLE_179 : IN STD_LOGIC;
-		 PAL : IN STD_LOGIC;
-		 lightpen : IN STD_LOGIC;
-		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 NMI_N_OUT : OUT STD_LOGIC;
-		 ANTIC_READY : OUT STD_LOGIC;
-		 COLOUR_CLOCK_ORIGINAL_OUT : OUT STD_LOGIC;
-		 COLOUR_CLOCK_OUT : OUT STD_LOGIC;
-		 HIGHRES_COLOUR_CLOCK_OUT : OUT STD_LOGIC;
-		 dma_fetch_out : OUT STD_LOGIC;
-		 refresh_out : OUT STD_LOGIC;
-		 dma_clock_out : OUT STD_LOGIC;
-		 AN : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
-		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 dma_address_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT ledsw
-	PORT(CLK : IN STD_LOGIC;
-		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
-		 SYNC_KEYS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 SYNC_SWITCHES : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT pokey_mixer
-	PORT(CLK : IN STD_LOGIC;
-		 GTIA_SOUND : IN STD_LOGIC;
-		 CHANNEL_0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 CHANNEL_1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 CHANNEL_2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 CHANNEL_3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 VOLUME_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT ps2_keyboard
-	PORT(CLK : IN STD_LOGIC;
-		 RESET_N : IN STD_LOGIC;
-		 PS2_CLK : IN STD_LOGIC;
-		 PS2_DAT : IN STD_LOGIC;
-		 KEY_EVENT : OUT STD_LOGIC;
-		 KEY_EXTENDED : OUT STD_LOGIC;
-		 KEY_UP : OUT STD_LOGIC;
-		 KEY_VALUE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT zpu_glue
-	PORT(CLK : IN STD_LOGIC;
-		 RESET : IN STD_LOGIC;
-		 PAUSE : IN STD_LOGIC;
-		 MEMORY_READY : IN STD_LOGIC;
-		 ZPU_CONFIG_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 ZPU_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 ZPU_RAM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 ZPU_ROM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 MEMORY_FETCH : OUT STD_LOGIC;
-		 ZPU_READ_ENABLE : OUT STD_LOGIC;
-		 ZPU_32BIT_WRITE_ENABLE : OUT STD_LOGIC;
-		 ZPU_16BIT_WRITE_ENABLE : OUT STD_LOGIC;
-		 ZPU_8BIT_WRITE_ENABLE : OUT STD_LOGIC;
-		 ZPU_CONFIG_WRITE : OUT STD_LOGIC;
-		 ZPU_ADDR_FETCH : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
-		 ZPU_ADDR_ROM_RAM : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
-		 ZPU_DO : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 ZPU_STACK_WRITE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT pokey
-	PORT(CLK : IN STD_LOGIC;
-		 CPU_MEMORY_READY : IN STD_LOGIC;
-		 ANTIC_MEMORY_READY : IN STD_LOGIC;
-		 WR_EN : IN STD_LOGIC;
-		 RESET_N : IN STD_LOGIC;
-		 SIO_IN1 : IN STD_LOGIC;
-		 SIO_IN2 : IN STD_LOGIC;
-		 SIO_IN3 : IN STD_LOGIC;
-		 SIO_CLOCK : INOUT STD_LOGIC;
-		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 keyboard_response : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
-		 POT_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 IRQ_N_OUT : OUT STD_LOGIC;
-		 SIO_OUT1 : OUT STD_LOGIC;
-		 SIO_OUT2 : OUT STD_LOGIC;
-		 SIO_OUT3 : OUT STD_LOGIC;
-		 POT_RESET : OUT STD_LOGIC;
-		 CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 keyboard_scan : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT pia
-	PORT(	CLK : IN STD_LOGIC;
-	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
-	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-	EN : IN STD_LOGIC;
-	WR_EN : IN STD_LOGIC;
-	
-	RESET_N : IN STD_LOGIC;
-	
-	CA1 : IN STD_LOGIC;
-	CB1 : IN STD_LOGIC;		
-	
-	CA2_DIR_OUT : OUT std_logic;
-	CA2_OUT : OUT std_logic;
-	CA2_IN : IN STD_LOGIC;
-
-	CB2_DIR_OUT : OUT std_logic;
-	CB2_OUT : OUT std_logic;
-	CB2_IN : IN STD_LOGIC;
-	
-	-- remember these two are different if connecting to gpio (push pull vs pull up - check 6520 data sheet...)
-	-- pull up - i.e. 0 driven only
-	PORTA_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- set bit to 1 to enable output mode
-	PORTA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); 
-	PORTA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
-	
-	PORTB_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
-	PORTB_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- push pull
-	PORTB_IN : IN STD_LOGIC_VECTOR(7 downto 0); -- push pull
-	
-	-- CPU interface
-	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-		
-	IRQA_N : OUT STD_LOGIC;
-	IRQB_N : OUT STD_LOGIC	);
-END COMPONENT;
-
-COMPONENT shared_enable
-	PORT(CLK : IN STD_LOGIC;
-		 RESET_N : IN STD_LOGIC;
-		 MEMORY_READY_CPU : IN STD_LOGIC;
-		 MEMORY_READY_ANTIC : IN STD_LOGIC;
-		 PAUSE_6502 : IN STD_LOGIC;
-		 THROTTLE_COUNT_6502 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
-		 POKEY_ENABLE_179 : OUT STD_LOGIC;
-		 ANTIC_ENABLE_179 : OUT STD_LOGIC;
-		 oldcpu_enable : OUT STD_LOGIC;
-		 CPU_ENABLE_OUT : OUT STD_LOGIC;
-		 SCANDOUBLER_ENABLE_LOW : OUT STD_LOGIC;
-		 SCANDOUBLER_ENABLE_HIGH : OUT STD_LOGIC
-	);
-END COMPONENT;
-
-COMPONENT pokey_ps2_decoder
-	PORT(CLK : IN STD_LOGIC;
-		 RESET_N : IN STD_LOGIC;
-		 KEY_EVENT : IN STD_LOGIC;
-		 KEY_EXTENDED : IN STD_LOGIC;
-		 KEY_UP : IN STD_LOGIC;
-		 KEY_CODE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 KEY_HELD : OUT STD_LOGIC;
-		 SHIFT_PRESSED : OUT STD_LOGIC;
-		 BREAK_PRESSED : OUT STD_LOGIC;
-		 KEY_INTERRUPT : OUT STD_LOGIC;
-		 CONSOL_START : OUT STD_LOGIC;
-		 CONSOL_SELECT : OUT STD_LOGIC;
-		 CONSOL_OPTION : OUT STD_LOGIC;
-		 SYSTEM_RESET : OUT STD_LOGIC;
-		 KBCODE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 VIRTUAL_STICKS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 VIRTUAL_TRIGGER : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT gpio
-	PORT(
-	clk : in std_logic;
-	
-	gpio_enable : in std_logic;
-
-	-- pia
-	porta_in : out std_logic_vector(7 downto 0);
-	virtual_stick_in : in std_logic_vector(7 downto 0);
-	porta_out : in std_logic_vector(7 downto 0);
-	porta_output : in std_logic_vector(7 downto 0);
-	CA2_DIR_OUT : IN std_logic;
-	CA2_OUT : IN std_logic;
-	CA2_IN : OUT STD_LOGIC;
-	CB2_DIR_OUT : IN std_logic;
-	CB2_OUT : IN std_logic;
-	CB2_IN : OUT STD_LOGIC;
-	
-	-- gtia
-	virtual_trig_in : in std_logic_vector(3 downto 0);
-	trig_in : out std_logic_vector(3 downto 0);
-	
-	-- antic
-	lightpen : out std_logic;
-	
-	-- pokey
-	pot_reset : in std_logic;
-	pot_in : out std_logic_vector(7 downto 0);
-	keyboard_scan : in std_logic_vector(5 downto 0);
-	keyboard_response : out std_logic_vector(1 downto 0);
-	virtual_keycode : in std_logic_vector(5 downto 0);
-	virtual_keyheld : in std_logic;
-	virtual_shift_pressed : in std_logic;
-	virtual_control_pressed : in std_logic;
-	virtual_break_pressed : in std_logic;
-	SIO_IN : OUT STD_LOGIC;
-	SIO_OUT : IN STD_LOGIC;
-	
-	-- cartridge
-	pbi_addr_out : in std_logic_vector(15 downto 0);
-	pbi_write_enable : in std_logic;
-	cart_data_read : out std_logic_vector(7 downto 0);
-	cart_request : in std_logic;
-	cart_complete : out std_logic;
-	cart_data_write : in std_logic_vector(7 downto 0);
-	rd4 : out std_logic;
-	rd5 : out std_logic;
-	s4_n : in std_logic;
-	s5_n : in std_logic;
-	cctl_n : in std_logic;
-	
-	monitor : in std_logic;
-	
-	-- gpio connections
-	GPIO_0_IN : in std_logic_vector(35 downto 0);
-	GPIO_0_OUT : out std_logic_vector(35 downto 0);
-	GPIO_0_DIR_OUT : out std_logic_vector(35 downto 0);
-	GPIO_1_IN : in std_logic_vector(35 downto 0);
-	GPIO_1_OUT : out std_logic_vector(35 downto 0);
-	GPIO_1_DIR_OUT : out std_logic_vector(35 downto 0)
-	);
-END COMPONENT;
-
-COMPONENT address_decoder
-	PORT(CLK : IN STD_LOGIC;
-		 CPU_FETCH : IN STD_LOGIC;
-		 CPU_WRITE_N : IN STD_LOGIC;
-		 ANTIC_FETCH : IN STD_LOGIC;
-		 antic_refresh : IN STD_LOGIC;
-		 ZPU_FETCH : IN STD_LOGIC;
-		 ZPU_READ_ENABLE : IN STD_LOGIC;
-		 ZPU_32BIT_WRITE_ENABLE : IN STD_LOGIC;
-		 ZPU_16BIT_WRITE_ENABLE : IN STD_LOGIC;
-		 ZPU_8BIT_WRITE_ENABLE : IN STD_LOGIC;
-		 RAM_REQUEST_COMPLETE : IN STD_LOGIC;
-		 ROM_REQUEST_COMPLETE : IN STD_LOGIC;
-		 CART_REQUEST_COMPLETE : IN STD_LOGIC;
-		 reset_n : IN STD_LOGIC;
-		 CART_RD4 : IN STD_LOGIC;
-		 CART_RD5 : IN STD_LOGIC;
-		 use_sdram : IN STD_LOGIC;
-		 SDRAM_REPLY : IN STD_LOGIC;
-		 ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-		 ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 CACHE_ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 CART_ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 CPU_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-		 CPU_WRITE_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 CACHE_GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 PIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 CACHE_POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 CACHE_POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 PORTB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 RAM_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-		 ram_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
-		 ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 rom_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
-		 SDRAM_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 ZPU_ADDR : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
-		 ZPU_WRITE_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 MEMORY_READY_ANTIC : OUT STD_LOGIC;
-		 MEMORY_READY_ZPU : OUT STD_LOGIC;
-		 MEMORY_READY_CPU : OUT STD_LOGIC;
-		 GTIA_WR_ENABLE : OUT STD_LOGIC;
-		 POKEY_WR_ENABLE : OUT STD_LOGIC;
-		 POKEY2_WR_ENABLE : OUT STD_LOGIC;
-		 ANTIC_WR_ENABLE : OUT STD_LOGIC;
-		 PIA_WR_ENABLE : OUT STD_LOGIC;
-		 PIA_RD_ENABLE : OUT STD_LOGIC;
-		 RAM_WR_ENABLE : OUT STD_LOGIC;
-		 PBI_WR_ENABLE : OUT STD_LOGIC;
-		 RAM_REQUEST : OUT STD_LOGIC;
-		 ROM_REQUEST : OUT STD_LOGIC;
-		 CART_REQUEST : OUT STD_LOGIC;
-		 CART_S4_n : OUT STD_LOGIC;
-		 CART_S5_n : OUT STD_LOGIC;
-		 CART_CCTL_n : OUT STD_LOGIC;
-		 WIDTH_8bit_ACCESS : OUT STD_LOGIC;
-		 WIDTH_16bit_ACCESS : OUT STD_LOGIC;
-		 WIDTH_32bit_ACCESS : OUT STD_LOGIC;
-		 SDRAM_READ_EN : OUT STD_LOGIC;
-		 SDRAM_WRITE_EN : OUT STD_LOGIC;
-		 SDRAM_REQUEST : OUT STD_LOGIC;
-		 SDRAM_REFRESH : OUT STD_LOGIC;
-		 MEMORY_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 PBI_ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
-		 RAM_ADDR : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
-		 ROM_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
-		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);
-		 WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT sdram_statemachine
-GENERIC (ADDRESS_WIDTH : INTEGER;
-			AP_BIT : INTEGER;
-			COLUMN_WIDTH : INTEGER;
-			ROW_WIDTH : INTEGER
-			);
-	PORT(CLK_SYSTEM : IN STD_LOGIC;
-		 CLK_SDRAM : IN STD_LOGIC;
-		 RESET_N : IN STD_LOGIC;
-		 READ_EN : IN STD_LOGIC;
-		 WRITE_EN : IN STD_LOGIC;
-		 REQUEST : IN STD_LOGIC;
-		 BYTE_ACCESS : IN STD_LOGIC;
-		 WORD_ACCESS : IN STD_LOGIC;
-		 LONGWORD_ACCESS : IN STD_LOGIC;
-		 REFRESH : IN STD_LOGIC;
-		 ADDRESS_IN : IN STD_LOGIC_VECTOR(22 DOWNTO 0);
-		 DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
-		 REPLY : OUT STD_LOGIC;
-		 SDRAM_BA0 : OUT STD_LOGIC;
-		 SDRAM_BA1 : OUT STD_LOGIC;
-		 SDRAM_CKE : OUT STD_LOGIC;
-		 SDRAM_CS_N : OUT STD_LOGIC;
-		 SDRAM_RAS_N : OUT STD_LOGIC;
-		 SDRAM_CAS_N : OUT STD_LOGIC;
-		 SDRAM_WE_N : OUT STD_LOGIC;
-		 SDRAM_ldqm : OUT STD_LOGIC;
-		 SDRAM_udqm : OUT STD_LOGIC;
-		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT zpu_rom
-	PORT(clock : IN STD_LOGIC;
-		 address : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
-		 q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT scandoubler
-	PORT(CLK : IN STD_LOGIC;
-		 RESET_N : IN STD_LOGIC;
-		 VGA : IN STD_LOGIC;
-		 COMPOSITE_ON_HSYNC : IN STD_LOGIC;
-		 colour_enable : IN STD_LOGIC;
-		 doubled_enable : IN STD_LOGIC;
-		 vsync_in : IN STD_LOGIC;
-		 hsync_in : IN STD_LOGIC;
-		 colour_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 VSYNC : OUT STD_LOGIC;
-		 HSYNC : OUT STD_LOGIC;
-		 B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT zpu_ram
-	PORT(wren : IN STD_LOGIC;
-		 clock : IN STD_LOGIC;
-		 address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
-		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT zpu_config_regs
-	PORT(CLK : IN STD_LOGIC;
-		 ENABLE_179 : IN STD_LOGIC;
-		 WR_EN : IN STD_LOGIC;
-		 SDCARD_DAT : IN STD_LOGIC;
-		 SIO_COMMAND_OUT : IN STD_LOGIC;
-		 SIO_DATA_OUT : IN STD_LOGIC;
-		 PLL_LOCKED : IN STD_LOGIC;
-		 REQUEST_RESET_ZPU : IN STD_LOGIC;
-		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
-		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-		 SWITCH : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
-		 SDCARD_CLK : OUT STD_LOGIC;
-		 SDCARD_CMD : OUT STD_LOGIC;
-		 SDCARD_DAT3 : OUT STD_LOGIC;
-		 SIO_DATA_IN : OUT STD_LOGIC;
-		 PAUSE_ZPU : OUT STD_LOGIC;
-		 PAL : OUT STD_LOGIC;
-		 USE_SDRAM : OUT STD_LOGIC;
-		 VGA : OUT STD_LOGIC;
-		 COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
-		 GPIO_ENABLE : OUT STD_LOGIC;
-		 RESET_6502 : OUT STD_LOGIC;
-		 RESET_ZPU : OUT STD_LOGIC;
-		 RESET_N : OUT STD_LOGIC;
-		 PAUSE_6502 : OUT STD_LOGIC;
-		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-		 LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
-		 RAM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
-		 ROM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
-		 THROTTLE_COUNT_6502 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
-		 ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT i2c_loader
-GENERIC (device_address : INTEGER;
-			log2_divider : INTEGER;
-			num_retries : INTEGER
-			);
-	PORT(CLK : IN STD_LOGIC;
-		 nRESET : IN STD_LOGIC;
-		 I2C_SCL : INOUT STD_LOGIC;
-		 I2C_SDA : INOUT STD_LOGIC;
-		 IS_DONE : OUT STD_LOGIC;
-		 IS_ERROR : OUT STD_LOGIC
-	);
-END COMPONENT;
-
-COMPONENT flashrom
-	PORT(CLK : IN STD_LOGIC;
-		 RESET_N : IN STD_LOGIC;
-		 REQUEST : IN STD_LOGIC;
-		 ADDRESS : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
-		 FLASH_D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 FLASH_CE_N : OUT STD_LOGIC;
-		 FLASH_OE_N : OUT STD_LOGIC;
-		 FLASH_WE_N : OUT STD_LOGIC;
-		 FLASH_RESET_N : OUT STD_LOGIC;
-		 COMPLETE : OUT STD_LOGIC;
-		 DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 FLASH_ADDRESS : OUT STD_LOGIC_VECTOR(21 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT pll
-	PORT(inclk0 : IN STD_LOGIC;
-		 c0 : OUT STD_LOGIC;
-		 c1 : OUT STD_LOGIC;
-		 c2 : OUT STD_LOGIC;
-		 locked : OUT STD_LOGIC
-	);
-END COMPONENT;
-
-COMPONENT i2sslave
-	PORT(CLK : IN STD_LOGIC;
-		 BCLK : IN STD_LOGIC;
-		 DACLRC : IN STD_LOGIC;
-		 LEFT_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-		 RIGHT_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-		 MCLK_2 : OUT STD_LOGIC;
-		 DACDAT : OUT STD_LOGIC
-	);
-END COMPONENT;
-
-COMPONENT gtia
-	PORT(CLK : IN STD_LOGIC;
-		 WR_EN : IN STD_LOGIC;
-		 CPU_MEMORY_READY : IN STD_LOGIC;
-		 ANTIC_MEMORY_READY : IN STD_LOGIC;
-		 ANTIC_FETCH : IN STD_LOGIC;
-		 CPU_ENABLE_ORIGINAL : IN STD_LOGIC;
-		 RESET_N : IN STD_LOGIC;
-		 PAL : IN STD_LOGIC;
-		 COLOUR_CLOCK_ORIGINAL : IN STD_LOGIC;
-		 COLOUR_CLOCK : IN STD_LOGIC;
-		 COLOUR_CLOCK_HIGHRES : IN STD_LOGIC;
-		 CONSOL_START : IN STD_LOGIC;
-		 CONSOL_SELECT : IN STD_LOGIC;
-		 CONSOL_OPTION : IN STD_LOGIC;
-		 TRIG0 : IN STD_LOGIC;
-		 TRIG1 : IN STD_LOGIC;
-		 TRIG2 : IN STD_LOGIC;
-		 TRIG3 : IN STD_LOGIC;
-		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
-		 AN : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
-		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 VSYNC : OUT STD_LOGIC;
-		 HSYNC : OUT STD_LOGIC;
-		 sound : OUT STD_LOGIC;
-		 COLOUR_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
-		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
-	);
-END COMPONENT;
-
-COMPONENT irq_glue
-	PORT(pokey_irq : IN STD_LOGIC;
-		 pia_irqa : IN STD_LOGIC;
-		 pia_irqb : IN STD_LOGIC;
-		 combined_irq : OUT STD_LOGIC
-	);
-END COMPONENT;
-
-component reg_file IS
-generic
-(
-	BYTES : natural := 1;
-	WIDTH : natural := 1
-);
-PORT 
-( 
-	CLK : IN STD_LOGIC;
-	ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
-	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
-	WR_EN : IN STD_LOGIC;
-	
-	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
-);
-END component;
-
-SIGNAL	ANTIC_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
-SIGNAL	ANTIC_AN :  STD_LOGIC_VECTOR(2 DOWNTO 0);
-SIGNAL	ANTIC_COLOUR_CLOCK_OUT :  STD_LOGIC;
-SIGNAL	ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	CACHE_ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	ANTIC_ENABLE_179 :  STD_LOGIC;
-SIGNAL	ANTIC_FETCH :  STD_LOGIC;
-SIGNAL	ANTIC_HIGHRES_COLOUR_CLOCK_OUT :  STD_LOGIC;
-SIGNAL	ANTIC_ORIGINAL_COLOUR_CLOCK_OUT :  STD_LOGIC;
-SIGNAL	ANTIC_RDY :  STD_LOGIC;
-SIGNAL	ANTIC_REFRESH :  STD_LOGIC;
-SIGNAL	ANTIC_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	AUDIO_LEFT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
-SIGNAL	AUDIO_RIGHT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
-SIGNAL	BREAK_PRESSED :  STD_LOGIC;
-SIGNAL	CART_CCTL_N :  STD_LOGIC;
-SIGNAL	CART_RD4 :  STD_LOGIC;
-SIGNAL	CART_RD5 :  STD_LOGIC;
-SIGNAL	CART_REQUEST :  STD_LOGIC;
-SIGNAL	CART_REQUEST_COMPLETE :  STD_LOGIC;
-SIGNAL	CART_ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	CART_S4_n :  STD_LOGIC;
-SIGNAL	CART_S5_N :  STD_LOGIC;
-SIGNAL	CA2_OUT :  STD_LOGIC;
-SIGNAL	CA2_DIR_OUT:  STD_LOGIC;
-SIGNAL	CB2_OUT :  STD_LOGIC;
-SIGNAL	CB2_DIR_OUT:  STD_LOGIC;
-SIGNAL	CLK :  STD_LOGIC;
-SIGNAL	CLK_SDRAM :  STD_LOGIC;
-SIGNAL	COMPOSITE_ON_HSYNC :  STD_LOGIC;
-SIGNAL	CONSOL_OPTION :  STD_LOGIC;
-SIGNAL	CONSOL_SELECT :  STD_LOGIC;
-SIGNAL	CONSOL_START :  STD_LOGIC;
-SIGNAL	CPU_6502_RESET :  STD_LOGIC;
-SIGNAL	CPU_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
-SIGNAL	CPU_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	CPU_FETCH :  STD_LOGIC;
-SIGNAL	CPU_SHARED_ENABLE :  STD_LOGIC;
-SIGNAL	ENABLE_179_MEMWAIT :  STD_LOGIC;
-SIGNAL   GPIO_0_IN : STD_LOGIC_VECTOR(35 downto 0);
-SIGNAL   GPIO_0_OUT : STD_LOGIC_VECTOR(35 downto 0);
-SIGNAL   GPIO_0_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
-SIGNAL   GPIO_1_IN : STD_LOGIC_VECTOR(35 downto 0);
-SIGNAL   GPIO_1_OUT : STD_LOGIC_VECTOR(35 downto 0);
-SIGNAL   GPIO_1_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
-SIGNAL	GPIO_CA2_IN:  STD_LOGIC;
-SIGNAL	GPIO_CB2_IN:  STD_LOGIC;
-SIGNAL	GPIO_ENABLE :  STD_LOGIC;
-SIGNAL	GPIO_PORTA_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	GPIO_PORTB_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL   GPIO_SIO_IN : STD_LOGIC;
-SIGNAL   GPIO_SIO_OUT : STD_LOGIC;
-SIGNAL	GREEN_LEDS :  STD_LOGIC_VECTOR(1 TO 1);
-SIGNAL	GREREN_LEDS :  STD_LOGIC_VECTOR(0 TO 0);
-SIGNAL	GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	CACHE_GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	GTIA_SOUND :  STD_LOGIC;
-SIGNAL	GTIA_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	IRQ_n :  STD_LOGIC;
-SIGNAL	KBCODE :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	KEY_HELD :  STD_LOGIC;
-SIGNAL	KEY_INTERRUPT :  STD_LOGIC;
-SIGNAL	KEYBOARD_RESPONSE :  STD_LOGIC_VECTOR(1 DOWNTO 0);
-SIGNAL	KEYBOARD_SCAN :  STD_LOGIC_VECTOR(5 DOWNTO 0);
-SIGNAL	LIGHTPEN :  STD_LOGIC;
-SIGNAL	MEMORY_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
-SIGNAL	MEMORY_READY_ANTIC :  STD_LOGIC;
-SIGNAL	MEMORY_READY_CPU :  STD_LOGIC;
-SIGNAL	MEMORY_READY_ZPU :  STD_LOGIC;
-SIGNAL	NMI_n :  STD_LOGIC;
-SIGNAL	PAL :  STD_LOGIC;
-SIGNAL	PAUSE_6502 :  STD_LOGIC;
-SIGNAL	PBI_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
-SIGNAL	PBI_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	PIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	PIA_IRQA :  STD_LOGIC;
-SIGNAL	PIA_IRQB :  STD_LOGIC;
-SIGNAL	PIA_READ_ENABLE :  STD_LOGIC;
-SIGNAL	PIA_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	PLL_LOCKED :  STD_LOGIC;
-SIGNAL	POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	CACHE_POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	POKEY2_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	CACHE_POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	POKEY_ENABLE_179 :  STD_LOGIC;
-SIGNAL	POKEY_IRQ :  STD_LOGIC;
-SIGNAL	POKEY_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	PORTA_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	PORTA_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	PORTB_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	PORTB_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	POT_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	POT_RESET :  STD_LOGIC;
-SIGNAL	R_W_N :  STD_LOGIC;
-SIGNAL	RAM_ADDR :  STD_LOGIC_VECTOR(18 DOWNTO 0);
-SIGNAL	RAM_DO :  STD_LOGIC_VECTOR(15 DOWNTO 0);
-SIGNAL	RAM_REQUEST :  STD_LOGIC;
-SIGNAL	RAM_REQUEST_COMPLETE :  STD_LOGIC;
-SIGNAL	RAM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
-SIGNAL	RAM_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	RESET_N :  STD_LOGIC;
-SIGNAL	ROM_ADDR :  STD_LOGIC_VECTOR(21 DOWNTO 0);
-SIGNAL	ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	ROM_REQUEST :  STD_LOGIC;
-SIGNAL	ROM_REQUEST_COMPLETE :  STD_LOGIC;
-SIGNAL	ROM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
-SIGNAL	SCANDOUBLER_SHARED_ENABLE_HIGH :  STD_LOGIC;
-SIGNAL	SCANDOUBLER_SHARED_ENABLE_LOW :  STD_LOGIC;
-SIGNAL	SDRAM_ADDR :  STD_LOGIC_VECTOR(22 DOWNTO 0);
-SIGNAL	SDRAM_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
-SIGNAL	SDRAM_READ_ENABLE :  STD_LOGIC;
-SIGNAL	SDRAM_REFRESH :  STD_LOGIC;
-SIGNAL	SDRAM_REPLY :  STD_LOGIC;
-SIGNAL	SDRAM_REQUEST :  STD_LOGIC;
-SIGNAL	SDRAM_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	SHIFT_PRESSED :  STD_LOGIC;
-SIGNAL	SIO_COMMAND_OUT :  STD_LOGIC;
-SIGNAL	SIO_DATA_IN :  STD_LOGIC;
-SIGNAL	SIO_DATA_OUT :  STD_LOGIC;
-SIGNAL	SYNC_KEYS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNC_SWITCHES :  STD_LOGIC_VECTOR(9 DOWNTO 0);
-SIGNAL	SYSTEM_RESET_REQUEST :  STD_LOGIC;
-SIGNAL	THROTTLE_COUNT_6502 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
-SIGNAL	TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	USE_SDRAM :  STD_LOGIC;
-SIGNAL	VGA :  STD_LOGIC;
-SIGNAL	VIRTUAL_STICKS :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	VIRTUAL_TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	WIDTH_16BIT_ACCESS :  STD_LOGIC;
-SIGNAL	WIDTH_32BIT_ACCESS :  STD_LOGIC;
-SIGNAL	WIDTH_8BIT_ACCESS :  STD_LOGIC;
-SIGNAL	WRITE_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
-SIGNAL	ZPU_16BIT_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	ZPU_32BIT_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	ZPU_8BIT_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	ZPU_ADDR_FETCH :  STD_LOGIC_VECTOR(23 DOWNTO 0);
-SIGNAL	ZPU_ADDR_ROM_RAM :  STD_LOGIC_VECTOR(23 DOWNTO 0);
-SIGNAL	ZPU_CONFIG_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
-SIGNAL	ZPU_CONFIG_WRITE_ENABLE :  STD_LOGIC;
-SIGNAL	ZPU_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
-SIGNAL	ZPU_FETCH :  STD_LOGIC;
-SIGNAL	ZPU_HEX :  STD_LOGIC_VECTOR(15 DOWNTO 0);
-SIGNAL	ZPU_PAUSE :  STD_LOGIC;
-SIGNAL	ZPU_RAM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
-SIGNAL	ZPU_READ_ENABLE :  STD_LOGIC;
-SIGNAL	ZPU_RESET :  STD_LOGIC;
-SIGNAL	ZPU_ROM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
-SIGNAL	ZPU_STACK_WRITE :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_6 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
-SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
-SIGNAL	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
-SIGNAL	SYNTHESIZED_WIRE_11 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-SIGNAL	SYNTHESIZED_WIRE_12 :  STD_LOGIC;
-SIGNAL	SYNTHESIZED_WIRE_13 :  STD_LOGIC;
-SIGNAL	SYNTHESIZED_WIRE_14 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
-
-
-BEGIN 
-
-
-
-b2v_a_6502 : cpu
-PORT MAP(CLK => CLK,
-		 RESET => CPU_6502_RESET,
-		 ENABLE => RESET_N,
-		 IRQ_n => IRQ_n,
-		 NMI_n => NMI_n,
-		 MEMORY_READY => MEMORY_READY_CPU,
-		 THROTTLE => CPU_SHARED_ENABLE,
-		 RDY => ANTIC_RDY,
-		 DI => MEMORY_DATA(7 DOWNTO 0),
-		 R_W_n => R_W_N,
-		 CPU_FETCH => CPU_FETCH,
-		 A => CPU_ADDR,
-		 DO => CPU_DO);
-
-
-b2v_hex0_inst : hexdecoder
-PORT MAP(CLK => CLK,
-		 NUMBER => ZPU_HEX(3 DOWNTO 0),
-		 DIGIT => HEX0);
-
-
-b2v_hex0_inst2 : hexdecoder
-PORT MAP(CLK => CLK,
-		 NUMBER => ZPU_HEX(7 DOWNTO 4),
-		 DIGIT => HEX1);
-
-
-b2v_hex0_inst3 : hexdecoder
-PORT MAP(CLK => CLK,
-		 NUMBER => ZPU_HEX(11 DOWNTO 8),
-		 DIGIT => HEX2);
-
-
-b2v_hex0_inst4 : hexdecoder
-PORT MAP(CLK => CLK,
-		 NUMBER => ZPU_HEX(15 DOWNTO 12),
-		 DIGIT => HEX3);
-
-
-b2v_inst : sram
-PORT MAP(WREN => RAM_WRITE_ENABLE,
-		 clk => CLK,
-		 reset_n => RESET_N,
-		 request => RAM_REQUEST,
-		 width_16bit => WIDTH_16BIT_ACCESS,
-		 ADDRESS => RAM_ADDR,
-		 DIN => WRITE_DATA(15 DOWNTO 0),
-		 SRAM_DQ => SRAM_DQ,
-		 SRAM_CE_N => SRAM_CE_N,
-		 SRAM_OE_N => SRAM_OE_N,
-		 SRAM_WE_N => SRAM_WE_N,
-		 SRAM_LB_N => SRAM_LB_N,
-		 SRAM_UB_N => SRAM_UB_N,
-		 complete => RAM_REQUEST_COMPLETE,
-		 DOUT => RAM_DO,
-		 SRAM_ADDR => SRAM_ADDR);
-
-
-b2v_inst1 : antic
-PORT MAP(CLK => CLK,
-		 WR_EN => ANTIC_WRITE_ENABLE,
-		 RESET_N => RESET_N,
-		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
-		 MEMORY_READY_CPU => MEMORY_READY_CPU,
-		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
-		 PAL => PAL,
-		 lightpen => LIGHTPEN,
-		 ADDR => PBI_ADDR(3 DOWNTO 0),
-		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
-		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
-		 NMI_N_OUT => NMI_n,
-		 ANTIC_READY => ANTIC_RDY,
-		 COLOUR_CLOCK_ORIGINAL_OUT => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
-		 COLOUR_CLOCK_OUT => ANTIC_COLOUR_CLOCK_OUT,
-		 HIGHRES_COLOUR_CLOCK_OUT => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
-		 dma_fetch_out => ANTIC_FETCH,
-		 refresh_out => ANTIC_REFRESH,
-		 AN => ANTIC_AN,
-		 DATA_OUT => ANTIC_DO,
-		 dma_address_out => ANTIC_ADDR);
-
-
-b2v_inst10 : ledsw
-PORT MAP(CLK => CLK,
-		 KEY => KEY,
-		 SW => SW,
-		 SYNC_KEYS => SYNC_KEYS,
-		 SYNC_SWITCHES => SYNC_SWITCHES);
-
-
-b2v_inst11 : pokey_mixer
-PORT MAP(CLK => CLK,
-		 GTIA_SOUND => GTIA_SOUND,
-		 CHANNEL_0 => SYNTHESIZED_WIRE_0,
-		 CHANNEL_1 => SYNTHESIZED_WIRE_1,
-		 CHANNEL_2 => SYNTHESIZED_WIRE_2,
-		 CHANNEL_3 => SYNTHESIZED_WIRE_3,
-		 CHANNEL_ENABLE => "1111",
-		 VOLUME_OUT => AUDIO_LEFT);
-
-
-b2v_inst12 : ps2_keyboard
-PORT MAP(CLK => CLK,
-		 RESET_N => RESET_N,
-		 PS2_CLK => PS2_CLK,
-		 PS2_DAT => PS2_DAT,
-		 KEY_EVENT => SYNTHESIZED_WIRE_8,
-		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
-		 KEY_UP => SYNTHESIZED_WIRE_10,
-		 KEY_VALUE => SYNTHESIZED_WIRE_11);
-
-
-b2v_inst13 : zpu_glue
-PORT MAP(CLK => CLK,
-		 RESET => ZPU_RESET,
-		 PAUSE => ZPU_PAUSE,
-		 MEMORY_READY => MEMORY_READY_ZPU,
-		 ZPU_CONFIG_DI => ZPU_CONFIG_DO,
-		 ZPU_DI => MEMORY_DATA,
-		 ZPU_RAM_DI => ZPU_RAM_DATA,
-		 ZPU_ROM_DI => ZPU_ROM_DATA,
-		 MEMORY_FETCH => ZPU_FETCH,
-		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
-		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
-		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
-		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
-		 ZPU_CONFIG_WRITE => ZPU_CONFIG_WRITE_ENABLE,
-		 ZPU_ADDR_FETCH => ZPU_ADDR_FETCH,
-		 ZPU_ADDR_ROM_RAM => ZPU_ADDR_ROM_RAM,
-		 ZPU_DO => ZPU_DO,
-		 ZPU_STACK_WRITE => ZPU_STACK_WRITE);
-
-
-b2v_inst14 : pokey_mixer
-PORT MAP(CLK => CLK,
-		 GTIA_SOUND => GTIA_SOUND,
-		 CHANNEL_0 => SYNTHESIZED_WIRE_4,
-		 CHANNEL_1 => SYNTHESIZED_WIRE_5,
-		 CHANNEL_2 => SYNTHESIZED_WIRE_6,
-		 CHANNEL_3 => SYNTHESIZED_WIRE_7,
-		 CHANNEL_ENABLE => "1111",
-		 VOLUME_OUT => AUDIO_RIGHT);
-
-
-b2v_inst15 : pokey
-PORT MAP(CLK => CLK,
-		 CPU_MEMORY_READY => MEMORY_READY_CPU,
-		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
-		 WR_EN => POKEY2_WRITE_ENABLE,
-		 RESET_N => RESET_N,
-		 ADDR => PBI_ADDR(3 DOWNTO 0),
-		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
-		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_4,
-		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_5,
-		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_6,
-		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_7,
-		 DATA_OUT => POKEY2_DO,
-		 SIO_IN1 => '1',
-		 SIO_IN2 => '1',
-		 SIO_IN3 => '1',
-		 keyboard_response => "00",
-		 pot_in=>"00000000");
-
-
--- PIA
---GPIO_0[0] <= CA2_OUT when CA2_DIR_OUT='1' else 'Z';
---CA2_IN <= GPIO_0[0];
-
---GPIO_O[1] <= CB2_OUT when CB2_DIR_OUT='1' else 'Z';
---CB2_IN <= GPIO_O[1];
-SIO_COMMAND_OUT <= CB2_OUT; -- we generate command frame, use internal rather than from pin
--- TODO - sioto gpio!
-GPIO_PORTB_IN <= PORTB_OUT;
-
-b2v_inst16 : pia
-PORT MAP(CLK => CLK,
-		 EN => PIA_READ_ENABLE,
-		 WR_EN => PIA_WRITE_ENABLE,
-		 RESET_N => RESET_N,
-		 CA1 => '1', --todo - high/low?
-		 CB1 => '1',
-		 CA2_DIR_OUT => CA2_DIR_OUT,
-		 CA2_IN => GPIO_CA2_IN,
-		 CA2_OUT => CA2_OUT,
-		 CB2_DIR_OUT => CB2_DIR_OUT,
-		 CB2_IN => GPIO_CB2_IN,
-		 CB2_OUT => CB2_OUT,
-		 ADDR => PBI_ADDR(1 DOWNTO 0),
-		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
-		 IRQA_N => PIA_IRQA,
-		 IRQB_N => PIA_IRQB,
-		 DATA_OUT => PIA_DO,
-		 PORTA_IN => GPIO_PORTA_IN,
-		 PORTA_DIR_OUT => PORTA_DIR_OUT,
-		 PORTA_OUT => PORTA_OUT,
-		 PORTB_IN => GPIO_PORTB_IN,
-		 PORTB_DIR_OUT => PORTB_DIR_OUT,
-		 PORTB_OUT => PORTB_OUT);
-
-b2v_inst17 : shared_enable
-PORT MAP(CLK => CLK,
-		 RESET_N => RESET_N,
-		 MEMORY_READY_CPU => MEMORY_READY_CPU,
-		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
-		 PAUSE_6502 => PAUSE_6502,
-		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
-		 POKEY_ENABLE_179 => POKEY_ENABLE_179,
-		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
-		 oldcpu_enable => ENABLE_179_MEMWAIT,
-		 CPU_ENABLE_OUT => CPU_SHARED_ENABLE,
-		 SCANDOUBLER_ENABLE_LOW => SCANDOUBLER_SHARED_ENABLE_LOW,
-		 SCANDOUBLER_ENABLE_HIGH => SCANDOUBLER_SHARED_ENABLE_HIGH);
-
-
-b2v_inst18 : pokey_ps2_decoder
-PORT MAP(CLK => CLK,
-		 RESET_N => RESET_N,
-		 KEY_EVENT => SYNTHESIZED_WIRE_8,
-		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
-		 KEY_UP => SYNTHESIZED_WIRE_10,
-		 KEY_CODE => SYNTHESIZED_WIRE_11,
-		 KEY_HELD => KEY_HELD,
-		 SHIFT_PRESSED => SHIFT_PRESSED,
-		 BREAK_PRESSED => BREAK_PRESSED,
-		 CONSOL_START => CONSOL_START,
-		 CONSOL_SELECT => CONSOL_SELECT,
-		 CONSOL_OPTION => CONSOL_OPTION,
-		 SYSTEM_RESET => SYSTEM_RESET_REQUEST,
-		 KBCODE => KBCODE,
-		 VIRTUAL_STICKS => VIRTUAL_STICKS,
-		 VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS);
-
-gpio0_gen:
-   for I in 0 to 35 generate
-		gpio_0(I) <= gpio_0_out(I) when gpio_0_dir_out(I)='1' else 'Z';
-   end generate gpio0_gen;
-
-gpio1_gen:
-   for I in 0 to 35 generate
-		gpio_1(I) <= gpio_1_out(I) when gpio_1_dir_out(I)='1' else 'Z';
-   end generate gpio1_gen;
-	
-b2v_inst19 : gpio
-PORT MAP(clk => CLK,
-		 gpio_enable => GPIO_ENABLE,
-		 pot_reset => POT_RESET,
-		 virtual_keyheld => KEY_HELD,
-		 virtual_shift_pressed => SHIFT_PRESSED,
-		 virtual_control_pressed => KBCODE(7),
-		 virtual_break_pressed => BREAK_PRESSED,
-		 pbi_write_enable => PBI_WRITE_ENABLE,
-		 cart_request => CART_REQUEST,
-		 s4_n => CART_S4_n,
-		 s5_n => CART_S5_N,
-		 cctl_n => CART_CCTL_N,
-		 cart_data_write => WRITE_DATA(7 DOWNTO 0),
-		 GPIO_0_IN => GPIO_0,
-		 GPIO_0_OUT => GPIO_0_OUT,
-		 GPIO_0_DIR_OUT => GPIO_0_DIR_OUT,
-		 GPIO_1_IN => GPIO_1,
-		 GPIO_1_OUT => GPIO_1_OUT,
-		 GPIO_1_DIR_OUT => GPIO_1_DIR_OUT,		 
-		 keyboard_scan => KEYBOARD_SCAN,
-		 pbi_addr_out => PBI_ADDR,
-		 porta_out => PORTA_OUT,
-		 porta_output => PORTA_DIR_OUT,
-		 virtual_keycode => KBCODE(5 DOWNTO 0),
-		 virtual_stick_in => VIRTUAL_STICKS,
-		 virtual_trig_in => VIRTUAL_TRIGGERS,
-		 lightpen => LIGHTPEN,
-		 cart_complete => CART_REQUEST_COMPLETE,
-		 rd4 => CART_RD4,
-		 rd5 => CART_RD5,
-		 cart_data_read => CART_ROM_DO,
-		 keyboard_response => KEYBOARD_RESPONSE,
-		 porta_in => GPIO_PORTA_IN,
-		 pot_in => POT_IN,
-		 trig_in => TRIGGERS,
-		 monitor => SIO_DATA_IN, -- i.e. zpu sio out
-		 CA2_DIR_OUT => CA2_DIR_OUT,
-		 CA2_OUT => CA2_OUT,
-		 CA2_IN => GPIO_CA2_IN,
-		 CB2_DIR_OUT => CB2_DIR_OUT,
-		 CB2_OUT => CB2_OUT,
-		 CB2_IN => GPIO_CB2_IN,
-		 SIO_IN => GPIO_SIO_IN,
-		 SIO_OUT => GPIO_SIO_OUT
-		 );
-
-
-b2v_inst2 : address_decoder
-PORT MAP(CLK => CLK,
-		 CPU_FETCH => CPU_FETCH,
-		 CPU_WRITE_N => R_W_N,
-		 ANTIC_FETCH => ANTIC_FETCH,
-		 antic_refresh => ANTIC_REFRESH,
-		 ZPU_FETCH => ZPU_FETCH,
-		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
-		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
-		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
-		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
-		 RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
-		 ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
-		 CART_REQUEST_COMPLETE => CART_REQUEST_COMPLETE,
-		 reset_n => RESET_N,
-		 CART_RD4 => CART_RD4,
-		 CART_RD5 => CART_RD5,
-		 use_sdram => USE_SDRAM,
-		 SDRAM_REPLY => SDRAM_REPLY,
-		 ANTIC_ADDR => ANTIC_ADDR,
-		 ANTIC_DATA => ANTIC_DO,
-		 CACHE_ANTIC_DATA => CACHE_ANTIC_DO,
-		 CART_ROM_DATA => CART_ROM_DO,
-		 CPU_ADDR => CPU_ADDR,
-		 CPU_WRITE_DATA => CPU_DO,
-		 GTIA_DATA => GTIA_DO,
-		 CACHE_GTIA_DATA => CACHE_GTIA_DO,
-		 PIA_DATA => PIA_DO,
-		 POKEY2_DATA => POKEY2_DO,
-		 CACHE_POKEY2_DATA => CACHE_POKEY2_DO,
-		 POKEY_DATA => POKEY_DO,
-		 CACHE_POKEY_DATA => CACHE_POKEY_DO,
-		 PORTB => PORTB_OUT,
-		 RAM_DATA => RAM_DO,
-		 ram_select => RAM_SELECT,
-		 ROM_DATA => ROM_DO,
-		 rom_select => ROM_SELECT,
-		 SDRAM_DATA => SDRAM_DO,
-		 ZPU_ADDR => ZPU_ADDR_FETCH,
-		 ZPU_WRITE_DATA => ZPU_DO,
-		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
-		 MEMORY_READY_ZPU => MEMORY_READY_ZPU,
-		 MEMORY_READY_CPU => MEMORY_READY_CPU,
-		 GTIA_WR_ENABLE => GTIA_WRITE_ENABLE,
-		 POKEY_WR_ENABLE => POKEY_WRITE_ENABLE,
-		 POKEY2_WR_ENABLE => POKEY2_WRITE_ENABLE,
-		 ANTIC_WR_ENABLE => ANTIC_WRITE_ENABLE,
-		 PIA_WR_ENABLE => PIA_WRITE_ENABLE,
-		 PIA_RD_ENABLE => PIA_READ_ENABLE,
-		 RAM_WR_ENABLE => RAM_WRITE_ENABLE,
-		 PBI_WR_ENABLE => PBI_WRITE_ENABLE,
-		 RAM_REQUEST => RAM_REQUEST,
-		 ROM_REQUEST => ROM_REQUEST,
-		 CART_REQUEST => CART_REQUEST,
-		 CART_S4_n => CART_S4_n,
-		 CART_S5_n => CART_S5_N,
-		 CART_CCTL_n => CART_CCTL_N,
-		 WIDTH_8bit_ACCESS => WIDTH_8BIT_ACCESS,
-		 WIDTH_16bit_ACCESS => WIDTH_16BIT_ACCESS,
-		 WIDTH_32bit_ACCESS => WIDTH_32BIT_ACCESS,
-		 SDRAM_READ_EN => SDRAM_READ_ENABLE,
-		 SDRAM_WRITE_EN => SDRAM_WRITE_ENABLE,
-		 SDRAM_REQUEST => SDRAM_REQUEST,
-		 SDRAM_REFRESH => SDRAM_REFRESH,
-		 MEMORY_DATA => MEMORY_DATA,
-		 PBI_ADDR => PBI_ADDR,
-		 RAM_ADDR => RAM_ADDR,
-		 ROM_ADDR => ROM_ADDR,
-		 SDRAM_ADDR => SDRAM_ADDR,
-		 WRITE_DATA => WRITE_DATA);
-
-
-b2v_inst20 : sdram_statemachine
-GENERIC MAP(ADDRESS_WIDTH => 22,
-			AP_BIT => 10,
-			COLUMN_WIDTH => 8,
-			ROW_WIDTH => 12
-			)
-PORT MAP(CLK_SYSTEM => CLK,
-		 CLK_SDRAM => CLK_SDRAM,
-		 RESET_N => RESET_N,
-		 READ_EN => SDRAM_READ_ENABLE,
-		 WRITE_EN => SDRAM_WRITE_ENABLE,
-		 REQUEST => SDRAM_REQUEST,
-		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
-		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
-		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
-		 REFRESH => SDRAM_REFRESH,
-		 ADDRESS_IN => SDRAM_ADDR,
-		 DATA_IN => WRITE_DATA,
-		 SDRAM_DQ => DRAM_DQ,
-		 REPLY => SDRAM_REPLY,
-		 SDRAM_BA0 => DRAM_BA_0,
-		 SDRAM_BA1 => DRAM_BA_1,
-		 SDRAM_CKE => DRAM_CKE,
-		 SDRAM_CS_N => DRAM_CS_N,
-		 SDRAM_RAS_N => DRAM_RAS_N,
-		 SDRAM_CAS_N => DRAM_CAS_N,
-		 SDRAM_WE_N => DRAM_WE_N,
-		 SDRAM_ldqm => DRAM_LDQM,
-		 SDRAM_udqm => DRAM_UDQM,
-		 DATA_OUT => SDRAM_DO,
-		 SDRAM_ADDR => DRAM_ADDR);
-
-
-b2v_inst21 : zpu_rom
-PORT MAP(clock => CLK,
-		 address => ZPU_ADDR_ROM_RAM(13 DOWNTO 2),
-		 q => ZPU_ROM_DATA);
-
-
-b2v_inst22 : scandoubler
-PORT MAP(CLK => CLK,
-		 RESET_N => RESET_N,
-		 VGA => VGA,
-		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
-		 colour_enable => SCANDOUBLER_SHARED_ENABLE_LOW,
-		 doubled_enable => SCANDOUBLER_SHARED_ENABLE_HIGH,
-		 vsync_in => SYNTHESIZED_WIRE_12,
-		 hsync_in => SYNTHESIZED_WIRE_13,
-		 colour_in => SYNTHESIZED_WIRE_14,
-		 VSYNC => VGA_VS,
-		 HSYNC => VGA_HS,
-		 B => VGA_B,
-		 G => VGA_G,
-		 R => VGA_R);
-
-
-b2v_inst23 : zpu_ram
-PORT MAP(wren => ZPU_STACK_WRITE(2),
-		 clock => CLK,
-		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
-		 data => ZPU_DO(23 DOWNTO 16),
-		 q => ZPU_RAM_DATA(23 DOWNTO 16));
-
-
-b2v_inst24 : zpu_config_regs
-PORT MAP(CLK => CLK,
-		 ENABLE_179 => POKEY_ENABLE_179,
-		 WR_EN => ZPU_CONFIG_WRITE_ENABLE,
-		 SDCARD_DAT => SD_DATA,
-		 SIO_COMMAND_OUT => SIO_COMMAND_OUT,
-		 SIO_DATA_OUT => SIO_DATA_OUT,
-		 PLL_LOCKED => PLL_LOCKED,
-		 REQUEST_RESET_ZPU => SYSTEM_RESET_REQUEST,
-		 ADDR => ZPU_ADDR_ROM_RAM(6 DOWNTO 2),
-		 CPU_DATA_IN => ZPU_DO,
-		 KEY => SYNC_KEYS,
-		 SWITCH => SYNC_SWITCHES,
-		 SDCARD_CLK => SD_CLK,
-		 SDCARD_CMD => SD_CMD,
-		 SDCARD_DAT3 => SD_THREE,
-		 SIO_DATA_IN => SIO_DATA_IN,
-		 PAUSE_ZPU => ZPU_PAUSE,
-		 PAL => PAL,
-		 USE_SDRAM => USE_SDRAM,
-		 VGA => VGA,
-		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
-		 GPIO_ENABLE => GPIO_ENABLE,
-		 RESET_6502 => CPU_6502_RESET,
-		 RESET_ZPU => ZPU_RESET,
-		 RESET_N => RESET_N,
-		 PAUSE_6502 => PAUSE_6502,
-		 DATA_OUT => ZPU_CONFIG_DO,
-		 LEDG => LEDG,
-		 LEDR => LEDR,
-		 RAM_SELECT => RAM_SELECT,
-		 ROM_SELECT => ROM_SELECT,
-		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
-		 ZPU_HEX => ZPU_HEX);
-
-
-b2v_inst25 : zpu_ram
-PORT MAP(wren => ZPU_STACK_WRITE(3),
-		 clock => CLK,
-		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
-		 data => ZPU_DO(31 DOWNTO 24),
-		 q => ZPU_RAM_DATA(31 DOWNTO 24));
-
-
-b2v_inst26 : zpu_ram
-PORT MAP(wren => ZPU_STACK_WRITE(0),
-		 clock => CLK,
-		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
-		 data => ZPU_DO(7 DOWNTO 0),
-		 q => ZPU_RAM_DATA(7 DOWNTO 0));
-
-
-b2v_inst27 : zpu_ram
-PORT MAP(wren => ZPU_STACK_WRITE(1),
-		 clock => CLK,
-		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
-		 data => ZPU_DO(15 DOWNTO 8),
-		 q => ZPU_RAM_DATA(15 DOWNTO 8));
-
-
-b2v_inst3 : i2c_loader
-GENERIC MAP(device_address => 26,
-			log2_divider => 6,
-			num_retries => 0
-			)
-PORT MAP(CLK => CLK,
-		 nRESET => RESET_N,
-		 I2C_SCL => I2C_SCLK,
-		 I2C_SDA => I2C_SDAT);
-
-
-b2v_inst4 : flashrom
-PORT MAP(CLK => CLK,
-		 RESET_N => RESET_N,
-		 REQUEST => ROM_REQUEST,
-		 ADDRESS => ROM_ADDR,
-		 FLASH_D => FL_DQ,
-		 FLASH_OE_N => FL_OE_N,
-		 FLASH_WE_N => FL_WE_N,
-		 FLASH_RESET_N => FL_RST_N,
-		 COMPLETE => ROM_REQUEST_COMPLETE,
-		 DOUT => ROM_DO,
-		 FLASH_ADDRESS => FL_ADDR);
-
-
-b2v_inst5 : pll
-PORT MAP(inclk0 => CLOCK_50,
-		 c0 => CLK_SDRAM,
-		 c1 => CLK,
-		 c2 => DRAM_CLK,
-		 locked => PLL_LOCKED);
-
-
-b2v_inst6 : i2sslave
-PORT MAP(CLK => CLK,
-		 BCLK => AUD_BCLK,
-		 DACLRC => AUD_DACLRCK,
-		 LEFT_IN => AUDIO_LEFT,
-		 RIGHT_IN => AUDIO_RIGHT,
-		 MCLK_2 => AUD_XCK,
-		 DACDAT => AUD_DACDAT);
-
-
-b2v_inst7 : pokey
-PORT MAP(CLK => CLK,
-		 CPU_MEMORY_READY => MEMORY_READY_CPU,
-		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
-		 WR_EN => POKEY_WRITE_ENABLE,
-		 RESET_N => RESET_N,
-		 SIO_IN1 => UART_RXD,
-		 SIO_IN2 => GPIO_SIO_IN,
-		 SIO_IN3 => SIO_DATA_IN,
-		 ADDR => PBI_ADDR(3 DOWNTO 0),
-		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
-		 keyboard_response => KEYBOARD_RESPONSE,
-		 POT_IN => POT_IN,
-		 IRQ_N_OUT => POKEY_IRQ,
-		 SIO_OUT1 => UART_TXD,
-		 SIO_OUT2 => GPIO_SIO_OUT,
-		 SIO_OUT3 => SIO_DATA_OUT,
-		 POT_RESET => POT_RESET,
-		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_0,
-		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_1,
-		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_2,
-		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_3,
-		 DATA_OUT => POKEY_DO,
-		 keyboard_scan => KEYBOARD_SCAN);
-
-b2v_inst8 : gtia
-PORT MAP(CLK => CLK,
-		 WR_EN => GTIA_WRITE_ENABLE,
-		 CPU_MEMORY_READY => MEMORY_READY_CPU,
-		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
-		 ANTIC_FETCH => ANTIC_FETCH,
-		 CPU_ENABLE_ORIGINAL => ENABLE_179_MEMWAIT,
-		 RESET_N => RESET_N,
-		 PAL => PAL,
-		 COLOUR_CLOCK_ORIGINAL => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
-		 COLOUR_CLOCK => ANTIC_COLOUR_CLOCK_OUT,
-		 COLOUR_CLOCK_HIGHRES => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
-		 CONSOL_START => CONSOL_START,
-		 CONSOL_SELECT => CONSOL_SELECT,
-		 CONSOL_OPTION => CONSOL_OPTION,
-		 TRIG0 => TRIGGERS(0),
-		 TRIG1 => TRIGGERS(1),
-		 TRIG2 => TRIGGERS(2),
-		 TRIG3 => TRIGGERS(3),
-		 ADDR => PBI_ADDR(4 DOWNTO 0),
-		 AN => ANTIC_AN,
-		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
-		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
-		 VSYNC => SYNTHESIZED_WIRE_12,
-		 HSYNC => SYNTHESIZED_WIRE_13,
-		 sound => GTIA_SOUND,
-		 COLOUR_out => SYNTHESIZED_WIRE_14,
-		 DATA_OUT => GTIA_DO);
-
-
-b2v_inst9 : irq_glue
-PORT MAP(pokey_irq => POKEY_IRQ,
-		 pia_irqa => PIA_IRQA,
-		 pia_irqb => PIA_IRQB,
-		 combined_irq => IRQ_n);
-		 
-pokey1_mirror : reg_file
-generic map(BYTES=>16,WIDTH=>4)
-port map(
-	CLK => CLK,
-	ADDR => PBI_ADDR(3 downto 0),
-	DATA_IN => WRITE_DATA(7 downto 0),
-	WR_EN => POKEY_WRITE_ENABLE,
-	DATA_OUT => CACHE_POKEY_DO
-);	 
-
-pokey2_mirror : reg_file
-generic map(BYTES=>16,WIDTH=>4)
-port map(
-	CLK => CLK,
-	ADDR => PBI_ADDR(3 downto 0),
-	DATA_IN => WRITE_DATA(7 downto 0),
-	WR_EN => POKEY2_WRITE_ENABLE,
-	DATA_OUT => CACHE_POKEY2_DO
-);	 		 
-
-gtia_mirror : reg_file
-generic map(BYTES=>32,WIDTH=>5)
-port map(
-	CLK => CLK,
-	ADDR => PBI_ADDR(4 downto 0),
-	DATA_IN => WRITE_DATA(7 downto 0),
-	WR_EN => GTIA_WRITE_ENABLE,
-	DATA_OUT => CACHE_GTIA_DO
-);	
-
-antic_mirror : reg_file
-generic map(BYTES=>16,WIDTH=>4)
-port map(
-	CLK => CLK,
-	ADDR => PBI_ADDR(3 downto 0),
-	DATA_IN => WRITE_DATA(7 downto 0),
-	WR_EN => ANTIC_WRITE_ENABLE,
-	DATA_OUT => CACHE_ANTIC_DO
-);	
-
-END bdf_type;
\ No newline at end of file
Index: de1/atari800core.qpf
===================================================================
--- de1/atari800core.qpf	(revision 23)
+++ de1/atari800core.qpf	(nonexistent)
@@ -1,30 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 1991-2012 Altera Corporation
-# Your use of Altera Corporation's design tools, logic functions 
-# and other software and tools, and its AMPP partner logic 
-# functions, and any output files from any of the foregoing 
-# (including device programming or simulation files), and any 
-# associated documentation or information are expressly subject 
-# to the terms and conditions of the Altera Program License 
-# Subscription Agreement, Altera MegaCore Function License 
-# Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by 
-# Altera or its authorized distributors.  Please refer to the 
-# applicable agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus II 64-Bit
-# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
-# Date created = 13:58:38  April 11, 2013
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "12.1"
-DATE = "13:58:38  April 11, 2013"
-
-# Revisions
-
-PROJECT_REVISION = "atari800core"
Index: de1/i2s_intf.vhd
===================================================================
--- de1/i2s_intf.vhd	(revision 23)
+++ de1/i2s_intf.vhd	(nonexistent)
@@ -1,183 +0,0 @@
--- ZX Spectrum for Altera DE1
---
--- Copyright (c) 2009-2010 Mike Stirling
--- Modified by Mark Watson for the Atari800
---
--- All rights reserved
---
--- Redistribution and use in source and synthezised forms, with or without
--- modification, are permitted provided that the following conditions are met:
---
--- * Redistributions of source code must retain the above copyright notice,
---   this list of conditions and the following disclaimer.
---
--- * Redistributions in synthesized form must reproduce the above copyright
---   notice, this list of conditions and the following disclaimer in the
---   documentation and/or other materials provided with the distribution.
---
--- * Neither the name of the author nor the names of other contributors may
---   be used to endorse or promote products derived from this software without
---   specific prior written permission.
---
--- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
--- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
--- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
--- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--- POSSIBILITY OF SUCH DAMAGE.
---
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-entity i2s_intf is
-generic(
-   inclk_rate : positive := 25000000;
-	sample_rate : positive := 8000;
-	preamble : positive := 1; -- I2S
-	word_length : positive := 16
-	);
-
-port (
-	CLK			:	in	std_logic;
-	nRESET		:	in	std_logic;
-	
-	-- Parallel IO
-	PCM_INL		:	out	std_logic_vector(word_length - 1 downto 0);
-	PCM_INR		:	out	std_logic_vector(word_length - 1 downto 0);
-	PCM_OUTL	:	in	std_logic_vector(word_length - 1 downto 0);
-	PCM_OUTR	:	in	std_logic_vector(word_length - 1 downto 0);
-	
-	-- Codec interface (right justified mode)
-	-- LRCLK is equal to the sample rate and is synchronous to
-	-- MCLK.  It must be related to MCLK by the oversampling ratio
-	-- given in the codec datasheet.
-	I2S_LRCLK	:	out	std_logic;
-	
-	-- Data is shifted out on the falling edge of BCLK, sampled
-	-- on the rising edge.  The bit rate is determined such that
-	-- it is fast enough to fit preamble + word_length bits into
-	-- each LRCLK half cycle.  The last cycle of each word may be 
-	-- stretched to fit to LRCLK.  This is OK at least for the 
-	-- WM8731 codec.
-	-- The first falling edge of each timeslot is always synchronised
-	-- with the LRCLK edge.
-	I2S_BCLK	:	out	std_logic;
-	-- Output bitstream
-	I2S_DOUT	:	out	std_logic;
-	-- Input bitstream
-	I2S_DIN		:	in	std_logic
-	);
-end i2s_intf;
-
-architecture i2s_intf_arch of i2s_intf is
-constant ratio_mclk_fs : positive := (inclk_rate / sample_rate);
-constant lrdivider_top : positive := (ratio_mclk_fs / 2) - 1;
-constant bdivider_top : positive := (ratio_mclk_fs / 8 / (preamble + word_length) * 2) - 1;
-constant nbits : positive := preamble + word_length;
-
-subtype lrdivider_t is integer range 0 to lrdivider_top;
-subtype bdivider_t is integer range 0 to bdivider_top;
-subtype bitcount_t is integer range 0 to nbits;
-
-signal lrdivider : lrdivider_t; 
-signal bdivider : bdivider_t;
-signal bitcount : bitcount_t;
-
-signal lrclk_r : std_logic;
-signal bclk_r : std_logic;
-
--- Shift register is long enough for the number of data bits
--- plus the preamble, plus an extra bit on the right to register
--- the incoming data
-signal shiftreg : std_logic_vector(nbits downto 0);
-begin
-	I2S_LRCLK <= lrclk_r;
-	I2S_BCLK <= bclk_r;
-	I2S_DOUT <= shiftreg(nbits); -- data goes out MSb first
-
-	process(nRESET,CLK)
-	begin
-		if nRESET = '0' then
-			PCM_INL <= (others => '0');
-			PCM_INR <= (others => '0');
-						
-			-- Preload down-counters for clock generation
-			lrdivider <= lrdivider_top;
-			bdivider <= bdivider_top;
-			bitcount <= nbits;
-			
-			lrclk_r <= '0';
-			bclk_r <= '0';
-			shiftreg <= (others => '0');
-		elsif rising_edge(CLK) then		
-			-- Generate LRCLK at rate specified by codec configuration
-			if lrdivider = 0 then
-				-- LRCLK divider has reached 0 - start again from the top
-				lrdivider <= lrdivider_top;
-				
-				-- Generate LRCLK edge and sync the BCLK counter
-				lrclk_r <= not lrclk_r;
-				bclk_r <= '0';
-				bitcount <= nbits; -- 1 extra required for setup
-				bdivider <= bdivider_top;
-				
-				-- Load shift register with output data padding preamble
-				-- with 0s.  Load output buses with input word from the 
-				-- previous timeslot.
-				shiftreg(nbits downto nbits - preamble + 1) <= (others => '0');
-				if lrclk_r = '0' then
-					-- Previous channel input is LEFT.  This is available in the
-					-- shift register at the end of a cycle, right justified
-					PCM_INL <= shiftreg(word_length - 1 downto 0);
-					-- Next channel to output is RIGHT.  Load this into the
-					-- shift register at the start of a cycle, left justified
-					shiftreg(word_length downto 1) <= PCM_OUTR;
-				else
-					-- Previous channel input is RIGHT
-					PCM_INR <= shiftreg(word_length - 1 downto 0);
-					-- Next channel is LEFT
-					shiftreg(word_length downto 1) <= PCM_OUTL;
-				end if;
-			else
-				-- Decrement the LRCLK counter
-				lrdivider <= lrdivider - 1;
-				
-				-- Generate BCLK at a suitable rate to fit the required number
-				-- of bits into each timeslot.  Data is changed on the falling edge,
-				-- sampled on the rising edge
-				if bdivider = 0 then
-					-- If all bits have been output for this phase then
-					-- stop and wait to sync back up with LRCLK
-					if bitcount > 0 then
-						-- Reset
-						bdivider <= bdivider_top;
-						
-						-- Toggle BCLK
-						bclk_r <= not bclk_r;
-						if bclk_r = '0' then
-							-- Rising edge - shift in current bit and decrement bit counter
-							bitcount <= bitcount - 1;
-							shiftreg(0) <= I2S_DIN;
-						else
-							-- Falling edge - shift out next bit
-							shiftreg(nbits downto 1) <= shiftreg(nbits - 1 downto 0);
-						end if;
-					end if;
-				else
-					-- Decrement the BCLK counter
-					bdivider <= bdivider - 1;
-				end if;
-			end if;
-			
-		end if;
-	end process;
-end i2s_intf_arch;
-
Index: de1/ledsw.vhd
===================================================================
--- de1/ledsw.vhd	(revision 23)
+++ de1/ledsw.vhd	(nonexistent)
@@ -1,70 +0,0 @@
----------------------------------------------------------------------------
--- (c) 2013 mark watson
--- I am happy for anyone to use this for non-commercial use.
--- If my vhdl files are used commercially or otherwise sold,
--- please contact me for explicit permission at scrameta (gmail).
--- This applies for source and binary form and derived works.
----------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
--- Simple module that connects the SW switches to the LEDR lights
-ENTITY ledsw IS
-PORT ( 
-	CLK : IN STD_LOGIC;
-
-	SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
-	KEY : IN STD_LOGIC_VECTOR(3 downto 0);
-	
-	SYNC_KEYS : out std_logic_vector(3 downto 0);
-	SYNC_SWITCHES : out std_logic_vector(9 downto 0)
-); 
-END ledsw;
-
-ARCHITECTURE Behavior OF ledsw IS
-	component synchronizer IS
-	PORT 
-	( 
-		CLK : IN STD_LOGIC;
-		RAW : IN STD_LOGIC;
-		SYNC : OUT STD_LOGIC
-	);
-	END component;
-		
-	signal sw_reg : std_logic_vector(9 downto 0);
-	signal key_reg : std_logic_vector(3 downto 0);
-	
-BEGIN
-	sw9_synchronizer : synchronizer
-		port map (clk=>clk, raw=>sw(9), sync=>sw_reg(9));	
-	sw8_synchronizer : synchronizer
-		port map (clk=>clk, raw=>sw(8), sync=>sw_reg(8));	
-	sw7_synchronizer : synchronizer
-		port map (clk=>clk, raw=>sw(7), sync=>sw_reg(7));	
-	sw6_synchronizer : synchronizer
-		port map (clk=>clk, raw=>sw(6), sync=>sw_reg(6));	
-	sw5_synchronizer : synchronizer
-		port map (clk=>clk, raw=>sw(5), sync=>sw_reg(5));			
-	sw4_synchronizer : synchronizer
-		port map (clk=>clk, raw=>sw(4), sync=>sw_reg(4));	
-	sw3_synchronizer : synchronizer
-		port map (clk=>clk, raw=>sw(3), sync=>sw_reg(3));	
-	sw2_synchronizer : synchronizer
-		port map (clk=>clk, raw=>sw(2), sync=>sw_reg(2));	
-	sw1_synchronizer : synchronizer
-		port map (clk=>clk, raw=>sw(1), sync=>sw_reg(1));	
-	sw0_synchronizer : synchronizer
-		port map (clk=>clk, raw=>sw(0), sync=>sw_reg(0));			
-
-	key3_synchronizer : synchronizer
-		port map (clk=>clk, raw=>not(key(3)), sync=>key_reg(3));	
-	key2_synchronizer : synchronizer
-		port map (clk=>clk, raw=>not(key(2)), sync=>key_reg(2));	
-	key1_synchronizer : synchronizer
-		port map (clk=>clk, raw=>not(key(1)), sync=>key_reg(1));	
-	key0_synchronizer : synchronizer
-		port map (clk=>clk, raw=>not(key(0)), sync=>key_reg(0));			
-	
-	-- outputs
-	SYNC_KEYS <= key_reg(3)&key_reg(2)&key_reg(1)&key_reg(0);
-	SYNC_SWITCHES <= sw_reg(9)&sw_reg(8)&sw_reg(7)&sw_reg(6)&sw_reg(5)&sw_reg(4)&sw_reg(3)&sw_reg(2)&sw_reg(1)&sw_reg(0);
-END Behavior;
Index: de1/atari800core.jdi
===================================================================
--- de1/atari800core.jdi	(revision 23)
+++ de1/atari800core.jdi	(nonexistent)
@@ -1,6 +0,0 @@
-<sld_project_info>
-  <project>
-    <hash md5_digest_80b="00000000000000000000"/>
-  </project>
-  <file_info/>
-</sld_project_info>
Index: de1/atari800core.qws
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: de1/atari800core.qws
___________________________________________________________________
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property
Index: de1/defunct/hexdecoder.vhd
===================================================================
--- de1/defunct/hexdecoder.vhd	(revision 23)
+++ de1/defunct/hexdecoder.vhd	(nonexistent)
@@ -1,75 +0,0 @@
----------------------------------------------------------------------------
--- (c) 2013 mark watson
--- I am happy for anyone to use this for non-commercial use.
--- If my vhdl files are used commercially or otherwise sold,
--- please contact me for explicit permission at scrameta (gmail).
--- This applies for source and binary form and derived works.
----------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.all;
-
-ENTITY hexdecoder IS
-PORT 
-( 
-	CLK : IN STD_LOGIC;
-	NUMBER : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-	DIGIT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
-);
-END hexdecoder;
-
-ARCHITECTURE vhdl OF hexdecoder IS
-	signal numinv : STD_LOGIC_VECTOR(3 downto 0);
-	signal digit_next : std_logic_vector(6 downto 0);
-	signal digit_reg : STD_LOGIC_VECTOR(6 DOWNTO 0);
-BEGIN
-	--numinv <= not(NUMBER);
-	numinv <= NUMBER;
-	process(numinv)
-	begin
-		case numinv is
-			when "0000" =>
-				digit_next <= "1111111";
-			when "0001" =>
-				digit_next <= "1111001";
-			when "0010" =>
-				digit_next <= "0100100";
-			when "0011" =>
-				digit_next <= "0110000";
-			when "0100" =>
-				digit_next <= "0011001";
-			when "0101" =>
-				digit_next <= "0010010";
-			when "0110" =>
-				digit_next <= "0000010";
-			when "0111" =>
-				digit_next <= "1111000";
-			when "1000" =>
-				digit_next <= "0000000";
-			when "1001" =>
-				digit_next <= "0011000";
-			when "1010" =>
-				digit_next <= "0001000";
-			when "1011" =>
-				digit_next <= "0000011";
-			when "1100" =>
-				digit_next <= "1000110";
-			when "1101" =>
-				digit_next <= "0100001";
-			when "1110" =>
-				digit_next <= "0000110";
-			when "1111" =>
-				digit_next <= "0001110";
-			when others =>
-				digit_next <= "1111111";
-		end case;
-	end process;
-	
-	process(clk)
-	begin
-		if (clk'event and clk='1') then
-			digit_reg <= digit_next;
-		end if;
-	end process;
-	
-	digit<=digit_reg;
-END vhdl;
\ No newline at end of file
Index: de1/COPYRIGHT_NOTICE
===================================================================
--- de1/COPYRIGHT_NOTICE	(revision 23)
+++ de1/COPYRIGHT_NOTICE	(revision 24)
@@ -70,7 +70,6 @@
 Parameters modified for my use case
 
 i2c_loader.vhd
-i2s_intf.vhd
 
 -----------------------------------------------------------------------------------
 (c) Peter Wendrich
Index: de1/atari800core.qsf
===================================================================
--- de1/atari800core.qsf	(revision 23)
+++ de1/atari800core.qsf	(revision 24)
@@ -38,7 +38,7 @@
 
 set_global_assignment -name FAMILY "Cyclone II"
 set_global_assignment -name DEVICE EP2C20F484C7
-set_global_assignment -name TOP_LEVEL_ENTITY atari800core
+set_global_assignment -name TOP_LEVEL_ENTITY atari800core_de1
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39  APRIL 11, 2013"
 set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
@@ -555,64 +555,6 @@
 set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
 set_global_assignment -name FITTER_EFFORT "AUTO FIT"
 set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
-set_global_assignment -name VHDL_FILE atari800core.vhd
-set_global_assignment -name VHDL_FILE spi_master.vhd
-set_global_assignment -name VHDL_FILE zpu_config_regs.vhdl
-set_global_assignment -name VHDL_FILE zpu_rom.vhd
-set_global_assignment -name SOURCE_FILE zpu_rom.cmp
-set_global_assignment -name VHDL_FILE zpu_core.vhd
-set_global_assignment -name VHDL_FILE zpupkg.vhd
-set_global_assignment -name VHDL_FILE sdram_statemachine.vhdl
-set_global_assignment -name VHDL_FILE cpu_65xx_e.vhd
-set_global_assignment -name VHDL_FILE cpu_65xx_a.vhd
-set_global_assignment -name VHDL_FILE i2s_intf.vhd
-set_global_assignment -name VHDL_FILE i2c_loader.vhd
-set_global_assignment -name VHDL_FILE cpu.vhd
-set_global_assignment -name VHDL_FILE ledsw.vhd
-set_global_assignment -name VHDL_FILE hexdecoder.vhd
-set_global_assignment -name QIP_FILE pll.qip
-set_global_assignment -name SDC_FILE atari800core.sdc
-set_global_assignment -name VHDL_FILE dumprom.vhdl
-set_global_assignment -name VHDL_FILE reg_file.vhdl
-set_global_assignment -name VHDL_FILE address_decoder.vhdl
-set_global_assignment -name VHDL_FILE i2sslave.vhdl
-set_global_assignment -name VHDL_FILE pokey.vhdl
-set_global_assignment -name VHDL_FILE nmigen.vhdl
-set_global_assignment -name VHDL_FILE enable_divider.vhdl
-set_global_assignment -name VHDL_FILE poly_17_9.vhdl
-set_global_assignment -name VHDL_FILE poly_5.vhdl
-set_global_assignment -name VHDL_FILE poly_4.vhdl
-set_global_assignment -name VHDL_FILE delay_line.vhdl
-set_global_assignment -name VHDL_FILE countdown_timer.vhdl
-set_global_assignment -name VHDL_FILE pokey_mixer.vhdl
-set_global_assignment -name VHDL_FILE pokey_noise_filter.vhdl
-set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl
-set_global_assignment -name VHDL_FILE tvsync.vhdl
-set_global_assignment -name VHDL_FILE ps2_keyboard.vhdl
-set_global_assignment -name VHDL_FILE pokey_ps2_decoder.vhdl
-set_global_assignment -name VHDL_FILE flashrom.vhdl
-set_global_assignment -name VHDL_FILE sram.vhdl
-set_global_assignment -name VHDL_FILE antic.vhdl
-set_global_assignment -name VHDL_FILE antic_dma_clock.vhdl
-set_global_assignment -name VHDL_FILE antic_counter.vhdl
-set_global_assignment -name VHDL_FILE simple_counter.vhdl
-set_global_assignment -name VHDL_FILE gtia.vhdl
-set_global_assignment -name VHDL_FILE gtia_palette.vhdl
-set_global_assignment -name VHDL_FILE pia.vhdl
-set_global_assignment -name VHDL_FILE shared_enable.vhdl
-set_global_assignment -name VHDL_FILE gtia_player.vhdl
-set_global_assignment -name VHDL_FILE gtia_priority.vhdl
-set_global_assignment -name VHDL_FILE synchronizer.vhdl
-set_global_assignment -name VHDL_FILE scandoubler.vhdl
-set_global_assignment -name VHDL_FILE scandouble_ram_infer.vhdl
-set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd
-set_global_assignment -name VHDL_FILE wide_delay_line.vhdl
-set_global_assignment -name VHDL_FILE irq_glue.vhdl
-set_global_assignment -name VHDL_FILE gpio.vhd
-set_global_assignment -name VHDL_FILE pokey_keyboard_scanner.vhdl
-set_global_assignment -name VHDL_FILE zpu_glue.vhdl
-set_global_assignment -name QIP_FILE zpu_ram.qip
-set_global_assignment -name QIP_FILE zpu_rom.qip
 set_location_assignment PIN_A13 -to GPIO_0[0]
 set_location_assignment PIN_B13 -to GPIO_0[1]
 set_location_assignment PIN_A14 -to GPIO_0[2]
@@ -621,6 +563,14 @@
 set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
 set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
 
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
 
+set_global_assignment -name VHDL_FILE atari800core_de1.vhd
+set_global_assignment -name VHDL_FILE hexdecoder.vhd
+set_global_assignment -name VHDL_FILE i2c_loader.vhd
+set_global_assignment -name VHDL_FILE i2s_intf.vhd
+set_global_assignment -name VHDL_FILE i2sslave.vhdl
+set_global_assignment -name QIP_FILE pll.qip
+set_global_assignment -name VHDL_FILE sram.vhdl
+set_global_assignment -name VHDL_FILE sync_switches.vhd
 
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: de1/atari800core_de1.vhd
===================================================================
--- de1/atari800core_de1.vhd	(nonexistent)
+++ de1/atari800core_de1.vhd	(revision 24)
@@ -0,0 +1,534 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+use ieee.numeric_std.all;
+
+LIBRARY work;
+
+ENTITY atari800core_de1 IS 
+	PORT
+	(
+		CLOCK_50 :  IN  STD_LOGIC;
+
+		AUD_BCLK :  IN  STD_LOGIC;
+		AUD_DACLRCK :  IN  STD_LOGIC;
+		I2C_SCLK :  INOUT  STD_LOGIC;
+		I2C_SDAT :  INOUT  STD_LOGIC;
+
+		PS2_CLK :  IN  STD_LOGIC;
+		PS2_DAT :  IN  STD_LOGIC;
+
+		UART_RXD :  IN  STD_LOGIC;
+		UART_TXD :  OUT  STD_LOGIC;
+
+		GPIO_0 :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+		GPIO_1 :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+
+		KEY :  IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		SW :  IN  STD_LOGIC_VECTOR(9 DOWNTO 0);
+
+		AUD_XCK :  OUT  STD_LOGIC;
+		AUD_DACDAT :  OUT  STD_LOGIC;
+
+		FL_OE_N :  OUT  STD_LOGIC;
+		FL_WE_N :  OUT  STD_LOGIC;
+		FL_RST_N :  OUT  STD_LOGIC;
+		FL_ADDR :  OUT  STD_LOGIC_VECTOR(21 DOWNTO 0);
+		FL_DQ :  IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+		SRAM_CE_N :  OUT  STD_LOGIC;
+		SRAM_OE_N :  OUT  STD_LOGIC;
+		SRAM_WE_N :  OUT  STD_LOGIC;
+		SRAM_LB_N :  OUT  STD_LOGIC;
+		SRAM_UB_N :  OUT  STD_LOGIC;
+		SRAM_ADDR :  OUT  STD_LOGIC_VECTOR(17 DOWNTO 0);
+		SRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+		DRAM_BA_0 :  OUT  STD_LOGIC;
+		DRAM_BA_1 :  OUT  STD_LOGIC;
+		DRAM_CS_N :  OUT  STD_LOGIC;
+		DRAM_RAS_N :  OUT  STD_LOGIC;
+		DRAM_CAS_N :  OUT  STD_LOGIC;
+		DRAM_WE_N :  OUT  STD_LOGIC;
+		DRAM_LDQM :  OUT  STD_LOGIC;
+		DRAM_UDQM :  OUT  STD_LOGIC;
+		DRAM_CLK :  OUT  STD_LOGIC;
+		DRAM_CKE :  OUT  STD_LOGIC;
+		DRAM_ADDR :  OUT  STD_LOGIC_VECTOR(11 DOWNTO 0);
+		DRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+		SD_CLK :  OUT  STD_LOGIC;
+		SD_CMD :  OUT  STD_LOGIC;
+		SD_THREE :  OUT  STD_LOGIC;
+		SD_DATA :  IN  STD_LOGIC;
+
+		HEX0 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		HEX1 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		HEX2 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		HEX3 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+
+		LEDG :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		LEDR :  OUT  STD_LOGIC_VECTOR(9 DOWNTO 0);
+
+		VGA_VS :  OUT  STD_LOGIC;
+		VGA_HS :  OUT  STD_LOGIC;
+		VGA_B :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_G :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_R :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END atari800core_de1;
+
+ARCHITECTURE vhdl OF atari800core_de1 IS 
+	-- SYSTEM
+	SIGNAL CLK : STD_LOGIC;
+	SIGNAL CLK_SDRAM : STD_LOGIC;
+	SIGNAL RESET_N : STD_LOGIC;
+	SIGNAL PLL_LOCKED : STD_LOGIC;
+
+	-- PIA
+	SIGNAL	CA1_IN :  STD_LOGIC;
+	SIGNAL	CB1_IN:  STD_LOGIC;
+	SIGNAL	CA2_OUT :  STD_LOGIC;
+	SIGNAL	CA2_DIR_OUT:  STD_LOGIC;
+	SIGNAL	CB2_OUT :  STD_LOGIC;
+	SIGNAL	CB2_DIR_OUT:  STD_LOGIC;
+	SIGNAL	CA2_IN:  STD_LOGIC;
+	SIGNAL	CB2_IN:  STD_LOGIC;
+	SIGNAL	PORTA_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL	PORTA_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL	PORTA_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL	PORTB_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL	PORTB_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+	--SIGNAL	PORTB_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+	
+	-- GTIA
+	signal GTIA_TRIG : std_logic_vector(3 downto 0);
+	
+	-- ANTIC
+	signal ANTIC_LIGHTPEN : std_logic;
+	
+	-- CARTRIDGE ACCESS
+	SIGNAL	CART_RD4 :  STD_LOGIC;
+	SIGNAL	CART_RD5 :  STD_LOGIC;
+	
+	-- PBI
+	SIGNAL PBI_WRITE_DATA : std_logic_vector(31 downto 0);
+	SIGNAL PBI_WIDTH_32BIT_ACCESS : std_logic;
+	SIGNAL PBI_WIDTH_16BIT_ACCESS : std_logic;
+	SIGNAL PBI_WIDTH_8BIT_ACCESS : std_logic;
+	
+	-- INTERNAL ROM/RAM
+	SIGNAL	RAM_ADDR :  STD_LOGIC_VECTOR(18 DOWNTO 0);
+	SIGNAL	RAM_DO :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+	SIGNAL	RAM_REQUEST :  STD_LOGIC;
+	SIGNAL	RAM_REQUEST_COMPLETE :  STD_LOGIC;
+	SIGNAL	RAM_WRITE_ENABLE :  STD_LOGIC;
+	
+	SIGNAL	ROM_ADDR :  STD_LOGIC_VECTOR(21 DOWNTO 0);
+	SIGNAL	ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+	SIGNAL	ROM_REQUEST :  STD_LOGIC;
+	SIGNAL	ROM_REQUEST_COMPLETE :  STD_LOGIC;
+
+	-- pokey keyboard
+	SIGNAL KEYBOARD_SCAN : std_logic_vector(5 downto 0);
+	SIGNAL KEYBOARD_RESPONSE : std_logic_vector(1 downto 0);
+	
+	-- gtia consol keys
+	SIGNAL CONSOL_START : std_logic;
+	SIGNAL CONSOL_SELECT : std_logic;
+	SIGNAL CONSOL_OPTION : std_logic;
+	
+	-- 6502 throttling
+	SIGNAL THROTTLE_COUNT_6502 : std_logic_vector(5 downto 0);
+
+	-- SIO
+	SIGNAL SIO_RXD : std_logic;
+	SIGNAL SIO_COMMAND : std_logic;
+	SIGNAL SIO_TXD : std_logic;
+
+	-- VIDEO
+	signal VGA_VS_RAW : std_logic;
+	signal VGA_HS_RAW : std_logic;
+
+	-- AUDIO
+	signal AUDIO_LEFT : std_logic_vector(15 downto 0);
+	signal AUDIO_RIGHT : std_logic_vector(15 downto 0);
+
+BEGIN 
+
+-- ANYTHING NOT CONNECTED...
+GPIO_0(0) <= 'Z';
+GPIO_0(35 downto 2) <= (others=>'Z');
+GPIO_1(35 downto 0) <= (others=>'Z');
+
+FL_OE_N <= '1';
+FL_WE_N <= '1';
+FL_RST_N <= '1';
+FL_ADDR <= (others=>'0');
+
+DRAM_BA_0 <= '1';
+DRAM_BA_1 <= '1';
+DRAM_CS_N <= '1';
+DRAM_RAS_N <= '1';
+DRAM_CAS_N <= '1';
+DRAM_WE_N <= '1';
+DRAM_LDQM <= '1';
+DRAM_UDQM <= '1';
+DRAM_CKE <= '0';
+DRAM_ADDR <= (others=>'0');
+DRAM_DQ <= (others=>'Z');
+
+SD_CLK <= '1';
+SD_CMD <= '1';
+SD_THREE <= '1';
+
+LEDG <= (others=>'1');
+LEDR <= (others=>'1');
+
+-- TODO FUJI? Or Program counter or...
+hexdecoder0 : entity work.hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => X"A",
+		 DIGIT => HEX0);
+
+
+hexdecoder1 : entity work.hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => X"7",
+		 DIGIT => HEX1);
+
+
+hexdecoder2 : entity work.hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => X"A",
+		 DIGIT => HEX2);
+
+
+hexdecoder3 : entity work.hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => X"1",
+		 DIGIT => HEX3);
+
+sram1 : entity work.sram
+PORT MAP(WREN => RAM_WRITE_ENABLE,
+		 clk => CLK,
+		 reset_n => RESET_N,
+		 request => RAM_REQUEST,
+		 width_16bit => PBI_WIDTH_16BIT_ACCESS,
+		 ADDRESS => RAM_ADDR,
+		 DIN => PBI_WRITE_DATA(15 DOWNTO 0),
+		 SRAM_DQ => SRAM_DQ,
+		 SRAM_CE_N => SRAM_CE_N,
+		 SRAM_OE_N => SRAM_OE_N,
+		 SRAM_WE_N => SRAM_WE_N,
+		 SRAM_LB_N => SRAM_LB_N,
+		 SRAM_UB_N => SRAM_UB_N,
+		 complete => RAM_REQUEST_COMPLETE,
+		 DOUT => RAM_DO,
+		 SRAM_ADDR => SRAM_ADDR);
+
+-- PIA mapping
+CA1_IN <= '1';
+CB1_IN <= '1';
+CA2_IN <= CA2_OUT when CA2_DIR_OUT='1' else '1';
+CB2_IN <= CB2_OUT when CB2_DIR_OUT='1' else '1';
+SIO_COMMAND <= CB2_OUT;
+--PORTA_IN <= ((JOY2_n(3)&JOY2_n(2)&JOY2_n(1)&JOY2_n(0)&JOY1_n(3)&JOY1_n(2)&JOY1_n(1)&JOY1_n(0)) and not (porta_dir_out)) or (porta_dir_out and porta_out);
+PORTA_IN <= (not (porta_dir_out)) or (porta_dir_out and porta_out);
+PORTB_IN <= PORTB_OUT;
+
+-- ANTIC lightpen
+ANTIC_LIGHTPEN <= '1'; --JOY2_n(4) and JOY1_n(4);
+
+-- GTIA triggers
+--GTIA_TRIG <= CART_RD5&"1"&JOY2_n(4)&JOY1_n(4);
+GTIA_TRIG <= CART_RD5&"111";
+
+-- Cartridge not inserted
+CART_RD4 <= '0';
+CART_RD5 <= '0';
+
+-- Since we're not exposing PBI, expose a few key parts needed for SDRAM
+--SDRAM_DI <= PBI_WRITE_DATA;
+
+-- Internal rom/ram
+internalromram1 : entity work.internalromram
+	GENERIC MAP
+	(
+		internal_rom => 1,
+		internal_ram => 0
+	)
+	PORT MAP (
+ 		clock   => CLK,
+		reset_n => RESET_N,
+
+		ROM_ADDR => ROM_ADDR,
+		ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
+		ROM_REQUEST => ROM_REQUEST,
+		ROM_DATA => ROM_DO,
+		
+		RAM_ADDR => RAM_ADDR,
+		RAM_WR_ENABLE => RAM_WRITE_ENABLE,
+		RAM_DATA_IN => PBI_WRITE_DATA(7 downto 0),
+		RAM_REQUEST_COMPLETE => open,
+		RAM_REQUEST => RAM_REQUEST,
+		RAM_DATA => open
+	);
+
+--sync_switches1 : entity work.sync_switches
+--PORT MAP(CLK => CLK,
+--		 KEY => KEY,
+--		 SW => SW,
+--		 SYNC_KEYS => SYNC_KEYS,
+--		 SYNC_SWITCHES => SYNC_SWITCHES);
+
+--gpio0_gen:
+--   for I in 0 to 35 generate
+--		gpio_0(I) <= gpio_0_out(I) when gpio_0_dir_out(I)='1' else 'Z';
+--   end generate gpio0_gen;
+--
+--gpio1_gen:
+--   for I in 0 to 35 generate
+--		gpio_1(I) <= gpio_1_out(I) when gpio_1_dir_out(I)='1' else 'Z';
+--   end generate gpio1_gen;
+	
+--b2v_inst19 : entity work.gpio
+--PORT MAP(clk => CLK,
+--		 gpio_enable => GPIO_ENABLE,
+--		 pot_reset => POT_RESET,
+--		 virtual_keyheld => KEY_HELD,
+--		 virtual_shift_pressed => SHIFT_PRESSED,
+--		 virtual_control_pressed => KBCODE(7),
+--		 virtual_break_pressed => BREAK_PRESSED,
+--		 pbi_write_enable => PBI_WRITE_ENABLE,
+--		 cart_request => CART_REQUEST,
+--		 s4_n => CART_S4_n,
+--		 s5_n => CART_S5_N,
+--		 cctl_n => CART_CCTL_N,
+--		 cart_data_write => WRITE_DATA(7 DOWNTO 0),
+--		 GPIO_0_IN => GPIO_0,
+--		 GPIO_0_OUT => GPIO_0_OUT,
+--		 GPIO_0_DIR_OUT => GPIO_0_DIR_OUT,
+--		 GPIO_1_IN => GPIO_1,
+--		 GPIO_1_OUT => GPIO_1_OUT,
+--		 GPIO_1_DIR_OUT => GPIO_1_DIR_OUT,		 
+--		 keyboard_scan => KEYBOARD_SCAN,
+--		 pbi_addr_out => PBI_ADDR,
+--		 porta_out => PORTA_OUT,
+--		 porta_output => PORTA_DIR_OUT,
+--		 virtual_keycode => KBCODE(5 DOWNTO 0),
+--		 virtual_stick_in => VIRTUAL_STICKS,
+--		 virtual_trig_in => VIRTUAL_TRIGGERS,
+--		 lightpen => LIGHTPEN,
+--		 cart_complete => CART_REQUEST_COMPLETE,
+--		 rd4 => CART_RD4,
+--		 rd5 => CART_RD5,
+--		 cart_data_read => CART_ROM_DO,
+--		 keyboard_response => KEYBOARD_RESPONSE,
+--		 porta_in => GPIO_PORTA_IN,
+--		 pot_in => POT_IN,
+--		 trig_in => TRIGGERS,
+--		 monitor => SIO_DATA_IN, -- i.e. zpu sio out
+--		 CA2_DIR_OUT => CA2_DIR_OUT,
+--		 CA2_OUT => CA2_OUT,
+--		 CA2_IN => GPIO_CA2_IN,
+--		 CB2_DIR_OUT => CB2_DIR_OUT,
+--		 CB2_OUT => CB2_OUT,
+--		 CB2_IN => GPIO_CB2_IN,
+--		 SIO_IN => GPIO_SIO_IN,
+--		 SIO_OUT => GPIO_SIO_OUT
+--		 );
+
+--b2v_inst22 : entity work.scandoubler
+--PORT MAP(CLK => CLK,
+--		 RESET_N => RESET_N,
+--		 VGA => VGA,
+--		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+--		 colour_enable => SCANDOUBLER_SHARED_ENABLE_LOW,
+--		 doubled_enable => SCANDOUBLER_SHARED_ENABLE_HIGH,
+--		 vsync_in => SYNTHESIZED_WIRE_12,
+--		 hsync_in => SYNTHESIZED_WIRE_13,
+--		 colour_in => SYNTHESIZED_WIRE_14,
+--		 VSYNC => VGA_VS,
+--		 HSYNC => VGA_HS,
+--		 B => VGA_B,
+--		 G => VGA_G,
+--		 R => VGA_R);
+
+
+audio_codec_config_over_i2c : entity work.i2c_loader
+GENERIC MAP(device_address => 26,
+			log2_divider => 6,
+			num_retries => 0
+			)
+PORT MAP(CLK => CLK,
+		 nRESET => RESET_N,
+		 I2C_SCL => I2C_SCLK,
+		 I2C_SDA => I2C_SDAT);
+
+audio_codec_data : entity work.i2sslave
+PORT MAP(CLK => CLK,
+		 BCLK => AUD_BCLK,
+		 DACLRC => AUD_DACLRCK,
+		 LEFT_IN => AUDIO_LEFT,
+		 RIGHT_IN => AUDIO_RIGHT,
+		 MCLK_2 => AUD_XCK,
+		 DACDAT => AUD_DACDAT);
+
+pll : entity work.pll
+PORT MAP(inclk0 => CLOCK_50,
+		 c0 => CLK_SDRAM,
+		 c1 => CLK,
+		 c2 => DRAM_CLK,
+		 locked => PLL_LOCKED);
+
+RESET_N <= PLL_LOCKED;
+
+-- PS2 to pokey
+keyboard_map1 : entity work.ps2_to_atari800
+	PORT MAP
+	( 
+		CLK => clk,
+		RESET_N => reset_n,
+		PS2_CLK => ps2_clk,
+		PS2_DAT => ps2_dat,
+		
+		KEYBOARD_SCAN => KEYBOARD_SCAN,
+		KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
+
+		CONSOL_START => CONSOL_START,
+		CONSOL_SELECT => CONSOL_SELECT,
+		CONSOL_OPTION => CONSOL_OPTION
+		
+		-- TODO - reset!
+	);
+
+-- SIO
+SIO_RXD <= UART_RXD;
+UART_TXD <= SIO_TXD;
+GPIO_0(1) <= SIO_COMMAND;
+
+-- THROTTLE
+THROTTLE_COUNT_6502 <= std_logic_vector(to_unsigned(32-1,6));
+
+-- VIDEO
+VGA_HS <= not(VGA_HS_RAW xor VGA_VS_RAW);
+VGA_VS <= not(VGA_VS_RAW);
+
+atari800 : entity work.atari800core
+	GENERIC MAP
+	(
+		cycle_length => 32,
+		video_bits => 4
+	)
+	PORT MAP
+	(
+		CLK => CLK,
+		RESET_N => RESET_N,
+
+		VGA_VS => VGA_VS_RAW,
+		VGA_HS => VGA_HS_RAW,
+		VGA_B => VGA_B,
+		VGA_G => VGA_G,
+		VGA_R => VGA_R,
+
+		AUDIO_L => AUDIO_LEFT,
+		AUDIO_R => AUDIO_RIGHT,
+
+		CA1_IN => CA1_IN,
+		CB1_IN => CB1_IN,
+		CA2_IN => CA2_IN,
+		CA2_OUT => CA2_OUT,
+		CA2_DIR_OUT => CA2_DIR_OUT,
+		CB2_IN => CB2_IN,
+		CB2_OUT => CB2_OUT,
+		CB2_DIR_OUT => CB2_DIR_OUT,
+		PORTA_IN => PORTA_IN,
+		PORTA_DIR_OUT => PORTA_DIR_OUT,
+		PORTA_OUT => PORTA_OUT,
+		PORTB_IN => PORTB_IN,
+		PORTB_DIR_OUT => open,--PORTB_DIR_OUT,
+		PORTB_OUT => PORTB_OUT,
+
+		KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
+		KEYBOARD_SCAN => KEYBOARD_SCAN,
+
+		POT_IN => "00000000",
+		POT_RESET => open,
+		
+		PBI_ADDR => open,
+		PBI_WRITE_ENABLE => open,
+		PBI_SNOOP_DATA => open,
+		PBI_WRITE_DATA => PBI_WRITE_DATA,
+		PBI_WIDTH_8bit_ACCESS => PBI_WIDTH_8bit_ACCESS,
+		PBI_WIDTH_16bit_ACCESS => PBI_WIDTH_16bit_ACCESS,
+		PBI_WIDTH_32bit_ACCESS => PBI_WIDTH_32bit_ACCESS,
+
+		PBI_ROM_DO => "11111111",
+		PBI_REQUEST => open,
+		PBI_REQUEST_COMPLETE => '1',
+
+		CART_RD4 => CART_RD4,
+		CART_RD5 => CART_RD5,
+		CART_S4_n => open,
+		CART_S5_N => open,
+		CART_CCTL_N => open,
+
+		SIO_RXD => SIO_RXD,
+		SIO_TXD => SIO_TXD,
+
+		CONSOL_OPTION => CONSOL_OPTION,
+		CONSOL_SELECT => CONSOL_SELECT,
+		CONSOL_START=> CONSOL_START,
+		GTIA_TRIG => GTIA_TRIG,
+		
+		ANTIC_LIGHTPEN => ANTIC_LIGHTPEN,
+
+		SDRAM_REQUEST => open,
+		SDRAM_REQUEST_COMPLETE => '0',
+		SDRAM_READ_ENABLE => open,
+		SDRAM_WRITE_ENABLE => open,
+		SDRAM_ADDR => open,
+		SDRAM_DO => (others=>'0'),
+
+		SDRAM_REFRESH => open, -- TODO
+
+		RAM_ADDR => RAM_ADDR,
+		RAM_DO => RAM_DO,
+		RAM_REQUEST => RAM_REQUEST,
+		RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
+		RAM_WRITE_ENABLE => RAM_WRITE_ENABLE,
+		
+		ROM_ADDR => ROM_ADDR,
+		ROM_DO => ROM_DO,
+		ROM_REQUEST => ROM_REQUEST,
+		ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
+
+		DMA_FETCH => '0',
+		DMA_READ_ENABLE => '0',
+		DMA_32BIT_WRITE_ENABLE => '0',
+		DMA_16BIT_WRITE_ENABLE => '0',
+		DMA_8BIT_WRITE_ENABLE => '0',
+		DMA_ADDR => (others=>'0'),
+		DMA_WRITE_DATA => (others=>'0'),
+		MEMORY_READY_DMA => open,
+
+		RAM_SELECT => (others=>'0'),
+		ROM_SELECT => (others=>'0'),
+		CART_EMULATION_SELECT => "0000000",
+		CART_EMULATION_ACTIVATE => '0',
+		PAL => '1',
+		USE_SDRAM => '0',
+		ROM_IN_RAM => '0',
+		THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+		HALT => '0' 
+	);
+
+END vhdl;
Index: de1/build.sh
===================================================================
--- de1/build.sh	(nonexistent)
+++ de1/build.sh	(revision 24)
@@ -0,0 +1,21 @@
+rm -rf build
+mkdir build
+cp atari800core_de1.vhd build
+cp pll.* build
+cp atari800core.sdc build
+cp hexdecoder.vhd build
+cp i2c_loader.vhd build
+cp i2sslave.vhdl build
+cp sram.vhdl build
+cp sync_switches.vhd build
+
+mkdir build/common
+mkdir build/common/a8core
+mkdir build/common/components
+cp ../common/a8core/* ./build/common/a8core
+cp ../common/components/* ./build/common/components
+
+cd build
+../makeqsf ../atari800core.qsf ./common/a8core ./common/components
+
+quartus_sh --flow compile atari800core

Property changes on: de1/build.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: de1/hexdecoder.vhd
===================================================================
--- de1/hexdecoder.vhd	(nonexistent)
+++ de1/hexdecoder.vhd	(revision 24)
@@ -0,0 +1,75 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY hexdecoder IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	NUMBER : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+	DIGIT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+);
+END hexdecoder;
+
+ARCHITECTURE vhdl OF hexdecoder IS
+	signal numinv : STD_LOGIC_VECTOR(3 downto 0);
+	signal digit_next : std_logic_vector(6 downto 0);
+	signal digit_reg : STD_LOGIC_VECTOR(6 DOWNTO 0);
+BEGIN
+	--numinv <= not(NUMBER);
+	numinv <= NUMBER;
+	process(numinv)
+	begin
+		case numinv is
+			when "0000" =>
+				digit_next <= "1111111";
+			when "0001" =>
+				digit_next <= "1111001";
+			when "0010" =>
+				digit_next <= "0100100";
+			when "0011" =>
+				digit_next <= "0110000";
+			when "0100" =>
+				digit_next <= "0011001";
+			when "0101" =>
+				digit_next <= "0010010";
+			when "0110" =>
+				digit_next <= "0000010";
+			when "0111" =>
+				digit_next <= "1111000";
+			when "1000" =>
+				digit_next <= "0000000";
+			when "1001" =>
+				digit_next <= "0011000";
+			when "1010" =>
+				digit_next <= "0001000";
+			when "1011" =>
+				digit_next <= "0000011";
+			when "1100" =>
+				digit_next <= "1000110";
+			when "1101" =>
+				digit_next <= "0100001";
+			when "1110" =>
+				digit_next <= "0000110";
+			when "1111" =>
+				digit_next <= "0001110";
+			when others =>
+				digit_next <= "1111111";
+		end case;
+	end process;
+	
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			digit_reg <= digit_next;
+		end if;
+	end process;
+	
+	digit<=digit_reg;
+END vhdl;
\ No newline at end of file
Index: de1/makeqsf
===================================================================
--- de1/makeqsf	(nonexistent)
+++ de1/makeqsf	(revision 24)
@@ -0,0 +1,33 @@
+#!/usr/bin/perl -w
+use strict;
+
+my $qsf_in = shift @ARGV;
+my $qsf_out = $qsf_in;
+$qsf_out =~ s/.*\///;
+
+open (QSF_IN,$qsf_in) or die "Failed to open $qsf_in";
+my @qsf_base = <QSF_IN>;
+close (QSF_IN);
+
+open (QSF_OUT,">$qsf_out") or die "Failed to open $qsf_out";
+print QSF_OUT @qsf_base;
+
+foreach (@ARGV)
+{
+	my @vhdl = glob ("$_/*.vhd");
+	push @vhdl, glob ("$_/*.vhdl");
+	my @verilog = glob ("$_/*.v");
+
+	foreach (@verilog)
+	{
+		print QSF_OUT "set_global_assignment -name VERILOG_FILE $_\n";
+	}
+
+	foreach (@vhdl)
+	{
+		print QSF_OUT "set_global_assignment -name VHDL_FILE $_\n";
+	}
+}
+
+close (QSF_OUT);
+

Property changes on: de1/makeqsf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: de1/sync_switches.vhd
===================================================================
--- de1/sync_switches.vhd	(nonexistent)
+++ de1/sync_switches.vhd	(revision 24)
@@ -0,0 +1,69 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+ENTITY sync_switches IS
+PORT ( 
+	CLK : IN STD_LOGIC;
+
+	SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+	KEY : IN STD_LOGIC_VECTOR(3 downto 0);
+	
+	SYNC_KEYS : out std_logic_vector(3 downto 0);
+	SYNC_SWITCHES : out std_logic_vector(9 downto 0)
+); 
+END sync_switches;
+
+ARCHITECTURE Behavior OF sync_switches IS
+	component synchronizer IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RAW : IN STD_LOGIC;
+		SYNC : OUT STD_LOGIC
+	);
+	END component;
+		
+	signal sw_reg : std_logic_vector(9 downto 0);
+	signal key_reg : std_logic_vector(3 downto 0);
+	
+BEGIN
+	sw9_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(9), sync=>sw_reg(9));	
+	sw8_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(8), sync=>sw_reg(8));	
+	sw7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(7), sync=>sw_reg(7));	
+	sw6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(6), sync=>sw_reg(6));	
+	sw5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(5), sync=>sw_reg(5));			
+	sw4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(4), sync=>sw_reg(4));	
+	sw3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(3), sync=>sw_reg(3));	
+	sw2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(2), sync=>sw_reg(2));	
+	sw1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(1), sync=>sw_reg(1));	
+	sw0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(0), sync=>sw_reg(0));			
+
+	key3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(3)), sync=>key_reg(3));	
+	key2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(2)), sync=>key_reg(2));	
+	key1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(1)), sync=>key_reg(1));	
+	key0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(0)), sync=>key_reg(0));			
+	
+	-- outputs
+	SYNC_KEYS <= key_reg(3)&key_reg(2)&key_reg(1)&key_reg(0);
+	SYNC_SWITCHES <= sw_reg(9)&sw_reg(8)&sw_reg(7)&sw_reg(6)&sw_reg(5)&sw_reg(4)&sw_reg(3)&sw_reg(2)&sw_reg(1)&sw_reg(0);
+END Behavior;
