Index: replay/out
===================================================================
--- replay/out	(revision 17)
+++ replay/out	(nonexistent)
@@ -1,11394 +0,0 @@
-. /home/markw/altera/xilinx/ise/14.7/ISE_DS/common/.settings32.sh /home/markw/altera/xilinx/ise/14.7/ISE_DS/common
-. /home/markw/altera/xilinx/ise/14.7/ISE_DS/EDK/.settings32.sh /home/markw/altera/xilinx/ise/14.7/ISE_DS/EDK
-. /home/markw/altera/xilinx/ise/14.7/ISE_DS/PlanAhead/.settings32.sh /home/markw/altera/xilinx/ise/14.7/ISE_DS/PlanAhead
-. /home/markw/altera/xilinx/ise/14.7/ISE_DS/ISE/.settings32.sh /home/markw/altera/xilinx/ise/14.7/ISE_DS/ISE
-~/altera/replay/src/hw/replay/cores/atari_800xl/build ~/altera/replay/src/hw/replay/cores/atari_800xl
-Starting Synthesis...
-Release 14.7 - xst P.20131013 (lin)
-Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
---> 
-
-TABLE OF CONTENTS
-  1) Synthesis Options Summary
-  2) HDL Compilation
-  3) Design Hierarchy Analysis
-  4) HDL Analysis
-  5) HDL Synthesis
-     5.1) HDL Synthesis Report
-  6) Advanced HDL Synthesis
-     6.1) Advanced HDL Synthesis Report
-  7) Low Level Synthesis
-  8) Partition Report
-  9) Final Report
-	9.1) Device utilization summary
-	9.2) Partition Resource Summary
-	9.3) TIMING REPORT
-
-
-=========================================================================
-*                      Synthesis Options Summary                        *
-=========================================================================
----- Source Parameters
-Input File Name                    : "Replay.prj"
-Input Format                       : VHDL
-
----- Target Parameters
-Output File Name                   : "Replay.ngc"
-Output Format                      : NGC
-Target Device                      : XC3S1600E-FG320-4
-
----- Source Options
-Top Module Name                    : Replay_Top
-
----- General Options
-Optimization Goal                  : Area
-Optimization Effort                : 1
-Keep Hierarchy                     : yes
-
-=========================================================================
-
-
-=========================================================================
-*                          HDL Compilation                              *
-=========================================================================
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/delay_line.vhdl" in Library work.
-Architecture vhdl of Entity delay_line is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Pack.vhd" in Library work.
-Architecture replay_pack of Entity replay_pack is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/complete_address_decoder.vhdl" in Library work.
-Architecture tree of Entity complete_address_decoder is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/countdown_timer.vhdl" in Library work.
-Architecture vhdl of Entity pokey_countdown_timer is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pokey_noise_filter.vhdl" in Library work.
-Architecture vhdl of Entity pokey_noise_filter is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/syncreset_enable_divider.vhd" in Library work.
-Architecture vhdl of Entity syncreset_enable_divider is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/poly_17_9.vhdl" in Library work.
-Architecture vhdl of Entity poly_17_9 is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/poly_5.vhdl" in Library work.
-Architecture vhdl of Entity poly_5 is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/poly_4.vhdl" in Library work.
-Architecture vhdl of Entity poly_4 is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/synchronizer.vhdl" in Library work.
-Architecture vhdl of Entity synchronizer is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pokey_keyboard_scanner.vhdl" in Library work.
-Architecture vhdl of Entity pokey_keyboard_scanner is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpupkg.vhd" in Library work.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_DDRCtrl_Pack.vhd" in Library work.
-Architecture replay_ddrctrl_pack of Entity replay_ddrctrl_pack is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_VideoTiming_Pack.vhd" in Library work.
-Architecture replay_videotiming_pack of Entity replay_videotiming_pack is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/basic.vhdl" in Library work.
-Architecture syn of Entity basic is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/os16.vhdl" in Library work.
-Architecture syn of Entity os16 is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/generic_ram_infer.vhdl" in Library work.
-Architecture rtl of Entity generic_ram_infer is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/simple_counter.vhdl" in Library work.
-Architecture vhdl of Entity simple_counter is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/gtia_player.vhdl" in Library work.
-Architecture vhdl of Entity gtia_player is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/gtia_priority.vhdl" in Library work.
-Architecture vhdl of Entity gtia_priority is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl" in Library work.
-Architecture vhdl of Entity wide_delay_line is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pokey.vhdl" in Library work.
-Architecture vhdl of Entity pokey is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/enable_divider.vhdl" in Library work.
-Architecture vhdl of Entity enable_divider is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_core.vhd" in Library work.
-Architecture behave of Entity zpumediumcore is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/antic_counter.vhdl" in Library work.
-Architecture vhdl of Entity antic_counter is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/antic_dma_clock.vhdl" in Library work.
-Architecture vhdl of Entity antic_dma_clock is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/reg_file.vhdl" in Library work.
-Architecture vhdl of Entity reg_file is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/cpu_65xx_e.vhd" in Library work.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/font0_rom.vhd" in Library work.
-Architecture rtl of Entity font0 is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/font1_rom.vhd" in Library work.
-Architecture rtl of Entity font1 is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/font2_rom.vhd" in Library work.
-Architecture rtl of Entity font2 is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_DDRCtrl_Datapath.vhd" in Library work.
-Architecture rtl of Entity replay_ddrctrl_datapath is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_VideoTiming.vhd" in Library work.
-Architecture rtl of Entity replay_videotiming is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_TranslatePS2_Pack.vhd" in Library work.
-Architecture replay_translateps2_pack of Entity replay_translateps2_pack is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/cpu.vhd" in Library work.
-Architecture vhdl of Entity cpu is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/antic.vhdl" in Library work.
-Architecture vhdl of Entity antic is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pokey_mixer.vhdl" in Library work.
-Architecture vhdl of Entity pokey_mixer is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_glue.vhdl" in Library work.
-Architecture sticky of Entity zpu_glue is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pia.vhdl" in Library work.
-Architecture vhdl of Entity pia is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/shared_enable.vhdl" in Library work.
-Architecture vhdl of Entity shared_enable is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/address_decoder.vhdl" in Library work.
-Architecture vhdl of Entity address_decoder is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_rom.vhdl" in Library work.
-Architecture syn of Entity zpu_rom is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" in Library work.
-Architecture vhdl of Entity zpu_config_regs is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/gtia.vhdl" in Library work.
-Architecture vhdl of Entity gtia is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/gtia_palette.vhdl" in Library work.
-Architecture altirra of Entity gtia_palette is up to date.
-Architecture laoo of Entity gtia_palette is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/irq_glue.vhdl" in Library work.
-Architecture vhdl of Entity irq_glue is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/internalromram.vhd" in Library work.
-Architecture vhdl of Entity internalromram is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/covox.vhd" in Library work.
-Architecture vhdl of Entity covox is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_I2C.vhd" in Library work.
-Architecture rtl of Entity replay_i2c is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_SPI8.vhd" in Library work.
-Architecture rtl of Entity replay_spi8 is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/FIFO_SyncBlock_D2048_W8.vhd" in Library work.
-Architecture rtl of Entity fifo_syncblock_d2048_w8 is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/FIFO_SyncSRL_D16.vhd" in Library work.
-Architecture rtl of Entity fifo_syncsrl_d16 is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_OSD.vhd" in Library work.
-Architecture rtl of Entity replay_osd is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_DDRCtrl.vhd" in Library work.
-Architecture rtl of Entity replay_ddrctrl is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" in Library work.
-Architecture low_level_definition of Entity kcpsm3 is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" in Library work.
-Architecture low_level_definition of Entity ps2_rom is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" in Library work.
-Entity <atari800core> compiled.
-Entity <atari800core> (Architecture <bdf_type>) compiled.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_TranslatePS2.vhd" in Library work.
-Architecture rtl of Entity replay_translateps2 is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_VideoConverter.vhd" in Library work.
-Architecture rtl of Entity replay_videoconverter is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_ClockGen_Sync.vhd" in Library work.
-Architecture rtl of Entity replay_resetgen is up to date.
-Architecture rtl of Entity replay_clockgen is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Core_Top.vhd" in Library work.
-Architecture rtl of Entity core_top is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_JoyPS2.vhd" in Library work.
-Architecture rtl of Entity replay_joyps2_core is up to date.
-Architecture rtl of Entity replay_joyps2 is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_DDRCtrl_Top.vhd" in Library work.
-Architecture rtl of Entity replay_ddrctrl_top is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Syscon.vhd" in Library work.
-Architecture rtl of Entity replay_syscon is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_FileIO_Sync.vhd" in Library work.
-Architecture rtl of Entity replay_fileio is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Video.vhd" in Library work.
-Architecture rtl of Entity replay_video is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Audio.vhd" in Library work.
-Architecture rtl of Entity replay_audio is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" in Library work.
-Architecture rtl of Entity replay_top is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/cpu_6510.vhd" in Library work.
-Architecture rtl of Entity cpu_6510 is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/cpu_65xx_a.vhd" in Library work.
-Architecture rtl of Entity cpu_65xx is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_MousePointer.vhd" in Library work.
-Architecture rtl of Entity replay_mousepointer is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/DPRAM_BE_D64.vhd" in Library work.
-Architecture rtl of Entity dpram_be_d64 is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/FIFO_SyncBlock_D1024_W18.vhd" in Library work.
-Architecture rtl of Entity fifo_syncblock_d1024_w18 is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/FIFO_Async_D32.vhd" in Library work.
-Architecture rtl of Entity fifo_async_d32 is up to date.
-Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/FIFO_Async_D16.vhd" in Library work.
-Architecture rtl of Entity fifo_async_d16 is up to date.
-
-=========================================================================
-*                     Design Hierarchy Analysis                         *
-=========================================================================
-Analyzing hierarchy for entity <Replay_Top> in library <work> (architecture <rtl>).
-
-Analyzing hierarchy for entity <Replay_ClockGen> in library <work> (architecture <RTL>) with generics.
-	G_DIVIDER = 11
-
-Analyzing hierarchy for entity <Core_Top> in library <work> (architecture <RTL>).
-
-Analyzing hierarchy for entity <Replay_JoyPS2> in library <work> (architecture <RTL>).
-
-Analyzing hierarchy for entity <Replay_DDRCtrl_Top> in library <work> (architecture <rtl>) with generics.
-	g_lp_big_endian = '1'
-
-Analyzing hierarchy for entity <Replay_Syscon> in library <work> (architecture <RTL>) with generics.
-	g_cfg_ctrl = "0000000010000000"
-	g_cfg_dynamic = "00000000000000000000000000000000"
-	g_cfg_fileio = "00000000"
-	g_cfg_static = "00000000000000000000000000000000"
-	g_version = "0000000000000001"
-
-Analyzing hierarchy for entity <Replay_FileIO> in library <work> (architecture <RTL>).
-
-Analyzing hierarchy for entity <Replay_Video> in library <work> (architecture <RTL>).
-
-Analyzing hierarchy for entity <Replay_Audio> in library <work> (architecture <RTL>).
-
-Analyzing hierarchy for entity <Replay_ResetGen> in library <work> (architecture <RTL>).
-
-Analyzing hierarchy for entity <atari800core> in library <work> (architecture <bdf_type>).
-
-Analyzing hierarchy for entity <Replay_TranslatePS2> in library <work> (architecture <RTL>) with generics.
-	g_kb_map = ("11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01100111",
-	            "11111111",
-	            "01010111",
-	            "11111111",
-	            "01000111",
-	            "11111111",
-	            "01000110",
-	            "01000000",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01000110",
-	            "01110111",
-	            "01000110",
-	            "01100000",
-	            "01000110",
-	            "01010111",
-	            "00110000",
-	            "11111111",
-	            "00000110",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "00110001",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "00100000",
-	            "11111111",
-	            "01100000",
-	            "11111111",
-	            "00000000",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01000001",
-	            "11111111",
-	            "01010001",
-	            "11111111",
-	            "00100001",
-	            "11111111",
-	            "00010001",
-	            "11111111",
-	            "01110000",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01000010",
-	            "11111111",
-	            "00110010",
-	            "11111111",
-	            "00100010",
-	            "11111111",
-	            "01100001",
-	            "11111111",
-	            "01110001",
-	            "11111111",
-	            "00000001",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01000000",
-	            "11111111",
-	            "00110011",
-	            "11111111",
-	            "01010010",
-	            "11111111",
-	            "01100010",
-	            "11111111",
-	            "00010010",
-	            "11111111",
-	            "00000010",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "00110100",
-	            "11111111",
-	            "01000011",
-	            "11111111",
-	            "01010011",
-	            "11111111",
-	            "00100011",
-	            "11111111",
-	            "00010011",
-	            "11111111",
-	            "01110010",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01000100",
-	            "11111111",
-	            "00100100",
-	            "11111111",
-	            "01100011",
-	            "11111111",
-	            "00000011",
-	            "11111111",
-	            "01110011",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "00110101",
-	            "11111111",
-	            "01010100",
-	            "11111111",
-	            "00010100",
-	            "11111111",
-	            "01100100",
-	            "11111111",
-	            "01110100",
-	            "11111111",
-	            "00000100",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01000101",
-	            "11111111",
-	            "00110110",
-	            "11111111",
-	            "00100101",
-	            "11111111",
-	            "00100110",
-	            "11111111",
-	            "00010101",
-	            "11111111",
-	            "00000101",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01010101",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01100101",
-	            "11111111",
-	            "01110101",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11000000",
-	            "11111111",
-	            "01000110",
-	            "11111111",
-	            "00010111",
-	            "11111111",
-	            "00010110",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01100110",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "00000111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "10000100",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "10000010",
-	            "11111111",
-	            "10010000",
-	            "11111111",
-	            "10001000",
-	            "11111111",
-	            "10000001",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01110111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "00100000",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01010000",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01010000",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "00000111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01000110",
-	            "00100111",
-	            "01110110",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "00110111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "00100111",
-	            "11111111",
-	            "01000110",
-	            "00110111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01010110",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "10100000",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111")
-
-Analyzing hierarchy for entity <Replay_VideoConverter> in library <work> (architecture <RTL>) with generics.
-	g_b_bitwidth = 8
-	g_g_bitwidth = 8
-	g_hadr_width = 9
-	g_hoffset = 0
-	g_hscale = "010000000"
-	g_hsize = 900
-	g_loffset = 0
-	g_match_line = 0
-	g_r_bitwidth = 8
-	g_vadr_width = 2
-	g_vid_param_hd = (rep_h => '0'
-	                  total_h => 864
-	                  active_h => 720
-	                  syncp_h => 12
-	                  syncw_h => 64
-	                  total_v => 625
-	                  active_v => 576
-	                  fline_f1_v => 44
-	                  lline_f1_v => 620
-	                  fline_f2_v => 0
-	                  lline_f2_v => 0
-	                  start_f1_v => 625
-	                  start_f2_v => 0
-	                  fsync_f1_v => 625
-	                  lsync_f1_v => 5
-	                  fsync_f2_v => 0
-	                  lsync_f2_v => 0
-	                  syncpol_h => '0'
-	                  syncpol_v => '0'
-	                  progressive => '1')
-	g_vid_param_sd = (rep_h => '1'
-	                  total_h => 1728
-	                  active_h => 1440
-	                  syncp_h => 24
-	                  syncw_h => 126
-	                  total_v => 625
-	                  active_v => 576
-	                  fline_f1_v => 22
-	                  lline_f1_v => 310
-	                  fline_f2_v => 335
-	                  lline_f2_v => 623
-	                  start_f1_v => 623
-	                  start_f2_v => 310
-	                  fsync_f1_v => 625
-	                  lsync_f1_v => 3
-	                  fsync_f2_v => 312
-	                  lsync_f2_v => 315
-	                  syncpol_h => '0'
-	                  syncpol_v => '0'
-	                  progressive => '0')
-	g_voffset = 21
-	g_vres_half = 1
-	g_vsize = 248
-
-Analyzing hierarchy for entity <Replay_JoyPS2_Core> in library <work> (architecture <RTL>) with generics.
-	g_id = '0'
-
-Analyzing hierarchy for entity <Replay_JoyPS2_Core> in library <work> (architecture <RTL>) with generics.
-	g_id = '1'
-
-Analyzing hierarchy for entity <ps2_rom> in library <work> (architecture <low_level_definition>).
-
-Analyzing hierarchy for entity <Replay_DDRCtrl> in library <work> (architecture <rtl>).
-
-Analyzing hierarchy for entity <Replay_SPI8> in library <work> (architecture <RTL>).
-
-Analyzing hierarchy for entity <FIFO_SyncSRL_D16> in library <work> (architecture <RTL>) with generics.
-	g_width = 8
-
-Analyzing hierarchy for entity <Replay_OSD> in library <work> (architecture <RTL>).
-
-Analyzing hierarchy for entity <FIFO_SyncBlock_D2048_W8> in library <work> (architecture <RTL>).
-
-Analyzing hierarchy for entity <Replay_I2C> in library <work> (architecture <RTL>).
-
-Analyzing hierarchy for entity <cpu> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <antic> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <pokey_mixer> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <zpu_glue> in library <work> (architecture <sticky>).
-
-Analyzing hierarchy for entity <pokey> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <pia> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <shared_enable> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <address_decoder> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <zpu_rom> in library <work> (architecture <syn>).
-
-Analyzing hierarchy for entity <generic_ram_infer> in library <work> (architecture <rtl>) with generics.
-	ADDRESS_WIDTH = 10
-	DATA_WIDTH = 8
-	SPACE = 1024
-
-Analyzing hierarchy for entity <zpu_config_regs> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <complete_address_decoder> in library <work> (architecture <tree>) with generics.
-	width = 3
-
-Analyzing hierarchy for entity <gtia> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <gtia_palette> in library <work> (architecture <altirra>).
-
-Analyzing hierarchy for entity <irq_glue> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <reg_file> in library <work> (architecture <vhdl>) with generics.
-	BYTES = 16
-	WIDTH = 4
-
-Analyzing hierarchy for entity <reg_file> in library <work> (architecture <vhdl>) with generics.
-	BYTES = 32
-	WIDTH = 5
-
-Analyzing hierarchy for entity <internalromram> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <covox> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <Replay_VideoTiming> in library <work> (architecture <RTL>) with generics.
-	g_enabledynamic = '1'
-	g_param = (rep_h => '0'
-	           total_h => 800
-	           active_h => 640
-	           syncp_h => 16
-	           syncw_h => 96
-	           total_v => 525
-	           active_v => 480
-	           fline_f1_v => 42
-	           lline_f1_v => 522
-	           fline_f2_v => 0
-	           lline_f2_v => 0
-	           start_f1_v => 525
-	           start_f2_v => 0
-	           fsync_f1_v => 7
-	           lsync_f1_v => 9
-	           fsync_f2_v => 0
-	           lsync_f2_v => 0
-	           syncpol_h => '0'
-	           syncpol_v => '0'
-	           progressive => '1')
-
-Analyzing hierarchy for entity <kcpsm3> in library <work> (architecture <low_level_definition>).
-
-Analyzing hierarchy for entity <Replay_DDRCtrl_Datapath> in library <work> (architecture <rtl>).
-
-Analyzing hierarchy for entity <FONT0> in library <work> (architecture <RTL>).
-
-Analyzing hierarchy for entity <FONT1> in library <work> (architecture <RTL>).
-
-Analyzing hierarchy for entity <FONT2> in library <work> (architecture <RTL>).
-
-Analyzing hierarchy for entity <cpu_65xx> in library <work> (architecture <rtl>) with generics.
-	pipelineAluMux = false
-	pipelineAluOut = false
-	pipelineOpcode = false
-
-Analyzing hierarchy for entity <antic_counter> in library <work> (architecture <vhdl>) with generics.
-	COUNT_WIDTH = 12
-	STORE_WIDTH = 16
-
-Analyzing hierarchy for entity <antic_counter> in library <work> (architecture <vhdl>) with generics.
-	COUNT_WIDTH = 10
-	STORE_WIDTH = 16
-
-Analyzing hierarchy for entity <simple_counter> in library <work> (architecture <vhdl>) with generics.
-	COUNT_WIDTH = 8
-
-Analyzing hierarchy for entity <simple_counter> in library <work> (architecture <vhdl>) with generics.
-	COUNT_WIDTH = 4
-
-Analyzing hierarchy for entity <wide_delay_line> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 16
-	WIDTH = 2
-
-Analyzing hierarchy for entity <antic_dma_clock> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <reg_file> in library <work> (architecture <vhdl>) with generics.
-	BYTES = 48
-	WIDTH = 6
-
-Analyzing hierarchy for entity <wide_delay_line> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 16
-	WIDTH = 4
-
-Analyzing hierarchy for entity <wide_delay_line> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 32
-	WIDTH = 7
-
-Analyzing hierarchy for entity <complete_address_decoder> in library <work> (architecture <tree>) with generics.
-	width = 4
-
-Analyzing hierarchy for entity <delay_line> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 24
-
-Analyzing hierarchy for entity <ZPUMediumCore> in library <work> (architecture <behave>) with generics.
-	ADDR_W = 24
-	BINOP_PIPE = 0
-	D_CARE_VAL = 'D'
-	ENA_IDLE = false
-	ENA_LEVEL0 = true
-	ENA_LEVEL1 = true
-	ENA_LEVEL2 = true
-	ENA_LSHR = true
-	FAST_FETCH = true
-	MEM_W = 16
-	MULT_PIPE = false
-	WORD_SIZE = 32
-
-Analyzing hierarchy for entity <pokey_countdown_timer> in library <work> (architecture <vhdl>) with generics.
-	UNDERFLOW_DELAY = 3
-
-Analyzing hierarchy for entity <delay_line> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 3
-
-Analyzing hierarchy for entity <pokey_noise_filter> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <syncreset_enable_divider> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 28
-	RESETCOUNT = 6
-
-Analyzing hierarchy for entity <syncreset_enable_divider> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 114
-	RESETCOUNT = 33
-
-Analyzing hierarchy for entity <poly_17_9> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <poly_5> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <poly_4> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <delay_line> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 2
-
-Analyzing hierarchy for entity <synchronizer> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <pokey_keyboard_scanner> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <complete_address_decoder> in library <work> (architecture <tree>) with generics.
-	width = 2
-
-Analyzing hierarchy for entity <enable_divider> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 2
-
-Analyzing hierarchy for entity <enable_divider> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 16
-
-Analyzing hierarchy for entity <delay_line> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 15
-
-Analyzing hierarchy for entity <delay_line> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 8
-
-Analyzing hierarchy for entity <pokey> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <complete_address_decoder> in library <work> (architecture <tree>) with generics.
-	width = 5
-
-Analyzing hierarchy for entity <gtia_player> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <gtia_priority> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <wide_delay_line> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 2
-	WIDTH = 6
-
-Analyzing hierarchy for entity <wide_delay_line> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 3
-	WIDTH = 2
-
-Analyzing hierarchy for entity <wide_delay_line> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 4
-	WIDTH = 2
-
-Analyzing hierarchy for entity <wide_delay_line> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 2
-	WIDTH = 7
-
-Analyzing hierarchy for entity <wide_delay_line> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 5
-	WIDTH = 8
-
-Analyzing hierarchy for entity <wide_delay_line> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 4
-	WIDTH = 8
-
-Analyzing hierarchy for entity <basic> in library <work> (architecture <syn>).
-
-Analyzing hierarchy for entity <os16> in library <work> (architecture <syn>).
-
-Analyzing hierarchy for entity <generic_ram_infer> in library <work> (architecture <rtl>) with generics.
-	ADDRESS_WIDTH = 14
-	DATA_WIDTH = 8
-	SPACE = 16384
-
-Analyzing hierarchy for entity <complete_address_decoder> in library <work> (architecture <tree>) with generics.
-	width = 2
-
-Analyzing hierarchy for entity <complete_address_decoder> in library <work> (architecture <tree>) with generics.
-	width = 6
-
-Analyzing hierarchy for entity <complete_address_decoder> in library <work> (architecture <tree>) with generics.
-	width = 4
-
-Analyzing hierarchy for entity <pokey_countdown_timer> in library <work> (architecture <vhdl>) with generics.
-	UNDERFLOW_DELAY = 3
-
-Analyzing hierarchy for entity <delay_line> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 3
-
-Analyzing hierarchy for entity <pokey_noise_filter> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <syncreset_enable_divider> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 28
-	RESETCOUNT = 6
-
-Analyzing hierarchy for entity <syncreset_enable_divider> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 114
-	RESETCOUNT = 33
-
-Analyzing hierarchy for entity <poly_17_9> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <poly_5> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <poly_4> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <delay_line> in library <work> (architecture <vhdl>) with generics.
-	COUNT = 2
-
-Analyzing hierarchy for entity <synchronizer> in library <work> (architecture <vhdl>).
-
-Analyzing hierarchy for entity <pokey_keyboard_scanner> in library <work> (architecture <vhdl>).
-
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 292: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1205: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 455: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 486: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 609: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 617: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 384: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 426: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 528: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 600: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 685: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1114: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1141: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1225: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1274: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 335: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 374: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 406: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 416: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 435: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 445: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 471: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 496: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 557: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 590: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 797: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 874: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 889: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 942: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 961: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1249: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1306: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1316: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1332: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1420: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1453: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 831: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 910: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1373: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INITP_00> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INITP_01> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INITP_02> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INITP_03> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INITP_04> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INITP_05> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INITP_06> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INITP_07> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_00> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_01> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_02> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_03> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_04> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_05> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_06> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_07> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_08> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_09> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_0A> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_0B> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_0C> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_0D> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_0E> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_0F> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_10> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_11> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_12> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_13> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_14> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_15> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_16> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_17> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_18> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_19> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_1A> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_1B> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_1C> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_1D> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_1E> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_1F> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_20> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_21> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_22> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_23> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_24> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_25> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_26> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_27> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_28> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_29> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_2A> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_2B> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_2C> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_2D> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_2E> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_2F> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_30> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_31> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_32> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_33> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_34> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_35> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_36> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_37> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_38> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_39> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_3A> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_3B> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_3C> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_3D> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_3E> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_3F> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
-
-=========================================================================
-*                            HDL Analysis                               *
-=========================================================================
-Analyzing Entity <Replay_Top> in library <work> (Architecture <rtl>).
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 300: Unconnected output port 'o_clk_sys' of component 'Replay_ClockGen'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 300: Unconnected output port 'o_rst_sys' of component 'Replay_ClockGen'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 444: Unconnected output port 'debug' of component 'Core_Top'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 534: Unconnected output port 'o_joy_a' of component 'Replay_JoyPS2'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 534: Unconnected output port 'o_joy_b' of component 'Replay_JoyPS2'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 611: Unconnected output port 'o_cfg_ready' of component 'Replay_DDRCtrl_Top'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 611: Unconnected output port 'o_cfg_present' of component 'Replay_DDRCtrl_Top'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 783: Unconnected output port 'o_fch_to_core' of component 'Replay_FileIO'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 783: Unconnected output port 'o_hch_to_core' of component 'Replay_FileIO'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 783: Unconnected output port 'o_mch_flush' of component 'Replay_FileIO'.
-Entity <Replay_Top> analyzed. Unit <Replay_Top> generated.
-
-Analyzing generic Entity <Replay_ClockGen> in library <work> (Architecture <RTL>).
-	G_DIVIDER = 11
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <u_clk_a_ibufg> in unit <Replay_ClockGen>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <u_clk_a_ibufg> in unit <Replay_ClockGen>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <u_clk_a_ibufg> in unit <Replay_ClockGen>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <u_clk_a_ibufg> in unit <Replay_ClockGen>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <u_clk_b_ibufg> in unit <Replay_ClockGen>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <u_clk_b_ibufg> in unit <Replay_ClockGen>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <u_clk_b_ibufg> in unit <Replay_ClockGen>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <u_clk_b_ibufg> in unit <Replay_ClockGen>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <u_clk_c_ibufg> in unit <Replay_ClockGen>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <u_clk_c_ibufg> in unit <Replay_ClockGen>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <u_clk_c_ibufg> in unit <Replay_ClockGen>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <u_clk_c_ibufg> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKDV_DIVIDE =  4.0000000000000000" for instance <u_a_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKFX_DIVIDE =  1" for instance <u_a_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <u_a_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <u_a_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKIN_PERIOD =  10.0000000000000000" for instance <u_a_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <u_a_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLK_FEEDBACK =  1X" for instance <u_a_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <u_a_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <u_a_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <u_a_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DSS_MODE =  NONE" for instance <u_a_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <u_a_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "FACTORY_JF =  C080" for instance <u_a_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "PHASE_SHIFT =  0" for instance <u_a_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <u_a_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKDV_DIVIDE =  2.0000000000000000" for instance <u_b_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKFX_DIVIDE =  1" for instance <u_b_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <u_b_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <u_b_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKIN_PERIOD =  10.0000000000000000" for instance <u_b_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <u_b_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLK_FEEDBACK =  1X" for instance <u_b_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <u_b_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <u_b_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <u_b_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DSS_MODE =  NONE" for instance <u_b_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <u_b_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "FACTORY_JF =  C080" for instance <u_b_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "PHASE_SHIFT =  0" for instance <u_b_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <u_b_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKDV_DIVIDE =  2.0000000000000000" for instance <u_c_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKFX_DIVIDE =  1" for instance <u_c_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <u_c_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <u_c_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKIN_PERIOD =  10.0000000000000000" for instance <u_c_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <u_c_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLK_FEEDBACK =  1X" for instance <u_c_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <u_c_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <u_c_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <u_c_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DSS_MODE =  NONE" for instance <u_c_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <u_c_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "FACTORY_JF =  C080" for instance <u_c_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "PHASE_SHIFT =  0" for instance <u_c_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <u_c_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKDV_DIVIDE =  2.0000000000000000" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKFX_DIVIDE =  1" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKIN_PERIOD =  10.0000000000000000" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLKOUT_PHASE_SHIFT =  VARIABLE" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "CLK_FEEDBACK =  1X" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DSS_MODE =  NONE" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "FACTORY_JF =  C080" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "PHASE_SHIFT =  0" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
-    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
-Entity <Replay_ClockGen> analyzed. Unit <Replay_ClockGen> generated.
-
-Analyzing Entity <Replay_ResetGen> in library <work> (Architecture <RTL>).
-Entity <Replay_ResetGen> analyzed. Unit <Replay_ResetGen> generated.
-
-Analyzing Entity <Core_Top> in library <work> (Architecture <RTL>).
-WARNING:Xst:819 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Core_Top.vhd" line 440: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
-   <hp_rdata>
-Entity <Core_Top> analyzed. Unit <Core_Top> generated.
-
-Analyzing Entity <atari800core> in library <work> (Architecture <bdf_type>).
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 716: Unconnected output port 'dma_clock_out' of component 'antic'.
-WARNING:Xst:754 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 788: Unconnected inout port 'SIO_CLOCK' of component 'pokey'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 788: Unconnected output port 'IRQ_N_OUT' of component 'pokey'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 788: Unconnected output port 'SIO_OUT1' of component 'pokey'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 788: Unconnected output port 'SIO_OUT2' of component 'pokey'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 788: Unconnected output port 'SIO_OUT3' of component 'pokey'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 788: Unconnected output port 'POT_RESET' of component 'pokey'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 788: Unconnected output port 'keyboard_scan' of component 'pokey'.
-WARNING:Xst:754 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 1076: Unconnected inout port 'SIO_CLOCK' of component 'pokey'.
-WARNING:Xst:819 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 1120: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
-   <KEYBOARD_SCAN>
-Entity <atari800core> analyzed. Unit <atari800core> generated.
-
-Analyzing Entity <cpu> in library <work> (Architecture <vhdl>).
-WARNING:Xst:752 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/cpu.vhd" line 89: Unconnected input port 'so_n' of component 'cpu_65xx' is tied to default value.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/cpu.vhd" line 89: Unconnected output port 'debug_flags' of component 'cpu_65xx'.
-Entity <cpu> analyzed. Unit <cpu> generated.
-
-Analyzing generic Entity <cpu_65xx> in library <work> (Architecture <rtl>).
-	pipelineAluMux = false
-	pipelineAluOut = false
-	pipelineOpcode = false
-Entity <cpu_65xx> analyzed. Unit <cpu_65xx> generated.
-
-Analyzing Entity <antic> in library <work> (Architecture <vhdl>).
-Entity <antic> analyzed. Unit <antic> generated.
-
-Analyzing generic Entity <antic_counter.1> in library <work> (Architecture <vhdl>).
-	COUNT_WIDTH = 12
-	STORE_WIDTH = 16
-Entity <antic_counter.1> analyzed. Unit <antic_counter.1> generated.
-
-Analyzing generic Entity <antic_counter.2> in library <work> (Architecture <vhdl>).
-	COUNT_WIDTH = 10
-	STORE_WIDTH = 16
-Entity <antic_counter.2> analyzed. Unit <antic_counter.2> generated.
-
-Analyzing generic Entity <simple_counter.1> in library <work> (Architecture <vhdl>).
-	COUNT_WIDTH = 8
-Entity <simple_counter.1> analyzed. Unit <simple_counter.1> generated.
-
-Analyzing generic Entity <simple_counter.2> in library <work> (Architecture <vhdl>).
-	COUNT_WIDTH = 4
-Entity <simple_counter.2> analyzed. Unit <simple_counter.2> generated.
-
-Analyzing generic Entity <wide_delay_line.1> in library <work> (Architecture <vhdl>).
-	COUNT = 16
-	WIDTH = 2
-Entity <wide_delay_line.1> analyzed. Unit <wide_delay_line.1> generated.
-
-Analyzing Entity <antic_dma_clock> in library <work> (Architecture <vhdl>).
-Entity <antic_dma_clock> analyzed. Unit <antic_dma_clock> generated.
-
-Analyzing generic Entity <reg_file.3> in library <work> (Architecture <vhdl>).
-	BYTES = 48
-	WIDTH = 6
-Entity <reg_file.3> analyzed. Unit <reg_file.3> generated.
-
-Analyzing generic Entity <complete_address_decoder.5> in library <work> (Architecture <tree>).
-	width = 6
-Entity <complete_address_decoder.5> analyzed. Unit <complete_address_decoder.5> generated.
-
-Analyzing generic Entity <wide_delay_line.2> in library <work> (Architecture <vhdl>).
-	COUNT = 16
-	WIDTH = 4
-Entity <wide_delay_line.2> analyzed. Unit <wide_delay_line.2> generated.
-
-Analyzing generic Entity <wide_delay_line.3> in library <work> (Architecture <vhdl>).
-	COUNT = 32
-	WIDTH = 7
-Entity <wide_delay_line.3> analyzed. Unit <wide_delay_line.3> generated.
-
-Analyzing generic Entity <complete_address_decoder.2> in library <work> (Architecture <tree>).
-	width = 4
-Entity <complete_address_decoder.2> analyzed. Unit <complete_address_decoder.2> generated.
-
-Analyzing generic Entity <delay_line.1> in library <work> (Architecture <vhdl>).
-	COUNT = 24
-Entity <delay_line.1> analyzed. Unit <delay_line.1> generated.
-
-Analyzing Entity <pokey_mixer> in library <work> (Architecture <vhdl>).
-Entity <pokey_mixer> analyzed. Unit <pokey_mixer> generated.
-
-Analyzing Entity <zpu_glue> in library <work> (Architecture <sticky>).
-WARNING:Xst:819 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_glue.vhdl" line 208: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
-   <special_mem>
-Entity <zpu_glue> analyzed. Unit <zpu_glue> generated.
-
-Analyzing generic Entity <ZPUMediumCore> in library <work> (Architecture <behave>).
-	ADDR_W = 24
-	BINOP_PIPE = 0
-	D_CARE_VAL = 'D'
-	ENA_IDLE = false
-	ENA_LEVEL0 = true
-	ENA_LEVEL1 = true
-	ENA_LEVEL2 = true
-	ENA_LSHR = true
-	FAST_FETCH = true
-	MEM_W = 16
-	MULT_PIPE = false
-	WORD_SIZE = 32
-INFO:Xst:1749 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_core.vhd" line 339: report: read/write collision
-INFO:Xst:1749 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_core.vhd" line 857: report: Illegal decode instruction?!
-INFO:Xst:1749 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_core.vhd" line 954: report: Illegal state?!
-INFO:Xst:2679 - Register <short_write_r> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <mult_a_r> in unit <ZPUMediumCore> has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <mult_b_r> in unit <ZPUMediumCore> has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dbg_o.sp<31>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dbg_o.sp<30>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dbg_o.sp<29>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dbg_o.sp<28>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dbg_o.sp<27>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dbg_o.sp<26>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dbg_o.sp<25>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dbg_o.sp<24>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dbg_o.sp<1>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <dbg_o.sp<0>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <insns<0>> in unit <ZPUMediumCore> has a constant value of 100101 during circuit operation. The register is replaced by logic.
-Entity <ZPUMediumCore> analyzed. Unit <ZPUMediumCore> generated.
-
-Analyzing Entity <pokey> in library <work> (Architecture <vhdl>).
-Entity <pokey> analyzed. Unit <pokey> generated.
-
-Analyzing generic Entity <pokey_countdown_timer> in library <work> (Architecture <vhdl>).
-	UNDERFLOW_DELAY = 3
-Entity <pokey_countdown_timer> analyzed. Unit <pokey_countdown_timer> generated.
-
-Analyzing generic Entity <delay_line.2> in library <work> (Architecture <vhdl>).
-	COUNT = 3
-Entity <delay_line.2> analyzed. Unit <delay_line.2> generated.
-
-Analyzing Entity <pokey_noise_filter> in library <work> (Architecture <vhdl>).
-Entity <pokey_noise_filter> analyzed. Unit <pokey_noise_filter> generated.
-
-Analyzing generic Entity <syncreset_enable_divider.1> in library <work> (Architecture <vhdl>).
-	COUNT = 28
-	RESETCOUNT = 6
-Entity <syncreset_enable_divider.1> analyzed. Unit <syncreset_enable_divider.1> generated.
-
-Analyzing generic Entity <syncreset_enable_divider.2> in library <work> (Architecture <vhdl>).
-	COUNT = 114
-	RESETCOUNT = 33
-Entity <syncreset_enable_divider.2> analyzed. Unit <syncreset_enable_divider.2> generated.
-
-Analyzing Entity <poly_17_9> in library <work> (Architecture <vhdl>).
-Entity <poly_17_9> analyzed. Unit <poly_17_9> generated.
-
-Analyzing Entity <poly_5> in library <work> (Architecture <vhdl>).
-Entity <poly_5> analyzed. Unit <poly_5> generated.
-
-Analyzing Entity <poly_4> in library <work> (Architecture <vhdl>).
-Entity <poly_4> analyzed. Unit <poly_4> generated.
-
-Analyzing generic Entity <delay_line.3> in library <work> (Architecture <vhdl>).
-	COUNT = 2
-Entity <delay_line.3> analyzed. Unit <delay_line.3> generated.
-
-Analyzing Entity <synchronizer> in library <work> (Architecture <vhdl>).
-Entity <synchronizer> analyzed. Unit <synchronizer> generated.
-
-Analyzing Entity <pokey_keyboard_scanner> in library <work> (Architecture <vhdl>).
-INFO:Xst:1561 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pokey_keyboard_scanner.vhdl" line 151: Mux is complete : default of case is discarded
-Entity <pokey_keyboard_scanner> analyzed. Unit <pokey_keyboard_scanner> generated.
-
-Analyzing Entity <pia> in library <work> (Architecture <vhdl>).
-Entity <pia> analyzed. Unit <pia> generated.
-
-Analyzing generic Entity <complete_address_decoder.3> in library <work> (Architecture <tree>).
-	width = 2
-Entity <complete_address_decoder.3> analyzed. Unit <complete_address_decoder.3> generated.
-
-Analyzing Entity <shared_enable> in library <work> (Architecture <vhdl>).
-Entity <shared_enable> analyzed. Unit <shared_enable> generated.
-
-Analyzing generic Entity <enable_divider.1> in library <work> (Architecture <vhdl>).
-	COUNT = 2
-Entity <enable_divider.1> analyzed. Unit <enable_divider.1> generated.
-
-Analyzing generic Entity <enable_divider.2> in library <work> (Architecture <vhdl>).
-	COUNT = 16
-Entity <enable_divider.2> analyzed. Unit <enable_divider.2> generated.
-
-Analyzing generic Entity <delay_line.4> in library <work> (Architecture <vhdl>).
-	COUNT = 15
-Entity <delay_line.4> analyzed. Unit <delay_line.4> generated.
-
-Analyzing generic Entity <delay_line.5> in library <work> (Architecture <vhdl>).
-	COUNT = 8
-Entity <delay_line.5> analyzed. Unit <delay_line.5> generated.
-
-Analyzing Entity <address_decoder> in library <work> (Architecture <vhdl>).
-Entity <address_decoder> analyzed. Unit <address_decoder> generated.
-
-Analyzing Entity <zpu_rom> in library <work> (Architecture <syn>).
-Entity <zpu_rom> analyzed. Unit <zpu_rom> generated.
-
-Analyzing generic Entity <generic_ram_infer.1> in library <work> (Architecture <rtl>).
-	ADDRESS_WIDTH = 10
-	DATA_WIDTH = 8
-	SPACE = 1024
-Entity <generic_ram_infer.1> analyzed. Unit <generic_ram_infer.1> generated.
-
-Analyzing Entity <zpu_config_regs> in library <work> (Architecture <vhdl>).
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected output port 'keyboard_scan' of component 'pokey'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected output port 'CHANNEL_0_OUT' of component 'pokey'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected output port 'CHANNEL_1_OUT' of component 'pokey'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected output port 'CHANNEL_2_OUT' of component 'pokey'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected output port 'CHANNEL_3_OUT' of component 'pokey'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected output port 'IRQ_N_OUT' of component 'pokey'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected output port 'SIO_OUT2' of component 'pokey'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected output port 'SIO_OUT3' of component 'pokey'.
-WARNING:Xst:754 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected inout port 'SIO_CLOCK' of component 'pokey'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected output port 'POT_RESET' of component 'pokey'.
-Entity <zpu_config_regs> analyzed. Unit <zpu_config_regs> generated.
-
-Analyzing generic Entity <complete_address_decoder.1> in library <work> (Architecture <tree>).
-	width = 3
-Entity <complete_address_decoder.1> analyzed. Unit <complete_address_decoder.1> generated.
-
-Analyzing Entity <gtia> in library <work> (Architecture <vhdl>).
-Entity <gtia> analyzed. Unit <gtia> generated.
-
-Analyzing generic Entity <complete_address_decoder.4> in library <work> (Architecture <tree>).
-	width = 5
-Entity <complete_address_decoder.4> analyzed. Unit <complete_address_decoder.4> generated.
-
-Analyzing Entity <gtia_player> in library <work> (Architecture <vhdl>).
-Entity <gtia_player> analyzed. Unit <gtia_player> generated.
-
-Analyzing Entity <gtia_priority> in library <work> (Architecture <vhdl>).
-Entity <gtia_priority> analyzed. Unit <gtia_priority> generated.
-
-Analyzing generic Entity <wide_delay_line.4> in library <work> (Architecture <vhdl>).
-	COUNT = 2
-	WIDTH = 6
-Entity <wide_delay_line.4> analyzed. Unit <wide_delay_line.4> generated.
-
-Analyzing generic Entity <wide_delay_line.5> in library <work> (Architecture <vhdl>).
-	COUNT = 3
-	WIDTH = 2
-Entity <wide_delay_line.5> analyzed. Unit <wide_delay_line.5> generated.
-
-Analyzing generic Entity <wide_delay_line.6> in library <work> (Architecture <vhdl>).
-	COUNT = 4
-	WIDTH = 2
-Entity <wide_delay_line.6> analyzed. Unit <wide_delay_line.6> generated.
-
-Analyzing generic Entity <wide_delay_line.7> in library <work> (Architecture <vhdl>).
-	COUNT = 2
-	WIDTH = 7
-Entity <wide_delay_line.7> analyzed. Unit <wide_delay_line.7> generated.
-
-Analyzing generic Entity <wide_delay_line.8> in library <work> (Architecture <vhdl>).
-	COUNT = 5
-	WIDTH = 8
-Entity <wide_delay_line.8> analyzed. Unit <wide_delay_line.8> generated.
-
-Analyzing generic Entity <wide_delay_line.9> in library <work> (Architecture <vhdl>).
-	COUNT = 4
-	WIDTH = 8
-Entity <wide_delay_line.9> analyzed. Unit <wide_delay_line.9> generated.
-
-Analyzing Entity <gtia_palette> in library <work> (Architecture <altirra>).
-Entity <gtia_palette> analyzed. Unit <gtia_palette> generated.
-
-Analyzing Entity <irq_glue> in library <work> (Architecture <vhdl>).
-Entity <irq_glue> analyzed. Unit <irq_glue> generated.
-
-Analyzing generic Entity <reg_file.1> in library <work> (Architecture <vhdl>).
-	BYTES = 16
-	WIDTH = 4
-Entity <reg_file.1> analyzed. Unit <reg_file.1> generated.
-
-Analyzing generic Entity <reg_file.2> in library <work> (Architecture <vhdl>).
-	BYTES = 32
-	WIDTH = 5
-Entity <reg_file.2> analyzed. Unit <reg_file.2> generated.
-
-Analyzing Entity <internalromram> in library <work> (Architecture <vhdl>).
-Entity <internalromram> analyzed. Unit <internalromram> generated.
-
-Analyzing Entity <basic> in library <work> (Architecture <syn>).
-Entity <basic> analyzed. Unit <basic> generated.
-
-Analyzing Entity <os16> in library <work> (Architecture <syn>).
-Entity <os16> analyzed. Unit <os16> generated.
-
-Analyzing generic Entity <generic_ram_infer.2> in library <work> (Architecture <rtl>).
-	ADDRESS_WIDTH = 14
-	DATA_WIDTH = 8
-	SPACE = 16384
-Entity <generic_ram_infer.2> analyzed. Unit <generic_ram_infer.2> generated.
-
-Analyzing Entity <covox> in library <work> (Architecture <vhdl>).
-Entity <covox> analyzed. Unit <covox> generated.
-
-Analyzing generic Entity <Replay_TranslatePS2> in library <work> (Architecture <RTL>).
-	g_kb_map = ("11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01100111",
-	            "11111111",
-	            "01010111",
-	            "11111111",
-	            "01000111",
-	            "11111111",
-	            "01000110",
-	            "01000000",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01000110",
-	            "01110111",
-	            "01000110",
-	            "01100000",
-	            "01000110",
-	            "01010111",
-	            "00110000",
-	            "11111111",
-	            "00000110",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "00110001",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "00100000",
-	            "11111111",
-	            "01100000",
-	            "11111111",
-	            "00000000",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01000001",
-	            "11111111",
-	            "01010001",
-	            "11111111",
-	            "00100001",
-	            "11111111",
-	            "00010001",
-	            "11111111",
-	            "01110000",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01000010",
-	            "11111111",
-	            "00110010",
-	            "11111111",
-	            "00100010",
-	            "11111111",
-	            "01100001",
-	            "11111111",
-	            "01110001",
-	            "11111111",
-	            "00000001",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01000000",
-	            "11111111",
-	            "00110011",
-	            "11111111",
-	            "01010010",
-	            "11111111",
-	            "01100010",
-	            "11111111",
-	            "00010010",
-	            "11111111",
-	            "00000010",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "00110100",
-	            "11111111",
-	            "01000011",
-	            "11111111",
-	            "01010011",
-	            "11111111",
-	            "00100011",
-	            "11111111",
-	            "00010011",
-	            "11111111",
-	            "01110010",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01000100",
-	            "11111111",
-	            "00100100",
-	            "11111111",
-	            "01100011",
-	            "11111111",
-	            "00000011",
-	            "11111111",
-	            "01110011",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "00110101",
-	            "11111111",
-	            "01010100",
-	            "11111111",
-	            "00010100",
-	            "11111111",
-	            "01100100",
-	            "11111111",
-	            "01110100",
-	            "11111111",
-	            "00000100",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01000101",
-	            "11111111",
-	            "00110110",
-	            "11111111",
-	            "00100101",
-	            "11111111",
-	            "00100110",
-	            "11111111",
-	            "00010101",
-	            "11111111",
-	            "00000101",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01010101",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01100101",
-	            "11111111",
-	            "01110101",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11000000",
-	            "11111111",
-	            "01000110",
-	            "11111111",
-	            "00010111",
-	            "11111111",
-	            "00010110",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01100110",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "00000111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "10000100",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "10000010",
-	            "11111111",
-	            "10010000",
-	            "11111111",
-	            "10001000",
-	            "11111111",
-	            "10000001",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01110111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "00100000",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01010000",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01010000",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "00000111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01000110",
-	            "00100111",
-	            "01110110",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "00110111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "00100111",
-	            "11111111",
-	            "01000110",
-	            "00110111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "01010110",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "10100000",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111",
-	            "11111111")
-Entity <Replay_TranslatePS2> analyzed. Unit <Replay_TranslatePS2> generated.
-
-Analyzing generic Entity <Replay_VideoConverter> in library <work> (Architecture <RTL>).
-	g_b_bitwidth = 8
-	g_g_bitwidth = 8
-	g_hadr_width = 9
-	g_hoffset = 0
-	g_hscale = "010000000"
-	g_hsize = 900
-	g_loffset = 0
-	g_match_line = 0
-	g_r_bitwidth = 8
-	g_vadr_width = 2
-	g_vid_param_hd = (rep_h => '0'
-	                  total_h => 864
-	                  active_h => 720
-	                  syncp_h => 12
-	                  syncw_h => 64
-	                  total_v => 625
-	                  active_v => 576
-	                  fline_f1_v => 44
-	                  lline_f1_v => 620
-	                  fline_f2_v => 0
-	                  lline_f2_v => 0
-	                  start_f1_v => 625
-	                  start_f2_v => 0
-	                  fsync_f1_v => 625
-	                  lsync_f1_v => 5
-	                  fsync_f2_v => 0
-	                  lsync_f2_v => 0
-	                  syncpol_h => '0'
-	                  syncpol_v => '0'
-	                  progressive => '1')
-	g_vid_param_sd = (rep_h => '1'
-	                  total_h => 1728
-	                  active_h => 1440
-	                  syncp_h => 24
-	                  syncw_h => 126
-	                  total_v => 625
-	                  active_v => 576
-	                  fline_f1_v => 22
-	                  lline_f1_v => 310
-	                  fline_f2_v => 335
-	                  lline_f2_v => 623
-	                  start_f1_v => 623
-	                  start_f2_v => 310
-	                  fsync_f1_v => 625
-	                  lsync_f1_v => 3
-	                  fsync_f2_v => 312
-	                  lsync_f2_v => 315
-	                  syncpol_h => '0'
-	                  syncpol_v => '0'
-	                  progressive => '0')
-	g_voffset = 21
-	g_vres_half = 1
-	g_vsize = 248
-WARNING:Xst:752 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_VideoConverter.vhd" line 392: Unconnected input port 'i_f2_flip' of component 'Replay_VideoTiming' is tied to default value.
-Entity <Replay_VideoConverter> analyzed. Unit <Replay_VideoConverter> generated.
-
-Analyzing generic Entity <Replay_VideoTiming> in library <work> (Architecture <RTL>).
-	g_enabledynamic = '1'
-	g_param = (rep_h => '0'
-	           total_h => 800
-	           active_h => 640
-	           syncp_h => 16
-	           syncw_h => 96
-	           total_v => 525
-	           active_v => 480
-	           fline_f1_v => 42
-	           lline_f1_v => 522
-	           fline_f2_v => 0
-	           lline_f2_v => 0
-	           start_f1_v => 525
-	           start_f2_v => 0
-	           fsync_f1_v => 7
-	           lsync_f1_v => 9
-	           fsync_f2_v => 0
-	           lsync_f2_v => 0
-	           syncpol_h => '0'
-	           syncpol_v => '0'
-	           progressive => '1')
-Entity <Replay_VideoTiming> analyzed. Unit <Replay_VideoTiming> generated.
-
-Analyzing Entity <Replay_JoyPS2> in library <work> (Architecture <RTL>).
-Entity <Replay_JoyPS2> analyzed. Unit <Replay_JoyPS2> generated.
-
-Analyzing generic Entity <Replay_JoyPS2_Core.1> in library <work> (Architecture <RTL>).
-	g_id = '0'
-Entity <Replay_JoyPS2_Core.1> analyzed. Unit <Replay_JoyPS2_Core.1> generated.
-
-Analyzing Entity <kcpsm3> in library <work> (Architecture <low_level_definition>).
-    Set user-defined property "INIT =  1" for instance <t_state_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <toggle_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  1" for instance <reset_flop1> in unit <kcpsm3>.
-    Set user-defined property "INIT =  1" for instance <reset_flop2> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <int_capture_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0080" for instance <int_pulse_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <int_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <ack_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <shadow_carry_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <shadow_zero_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  EAAA" for instance <int_update_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  04" for instance <int_value_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <int_enable_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  7400" for instance <move_group_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  5A3C" for instance <condition_met_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  2F" for instance <normal_count_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  1000" for instance <call_type_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  5400" for instance <push_pop_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  D" for instance <valid_move_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  41FC" for instance <flag_type_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <flag_write_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  8" for instance <flag_enable_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0001" for instance <low_zero_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0001" for instance <high_zero_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  3F" for instance <sel_shadow_zero_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <zero_flag_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  6996" for instance <low_parity_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  6996" for instance <high_parity_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  F3FF" for instance <sel_parity_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  F3" for instance <sel_arith_carry_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  C" for instance <sel_shift_carry_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  3" for instance <sel_shadow_carry_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <carry_flag_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[0].vector_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[0].value_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <pc_loop[0].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[1].vector_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[1].value_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <pc_loop[1].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[2].vector_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[2].value_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <pc_loop[2].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[3].vector_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[3].value_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <pc_loop[3].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[4].vector_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[4].value_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <pc_loop[4].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[5].vector_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[5].value_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <pc_loop[5].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[6].vector_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[6].value_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <pc_loop[6].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[7].vector_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[7].value_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <pc_loop[7].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[8].vector_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[8].value_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <pc_loop[8].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[9].vector_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <pc_loop[9].value_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <pc_loop[9].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0145" for instance <register_type_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <register_write_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  8" for instance <register_enable_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0000" for instance <reg_loop[0].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <reg_loop[0].operand_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0000" for instance <reg_loop[1].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <reg_loop[1].operand_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0000" for instance <reg_loop[2].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <reg_loop[2].operand_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0000" for instance <reg_loop[3].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <reg_loop[3].operand_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0000" for instance <reg_loop[4].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <reg_loop[4].operand_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0000" for instance <reg_loop[5].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <reg_loop[5].operand_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0000" for instance <reg_loop[6].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <reg_loop[6].operand_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0000" for instance <reg_loop[7].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <reg_loop[7].operand_select_mux> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0400" for instance <memory_type_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <memory_write_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  8000" for instance <memory_enable_lut> in unit <kcpsm3>.
-WARNING:Xst:1962 - The length of the hex value for the attribute INIT on instance store_loop[0].memory_bit should be 32 bits long. The current value set is 16 bits long.  Value has been extended
-    Set user-defined property "INIT =  00000000" for instance <store_loop[0].memory_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <store_loop[0].store_flop> in unit <kcpsm3>.
-WARNING:Xst:1962 - The length of the hex value for the attribute INIT on instance store_loop[1].memory_bit should be 32 bits long. The current value set is 16 bits long.  Value has been extended
-    Set user-defined property "INIT =  00000000" for instance <store_loop[1].memory_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <store_loop[1].store_flop> in unit <kcpsm3>.
-WARNING:Xst:1962 - The length of the hex value for the attribute INIT on instance store_loop[2].memory_bit should be 32 bits long. The current value set is 16 bits long.  Value has been extended
-    Set user-defined property "INIT =  00000000" for instance <store_loop[2].memory_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <store_loop[2].store_flop> in unit <kcpsm3>.
-WARNING:Xst:1962 - The length of the hex value for the attribute INIT on instance store_loop[3].memory_bit should be 32 bits long. The current value set is 16 bits long.  Value has been extended
-    Set user-defined property "INIT =  00000000" for instance <store_loop[3].memory_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <store_loop[3].store_flop> in unit <kcpsm3>.
-WARNING:Xst:1962 - The length of the hex value for the attribute INIT on instance store_loop[4].memory_bit should be 32 bits long. The current value set is 16 bits long.  Value has been extended
-    Set user-defined property "INIT =  00000000" for instance <store_loop[4].memory_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <store_loop[4].store_flop> in unit <kcpsm3>.
-WARNING:Xst:1962 - The length of the hex value for the attribute INIT on instance store_loop[5].memory_bit should be 32 bits long. The current value set is 16 bits long.  Value has been extended
-    Set user-defined property "INIT =  00000000" for instance <store_loop[5].memory_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <store_loop[5].store_flop> in unit <kcpsm3>.
-WARNING:Xst:1962 - The length of the hex value for the attribute INIT on instance store_loop[6].memory_bit should be 32 bits long. The current value set is 16 bits long.  Value has been extended
-    Set user-defined property "INIT =  00000000" for instance <store_loop[6].memory_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <store_loop[6].store_flop> in unit <kcpsm3>.
-WARNING:Xst:1962 - The length of the hex value for the attribute INIT on instance store_loop[7].memory_bit should be 32 bits long. The current value set is 16 bits long.  Value has been extended
-    Set user-defined property "INIT =  00000000" for instance <store_loop[7].memory_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <store_loop[7].store_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  FFE2" for instance <sel_logical_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  6E8A" for instance <logical_loop[0].logical_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <logical_loop[0].logical_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  6E8A" for instance <logical_loop[1].logical_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <logical_loop[1].logical_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  6E8A" for instance <logical_loop[2].logical_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <logical_loop[2].logical_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  6E8A" for instance <logical_loop[3].logical_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <logical_loop[3].logical_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  6E8A" for instance <logical_loop[4].logical_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <logical_loop[4].logical_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  6E8A" for instance <logical_loop[5].logical_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <logical_loop[5].logical_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  6E8A" for instance <logical_loop[6].logical_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <logical_loop[6].logical_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  6E8A" for instance <logical_loop[7].logical_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <logical_loop[7].logical_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <high_shift_in_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <low_shift_in_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <shift_carry_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <pipeline_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <shift_loop[0].lsb_shift.shift_mux_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <shift_loop[0].shift_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <shift_loop[1].mid_shift.shift_mux_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <shift_loop[1].shift_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <shift_loop[2].mid_shift.shift_mux_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <shift_loop[2].shift_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <shift_loop[3].mid_shift.shift_mux_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <shift_loop[3].shift_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <shift_loop[4].mid_shift.shift_mux_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <shift_loop[4].shift_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <shift_loop[5].mid_shift.shift_mux_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <shift_loop[5].shift_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <shift_loop[6].mid_shift.shift_mux_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <shift_loop[6].shift_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <shift_loop[7].msb_shift.shift_mux_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <shift_loop[7].shift_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  1F" for instance <sel_arith_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  6C" for instance <arith_loop[0].lsb_arith.arith_carry_in_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  96" for instance <arith_loop[0].arith_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <arith_loop[0].arith_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  96" for instance <arith_loop[1].arith_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <arith_loop[1].arith_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  96" for instance <arith_loop[2].arith_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <arith_loop[2].arith_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  96" for instance <arith_loop[3].arith_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <arith_loop[3].arith_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  96" for instance <arith_loop[4].arith_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <arith_loop[4].arith_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  96" for instance <arith_loop[5].arith_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <arith_loop[5].arith_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  96" for instance <arith_loop[6].arith_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <arith_loop[6].arith_flop> in unit <kcpsm3>.
-WARNING:Xst:1961 - The length of the hex value for the attribute INIT on instance arith_loop[7].msb_arith.arith_carry_out_lut should be 2 bits long. The current value set is 4 bits long.  Value has been truncated
-    Set user-defined property "INIT =  2" for instance <arith_loop[7].msb_arith.arith_carry_out_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <arith_loop[7].msb_arith.arith_carry_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  96" for instance <arith_loop[7].arith_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <arith_loop[7].arith_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0002" for instance <input_fetch_type_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <sel_group_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  FE" for instance <alu_mux_loop[0].or_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <alu_mux_loop[0].mux_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  FE" for instance <alu_mux_loop[1].or_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <alu_mux_loop[1].mux_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  FE" for instance <alu_mux_loop[2].or_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <alu_mux_loop[2].mux_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  FE" for instance <alu_mux_loop[3].or_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <alu_mux_loop[3].mux_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  FE" for instance <alu_mux_loop[4].or_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <alu_mux_loop[4].mux_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  FE" for instance <alu_mux_loop[5].or_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <alu_mux_loop[5].mux_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  FE" for instance <alu_mux_loop[6].or_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <alu_mux_loop[6].mux_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  FE" for instance <alu_mux_loop[7].or_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  E4" for instance <alu_mux_loop[7].mux_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0010" for instance <io_decode_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  4000" for instance <write_active_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <write_strobe_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0100" for instance <read_active_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <read_strobe_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[0].stack_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <stack_ram_loop[0].stack_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[1].stack_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <stack_ram_loop[1].stack_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[2].stack_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <stack_ram_loop[2].stack_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[3].stack_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <stack_ram_loop[3].stack_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[4].stack_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <stack_ram_loop[4].stack_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[5].stack_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <stack_ram_loop[5].stack_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[6].stack_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <stack_ram_loop[6].stack_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[7].stack_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <stack_ram_loop[7].stack_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[8].stack_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <stack_ram_loop[8].stack_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[9].stack_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <stack_ram_loop[9].stack_flop> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <stack_count_loop[0].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  6555" for instance <stack_count_loop[0].lsb_stack_count.count_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <stack_count_loop[1].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  A999" for instance <stack_count_loop[1].mid_stack_count.count_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <stack_count_loop[2].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  A999" for instance <stack_count_loop[2].mid_stack_count.count_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <stack_count_loop[3].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  A999" for instance <stack_count_loop[3].mid_stack_count.count_lut> in unit <kcpsm3>.
-    Set user-defined property "INIT =  0" for instance <stack_count_loop[4].register_bit> in unit <kcpsm3>.
-    Set user-defined property "INIT =  A999" for instance <stack_count_loop[4].msb_stack_count.count_lut> in unit <kcpsm3>.
-Entity <kcpsm3> analyzed. Unit <kcpsm3> generated.
-
-Analyzing generic Entity <Replay_JoyPS2_Core.2> in library <work> (Architecture <RTL>).
-	g_id = '1'
-Entity <Replay_JoyPS2_Core.2> analyzed. Unit <Replay_JoyPS2_Core.2> generated.
-
-Analyzing Entity <ps2_rom> in library <work> (Architecture <low_level_definition>).
-    Set user-defined property "INITP_00 =  E8F3CF3CF3CA3DDF0DDFC3CBCF2D34F4AA834F2B0F550C3F4DF8FC38D82AAAA3" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INITP_01 =  E0213FF8E38E2822A80222940D08A940D08A8A3774AD22377FB78844903C2F28" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INITP_02 =  37649AA08DAAAD2777748B72DCB4BC3B0B0BC2570E5C3F93F93F93A38FFE363F" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INITP_03 =  00000000000000000000000000000000000300D23554348A50D2AA8A214228DA" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INITP_07 =  C000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_00 =  5C0DC101F0100000011FC083C082C081C080C010C008C004C002C0010000C000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_01 =  4100610110A74101008B0052C002000101200114014200D00107C001C0040001" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_02 =  61096008C00058364380F310D200A32763076206C00161096008C000401B5022" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_03 =  000E000E000E000E000EA0E04001581B20026000009C00E70FF4E107E006C001" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_04 =  00E76F05009C00E70FEDE005505121104101505121084101401B144450106105" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_05 =  00F40101548740AA54584101008B0135012600100127009C00E70FFFA000009C" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_06 =  009C00E70F02009C00E70FE8C008E00000030098547F4000547F4101008B0142" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_07 =  0098A000E00F0000009C00E70FF4009C00E70F64009C00E70FF3009C00E70FE6" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_08 =  B00050206204600301004000014200F40101A000009C00E70F00C008E0000001" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_09 =  4101008B0135013EA00050984101008BA0000101E204A2078201701091200110" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_0A =  410150B64100610FA000C04058AC21026100A0000001A000000054A540FA549D" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_0B =  50C122100100620EE10F0102A000E00EE10F0101A000E10F010050C8410250BA" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_0C =  620C01FF50CF22200100620EE10F0100A000E30BE20AB3109200630B620A01FF" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_0D =  010601060106A10F610DA00F600BC081600CC080600AE30DE20CF310D200630D" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_0E =  014CC11001030151C11001020114C0020000A000C083A007600EC082D0100106" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_0F =  0114C110E101A101EF800F0811F02FFF0E080148011A014801140148C1100101" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_10 =  C201020101200114011A01140148C11001005CFCCE010F0811F00148011A0148" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_11 =  411B0135B00021084101013A41150135B40021084101013AA000C00200010148" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_12 =  61096008C000A000B5109400C00165096408C00041210135B40021104101013A" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_13 =  00F40101A000012600FA0100A0005C00012D13501240A0004380F310D200C001" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_14 =  554DC10101480114A0005549C001000BA0005943012D135012400126A0000126" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_15 =  410B5187410A51764109516C41006101C2010201A0005552C101014801C8A000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_16 =  E101010155752004A000E202020FA000E202020E556920046202E10181015192" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_17 =  020B5581220155822004020022FF6202E1018101A000A000E107E00661096008" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_18 =  6102E203A2078201932003106203E1010100A000F2F0020B51862201A000F2F0" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_19 =  A10080016109600851B120024001E31FE21EE11DE01CA000E1010100A000F130" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_1A =  010059B14380F310D200A30082FA6307620651B142006201C2010202E109E008" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_1B =  00000000000000000000000000008001601C611D621E631F155620014001E101" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_3F =  4195000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_A =  00000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "INIT_B =  00000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "SRVAL_A =  00000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "SRVAL_B =  00000" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <ram_1024_x_18> in unit <ps2_rom>.
-    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <ram_1024_x_18> in unit <ps2_rom>.
-Entity <ps2_rom> analyzed. Unit <ps2_rom> generated.
-
-Analyzing generic Entity <Replay_DDRCtrl_Top> in library <work> (Architecture <rtl>).
-	g_lp_big_endian = '1'
-INFO:Xst:2679 - Register <o_cfg_present> in unit <Replay_DDRCtrl_Top> has a constant value of 1 during circuit operation. The register is replaced by logic.
-Entity <Replay_DDRCtrl_Top> analyzed. Unit <Replay_DDRCtrl_Top> generated.
-
-Analyzing Entity <Replay_DDRCtrl> in library <work> (Architecture <rtl>).
-    Set user-defined property "INIT =  0" for instance <u_ack_reg> in unit <Replay_DDRCtrl>.
-Entity <Replay_DDRCtrl> analyzed. Unit <Replay_DDRCtrl> generated.
-
-Analyzing Entity <Replay_DDRCtrl_Datapath> in library <work> (Architecture <rtl>).
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[0].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[0].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[1].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[1].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[2].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[2].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[3].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[3].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[4].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[4].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[5].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[5].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[6].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[6].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[7].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[7].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[8].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[8].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[9].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[9].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[10].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[10].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[11].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[11].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[12].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[12].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[13].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[13].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[14].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[14].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[15].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[15].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <fdp_ram_ras_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <fdp_ram_cas_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <fdp_ram_we_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <fdp_ram_cs_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fdc_ram_cke> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <obuf_ras_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <obuf_ras_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <obuf_ras_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <obuf_ras_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <obuf_cas_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <obuf_cas_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <obuf_cas_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <obuf_cas_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <obuf_we_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <obuf_we_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <obuf_we_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <obuf_we_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <obuf_cs_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <obuf_cs_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <obuf_cs_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <obuf_cs_l> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <obuf_cke> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <obuf_cke> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <obuf_cke> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <obuf_cke> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fdcs_ram_ba[0].fdc_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_ba[0].obuf_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_ba[0].obuf_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_ba[0].obuf_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_ba[0].obuf_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fdcs_ram_ba[1].fdc_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_ba[1].obuf_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_ba[1].obuf_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_ba[1].obuf_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_ba[1].obuf_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[0].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[0].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[0].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[0].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[0].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[1].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[1].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[1].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[1].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[1].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[2].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[2].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[2].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[2].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[2].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[3].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[3].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[3].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[3].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[3].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[4].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[4].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[4].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[4].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[4].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[5].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[5].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[5].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[5].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[5].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[6].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[6].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[6].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[6].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[6].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[7].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[7].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[7].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[7].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[7].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[8].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[8].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[8].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[8].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[8].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[9].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[9].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[9].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[9].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[9].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[10].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[10].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[10].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[10].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[10].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[11].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[11].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[11].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[11].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[11].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[12].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[12].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[12].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[12].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[12].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <u_ck_p_oddr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <u_ck_p_oddr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <u_ck_p_oddr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <u_ck_n_oddr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <u_ck_n_oddr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <u_ck_n_oddr> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <obuf_ck_p> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <obuf_ck_p> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <obuf_ck_p> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <obuf_ck_p> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <obuf_ck_n> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <obuf_ck_n> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <obuf_ck_n> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <obuf_ck_n> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dm[0].oddr_dm> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dm[0].oddr_dm> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dm[0].oddr_dm> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dm[0].obuf_dm> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dm[0].obuf_dm> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dm[0].obuf_dm> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dm[0].obuf_dm> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dm[1].oddr_dm> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dm[1].oddr_dm> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dm[1].oddr_dm> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dm[1].obuf_dm> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dm[1].obuf_dm> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dm[1].obuf_dm> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dm[1].obuf_dm> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dqs_w[0].oddr_dqs_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dqs_w[0].oddr_dqs_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dqs_w[0].oddr_dqs_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dqs_w[0].oddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dqs_w[0].oddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dqs_w[0].oddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dqs_w[0].obuft_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dqs_w[0].obuft_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dqs_w[0].obuft_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dqs_w[0].obuft_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dqs_w[1].oddr_dqs_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dqs_w[1].oddr_dqs_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dqs_w[1].oddr_dqs_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dqs_w[1].oddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dqs_w[1].oddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dqs_w[1].oddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dqs_w[1].obuft_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dqs_w[1].obuft_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dqs_w[1].obuft_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dqs_w[1].obuft_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[0].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[0].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[0].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[0].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[0].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[0].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[0].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[0].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[0].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[0].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[1].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[1].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[1].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[1].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[1].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[1].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[1].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[1].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[1].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[1].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[2].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[2].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[2].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[2].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[2].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[2].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[2].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[2].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[2].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[2].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[3].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[3].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[3].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[3].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[3].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[3].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[3].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[3].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[3].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[3].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[4].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[4].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[4].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[4].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[4].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[4].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[4].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[4].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[4].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[4].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[5].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[5].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[5].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[5].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[5].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[5].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[5].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[5].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[5].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[5].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[6].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[6].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[6].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[6].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[6].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[6].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[6].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[6].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[6].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[6].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[7].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[7].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[7].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[7].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[7].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[7].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[7].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[7].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[7].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[7].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[8].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[8].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[8].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[8].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[8].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[8].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[8].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[8].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[8].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[8].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[9].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[9].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[9].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[9].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[9].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[9].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[9].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[9].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[9].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[9].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[10].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[10].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[10].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[10].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[10].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[10].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[10].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[10].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[10].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[10].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[11].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[11].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[11].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[11].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[11].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[11].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[11].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[11].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[11].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[11].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[12].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[12].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[12].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[12].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[12].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[12].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[12].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[12].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[12].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[12].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[13].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[13].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[13].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[13].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[13].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[13].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[13].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[13].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[13].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[13].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[14].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[14].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[14].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[14].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[14].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[14].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[14].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[14].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[14].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[14].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[15].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[15].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[15].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[15].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  1" for instance <gen_dq_w[15].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[15].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[15].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[15].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[15].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[15].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dqs_r[0].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dqs_r[0].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dqs_r[0].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dqs_r[0].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dqs_r[0].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dqs_r[0].iddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q0 =  1" for instance <gen_dqs_r[0].iddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q1 =  1" for instance <gen_dqs_r[0].iddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dqs_r[0].iddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dqs_r[1].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dqs_r[1].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dqs_r[1].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dqs_r[1].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dqs_r[1].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dqs_r[1].iddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q0 =  1" for instance <gen_dqs_r[1].iddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q1 =  1" for instance <gen_dqs_r[1].iddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dqs_r[1].iddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fd_dq_t1_ena_1> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "U_SET =  dram_mux" for instance <fd_dq_t1_ena_1> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "RLOC =  X0Y0" for instance <fd_dq_t1_ena_1> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fd_dq_t1_ena> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "U_SET =  dram_mux" for instance <fd_dq_t1_ena> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "RLOC =  X1Y0" for instance <fd_dq_t1_ena> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fd_dq_t2_ena_1> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "U_SET =  dram_mux" for instance <fd_dq_t2_ena_1> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "RLOC =  X0Y0" for instance <fd_dq_t2_ena_1> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fd_dq_t2_ena> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "U_SET =  dram_mux" for instance <fd_dq_t2_ena> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "RLOC =  X1Y0" for instance <fd_dq_t2_ena> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fd_sel0> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fd_sel1> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  F0CA" for instance <lut4_dq_mux1> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "U_SET =  dram_mux" for instance <lut4_dq_mux1> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "RLOC =  X2Y0" for instance <lut4_dq_mux1> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  F0CA" for instance <lut4_dq_mux2> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "U_SET =  dram_mux" for instance <lut4_dq_mux2> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "RLOC =  X2Y0" for instance <lut4_dq_mux2> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "U_SET =  dram_mux" for instance <muxf5_dq_mux> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "RLOC =  X2Y0" for instance <muxf5_dq_mux> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fd_dq_ena_cc> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "U_SET =  dram_mux" for instance <fd_dq_ena_cc> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "RLOC =  X2Y0" for instance <fd_dq_ena_cc> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[0].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[0].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[0].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[0].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[0].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[0].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[0].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[0].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[0].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[1].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[1].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[1].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[1].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[1].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[1].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[1].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[1].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[1].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[2].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[2].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[2].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[2].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[2].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[2].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[2].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[2].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[2].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[3].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[3].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[3].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[3].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[3].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[3].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[3].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[3].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[3].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[4].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[4].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[4].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[4].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[4].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[4].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[4].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[4].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[4].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[5].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[5].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[5].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[5].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[5].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[5].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[5].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[5].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[5].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[6].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[6].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[6].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[6].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[6].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[6].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[6].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[6].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[6].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[7].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[7].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[7].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[7].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[7].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[7].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[7].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[7].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[7].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[8].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[8].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[8].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[8].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[8].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[8].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[8].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[8].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[8].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[9].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[9].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[9].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[9].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[9].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[9].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[9].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[9].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[9].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[10].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[10].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[10].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[10].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[10].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[10].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[10].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[10].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[10].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[11].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[11].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[11].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[11].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[11].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[11].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[11].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[11].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[11].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[12].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[12].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[12].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[12].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[12].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[12].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[12].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[12].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[12].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[13].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[13].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[13].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[13].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[13].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[13].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[13].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[13].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[13].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[14].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[14].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[14].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[14].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[14].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[14].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[14].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[14].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[14].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[15].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[15].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[15].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[15].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[15].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[15].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[15].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[15].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[15].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fd_dq_we> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0" for instance <fd_dq_st> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[0].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[1].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[2].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[3].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[4].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[5].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[6].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[7].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[8].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[9].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[10].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[11].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[12].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[13].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[14].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[15].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[16].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[17].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[18].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[19].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[20].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[21].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[22].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[23].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[24].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[25].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[26].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[27].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[28].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[29].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[30].inst> in unit <Replay_DDRCtrl_Datapath>.
-    Set user-defined property "INIT =  0000" for instance <rbuf[31].inst> in unit <Replay_DDRCtrl_Datapath>.
-Entity <Replay_DDRCtrl_Datapath> analyzed. Unit <Replay_DDRCtrl_Datapath> generated.
-
-Analyzing generic Entity <Replay_Syscon> in library <work> (Architecture <RTL>).
-	g_cfg_ctrl = "0000000010000000"
-	g_cfg_dynamic = "00000000000000000000000000000000"
-	g_cfg_fileio = "00000000"
-	g_cfg_static = "00000000000000000000000000000000"
-	g_version = "0000000000000001"
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Syscon.vhd" line 235: Unconnected output port 'o_rxbytecnt' of component 'Replay_SPI8'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Syscon.vhd" line 235: Unconnected output port 'o_first' of component 'Replay_SPI8'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Syscon.vhd" line 317: Unconnected output port 'o_w_full' of component 'FIFO_SyncSRL_D16'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Syscon.vhd" line 317: Unconnected output port 'o_w_hfull' of component 'FIFO_SyncSRL_D16'.
-INFO:Xst:2679 - Register <osd_vexp> in unit <Replay_Syscon> has a constant value of 0 during circuit operation. The register is replaced by logic.
-Entity <Replay_Syscon> analyzed. Unit <Replay_Syscon> generated.
-
-Analyzing Entity <Replay_SPI8> in library <work> (Architecture <RTL>).
-Entity <Replay_SPI8> analyzed. Unit <Replay_SPI8> generated.
-
-Analyzing generic Entity <FIFO_SyncSRL_D16> in library <work> (Architecture <RTL>).
-	g_width = 8
-    Set user-defined property "INIT =  0000" for instance <ram[0].inst> in unit <FIFO_SyncSRL_D16>.
-    Set user-defined property "INIT =  0000" for instance <ram[1].inst> in unit <FIFO_SyncSRL_D16>.
-    Set user-defined property "INIT =  0000" for instance <ram[2].inst> in unit <FIFO_SyncSRL_D16>.
-    Set user-defined property "INIT =  0000" for instance <ram[3].inst> in unit <FIFO_SyncSRL_D16>.
-    Set user-defined property "INIT =  0000" for instance <ram[4].inst> in unit <FIFO_SyncSRL_D16>.
-    Set user-defined property "INIT =  0000" for instance <ram[5].inst> in unit <FIFO_SyncSRL_D16>.
-    Set user-defined property "INIT =  0000" for instance <ram[6].inst> in unit <FIFO_SyncSRL_D16>.
-    Set user-defined property "INIT =  0000" for instance <ram[7].inst> in unit <FIFO_SyncSRL_D16>.
-Entity <FIFO_SyncSRL_D16> analyzed. Unit <FIFO_SyncSRL_D16> generated.
-
-Analyzing Entity <Replay_OSD> in library <work> (Architecture <RTL>).
-    Set user-defined property "INIT =  0000" for instance <h_offset_ram_1[0].inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT =  0000" for instance <h_offset_ram_1[1].inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT =  0000" for instance <h_offset_ram_1[2].inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT =  0000" for instance <h_offset_ram_1[3].inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT =  0000" for instance <h_offset_ram_1[4].inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT =  0000" for instance <h_offset_ram_1[5].inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT =  0000" for instance <h_offset_ram_1[6].inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT =  0000" for instance <h_offset_ram_1[7].inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT =  0000" for instance <h_offset_ram_2[0].inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT =  0000" for instance <h_offset_ram_2[1].inst> in unit <Replay_OSD>.
-    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_13 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_14 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_15 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_16 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_17 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_A =  000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "INIT_B =  00000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "SRVAL_A =  000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "SRVAL_B =  00000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
-Entity <Replay_OSD> analyzed. Unit <Replay_OSD> generated.
-
-Analyzing Entity <FONT0> in library <work> (Architecture <RTL>).
-WARNING:Xst:2211 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/font0_rom.vhd" line 269: Instantiating black box module <RAMB16_S2>.
-    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_02 =  0000F0000000F4000000F8000000F8000000F8000000F8000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_03 =  0000000000000000000000000002F8000001F800000050000000B0000000B000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_04 =  0000000000000000002E03C0002E03C0003F0BC0003F0BE00000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_06 =  2FFFFFFE003C0F00003C0F000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_07 =  000000000000000000000000003C0F00003C0F002FFFFFFE003C0F00003C0F00" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_08 =  002FFE000000FFE00000F0FC03D0F03C02F0F0FC00BFFFF0000AFA000000F000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_09 =  000000000000F000000AFA0000BFFFF403F0F0BD03C0F02E03E0F00001FEF000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_0A =  0002F000000BC000002E2FF800F8FC3F03E0F00F0F80F82F2D002FF800000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_0B =  0000000000000000000000000FFF00383E0BC1F03E0BC7C00FFF1F000000BC00" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_0C =  00000FF00002FEF4000BC07C000F003C000F80FC0002FFE00000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_0D =  0000000000000000000000000B87FFF40BFE407E02FF400F0BCBF01F0F40BE7D" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_0E =  00000000000000000000F0000000F4000000F8000001F8000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_10 =  000003C0000007C000000F8000001F0000003D000001F400000BC000002E0000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_11 =  002E0000000BC0000001F40000003C0000001F0000000F80000007C0000003C0" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_12 =  003C0000003D0000002F0000000F40000003C0000001F40000003E0000000B80" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_13 =  00000B8000003E000001F4000003C000000F4000002F0000003D0000003C0000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_14 =  03F8B2FD0240B0080000F0000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_15 =  0000000000000000000000000000F0000240B00803F8B2FD001FFF80001FFF80" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_16 =  0000F0000000F0000000F0000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_17 =  0000000000000000000000000000F0000000F0000000F0000000F0000FFFFFFF" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_19 =  00000B8000001F0000003D000000FC000003F000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_1B =  000000000000000000000000000000000000000000000000000000000FFFFFFF" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_1D =  0000000000000000000000000002F8000002F800000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_1E =  0002F0000007C000000F0000003D000000F8000002E0000003C0000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_1F =  000000000000002D000000BC000001F0000003C000000F4000003D000000B800" for instance <rom0.inst> in unit <FONT0>.
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-    Set user-defined property "INIT_21 =  000000000000000000000000002FFF8001F801F807C0007D0F8003FF0F002E0F" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_22 =  0000F0000000F06F0000F3FE0000FF800000FC000000F4000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_23 =  000000000000000000000000003FFFC00000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_24 =  00BF000002F4000003D0000F03C0002F02F801BC002FFFE00000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_25 =  00000000000000000000000003FFFFFE03C002F803C01FD00280FE00000BE000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_26 =  003FF80001FA000003D0003C03C000BC02F802F4007FFF800000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_27 =  000000000000000000000000006FFF8002F802F003D000BC03C0002802F80000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_28 =  003C02F0003C0BC0003C2F00003CF800003FE000003F40000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_29 =  0000000000000000000000000FFFF000003C0000003C00000FFFFFFE003C007D" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_2A =  0FC000A003F80BF000BFFDF0000000F0000000F00FFFFFF00000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_2B =  000000000000000000000000006FFFD002F402FC0B80003E0F00002A0F000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_2C =  0FC0003F03F806EF007FFE2E0000007C02D007F001FFFE400000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_2D =  000000000000000000000000007FFF8003F401F80F80002D0F00000F0F00000F" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_2E =  0003C000000F4000002E000000B8003C07D0003C0BFFFFFC0000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_2F =  0000000000000000000000000000F0000000F0000002F0000002F0000003E000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_30 =  03F802FC00BFFFE002F802F803C0003C03F401FC00BFFFE00000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_31 =  00000000000000000000000000BFFFE007E401BD0F80002F0F00000F0F80002F" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_32 =  0FC0003F0F00000F0F00000F0780002F01F401FC002FFFD00000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_33 =  000000000000000000000000001BFFF800FD007803D000000B8BFFD00FB902FC" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_34 =  000000000000F0000000F0000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_35 =  0000000000000000000000000000F0000000F000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_36 =  000000000000F0000000F0000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_37 =  00000B4000001F0000007C000000F8000003F000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_38 =  00007E000002F000002F80000078000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_39 =  00000000000000000000000000780000002F80000002F00000007E0000000FC0" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_3A =  000000000FFFFFFF000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_3B =  00000000000000000000000000000000000000000FFFFFFF0000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_3C =  000BE0000000BD0000000F80000002E000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_3D =  000000000000000000000000000002E000000F800000BD00000BE000002F4000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_3E =  002F400000F8000003E0004003C002F003F00BD000BFFE000000000000000000" for instance <rom0.inst> in unit <FONT0>.
-    Set user-defined property "INIT_3F =  0000000000000000000000000000F0000000F0000000A0000001F0000007D000" for instance <rom0.inst> in unit <FONT0>.
-Entity <FONT0> analyzed. Unit <FONT0> generated.
-
-Analyzing Entity <FONT1> in library <work> (Architecture <RTL>).
-WARNING:Xst:2211 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/font1_rom.vhd" line 269: Instantiating black box module <RAMB16_S2>.
-    Set user-defined property "INIT_00 =  3CF40F0F3CF01F0F3EF83E2F1FFFF83D0BE002F400BFFF800000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_01 =  00000000000000000000000000BFFF4001E006F00000007C0FFBFC2E3EFD2F0F" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_02 =  02F00BC000F80F4000BC2E00003E7C00001FF800000BF0000000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_03 =  000000000000000000000000BC00003F3E00007C1F4000F80FFFFFF003E003E0" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_04 =  01F9003C003FFFFC02F8003C03C0003C03F8003C00BFFFFC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_05 =  000000000000000000000000002FFFFC01F9003C03E0003C03C0003C03E0003C" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_06 =  0000000F0000000F03C0002F03E0003D03FD02F803DFFF800000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_07 =  000000000000000000000000002FFF8000FD02F803F0003D0180002F0000000F" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_08 =  0F00003C0F00003C0F80003C07D0003C01F9003C002FFFFC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_09 =  000000000000000000000000002FFFFC02F9003C07D0003C0F80003C0F00003C" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_0A =  002FFFFC0000003C0000003C0000003C0000003C0BFFFFFC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_0B =  0000000000000000000000000BFFFFFC0000003C0000003C0000003C0000003C" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_0C =  002FFFFC0000003C0000003C0000003C0000003C0BFFFFFC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_0D =  0000000000000000000000000000003C0000003C0000003C0000003C0000003C" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_0E =  0FFF000F0000000F0F00002F0F80003D0FF402F40F7FFF800000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_0F =  000000000000000000000000002FFF8001F802F807C0003D0F80002F0F00000F" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_10 =  03FFFFFC03C0003C03C0003C03C0003C03C0003C03C0003C0000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_11 =  00000000000000000000000003C0003C03C0003C03C0003C03C0003C03C0003C" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_12 =  0000F0000000F0000000F0000000F0000000F000003FFFC00000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_13 =  000000000000000000000000003FFFC00000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_14 =  03C0000003C0000003C0000003C0000003C0000003C000000000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_15 =  000000000000000000000000002FFFE000F801BC03E0002F03C0000903C00000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_16 =  0000BFFC00007F3C0002F83C001FC03C00BE003C0BF0003C0000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_17 =  0000000000000000000000000BD0003C01F8003C003E003C000FC03C0002F0BC" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_18 =  0000003C0000003C0000003C0000003C0000003C0000003C0000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_19 =  0000000000000000000000000BFFFFFC0000003C0000003C0000003C0000003C" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_1A =  03C3FC3C03CBAE3C03DF0F7C03FD03FC03F802FC03F000FC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_1B =  00000000000000000000000003C0003C03C0003C03C0003C03C0F03C03C2F83C" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_1C =  03C2F03C03C0BC3C03C03F3C03C00FBC03C003FC03C001FC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_1D =  00000000000000000000000003F0003C03FC003C03FE003C03CF803C03C7D03C" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_1E =  0F00000F0F00000F0F80002F07C0003D01F802F4002FFF800000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_1F =  000000000000000000000000002FFF8001F802F807C0003D0F80002F0F00000F" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_20 =  00BFFFFC02F9003C03C0003C03C0003C02F8003C007FFFFC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_21 =  0000000000000000000000000000003C0000003C0000003C0000003C0000003C" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_22 =  0F00000F0F00000F0F80002F07C0003D01F802F4002FFF800000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_23 =  0BFF40000007E0000000F000002FFF8002F906F807D0007D0F80002F0F00000F" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_24 =  006FFFFC02F8003C03C0003C03C0003C02F8003C007FFFFC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_25 =  00000000000000000000000002F0003C00BC003C002F003C0007C03C0001F03C" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_26 =  001BFF8000000BFC0000002F03D0000F03F900BE03DFFFE00000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_27 =  000000000000000000000000006FFF8F02F402FF03C0002F03E0000A01FE8000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_28 =  0000F0000000F0000F00F00F0F00F00F0F00F00F0FFFFFFF0000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_29 =  000000000000000000000000003FFFC00000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_2A =  03C0003C03C0003C03C0003C03C0003C03C0003C03C0003C0000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_2B =  000000000000000000000000002FFF8001F802F403E000BC03C0003C03C0003C" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_2C =  02F00BC003D003E00BC002F01F0000F83E00007CBC00002F0000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_2D =  000000000000000000000000000BF000001FF800003E7C0000BC2E0000F80F40" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_2E =  0F4FF0F41F0BF0FC2F03E0BC3E00003D7C00003EBC00002F0000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_2F =  00000000000000000000000002F80FC003FC2FC003FD3FE007DE7EF00F8FB9F0" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_30 =  000BF000000FF400003E3D0000F81F4003F00BC03FFC2FFC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_31 =  0000000000000000000000003FF80FFE03F00BD000F81F40003E3D00000FF800" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_32 =  0003FC00000BAE00002F0F8000BC03E001F401F40FFE0BFF0000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_33 =  000000000000000000000000003FFFC00000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_34 =  0000F8000003E000000F403C003D003C00F4003C02FFFFFC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_35 =  00000000000000000000000003FFFFFC03C000F803C003E003C00F8000003E00" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_36 =  00003C0000003C0000003C0000003C0000003C0000003C0000003C00000FFC00" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_37 =  000FFC0000003C0000003C0000003C0000003C0000003C0000003C0000003C00" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_38 =  0003D0000000F00000007C0000002F0000000B80000003D0000000F000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_39 =  000000002E0000000F40000003C0000001F0000000BC0000002E0000000F4000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_3A =  0000F0000000F0000000F0000000F0000000F0000000F0000000F0000000FFC0" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_3B =  0000FFC00000F0000000F0000000F0000000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_3C =  0BD0003F02F000FC00BC03F0002F0BC0000FEF000003FC000000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT1>.
-    Set user-defined property "INIT_3F =  000000000FFFFFFF000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT1>.
-Entity <FONT1> analyzed. Unit <FONT1> generated.
-
-Analyzing Entity <FONT2> in library <work> (Architecture <RTL>).
-WARNING:Xst:2211 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/font2_rom.vhd" line 269: Instantiating black box module <RAMB16_S2>.
-    Set user-defined property "INIT_00 =  00000000000000000000000000000000000F80000002FE0000001B4000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_02 =  03C0000002F400B8007FFFE80000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_03 =  00000000000000000000000003CBFFF803FE003F03E0000F03C002BE03FFFFE4" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_04 =  03E0003C00F901FC002FFFBC0000003C0000003C0000003C0000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_05 =  000000000000000000000000002FFFBC00F901FC03E0003C03C0003C03C0003C" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_06 =  03E0002F03F801FC03DFFFE00000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_07 =  00000000000000000000000000BFFF9003E402FC0000003F0000000F0280000F" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_08 =  03C0002F03F401FC03EFFFD003C0000003C0000003FF00000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_09 =  00000000000000000000000003EFFFD003F801FC03C0002F03C0000F03C0000F" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_0A =  0BC0002F03F401BC007FFFD00000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_0B =  00000000000000000000000000BFFF9003E402FC0000003F0000001F0FFFFFFF" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_0C =  0000F0000000F0000FFFFFC00000F0000007E0000FFF80000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_0D =  000000000000000000000000003FFFC00000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_0E =  03C0003F03F801FC03EFFFD00000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_0F =  002FFFE002F902BD03D0000403EFFFE003F801BC03C0002F03C0000F03C0000F" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_10 =  03C000FC02F40BBC00BFFE3C0000003C0000003C0000003C0000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_11 =  00000000000000000000000003C0003C03C0003C03C0003C03C0003C03C0007C" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_12 =  0000F0000000F0000000FFC0000000000000F0000000F0000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_13 =  000000000000000000000000003FFFC00000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_14 =  003C0000003C0000003FF00000000000003C0000003C00000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_15 =  0007FFF4002F80BE003D0004003C0000003C0000003C0000003C0000003C0000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_16 =  000BF03C00BF403C0BF8003C0000003C0000003C0000003C0000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_17 =  0000000000000000000000000BF0003C00BE003C000FC0BC0002FBFC0000BE3C" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_18 =  0000F0000000F0000000F0000000F0000000F0000000FFC00000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_19 =  000000000000000000000000003FFFC00000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_1A =  0F01F01F0F83F83F07FE7FEF0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_1B =  0000000000000000000000000F00F00F0F00F00F0F00F00F0F00F00F0F00F00F" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_1C =  03C000FC02F40BBC00BFFE3C0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_1D =  00000000000000000000000003C0003C03C0003C03C0003C03C0003C03C0007C" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_1E =  0FC0003F03F801FC007FFFD00000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_1F =  000000000000000000000000007FFFD003F401FC0F80002F0F00000F0F00000F" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_20 =  03E0003C00F901FC002FFFBC0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_21 =  0000003C0000003C0000003C002FFFBC00F901FC03E0003C03C0003C03C0003C" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_22 =  03C0002F03F401FC03EFFFD00000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_23 =  03C0000003C0000003C0000003EFFFD003F401FC03C0002F03C0000F03C0000F" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_24 =  00000FC00000BBC007FFE3FF0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_25 =  0000000000000000000000000000FFFF000003C0000003C0000003C0000007C0" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_26 =  000001BF00E4006F00BFFFF80000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_27 =  00000000000000000000000000BFFFFA03F4006F03C0000003FA0000006FFFF8" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_28 =  000003C0000003C0003FFFFF000003C0000003C0000003C00000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_29 =  00000000000000000000000001FFFD0007E01F800B4007C0000003C0000003C0" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_2A =  03C0003C03C0003C03C0003C0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_2B =  00000000000000000000000003CBFFE003EE01F803F0003C03D0003C03C0003C" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_2C =  0BC003F00F8000F83F0000BD0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_2D =  000000000000000000000000000FF000002FBC00007D3E0000F81F4002F00BC0" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_2E =  1F0FF0FC3E0BF07C3D03E03E0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_2F =  00000000000000000000000003F40FC003FC2FD007FC3EE00FAE3DF00F0FB8F4" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_30 =  003E7E0001F80F803FFC2FFC0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_31 =  0000000000000000000000003FFC2FFE02F40FC0007D3E00000FF400000FF400" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_32 =  07C003F00F8000F83F0000BD0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_33 =  00003FFC0000FC040003F000000BF000001FB800003C3E0000F80F0002F00BC0" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_34 =  002F803C00FC003C02FFFFFC0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_35 =  00000000000000000000000003FFFFFC03C002F803C00FC00280BE000003F028" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_36 =  00002F4000003C0000003C0000003C0000003C0000003C000000BC00000FE000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_37 =  000FF0000000BC0000003C0000003C0000003C0000003C0000003E0000000BF0" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_38 =  0000F0000000F0000000F0000000F0000000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_39 =  000000000000F0000000F0000000F0000000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_3A =  0007E0000000F0000000F0000000F0000000F0000000F0000000F80000002FC0" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_3B =  00003FC00000F8000000F0000000F0000000F0000000F0000002F000003F8000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_3C =  0F802FF800000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_3D =  000000000000000000000000000000000000000000BF800F03EBF02F0BC0FD7E" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
-Entity <FONT2> analyzed. Unit <FONT2> generated.
-
-Analyzing Entity <Replay_FileIO> in library <work> (Architecture <RTL>).
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_FileIO_Sync.vhd" line 628: Unconnected output port 'o_w_full' of component 'FIFO_SyncBlock_D2048_W8'.
-Entity <Replay_FileIO> analyzed. Unit <Replay_FileIO> generated.
-
-Analyzing Entity <FIFO_SyncBlock_D2048_W8> in library <work> (Architecture <RTL>).
-    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_13 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_14 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_15 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_16 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_17 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_A =  000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "INIT_B =  000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "SRVAL_A =  000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "SRVAL_B =  000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
-Entity <FIFO_SyncBlock_D2048_W8> analyzed. Unit <FIFO_SyncBlock_D2048_W8> generated.
-
-Analyzing Entity <Replay_Video> in library <work> (Architecture <RTL>).
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Video.vhd" line 114: Unconnected output port 'o_devid' of component 'Replay_I2C'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Video.vhd" line 114: Unconnected output port 'o_rw_l' of component 'Replay_I2C'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Video.vhd" line 114: Unconnected output port 'o_rab' of component 'Replay_I2C'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Video.vhd" line 114: Unconnected output port 'o_write_data' of component 'Replay_I2C'.
-WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Video.vhd" line 114: Unconnected output port 'o_write_ena' of component 'Replay_I2C'.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[0].inst> in unit <Replay_Video>.
-    Set user-defined property "INIT =  0" for instance <vidout[0].inst> in unit <Replay_Video>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[0].inst> in unit <Replay_Video>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[1].inst> in unit <Replay_Video>.
-    Set user-defined property "INIT =  0" for instance <vidout[1].inst> in unit <Replay_Video>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[1].inst> in unit <Replay_Video>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[2].inst> in unit <Replay_Video>.
-    Set user-defined property "INIT =  0" for instance <vidout[2].inst> in unit <Replay_Video>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[2].inst> in unit <Replay_Video>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[3].inst> in unit <Replay_Video>.
-    Set user-defined property "INIT =  0" for instance <vidout[3].inst> in unit <Replay_Video>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[3].inst> in unit <Replay_Video>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[4].inst> in unit <Replay_Video>.
-    Set user-defined property "INIT =  0" for instance <vidout[4].inst> in unit <Replay_Video>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[4].inst> in unit <Replay_Video>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[5].inst> in unit <Replay_Video>.
-    Set user-defined property "INIT =  0" for instance <vidout[5].inst> in unit <Replay_Video>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[5].inst> in unit <Replay_Video>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[6].inst> in unit <Replay_Video>.
-    Set user-defined property "INIT =  0" for instance <vidout[6].inst> in unit <Replay_Video>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[6].inst> in unit <Replay_Video>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[7].inst> in unit <Replay_Video>.
-    Set user-defined property "INIT =  0" for instance <vidout[7].inst> in unit <Replay_Video>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[7].inst> in unit <Replay_Video>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[8].inst> in unit <Replay_Video>.
-    Set user-defined property "INIT =  0" for instance <vidout[8].inst> in unit <Replay_Video>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[8].inst> in unit <Replay_Video>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[9].inst> in unit <Replay_Video>.
-    Set user-defined property "INIT =  0" for instance <vidout[9].inst> in unit <Replay_Video>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[9].inst> in unit <Replay_Video>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[10].inst> in unit <Replay_Video>.
-    Set user-defined property "INIT =  0" for instance <vidout[10].inst> in unit <Replay_Video>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[10].inst> in unit <Replay_Video>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[11].inst> in unit <Replay_Video>.
-    Set user-defined property "INIT =  0" for instance <vidout[11].inst> in unit <Replay_Video>.
-    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[11].inst> in unit <Replay_Video>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <u_Clk_P> in unit <Replay_Video>.
-    Set user-defined property "INIT =  0" for instance <u_Clk_P> in unit <Replay_Video>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <u_Clk_P> in unit <Replay_Video>.
-    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <u_Clk_N> in unit <Replay_Video>.
-    Set user-defined property "INIT =  0" for instance <u_Clk_N> in unit <Replay_Video>.
-    Set user-defined property "SRTYPE =  ASYNC" for instance <u_Clk_N> in unit <Replay_Video>.
-Entity <Replay_Video> analyzed. Unit <Replay_Video> generated.
-
-Analyzing Entity <Replay_I2C> in library <work> (Architecture <RTL>).
-INFO:Xst:2679 - Register <o_drive_scl_low> in unit <Replay_I2C> has a constant value of 0 during circuit operation. The register is replaced by logic.
-Entity <Replay_I2C> analyzed. Unit <Replay_I2C> generated.
-
-Analyzing Entity <Replay_Audio> in library <work> (Architecture <RTL>).
-Entity <Replay_Audio> analyzed. Unit <Replay_Audio> generated.
-
-
-=========================================================================
-*                           HDL Synthesis                               *
-=========================================================================
-
-Performing bidirectional port resolution...
-INFO:Xst:2561 - Always blocking tristate driving signal <b_Clk_Aux> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_FPGA_SPI_MOSI> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_2V5_IO_0> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_2V5_IO_1> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_Aux_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_Aux_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_Aux_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2561 - Always blocking tristate driving signal <b_Aux_IO> in unit <Replay_Top> is removed.
-INFO:Xst:2679 - Register <CART_CCTL_n> in unit <address_decoder> has a constant value of 1 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <PBI_WR_ENABLE> in unit <address_decoder> has a constant value of 0 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <CART_S4_n> in unit <address_decoder> has a constant value of 1 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <CART_S5_n> in unit <address_decoder> has a constant value of 1 during circuit operation. The register is replaced by logic.
-INFO:Xst:2679 - Register <CART_REQUEST> in unit <address_decoder> has a constant value of 0 during circuit operation. The register is replaced by logic.
-
-Synthesizing Unit <Replay_Audio>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Audio.vhd".
-    Found 1-bit register for signal <o_sample_taken>.
-    Found 1-bit register for signal <o_audio_din>.
-    Found 1-bit register for signal <o_audio_bckin>.
-    Found 1-bit register for signal <o_audio_mclk>.
-    Found 1-bit register for signal <o_audio_lrcin>.
-    Found 8-bit up counter for signal <cnt>.
-    Found 24-bit register for signal <shifter>.
-    Summary:
-	inferred   1 Counter(s).
-	inferred  29 D-type flip-flop(s).
-Unit <Replay_Audio> synthesized.
-
-
-Synthesizing Unit <Replay_ResetGen>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_ClockGen_Sync.vhd".
-    Found 1-bit register for signal <o_rst>.
-    Found 1-bit register for signal <o_rst_soft>.
-    Found 1-bit register for signal <por_l_meta1>.
-    Found 1-bit register for signal <por_l_meta2>.
-    Found 5-bit up counter for signal <por_rst_cnt>.
-    Found 5-bit up counter for signal <por_rst_soft_cnt>.
-    Found 1-bit register for signal <rst_soft>.
-    Summary:
-	inferred   2 Counter(s).
-	inferred   5 D-type flip-flop(s).
-Unit <Replay_ResetGen> synthesized.
-
-
-Synthesizing Unit <Replay_TranslatePS2>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_TranslatePS2.vhd".
-WARNING:Xst:647 - Input <i_ena_sys> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:1780 - Signal <matrix_adr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <cs_trig> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <cs_control0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <cs_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-    Found 512x8-bit dual-port RAM <Mram_keylut> for signal <keylut>.
-    Found finite state machine <FSM_0> for signal <key_state>.
-    -----------------------------------------------------------------------
-    | States             | 13                                             |
-    | Transitions        | 32                                             |
-    | Inputs             | 4                                              |
-    | Outputs            | 8                                              |
-    | Clock              | i_clk_sys                 (rising_edge)        |
-    | Reset              | key_state$or0000          (positive)           |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | normal                                         |
-    | Power Up State     | normal                                         |
-    | Encoding           | automatic                                      |
-    | Implementation     | automatic                                      |
-    -----------------------------------------------------------------------
-    Found 1-bit register for signal <key_break>.
-    Found 8-bit register for signal <key_code>.
-    Found 1-bit register for signal <key_opt>.
-    Found 1-bit register for signal <key_pause>.
-    Found 1-bit register for signal <key_trans_en>.
-    Found 8-bit register for signal <key_translated>.
-    Found 128-bit register for signal <matrix>.
-    Found 1-of-16 decoder for signal <matrix_mask>.
-    Found 7-bit register for signal <static_out>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred   1 RAM(s).
-	inferred 155 D-type flip-flop(s).
-	inferred   1 Decoder(s).
-Unit <Replay_TranslatePS2> synthesized.
-
-
-Synthesizing Unit <pokey_mixer>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pokey_mixer.vhdl".
-WARNING:Xst:647 - Input <CHANNEL_ENABLE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:646 - Signal <volume_next<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 64x16-bit ROM for signal <volume_next>.
-    Found 16-bit adder for signal <volume_next_real>.
-    Found 16-bit adder for signal <volume_next_real$addsub0000> created at line 237.
-    Found 16-bit adder for signal <volume_next_real$addsub0001> created at line 237.
-    Found 16-bit register for signal <volume_reg>.
-    Found 6-bit adder for signal <volume_sum>.
-    Found 5-bit adder for signal <volume_sum$add0000> created at line 82.
-    Found 5-bit adder for signal <volume_sum$add0001> created at line 82.
-    Summary:
-	inferred   1 ROM(s).
-	inferred  16 D-type flip-flop(s).
-	inferred   6 Adder/Subtractor(s).
-Unit <pokey_mixer> synthesized.
-
-
-Synthesizing Unit <address_decoder>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/address_decoder.vhdl".
-WARNING:Xst:647 - Input <cart_activate> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <antic_refresh> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:646 - Signal <SDRAM_OS_ROM_ADDR<13:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <SDRAM_CART_ADDR> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found finite state machine <FSM_1> for signal <state_reg>.
-    -----------------------------------------------------------------------
-    | States             | 4                                              |
-    | Transitions        | 21                                             |
-    | Inputs             | 8                                              |
-    | Outputs            | 4                                              |
-    | Clock              | CLK                       (rising_edge)        |
-    | Reset              | reset_n                   (negative)           |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | 00                                             |
-    | Encoding           | automatic                                      |
-    | Implementation     | automatic                                      |
-    -----------------------------------------------------------------------
-    Found 24-bit register for signal <ADDR_reg>.
-    Found 24-bit 8-to-1 multiplexer for signal <ADDR_reg$mux0000> created at line 277.
-    Found 1-bit register for signal <antic_fetch_real_reg>.
-    Found 1-bit register for signal <cpu_fetch_real_reg>.
-    Found 32-bit register for signal <DATA_WRITE_reg>.
-    Found 9-bit 8-to-1 multiplexer for signal <extended_bank>.
-    Found 1-bit 8-to-1 multiplexer for signal <extended_self_test>.
-    Found 9-bit adder for signal <fetch_wait_next$addsub0000>.
-    Found 9-bit register for signal <fetch_wait_reg>.
-    Found 1-bit register for signal <width_16bit_reg>.
-    Found 1-bit register for signal <width_32bit_reg>.
-    Found 1-bit register for signal <width_8bit_reg>.
-    Found 1-bit register for signal <write_enable_reg>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred  71 D-type flip-flop(s).
-	inferred   1 Adder/Subtractor(s).
-	inferred  34 Multiplexer(s).
-Unit <address_decoder> synthesized.
-
-
-Synthesizing Unit <zpu_rom>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_rom.vhdl".
-WARNING:Xst:1781 - Signal <ROM> is used but never assigned. Tied to default value.
-    Found 4096x32-bit ROM for signal <rdata>.
-    Found 32-bit register for signal <q>.
-    Summary:
-	inferred   1 ROM(s).
-	inferred  32 D-type flip-flop(s).
-Unit <zpu_rom> synthesized.
-
-
-Synthesizing Unit <generic_ram_infer_1>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/generic_ram_infer.vhdl".
-    Found 1024x8-bit single-port RAM <Mram_ram_block> for signal <ram_block>.
-    Found 8-bit register for signal <q>.
-    Summary:
-	inferred   1 RAM(s).
-	inferred   8 D-type flip-flop(s).
-Unit <generic_ram_infer_1> synthesized.
-
-
-Synthesizing Unit <complete_address_decoder_1>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/complete_address_decoder.vhdl".
-WARNING:Xst:1780 - Signal <p<3><7:1>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <p<2><7:2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <p<1><7:4>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-Unit <complete_address_decoder_1> synthesized.
-
-
-Synthesizing Unit <gtia_palette>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/gtia_palette.vhdl".
-    Found 256x24-bit ROM for signal <ATARI_COLOUR$rom0000>.
-    Summary:
-	inferred   1 ROM(s).
-Unit <gtia_palette> synthesized.
-
-
-Synthesizing Unit <irq_glue>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/irq_glue.vhdl".
-Unit <irq_glue> synthesized.
-
-
-Synthesizing Unit <cpu_65xx>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/cpu_65xx_a.vhd".
-WARNING:Xst:646 - Signal <nextOpcInfoReg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <aluZReg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <aluVReg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <aluRmwReg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <aluNineReg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <aluNReg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <aluInputReg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <aluCmpInputReg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <aluCReg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 256x44-bit ROM for signal <nextOpcInfo$rom0000> created at line 911.
-    Found finite state machine <FSM_2> for signal <theCpuCycle>.
-    -----------------------------------------------------------------------
-    | States             | 19                                             |
-    | Transitions        | 97                                             |
-    | Inputs             | 25                                             |
-    | Outputs            | 43                                             |
-    | Clock              | clk                       (rising_edge)        |
-    | Clock enable       | enable                    (positive)           |
-    | Reset              | reset                     (positive)           |
-    | Reset type         | synchronous                                    |
-    | Reset State        | cycle2                                         |
-    | Power Up State     | opcodefetch                                    |
-    | Encoding           | automatic                                      |
-    | Implementation     | automatic                                      |
-    -----------------------------------------------------------------------
-    Using one-hot encoding for signal <nextAddr>.
-    Found 8-bit register for signal <A>.
-    Found 1-bit register for signal <Creg>.
-    Found 8-bit register for signal <doReg>.
-    Found 1-bit register for signal <Dreg>.
-    Found 1-bit register for signal <halt_dly>.
-    Found 9-bit adder for signal <indexOut$share0000> created at line 1535.
-    Found 1-bit register for signal <Ireg>.
-    Found 1-bit register for signal <irqActive>.
-    Found 1-bit register for signal <irqReg>.
-    Found 6-bit adder for signal <lowBits$add0000> created at line 758.
-    Found 6-bit adder for signal <lowBits$addsub0000> created at line 755.
-    Found 16-bit register for signal <myAddr>.
-    Found 8-bit subtractor for signal <myAddrDecrH>.
-    Found 16-bit adder for signal <myAddrIncr>.
-    Found 8-bit adder for signal <myAddrIncrH$addsub0000> created at line 1585.
-    Found 9-bit adder carry in for signal <nineBits$addsub0000>.
-    Found 9-bit adder for signal <nineBits$addsub0001>.
-    Found 8-bit xor2 for signal <nineBits$xor0000> created at line 765.
-    Found 5-bit adder for signal <nineBits_0$add0000> created at line 831.
-    Found 5-bit comparator greater for signal <nineBits_0$cmp_gt0000> created at line 831.
-    Found 5-bit comparator greater for signal <nineBits_0$cmp_gt0001> created at line 784.
-    Found 4-bit adder for signal <nineBits_3_0$add0000> created at line 785.
-    Found 4-bit adder for signal <nineBits_3_0$add0001> created at line 832.
-    Found 4-bit subtractor for signal <nineBits_3_0$sub0000> created at line 822.
-    Found 5-bit adder for signal <nineBits_4$add0000> created at line 834.
-    Found 5-bit comparator greater for signal <nineBits_4$cmp_gt0000> created at line 812.
-    Found 5-bit comparator greater for signal <nineBits_4$cmp_gt0001> created at line 834.
-    Found 5-bit adder for signal <nineBits_8_4$add0000> created at line 787.
-    Found 5-bit adder for signal <nineBits_8_4$add0001> created at line 813.
-    Found 5-bit subtractor for signal <nineBits_8_4$sub0000> created at line 826.
-    Found 1-bit register for signal <nmiEdge>.
-    Found 1-bit register for signal <nmiReg>.
-    Found 1-bit register for signal <Nreg>.
-    Found 44-bit register for signal <opcInfo>.
-    Found 16-bit register for signal <PC>.
-    Found 1-bit register for signal <processInt>.
-    Found 1-bit register for signal <processIrq>.
-    Found 1-bit register for signal <processNmi>.
-    Found 8-bit adder for signal <rmwBits$add0000> created at line 733.
-    Found 8-bit subtractor for signal <rmwBits$sub0000> created at line 735.
-    Found 8-bit register for signal <S>.
-    Found 8-bit addsub for signal <sIncDec$mux0000> created at line 1295.
-    Found 1-bit register for signal <so_reg>.
-    Found 8-bit register for signal <T>.
-    Found 8-bit register for signal <theOpcode>.
-    Found 1-bit register for signal <theWe>.
-    Found 1-bit xor2 for signal <varV$xor0000> created at line 804.
-    Found 1-bit xor2 for signal <varV$xor0001> created at line 810.
-    Found 1-bit xor2 for signal <varV$xor0002> created at line 810.
-    Found 1-bit xor2 for signal <varV$xor0003> created at line 818.
-    Found 1-bit register for signal <Vreg>.
-    Found 8-bit register for signal <X>.
-    Found 8-bit register for signal <Y>.
-    Found 1-bit register for signal <Zreg>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred   1 ROM(s).
-	inferred 148 D-type flip-flop(s).
-	inferred  19 Adder/Subtractor(s).
-	inferred   4 Comparator(s).
-Unit <cpu_65xx> synthesized.
-
-
-Synthesizing Unit <antic_counter_1>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/antic_counter.vhdl".
-    Found 12-bit adder for signal <value_next$add0000> created at line 51.
-    Found 16-bit register for signal <value_reg>.
-    Summary:
-	inferred  16 D-type flip-flop(s).
-	inferred   1 Adder/Subtractor(s).
-Unit <antic_counter_1> synthesized.
-
-
-Synthesizing Unit <antic_counter_2>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/antic_counter.vhdl".
-    Found 10-bit adder for signal <value_next$add0000> created at line 51.
-    Found 16-bit register for signal <value_reg>.
-    Summary:
-	inferred  16 D-type flip-flop(s).
-	inferred   1 Adder/Subtractor(s).
-Unit <antic_counter_2> synthesized.
-
-
-Synthesizing Unit <simple_counter_1>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/simple_counter.vhdl".
-    Found 8-bit up counter for signal <value_reg>.
-    Summary:
-	inferred   1 Counter(s).
-Unit <simple_counter_1> synthesized.
-
-
-Synthesizing Unit <simple_counter_2>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/simple_counter.vhdl".
-    Found 4-bit up counter for signal <value_reg>.
-    Summary:
-	inferred   1 Counter(s).
-Unit <simple_counter_2> synthesized.
-
-
-Synthesizing Unit <wide_delay_line_1>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl".
-    Found 32-bit register for signal <shift_reg>.
-    Summary:
-	inferred  32 D-type flip-flop(s).
-Unit <wide_delay_line_1> synthesized.
-
-
-Synthesizing Unit <antic_dma_clock>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/antic_dma_clock.vhdl".
-    Found 8-bit register for signal <dma_shiftreg_reg>.
-    Summary:
-	inferred   8 D-type flip-flop(s).
-Unit <antic_dma_clock> synthesized.
-
-
-Synthesizing Unit <wide_delay_line_2>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl".
-    Found 64-bit register for signal <shift_reg>.
-    Summary:
-	inferred  64 D-type flip-flop(s).
-Unit <wide_delay_line_2> synthesized.
-
-
-Synthesizing Unit <wide_delay_line_3>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl".
-    Found 224-bit register for signal <shift_reg>.
-    Summary:
-	inferred 224 D-type flip-flop(s).
-Unit <wide_delay_line_3> synthesized.
-
-
-Synthesizing Unit <complete_address_decoder_2>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/complete_address_decoder.vhdl".
-WARNING:Xst:1780 - Signal <p<4><15:1>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <p<3><15:2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <p<2><15:4>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <p<1><15:8>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-Unit <complete_address_decoder_2> synthesized.
-
-
-Synthesizing Unit <delay_line_1>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/delay_line.vhdl".
-    Found 24-bit register for signal <shift_reg>.
-    Summary:
-	inferred  24 D-type flip-flop(s).
-Unit <delay_line_1> synthesized.
-
-
-Synthesizing Unit <complete_address_decoder_5>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/complete_address_decoder.vhdl".
-WARNING:Xst:1780 - Signal <p<6><63:1>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <p<5><63:2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <p<4><63:4>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <p<3><63:8>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <p<2><63:16>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <p<1><63:32>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-Unit <complete_address_decoder_5> synthesized.
-
-
-Synthesizing Unit <ZPUMediumCore>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_core.vhd".
-WARNING:Xst:1780 - Signal <mult_res3_r> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <mult_res2_r> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <mult_b_r> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <mult_a_r> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <bin_op_res2_r> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:653 - Signal <bin_op_res1_r> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
-INFO:Xst:1799 - State st_idle is never reached in FSM <state>.
-INFO:Xst:1799 - State st_mult3 is never reached in FSM <state>.
-INFO:Xst:1799 - State st_mult2 is never reached in FSM <state>.
-INFO:Xst:1799 - State st_mult4 is never reached in FSM <state>.
-INFO:Xst:1799 - State st_binary_op_res2 is never reached in FSM <state>.
-INFO:Xst:1799 - State st_binary_op_res is never reached in FSM <state>.
-    Found finite state machine <FSM_3> for signal <state>.
-    -----------------------------------------------------------------------
-    | States             | 15                                             |
-    | Transitions        | 58                                             |
-    | Inputs             | 30                                             |
-    | Outputs            | 18                                             |
-    | Clock              | clk_i                     (rising_edge)        |
-    | Reset              | reset_i                   (positive)           |
-    | Reset type         | synchronous                                    |
-    | Reset State        | st_resync                                      |
-    | Power Up State     | st_resync                                      |
-    | Encoding           | automatic                                      |
-    | Implementation     | automatic                                      |
-    -----------------------------------------------------------------------
-    Found 32x6-bit ROM for signal <tdecoded$mux0111>.
-    Found 32x6-bit ROM for signal <tdecoded$mux0112>.
-    Found 32x6-bit ROM for signal <tdecoded$mux0113>.
-    Found 32x6-bit ROM for signal <insn$mux0002>.
-    Found 1-bit register for signal <break_o>.
-    Found 22-bit register for signal <dbg_o.sp<23:2>>.
-    Found 8-bit register for signal <dbg_o.opcode>.
-    Found 32-bit register for signal <data_o>.
-    Found 32-bit register for signal <dbg_o.stk_a>.
-    Found 32-bit register for signal <dbg_o.stk_b>.
-    Found 1-bit register for signal <dbg_o.b_inst>.
-    Found 32-bit register for signal <dbg_o.pc>.
-    Found 6-bit 4-to-1 multiplexer for signal <$varindex0000> created at line 508.
-    Found 32-bit register for signal <a_r>.
-    Found 32-bit adder for signal <a_r$add0000> created at line 625.
-    Found 32-bit adder for signal <a_r$add0001> created at line 887.
-    Found 32-bit subtractor for signal <a_r$sub0000> created at line 633.
-    Found 22-bit adder for signal <a_r_23_2$add0000> created at line 772.
-    Found 6-bit subtractor for signal <a_r_5_0$sub0000> created at line 849.
-    Found 22-bit register for signal <addr_r>.
-    Found 22-bit adder carry in for signal <addr_r$share0000> created at line 356.
-    Found 2-bit register for signal <addrl_r>.
-    Found 32-bit register for signal <b_r>.
-    Found 1-bit register for signal <byte_read_r>.
-    Found 1-bit register for signal <byte_write_r>.
-    Found 32-bit register for signal <fetched_w_r>.
-    Found 1-bit register for signal <idim_r>.
-    Found 22-bit adder for signal <inc_inc_sp$add0000> created at line 276.
-    Found 22-bit adder for signal <inc_sp$add0000> created at line 275.
-    Found 6-bit register for signal <insn>.
-    Found 18-bit register for signal <insns<1:3>>.
-    Found 32x32-bit multiplier for signal <mult_res$mult0000> created at line 796.
-    Found 32-bit register for signal <mult_res1_r>.
-    Found 24-bit adder for signal <next_pc$add0000> created at line 345.
-    Found 1-bit register for signal <not_lshr>.
-    Found 32-bit register for signal <opcode_r>.
-    Found 24-bit register for signal <pc_r>.
-    Found 24-bit adder for signal <pc_r$add0000> created at line 578.
-    Found 1-bit register for signal <read_en_r>.
-    Found 32-bit comparator equal for signal <res$cmp_eq0000> created at line 674.
-    Found 32-bit comparator less for signal <res0$cmp_lt0000> created at line 680.
-    Found 32-bit comparator lessequal for signal <res1$cmp_le0000> created at line 686.
-    Found 32-bit comparator less for signal <res2$cmp_lt0000> created at line 692.
-    Found 32-bit comparator lessequal for signal <res3$cmp_le0000> created at line 699.
-    Found 8-bit 4-to-1 multiplexer for signal <sp_offset_4$varindex0000> created at line 343.
-    Found 22-bit register for signal <sp_r>.
-    Found 22-bit subtractor for signal <sp_r$share0000> created at line 516.
-    Found 1-bit register for signal <write_en_r>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred   4 ROM(s).
-	inferred 420 D-type flip-flop(s).
-	inferred  11 Adder/Subtractor(s).
-	inferred   1 Multiplier(s).
-	inferred   5 Comparator(s).
-	inferred  14 Multiplexer(s).
-Unit <ZPUMediumCore> synthesized.
-
-
-Synthesizing Unit <delay_line_2>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/delay_line.vhdl".
-    Found 3-bit register for signal <shift_reg>.
-    Summary:
-	inferred   3 D-type flip-flop(s).
-Unit <delay_line_2> synthesized.
-
-
-Synthesizing Unit <pokey_noise_filter>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pokey_noise_filter.vhdl".
-Unit <pokey_noise_filter> synthesized.
-
-
-Synthesizing Unit <syncreset_enable_divider_1>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/syncreset_enable_divider.vhd".
-    Found 5-bit register for signal <count_reg>.
-    Found 5-bit adder for signal <count_reg$addsub0000> created at line 64.
-    Found 1-bit register for signal <enabled_out_reg>.
-    Summary:
-	inferred   6 D-type flip-flop(s).
-	inferred   1 Adder/Subtractor(s).
-Unit <syncreset_enable_divider_1> synthesized.
-
-
-Synthesizing Unit <syncreset_enable_divider_2>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/syncreset_enable_divider.vhd".
-    Found 7-bit register for signal <count_reg>.
-    Found 7-bit adder for signal <count_reg$addsub0000> created at line 64.
-    Found 1-bit register for signal <enabled_out_reg>.
-    Summary:
-	inferred   8 D-type flip-flop(s).
-	inferred   1 Adder/Subtractor(s).
-Unit <syncreset_enable_divider_2> synthesized.
-
-
-Synthesizing Unit <poly_17_9>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/poly_17_9.vhdl".
-    Found 1-bit xor2 for signal <feedback$xor0000>.
-    Found 17-bit register for signal <shift_reg>.
-Unit <poly_17_9> synthesized.
-
-
-Synthesizing Unit <poly_5>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/poly_5.vhdl".
-    Found 1-bit xor2 for signal <shift_next$xor0000>.
-    Found 5-bit register for signal <shift_reg>.
-Unit <poly_5> synthesized.
-
-
-Synthesizing Unit <poly_4>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/poly_4.vhdl".
-    Found 1-bit xor2 for signal <shift_next$xor0000>.
-    Found 4-bit register for signal <shift_reg>.
-Unit <poly_4> synthesized.
-
-
-Synthesizing Unit <delay_line_3>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/delay_line.vhdl".
-    Found 2-bit register for signal <shift_reg>.
-    Summary:
-	inferred   2 D-type flip-flop(s).
-Unit <delay_line_3> synthesized.
-
-
-Synthesizing Unit <synchronizer>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/synchronizer.vhdl".
-    Found 3-bit register for signal <ff_reg>.
-    Summary:
-	inferred   3 D-type flip-flop(s).
-Unit <synchronizer> synthesized.
-
-
-Synthesizing Unit <pokey_keyboard_scanner>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pokey_keyboard_scanner.vhdl".
-    Found finite state machine <FSM_4> for signal <state_reg>.
-    -----------------------------------------------------------------------
-    | States             | 4                                              |
-    | Transitions        | 11                                             |
-    | Inputs             | 2                                              |
-    | Outputs            | 6                                              |
-    | Clock              | clk                       (rising_edge)        |
-    | Clock enable       | state_reg$and0000         (positive)           |
-    | Reset              | reset_n                   (negative)           |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | 00                                             |
-    | Encoding           | automatic                                      |
-    | Implementation     | automatic                                      |
-    -----------------------------------------------------------------------
-    Found 6-bit up counter for signal <bincnt_reg>.
-    Found 1-bit register for signal <break_pressed_reg>.
-    Found 6-bit register for signal <compare_latch_reg>.
-    Found 1-bit register for signal <control_pressed_reg>.
-    Found 1-bit register for signal <irq_reg>.
-    Found 1-bit register for signal <key_held_reg>.
-    Found 6-bit register for signal <keycode_latch_reg>.
-    Found 6-bit comparator equal for signal <my_key$cmp_eq0000> created at line 109.
-    Found 1-bit register for signal <shift_pressed_reg>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred   1 Counter(s).
-	inferred  17 D-type flip-flop(s).
-	inferred   1 Comparator(s).
-Unit <pokey_keyboard_scanner> synthesized.
-
-
-Synthesizing Unit <complete_address_decoder_3>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/complete_address_decoder.vhdl".
-WARNING:Xst:1780 - Signal <p<2><3:1>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <p<1><3:2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-Unit <complete_address_decoder_3> synthesized.
-
-
-Synthesizing Unit <enable_divider_1>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/enable_divider.vhdl".
-    Found 1-bit register for signal <count_reg<0>>.
-    Found 1-bit register for signal <enabled_out_reg>.
-    Summary:
-	inferred   2 D-type flip-flop(s).
-Unit <enable_divider_1> synthesized.
-
-
-Synthesizing Unit <enable_divider_2>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/enable_divider.vhdl".
-    Found 4-bit up counter for signal <count_reg>.
-    Found 1-bit register for signal <enabled_out_reg>.
-    Summary:
-	inferred   1 Counter(s).
-	inferred   1 D-type flip-flop(s).
-Unit <enable_divider_2> synthesized.
-
-
-Synthesizing Unit <delay_line_4>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/delay_line.vhdl".
-    Found 15-bit register for signal <shift_reg>.
-    Summary:
-	inferred  15 D-type flip-flop(s).
-Unit <delay_line_4> synthesized.
-
-
-Synthesizing Unit <delay_line_5>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/delay_line.vhdl".
-    Found 8-bit register for signal <shift_reg>.
-    Summary:
-	inferred   8 D-type flip-flop(s).
-Unit <delay_line_5> synthesized.
-
-
-Synthesizing Unit <complete_address_decoder_4>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/complete_address_decoder.vhdl".
-WARNING:Xst:1780 - Signal <p<5><31:1>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <p<4><31:2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <p<3><31:4>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <p<2><31:8>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <p<1><31:16>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-Unit <complete_address_decoder_4> synthesized.
-
-
-Synthesizing Unit <gtia_player>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/gtia_player.vhdl".
-    Found finite state machine <FSM_5> for signal <count_reg>.
-    -----------------------------------------------------------------------
-    | States             | 4                                              |
-    | Transitions        | 16                                             |
-    | Inputs             | 5                                              |
-    | Outputs            | 4                                              |
-    | Clock              | CLK                       (rising_edge)        |
-    | Clock enable       | COLOUR_ENABLE             (positive)           |
-    | Reset              | RESET_N                   (negative)           |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | 00                                             |
-    | Encoding           | automatic                                      |
-    | Implementation     | automatic                                      |
-    -----------------------------------------------------------------------
-    Found 8-bit comparator equal for signal <count_reg$cmp_eq0000> created at line 108.
-    Found 8-bit register for signal <shift_reg>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred   8 D-type flip-flop(s).
-	inferred   1 Comparator(s).
-Unit <gtia_player> synthesized.
-
-
-Synthesizing Unit <gtia_priority>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/gtia_priority.vhdl".
-WARNING:Xst:647 - Input <BK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <PRIOR<7:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <PRIOR<4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-    Found 1-bit register for signal <SB_reg>.
-    Found 1-bit register for signal <SF0_reg>.
-    Found 1-bit register for signal <SF1_reg>.
-    Found 1-bit register for signal <SF2_reg>.
-    Found 1-bit register for signal <SF3_reg>.
-    Found 1-bit register for signal <SP0_reg>.
-    Found 1-bit register for signal <SP1_reg>.
-    Found 1-bit register for signal <SP2_reg>.
-    Found 1-bit register for signal <SP3_reg>.
-    Summary:
-	inferred   9 D-type flip-flop(s).
-Unit <gtia_priority> synthesized.
-
-
-Synthesizing Unit <wide_delay_line_4>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl".
-    Found 12-bit register for signal <shift_reg>.
-    Summary:
-	inferred  12 D-type flip-flop(s).
-Unit <wide_delay_line_4> synthesized.
-
-
-Synthesizing Unit <wide_delay_line_5>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl".
-    Found 6-bit register for signal <shift_reg>.
-    Summary:
-	inferred   6 D-type flip-flop(s).
-Unit <wide_delay_line_5> synthesized.
-
-
-Synthesizing Unit <wide_delay_line_6>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl".
-    Found 8-bit register for signal <shift_reg>.
-    Summary:
-	inferred   8 D-type flip-flop(s).
-Unit <wide_delay_line_6> synthesized.
-
-
-Synthesizing Unit <wide_delay_line_7>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl".
-    Found 14-bit register for signal <shift_reg>.
-    Summary:
-	inferred  14 D-type flip-flop(s).
-Unit <wide_delay_line_7> synthesized.
-
-
-Synthesizing Unit <wide_delay_line_8>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl".
-    Found 40-bit register for signal <shift_reg>.
-    Summary:
-	inferred  40 D-type flip-flop(s).
-Unit <wide_delay_line_8> synthesized.
-
-
-Synthesizing Unit <wide_delay_line_9>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl".
-    Found 32-bit register for signal <shift_reg>.
-    Summary:
-	inferred  32 D-type flip-flop(s).
-Unit <wide_delay_line_9> synthesized.
-
-
-Synthesizing Unit <basic>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/basic.vhdl".
-WARNING:Xst:1781 - Signal <ROM> is used but never assigned. Tied to default value.
-    Found 8192x8-bit ROM for signal <rdata>.
-    Found 8-bit register for signal <q>.
-    Summary:
-	inferred   1 ROM(s).
-	inferred   8 D-type flip-flop(s).
-Unit <basic> synthesized.
-
-
-Synthesizing Unit <os16>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/os16.vhdl".
-WARNING:Xst:1781 - Signal <ROM> is used but never assigned. Tied to default value.
-    Found 16384x8-bit ROM for signal <rdata>.
-    Found 8-bit register for signal <q>.
-    Summary:
-	inferred   1 ROM(s).
-	inferred   8 D-type flip-flop(s).
-Unit <os16> synthesized.
-
-
-Synthesizing Unit <generic_ram_infer_2>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/generic_ram_infer.vhdl".
-    Found 16384x8-bit single-port RAM <Mram_ram_block> for signal <ram_block>.
-    Found 8-bit register for signal <q>.
-    Summary:
-	inferred   1 RAM(s).
-	inferred   8 D-type flip-flop(s).
-Unit <generic_ram_infer_2> synthesized.
-
-
-Synthesizing Unit <Replay_VideoTiming>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_VideoTiming.vhd".
-    Register <h_sync_l> equivalent to <h_sync> has been removed
-    Register <v_sync_l> equivalent to <v_sync> has been removed
-    Using one-hot encoding for signal <standard_ana>.
-    Found 15-bit subtractor for signal <$sub0000> created at line 181.
-    Found 15-bit subtractor for signal <$sub0001> created at line 185.
-    Found 14-bit register for signal <act_h_cnt>.
-    Found 14-bit adder for signal <act_h_cnt$addsub0000> created at line 526.
-    Found 14-bit register for signal <act_v_cnt>.
-    Found 14-bit adder for signal <act_v_cnt$addsub0000> created at line 534.
-    Found 14-bit adder carry out for signal <add0000$addsub0000> created at line 188.
-    Found 1-bit register for signal <ana_cs>.
-    Found 1-bit register for signal <ana_de>.
-    Found 1-bit register for signal <ana_hs>.
-    Found 1-bit register for signal <ana_vs>.
-    Found 5-bit register for signal <cs_gate>.
-    Found 1-bit register for signal <dig_de>.
-    Found 1-bit register for signal <dig_ha>.
-    Found 1-bit register for signal <dig_hs>.
-    Found 1-bit register for signal <dig_sof>.
-    Found 1-bit register for signal <dig_sol>.
-    Found 1-bit register for signal <dig_va>.
-    Found 1-bit register for signal <dig_vs>.
-    Found 1-bit register for signal <h_act>.
-    Found 14-bit comparator equal for signal <h_act$cmp_eq0000> created at line 246.
-    Found 1-bit register for signal <h_ana_act>.
-    Found 14-bit comparator equal for signal <h_ana_act$cmp_eq0000> created at line 278.
-    Found 14-bit comparator equal for signal <h_ana_act$cmp_eq0001> created at line 277.
-    Found 1-bit register for signal <h_ana_b1>.
-    Found 14-bit comparator equal for signal <h_ana_b1$cmp_eq0000> created at line 296.
-    Found 1-bit register for signal <h_ana_b2>.
-    Found 14-bit comparator equal for signal <h_ana_b2$cmp_eq0000> created at line 302.
-    Found 14-bit comparator equal for signal <h_ana_b2$cmp_eq0001> created at line 301.
-    Found 1-bit register for signal <h_ana_n1>.
-    Found 14-bit comparator equal for signal <h_ana_n1$cmp_eq0000> created at line 284.
-    Found 1-bit register for signal <h_ana_n2>.
-    Found 14-bit comparator equal for signal <h_ana_n2$cmp_eq0000> created at line 290.
-    Found 14-bit register for signal <h_cnt>.
-    Found 14-bit adder for signal <h_cnt$addsub0000> created at line 242.
-    Found 1-bit register for signal <h_eol>.
-    Found 14-bit comparator equal for signal <h_eol$cmp_eq0000> created at line 237.
-    Found 1-bit register for signal <h_eol_t1>.
-    Found 1-bit register for signal <h_sol>.
-    Found 1-bit register for signal <h_sync>.
-    Found 14-bit comparator equal for signal <h_sync$cmp_eq0000> created at line 254.
-    Found 14-bit comparator equal for signal <h_sync$cmp_eq0001> created at line 252.
-    Found 1-bit register for signal <h_vgate_f1>.
-    Found 1-bit register for signal <h_vgate_f2>.
-    Found 14-bit register for signal <param_c.h_len>.
-    Found 14-bit subtractor for signal <param_c.h_len$sub0000> created at line 180.
-    Found 14-bit register for signal <param_c.h_start_2nd>.
-    Found 14-bit adder for signal <param_c.h_start_2nd$addsub0000> created at line 192.
-    Found 14-bit subtractor for signal <param_c.h_start_2nd$sub0001> created at line 192.
-    Found 14-bit register for signal <param_c.h_start_act>.
-    Found 14-bit subtractor for signal <param_c.h_start_act$sub0001> created at line 181.
-    Found 14-bit register for signal <param_c.h_start_ana>.
-    Found 14-bit adder for signal <param_c.h_start_ana$add0000> created at line 184.
-    Found 14-bit register for signal <param_c.h_start_sync>.
-    Found 14-bit subtractor for signal <param_c.h_start_sync$sub0000> created at line 187.
-    Found 14-bit register for signal <param_c.h_stop_ana>.
-    Found 14-bit subtractor for signal <param_c.h_stop_ana$sub0000> created at line 185.
-    Found 14-bit register for signal <param_c.h_stop_bd1>.
-    Found 14-bit adder for signal <param_c.h_stop_bd1$add0000> created at line 197.
-    Found 14-bit register for signal <param_c.h_stop_bd2>.
-    Found 14-bit adder for signal <param_c.h_stop_bd2$add0000> created at line 198.
-    Found 14-bit register for signal <param_c.h_stop_eq1>.
-    Found 14-bit adder for signal <param_c.h_stop_eq1$add0000> created at line 195.
-    Found 14-bit register for signal <param_c.h_stop_eq2>.
-    Found 14-bit adder for signal <param_c.h_stop_eq2$add0000> created at line 196.
-    Found 14-bit register for signal <param_c.h_stop_sync>.
-    Found 14-bit subtractor for signal <param_c.h_stop_sync$sub0000> created at line 188.
-    Found 2-bit register for signal <standard_ana>.
-    Found 1-bit register for signal <v_act>.
-    Found 14-bit comparator equal for signal <v_act$cmp_eq0000> created at line 366.
-    Found 14-bit comparator equal for signal <v_act$cmp_eq0001> created at line 367.
-    Found 14-bit comparator equal for signal <v_act$cmp_eq0002> created at line 369.
-    Found 14-bit comparator not equal for signal <v_act$cmp_ne0000> created at line 371.
-    Found 14-bit comparator not equal for signal <v_act$cmp_ne0001> created at line 369.
-    Found 14-bit comparator not equal for signal <v_act$cmp_ne0002> created at line 367.
-    Found 14-bit comparator not equal for signal <v_act$cmp_ne0003> created at line 366.
-    Found 14-bit register for signal <v_cnt>.
-    Found 14-bit adder for signal <v_cnt$addsub0000> created at line 346.
-    Found 1-bit register for signal <v_f2>.
-    Found 14-bit comparator equal for signal <v_f2$cmp_eq0000> created at line 376.
-    Found 14-bit comparator not equal for signal <v_f2$cmp_ne0000> created at line 377.
-    Found 14-bit comparator not equal for signal <v_f2$cmp_ne0001> created at line 376.
-    Found 1-bit register for signal <v_sof>.
-    Found 1-bit register for signal <v_sync>.
-    Found 14-bit comparator equal for signal <v_sync$cmp_eq0001> created at line 384.
-    Found 14-bit comparator equal for signal <v_sync$cmp_eq0002> created at line 387.
-    Found 14-bit comparator not equal for signal <v_sync$cmp_ne0000> created at line 390.
-    Found 14-bit comparator not equal for signal <v_sync$cmp_ne0001> created at line 387.
-    Found 14-bit comparator not equal for signal <v_sync$cmp_ne0002> created at line 384.
-    Summary:
-	inferred 230 D-type flip-flop(s).
-	inferred  19 Adder/Subtractor(s).
-	inferred  26 Comparator(s).
-Unit <Replay_VideoTiming> synthesized.
-
-
-Synthesizing Unit <Replay_SPI8>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_SPI8.vhd".
-    Found 4-bit register for signal <o_rxbytecnt>.
-    Found 1-bit register for signal <o_rdy>.
-    Found 8-bit register for signal <o_rxdata>.
-    Found 8-bit register for signal <o_rxcmd>.
-    Found 1-bit register for signal <o_sof>.
-    Found 8-bit register for signal <o_rxbytesel>.
-    Found 3-bit up counter for signal <bit_cnt>.
-    Found 8-bit register for signal <byte>.
-    Found 4-bit up counter for signal <byte_cnt>.
-    Found 7-bit register for signal <din>.
-    Found 8-bit register for signal <dout>.
-    Summary:
-	inferred   2 Counter(s).
-	inferred  45 D-type flip-flop(s).
-Unit <Replay_SPI8> synthesized.
-
-
-Synthesizing Unit <Replay_I2C>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_I2C.vhd".
-WARNING:Xst:647 - Input <i_spc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-    Found finite state machine <FSM_6> for signal <State>.
-    -----------------------------------------------------------------------
-    | States             | 8                                              |
-    | Transitions        | 28                                             |
-    | Inputs             | 4                                              |
-    | Outputs            | 8                                              |
-    | Clock              | i_clk                     (rising_edge)        |
-    | Clock enable       | State$not0000             (positive)           |
-    | Reset              | i_rst                     (positive)           |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | s_idle                                         |
-    | Power Up State     | s_idle                                         |
-    | Encoding           | automatic                                      |
-    | Implementation     | automatic                                      |
-    -----------------------------------------------------------------------
-    Found 1-bit register for signal <o_drive_spc_low>.
-    Found 1-bit register for signal <o_drive_sda_low>.
-    Found 1-bit register for signal <o_drive_spd_low>.
-    Found 1-bit register for signal <actv>.
-    Found 7-bit register for signal <devid>.
-    Found 9-bit register for signal <din_shift>.
-    Found 8-bit register for signal <rab>.
-    Found 1-bit register for signal <rw_l>.
-    Found 1-bit register for signal <scl_falling<0>>.
-    Found 4-bit register for signal <scl_in>.
-    Found 1-bit register for signal <scl_r>.
-    Found 1-bit 4-to-1 multiplexer for signal <scl_r$mux0000>.
-    Found 1-bit register for signal <scl_rising<0>>.
-    Found 1-bit register for signal <sda_falling<0>>.
-    Found 4-bit register for signal <sda_in>.
-    Found 1-bit register for signal <sda_r>.
-    Found 1-bit 4-to-1 multiplexer for signal <sda_r$mux0000>.
-    Found 1-bit register for signal <sda_rising<0>>.
-    Found 2-bit register for signal <spd_in>.
-    Found 8-bit register for signal <write_data>.
-    Found 1-bit register for signal <write_ena>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred  45 D-type flip-flop(s).
-	inferred   2 Multiplexer(s).
-Unit <Replay_I2C> synthesized.
-
-
-Synthesizing Unit <Replay_ClockGen>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_ClockGen_Sync.vhd".
-WARNING:Xst:646 - Signal <status> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <ps_rst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <clk_b_dcm_div> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 1-bit register for signal <o_rst_ram_capture>.
-    Found 8-bit down counter for signal <ctl_divider_100us>.
-    Found 8-bit down counter for signal <ctl_divider_1us>.
-    Found 8-bit comparator equal for signal <new_phase$cmp_eq0000> created at line 530.
-    Found 8-bit comparator greater for signal <new_phase$cmp_gt0000> created at line 531.
-    Found 1-bit register for signal <ps_en>.
-    Found 1-bit register for signal <ps_eq>.
-    Found 1-bit register for signal <ps_eq_meta>.
-    Found 1-bit register for signal <ps_inc>.
-    Found 8-bit up accumulator for signal <ps_phase>.
-    Found 1-bit register for signal <ps_state>.
-    Found 1-bit register for signal <rst_aux>.
-    Found 1-bit register for signal <rst_ctl>.
-    Found 1-bit register for signal <rst_ctl_hard>.
-    Found 1-bit register for signal <rst_ram>.
-    Found 1-bit register for signal <rst_video>.
-    Found 1-bit register for signal <rst_video_hard>.
-    Found 1-bit register for signal <tick_ctl_100us>.
-    Found 1-bit register for signal <tick_ctl_1us>.
-    Summary:
-	inferred   2 Counter(s).
-	inferred   1 Accumulator(s).
-	inferred  14 D-type flip-flop(s).
-	inferred   2 Comparator(s).
-Unit <Replay_ClockGen> synthesized.
-
-
-Synthesizing Unit <Replay_Video>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Video.vhd".
-WARNING:Xst:647 - Input <i_video_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:646 - Signal <vidout_debug_r> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <vidout_debug_g> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <vidout_debug_b> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 1-bit register for signal <o_video_de>.
-    Found 1-bit register for signal <o_video_hsync>.
-    Found 1-bit register for signal <o_video_rst_l>.
-    Found 1-bit tristate buffer for signal <b_video_ddc_clk>.
-    Found 1-bit register for signal <o_video_vsync>.
-    Found 1-bit tristate buffer for signal <b_video_ddc_data>.
-    Found 1-bit register for signal <o_video_h>.
-    Found 1-bit register for signal <o_video_v>.
-    Found 4-bit register for signal <ana_hs_dac_t>.
-    Found 4-bit register for signal <ana_vs_dac_t>.
-    Found 1-bit register for signal <vidout_clamp>.
-    Found 12-bit register for signal <vidout_falling_t1>.
-    Summary:
-	inferred  27 D-type flip-flop(s).
-	inferred   2 Tristate(s).
-Unit <Replay_Video> synthesized.
-
-
-Synthesizing Unit <Replay_VideoConverter>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_VideoConverter.vhd".
-WARNING:Xst:646 - Signal <vidin_match_n_s> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <cs_trig> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <cs_control0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <cs_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-    Found 2048x24-bit dual-port RAM <Mram_dupo_buf_s> for signal <dupo_buf_s>.
-    Found 1-bit register for signal <o_vid_sync.ana_vs>.
-    Found 1-bit register for signal <o_vid_sync.dig_vs>.
-    Found 24-bit register for signal <o_vid_rgb>.
-    Found 1-bit register for signal <o_vid_sync.ana_de>.
-    Found 1-bit register for signal <o_vid_sync.ana_hs>.
-    Found 1-bit register for signal <o_vid_sync.dig_de>.
-    Found 1-bit register for signal <o_vid_sync.dig_hs>.
-    Found 24-bit register for signal <bufout_dat_s>.
-    Found 32-bit comparator greater for signal <bufout_en_s$cmp_gt0000> created at line 456.
-    Found 32-bit comparator greater for signal <bufout_en_s$cmp_gt0001> created at line 456.
-    Found 14-bit comparator lessequal for signal <bufout_en_s$cmp_le0000> created at line 456.
-    Found 14-bit comparator lessequal for signal <bufout_en_s$cmp_le0001> created at line 456.
-    Found 3-bit register for signal <vidin_fsync_s>.
-    Found 1-bit register for signal <vidin_fsyncd_s>.
-    Found 14-bit up counter for signal <vidin_hcnt_s>.
-    Found 1-bit register for signal <vidin_hsyncdn_s>.
-    Found 1-bit register for signal <vidin_sof_detected_s>.
-    Found 14-bit up counter for signal <vidin_vcnt_s>.
-    Found 1-bit register for signal <vidin_vsyncdn_s>.
-    Found 1-bit register for signal <vidout_sync_1st_s.ana_de>.
-    Found 1-bit register for signal <vidout_sync_1st_s.ana_hs>.
-    Found 1-bit register for signal <vidout_sync_1st_s.ana_vs>.
-    Found 1-bit register for signal <vidout_sync_1st_s.dig_de>.
-    Found 1-bit register for signal <vidout_sync_1st_s.dig_hs>.
-    Found 1-bit register for signal <vidout_sync_1st_s.dig_vs>.
-    Found 28-bit register for signal <vidout_watchdogcnt_s>.
-    Found 28-bit subtractor for signal <vidout_watchdogcnt_s$addsub0000> created at line 376.
-    Found 14x14-bit multiplier for signal <vidout_watchdogcnt_s$mult0001> created at line 364.
-    Found 28-bit adder for signal <vidout_watchdogcnt_s$mux0000> created at line 370.
-    Summary:
-	inferred   1 RAM(s).
-	inferred   2 Counter(s).
-	inferred  95 D-type flip-flop(s).
-	inferred   2 Adder/Subtractor(s).
-	inferred   1 Multiplier(s).
-	inferred   4 Comparator(s).
-Unit <Replay_VideoConverter> synthesized.
-
-
-Synthesizing Unit <cpu>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/cpu.vhd".
-WARNING:Xst:646 - Signal <not_rdy> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <debugY> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <debugX> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <debugS> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <debugPc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <debugOpcode> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <debugA> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <CPU_ENABLE_RESET> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 1-bit register for signal <nmi_n_reg>.
-    Found 1-bit register for signal <nmi_pending_reg>.
-    Summary:
-	inferred   2 D-type flip-flop(s).
-Unit <cpu> synthesized.
-
-
-Synthesizing Unit <zpu_glue>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_glue.vhdl".
-WARNING:Xst:646 - Signal <zpu_debug.stk_b> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <zpu_debug.stk_a> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <zpu_debug.sp> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <zpu_debug.pc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <zpu_debug.opcode> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <zpu_debug.b_inst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <zpu_break> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Using one-hot encoding for signal <result_reg>.
-INFO:Xst:2117 - HDL ADVISOR - Mux Selector <result_reg> of Case statement line 334 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
-   	- add an 'INIT' attribute on signal <result_reg> (optimization is then done without any risk)
-   	- use the attribute 'signal_encoding user' to avoid onehot optimization
-   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
-INFO:Xst:2117 - HDL ADVISOR - Mux Selector <result_reg> of Case statement line 334 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
-   	- add an 'INIT' attribute on signal <result_reg> (optimization is then done without any risk)
-   	- use the attribute 'signal_encoding user' to avoid onehot optimization
-   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
-INFO:Xst:2117 - HDL ADVISOR - Mux Selector <result_reg> of Case statement line 334 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
-   	- add an 'INIT' attribute on signal <result_reg> (optimization is then done without any risk)
-   	- use the attribute 'signal_encoding user' to avoid onehot optimization
-   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
-INFO:Xst:2117 - HDL ADVISOR - Mux Selector <result_reg> of Case statement line 334 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
-   	- add an 'INIT' attribute on signal <result_reg> (optimization is then done without any risk)
-   	- use the attribute 'signal_encoding user' to avoid onehot optimization
-   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
-INFO:Xst:2117 - HDL ADVISOR - Mux Selector <result_reg> of Case statement line 334 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
-   	- add an 'INIT' attribute on signal <result_reg> (optimization is then done without any risk)
-   	- use the attribute 'signal_encoding user' to avoid onehot optimization
-   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
-INFO:Xst:2117 - HDL ADVISOR - Mux Selector <result_reg> of Case statement line 334 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
-   	- add an 'INIT' attribute on signal <result_reg> (optimization is then done without any risk)
-   	- use the attribute 'signal_encoding user' to avoid onehot optimization
-   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
-INFO:Xst:2117 - HDL ADVISOR - Mux Selector <result_reg> of Case statement line 334 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
-   	- add an 'INIT' attribute on signal <result_reg> (optimization is then done without any risk)
-   	- use the attribute 'signal_encoding user' to avoid onehot optimization
-   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
-INFO:Xst:2117 - HDL ADVISOR - Mux Selector <result_reg> of Case statement line 334 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
-   	- add an 'INIT' attribute on signal <result_reg> (optimization is then done without any risk)
-   	- use the attribute 'signal_encoding user' to avoid onehot optimization
-   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
-    Found 1-bit register for signal <memory_ready_reg>.
-    Found 18-bit register for signal <result_reg>.
-    Found 1-bit register for signal <ZPU_16BIT_WRITE_ENABLE_reg>.
-    Found 1-bit register for signal <ZPU_32BIT_WRITE_ENABLE_reg>.
-    Found 1-bit register for signal <ZPU_8BIT_WRITE_ENABLE_reg>.
-    Found 24-bit register for signal <zpu_addr_reg>.
-    Found 32-bit register for signal <zpu_di_reg>.
-    Found 32-bit register for signal <ZPU_DO_reg>.
-    Found 1-bit register for signal <zpu_memory_fetch_pending_reg>.
-    Found 1-bit register for signal <ZPU_READ_reg>.
-    Summary:
-	inferred  94 D-type flip-flop(s).
-Unit <zpu_glue> synthesized.
-
-
-Synthesizing Unit <pia>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pia.vhdl".
-WARNING:Xst:646 - Signal <write_ora> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Register <CB1_reg> equivalent to <CA1_reg> has been removed
-    Found 1-bit register for signal <ca1_edge_reg>.
-    Found 1-bit register for signal <CA1_reg>.
-    Found 1-bit register for signal <ca2_edge_reg>.
-    Found 1-bit register for signal <CA2_output_reg>.
-    Found 1-bit 4-to-1 multiplexer for signal <CA2_output_reg$mux0000> created at line 294.
-    Found 1-bit register for signal <CA2_reg>.
-    Found 1-bit register for signal <cb1_edge_reg>.
-    Found 1-bit register for signal <cb2_edge_reg>.
-    Found 1-bit register for signal <CB2_output_reg>.
-    Found 1-bit 4-to-1 multiplexer for signal <CB2_output_reg$mux0000> created at line 349.
-    Found 1-bit register for signal <CB2_reg>.
-    Found 2-bit register for signal <irqa_reg>.
-    Found 2-bit register for signal <irqb_reg>.
-    Found 6-bit register for signal <porta_control_reg>.
-    Found 8-bit register for signal <porta_direction_reg>.
-    Found 8-bit register for signal <porta_input_reg>.
-    Found 8-bit register for signal <porta_output_reg>.
-    Found 6-bit register for signal <portb_control_reg>.
-    Found 8-bit register for signal <portb_direction_reg>.
-    Found 8-bit register for signal <portb_input_reg>.
-    Found 8-bit register for signal <portb_output_reg>.
-    Summary:
-	inferred  73 D-type flip-flop(s).
-	inferred   2 Multiplexer(s).
-Unit <pia> synthesized.
-
-
-Synthesizing Unit <shared_enable>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/shared_enable.vhdl".
-    Found 1-bit register for signal <cpu_extra_enable_reg>.
-    Found 1-bit register for signal <oldcpu_extra_enable_reg>.
-    Found 6-bit adder for signal <throttle_count_next$addsub0000> created at line 99.
-    Found 6-bit comparator equal for signal <throttle_count_next$cmp_eq0000> created at line 103.
-    Found 6-bit register for signal <throttle_count_reg>.
-    Found 1-bit register for signal <turbo_reg>.
-    Summary:
-	inferred   9 D-type flip-flop(s).
-	inferred   1 Adder/Subtractor(s).
-	inferred   1 Comparator(s).
-Unit <shared_enable> synthesized.
-
-
-Synthesizing Unit <gtia>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/gtia.vhdl".
-WARNING:Xst:646 - Signal <an_prev3_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found finite state machine <FSM_7> for signal <pmg_dma_state_reg>.
-    -----------------------------------------------------------------------
-    | States             | 7                                              |
-    | Transitions        | 38                                             |
-    | Inputs             | 7                                              |
-    | Outputs            | 5                                              |
-    | Clock              | CLK                       (rising_edge)        |
-    | Reset              | RESET_N                   (negative)           |
-    | Reset type         | asynchronous                                   |
-    | Reset State        | 101                                            |
-    | Encoding           | automatic                                      |
-    | Implementation     | automatic                                      |
-    -----------------------------------------------------------------------
-    Found 8-bit register for signal <active_bk_modify_reg>.
-    Found 8-bit register for signal <active_bk_valid_reg>.
-    Found 2-bit register for signal <active_hr_reg>.
-    Found 1-bit 4-to-1 multiplexer for signal <active_pf2_collision_live$mux0002> created at line 687.
-    Found 3-bit register for signal <an_prev2_reg>.
-    Found 3-bit register for signal <an_prev_reg>.
-    Found 7-bit register for signal <colbk_raw_reg>.
-    Found 8-bit register for signal <COLOUR_REG>.
-    Found 7-bit register for signal <colpf0_raw_reg>.
-    Found 7-bit register for signal <colpf1_raw_reg>.
-    Found 7-bit register for signal <colpf2_raw_reg>.
-    Found 7-bit register for signal <colpf3_raw_reg>.
-    Found 7-bit register for signal <colpm0_raw_reg>.
-    Found 7-bit register for signal <colpm1_raw_reg>.
-    Found 7-bit register for signal <colpm2_raw_reg>.
-    Found 7-bit register for signal <colpm3_raw_reg>.
-    Found 4-bit register for signal <consol_output_reg>.
-    Found 3-bit register for signal <gractl_reg>.
-    Found 8-bit register for signal <grafm_reg>.
-    Found 8-bit register for signal <grafp0_reg>.
-    Found 8-bit register for signal <grafp1_reg>.
-    Found 8-bit register for signal <grafp2_reg>.
-    Found 8-bit register for signal <grafp3_reg>.
-    Found 1-bit register for signal <hblank_reg>.
-    Found 1-bit register for signal <highres_reg>.
-    Found 8-bit register for signal <hposm0_raw_reg>.
-    Found 8-bit register for signal <hposm1_raw_reg>.
-    Found 8-bit register for signal <hposm2_raw_reg>.
-    Found 8-bit register for signal <hposm3_raw_reg>.
-    Found 8-bit register for signal <hposp0_raw_reg>.
-    Found 8-bit register for signal <hposp1_raw_reg>.
-    Found 8-bit register for signal <hposp2_raw_reg>.
-    Found 8-bit register for signal <hposp3_raw_reg>.
-    Found 8-bit register for signal <HRCOLOUR_REG>.
-    Found 1-bit register for signal <hsync_reg>.
-    Found 4-bit register for signal <m0pf_reg>.
-    Found 4-bit register for signal <m0pl_reg>.
-    Found 4-bit register for signal <m1pf_reg>.
-    Found 4-bit register for signal <m1pl_reg>.
-    Found 4-bit register for signal <m2pf_reg>.
-    Found 4-bit register for signal <m2pl_reg>.
-    Found 4-bit register for signal <m3pf_reg>.
-    Found 4-bit register for signal <m3pl_reg>.
-    Found 1-bit register for signal <odd_scanline_reg>.
-    Found 4-bit register for signal <p0pf_reg>.
-    Found 4-bit register for signal <p0pl_reg>.
-    Found 4-bit register for signal <p1pf_reg>.
-    Found 4-bit register for signal <p1pl_reg>.
-    Found 4-bit register for signal <p2pf_reg>.
-    Found 4-bit register for signal <p2pl_reg>.
-    Found 4-bit register for signal <p3pf_reg>.
-    Found 4-bit register for signal <p3pl_reg>.
-    Found 8-bit register for signal <prior_raw_reg>.
-    Found 8-bit register for signal <sizem_raw_reg>.
-    Found 2-bit register for signal <sizep0_raw_reg>.
-    Found 2-bit register for signal <sizep1_raw_reg>.
-    Found 2-bit register for signal <sizep2_raw_reg>.
-    Found 2-bit register for signal <sizep3_raw_reg>.
-    Found 1-bit register for signal <trig0_reg>.
-    Found 1-bit register for signal <trig1_reg>.
-    Found 1-bit register for signal <trig2_reg>.
-    Found 1-bit register for signal <trig3_reg>.
-    Found 8-bit register for signal <vdelay_reg>.
-    Found 1-bit register for signal <vsync_reg>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred 319 D-type flip-flop(s).
-	inferred   1 Multiplexer(s).
-Unit <gtia> synthesized.
-
-
-Synthesizing Unit <reg_file_1>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/reg_file.vhdl".
-    Found 128-bit register for signal <digit_reg>.
-    Summary:
-	inferred 128 D-type flip-flop(s).
-Unit <reg_file_1> synthesized.
-
-
-Synthesizing Unit <reg_file_2>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/reg_file.vhdl".
-    Found 256-bit register for signal <digit_reg>.
-INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred for signal <digit_reg>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
-    Summary:
-	inferred 256 D-type flip-flop(s).
-Unit <reg_file_2> synthesized.
-
-
-Synthesizing Unit <internalromram>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/internalromram.vhd".
-WARNING:Xst:647 - Input <ROM_ADDR<21:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <ROM_ADDR<14>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <RAM_ADDR<18:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-    Found 1-bit register for signal <ram_request_reg>.
-    Found 1-bit register for signal <rom_request_reg>.
-    Summary:
-	inferred   2 D-type flip-flop(s).
-Unit <internalromram> synthesized.
-
-
-Synthesizing Unit <covox>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/covox.vhd".
-    Found 8-bit register for signal <channel0_reg>.
-    Found 8-bit register for signal <channel1_reg>.
-    Found 8-bit register for signal <channel2_reg>.
-    Found 8-bit register for signal <channel3_reg>.
-    Summary:
-	inferred  32 D-type flip-flop(s).
-Unit <covox> synthesized.
-
-
-Synthesizing Unit <reg_file_3>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/reg_file.vhdl".
-WARNING:Xst:646 - Signal <addr_decoded<63:48>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 384-bit register for signal <digit_reg>.
-INFO:Xst:738 - HDL ADVISOR - 384 flip-flops were inferred for signal <digit_reg>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
-    Summary:
-	inferred 384 D-type flip-flop(s).
-Unit <reg_file_3> synthesized.
-
-
-Synthesizing Unit <pokey_countdown_timer>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/countdown_timer.vhdl".
-    Found 8-bit 4-to-1 multiplexer for signal <count_next>.
-    Found 8-bit subtractor for signal <count_next$addsub0000> created at line 82.
-    Found 8-bit register for signal <count_reg>.
-    Summary:
-	inferred   8 D-type flip-flop(s).
-	inferred   1 Adder/Subtractor(s).
-	inferred   8 Multiplexer(s).
-Unit <pokey_countdown_timer> synthesized.
-
-
-Synthesizing Unit <ps2_rom>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd".
-Unit <ps2_rom> synthesized.
-
-
-Synthesizing Unit <kcpsm3>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd".
-Unit <kcpsm3> synthesized.
-
-
-Synthesizing Unit <Replay_DDRCtrl_Datapath>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_DDRCtrl_Datapath.vhd".
-WARNING:Xst:646 - Signal <wpipe<2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <rpipe<2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <r_valid> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <r_ena> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <r_empty> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <dqs_q1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <dqs_q0> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <dq_rst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Register <dqs_oe0_l> equivalent to <dq_oe0_m1_l> has been removed
-    Found 2-bit register for signal <dm_d0>.
-    Found 2-bit register for signal <dm_d0_r90>.
-    Found 2-bit register for signal <dm_d1>.
-    Found 2-bit register for signal <dm_d1_r90>.
-    Found 16-bit register for signal <dq_d0>.
-    Found 16-bit register for signal <dq_d0_r90>.
-    Found 16-bit register for signal <dq_d1>.
-    Found 16-bit register for signal <dq_d1_r90>.
-    Found 1-bit register for signal <dq_ena>.
-    Found 1-bit register for signal <dq_oe0_m1_l>.
-    Found 1-bit register for signal <dq_oe1_m1_l>.
-    Found 1-bit register for signal <dq_st_hold>.
-    Found 1-bit register for signal <dqs_enable>.
-    Found 1-bit register for signal <dqs_oe1_l>.
-    Found 13-bit register for signal <ram_addr>.
-    Found 2-bit register for signal <ram_ba>.
-    Found 1-bit register for signal <ram_cas_l>.
-    Found 1-bit register for signal <ram_cke>.
-    Found 1-bit register for signal <ram_cs_l>.
-    Found 1-bit register for signal <ram_ras_l>.
-    Found 1-bit register for signal <ram_we_l>.
-    Found 4-bit up counter for signal <rbuf_w_addr>.
-    Found 3-bit register for signal <rpipe>.
-    Found 3-bit register for signal <wpipe>.
-    Summary:
-	inferred   1 Counter(s).
-	inferred 104 D-type flip-flop(s).
-Unit <Replay_DDRCtrl_Datapath> synthesized.
-
-
-Synthesizing Unit <FIFO_SyncSRL_D16>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/FIFO_SyncSRL_D16.vhd".
-    Found 4-bit up accumulator for signal <r_addr>.
-    Found 1-bit register for signal <valid>.
-    Summary:
-	inferred   1 Accumulator(s).
-	inferred   1 D-type flip-flop(s).
-Unit <FIFO_SyncSRL_D16> synthesized.
-
-
-Synthesizing Unit <FONT0>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/font0_rom.vhd".
-Unit <FONT0> synthesized.
-
-
-Synthesizing Unit <FONT1>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/font1_rom.vhd".
-Unit <FONT1> synthesized.
-
-
-Synthesizing Unit <FONT2>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/font2_rom.vhd".
-Unit <FONT2> synthesized.
-
-
-Synthesizing Unit <FIFO_SyncBlock_D2048_W8>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/FIFO_SyncBlock_D2048_W8.vhd".
-    Found 4x12-bit ROM for signal <offset$mux0000> created at line 109.
-    Found 1-bit register for signal <empty_i>.
-    Found 1-bit 4-to-1 multiplexer for signal <empty_i$mux0000> created at line 109.
-    Found 1-bit register for signal <full_i>.
-    Found 1-bit 4-to-1 multiplexer for signal <full_i$mux0000> created at line 109.
-    Found 12-bit up accumulator for signal <level>.
-    Found 11-bit up counter for signal <r_addr>.
-    Found 1-bit register for signal <valid>.
-    Found 11-bit up counter for signal <w_addr>.
-    Summary:
-	inferred   1 ROM(s).
-	inferred   2 Counter(s).
-	inferred   1 Accumulator(s).
-	inferred   3 D-type flip-flop(s).
-	inferred   2 Multiplexer(s).
-Unit <FIFO_SyncBlock_D2048_W8> synthesized.
-
-
-Synthesizing Unit <Replay_FileIO>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_FileIO_Sync.vhd".
-WARNING:Xst:647 - Input <i_fch_fm_core.data_valid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <i_hch_fm_core.data_valid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:646 - Signal <spi_rx_cmd<3:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <spi_data_t> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <spi_cmd_low<15:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <spi_cmd_high<15:12>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <spi_cmd_high<9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <spi_cmd_high<3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <spi_cmd_high<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <spi_byte_sel<7:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <spi_byte_cnt> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <mem_fifo_level<15:12>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <mem_fifo_level<9:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Register <o_hch_to_core.pos> equivalent to <o_fch_to_core.pos> has been removed
-    Register <o_hch_to_core.update> equivalent to <o_fch_to_core.update> has been removed
-    Register <spi_hch_tx> equivalent to <spi_fch_tx> has been removed
-    Found 4-bit register for signal <o_fch_to_core.inserted>.
-    Found 1-bit register for signal <o_fch_to_core.data_taken>.
-    Found 1-bit register for signal <o_hch_to_core.cmd_err>.
-    Found 1-bit register for signal <o_fch_to_core.cmd_done>.
-    Found 1-bit register for signal <o_hch_to_core.cmd_ack>.
-    Found 1-bit register for signal <o_fch_to_core.cmd_err>.
-    Found 1-bit register for signal <o_hch_to_core.status_we>.
-    Found 1-bit register for signal <o_fch_to_core.cmd_ack>.
-    Found 8-bit register for signal <o_hch_to_core.data>.
-    Found 1-bit register for signal <o_hch_to_core.cmd_done>.
-    Found 4-bit register for signal <o_fch_to_core.writable>.
-    Found 1-bit register for signal <o_hch_to_core.data_we>.
-    Found 1-bit register for signal <o_fch_to_core.data_we>.
-    Found 1-bit register for signal <o_fch_to_core.update>.
-    Found 1-bit register for signal <o_hch_to_core.data_taken>.
-    Found 4-bit register for signal <o_fch_to_core.pos>.
-    Found 8-bit register for signal <o_hch_to_core.status>.
-    Found 8-bit register for signal <o_fch_to_core.data>.
-    Found 32-bit register for signal <mem_addr>.
-    Found 32-bit adder for signal <mem_addr$add0000> created at line 495.
-    Found 1-bit register for signal <mem_fifo_rst>.
-    Found 10-bit register for signal <mem_len>.
-    Found 10-bit subtractor for signal <mem_len$sub0000> created at line 517.
-    Found 1-bit register for signal <mem_rd>.
-    Found 1-bit register for signal <mem_rd_ena>.
-    Found 8-bit register for signal <spi_byte_sel>.
-    Found 16-bit register for signal <spi_cmd_high>.
-    Found 16-bit register for signal <spi_cmd_low>.
-    Found 4-bit register for signal <spi_cs_meta>.
-    Found 8-bit register for signal <spi_data>.
-    Found 1-bit register for signal <spi_done>.
-    Found 8-bit register for signal <spi_fch_tx>.
-    Found 1-bit register for signal <spi_first>.
-    Found 1-bit register for signal <spi_mem_fifo_hfull>.
-    Found 8-bit register for signal <spi_mem_fifo_tx>.
-    Found 1-bit register for signal <spi_mem_fifo_valid>.
-    Found 1-bit register for signal <spi_mem_rd_ena>.
-    Found 4-bit up counter for signal <spi_pos_cnt>.
-    Found 1-bit register for signal <spi_rx_rdy_meta_1>.
-    Found 1-bit register for signal <spi_rx_rdy_meta_2>.
-    Found 1-bit register for signal <spi_rx_sof_meta_1>.
-    Found 1-bit register for signal <spi_rx_sof_meta_2>.
-    Found 1-bit register for signal <spi_sof>.
-    Found 48-bit register for signal <spi_stat_gen<6:1>>.
-    Found 1-bit register for signal <spi_stb>.
-    Summary:
-	inferred   1 Counter(s).
-	inferred 228 D-type flip-flop(s).
-	inferred   2 Adder/Subtractor(s).
-Unit <Replay_FileIO> synthesized.
-
-
-Synthesizing Unit <antic>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/antic.vhdl".
-WARNING:Xst:1780 - Signal <nmi_reset> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <line_buffer_address_reg<7:6>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <displayed_character_reg<4:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <addr_decoded<6>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Using one-hot encoding for signal <dma_fetch_destination_reg>.
-    Using one-hot encoding for signal <instruction_type_reg>.
-INFO:Xst:2117 - HDL ADVISOR - Mux Selector <shift_rate_reg> of Case statement line 1502 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
-   	- add an 'INIT' attribute on signal <shift_rate_reg> (optimization is then done without any risk)
-   	- use the attribute 'signal_encoding user' to avoid onehot optimization
-   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
-    Using one-hot encoding for signal <shift_rate_reg>.
-    Using one-hot encoding for signal <dma_speed_reg>.
-    Found 16x15-bit ROM for signal <instruction_reg_3_0$rom0000>.
-    Found 4x8-bit ROM for signal <playfield_display_end_cycle>.
-    Found 4x1-bit ROM for signal <dmactl_delayed_enabled>.
-    Found 8-bit adder for signal <$add0000> created at line 750.
-    Found 1-bit register for signal <allow_real_dma_reg>.
-    Found 3-bit register for signal <an_prev_reg>.
-    Found 3-bit register for signal <an_reg>.
-    Found 3-bit register for signal <chactl_reg>.
-    Found 8-bit register for signal <character_reg>.
-    Found 7-bit register for signal <chbase_raw_reg>.
-    Found 4-bit adder for signal <colour_clock_count_next$addsub0000> created at line 658.
-    Found 4-bit register for signal <colour_clock_count_reg>.
-    Found 4-bit comparator greatequal for signal <data_live_0$cmp_ge0000> created at line 1571.
-    Found 4-bit comparator less for signal <data_live_0$cmp_lt0000> created at line 1567.
-    Found 25-bit register for signal <delay_display_shift_reg>.
-    Found 1-bit register for signal <descenders_reg>.
-    Found 8-bit register for signal <display_list_address_low_temp_reg>.
-    Found 8-bit register for signal <display_shift_reg>.
-    Found 8-bit register for signal <displayed_character_reg>.
-    Found 1-bit register for signal <dli_enabled_reg>.
-    Found 1-bit register for signal <dli_nmi_reg>.
-    Found 3-bit adder for signal <dma_address_next$add0000> created at line 1011.
-    Found 3-bit xor2 for signal <dma_address_next$xor0000> created at line 954.
-    Found 3-bit xor2 for signal <dma_address_next$xor0001> created at line 960.
-    Found 16-bit register for signal <dma_address_reg>.
-    Found 6-bit register for signal <dma_fetch_destination_reg>.
-    Found 1-bit register for signal <dma_fetch_reg>.
-    Found 4-bit register for signal <dma_speed_reg>.
-    Found 7-bit register for signal <dmactl_raw_reg>.
-    Found 1-bit register for signal <first_line_of_instruction_reg>.
-    Found 1-bit 16-to-1 multiplexer for signal <force_final_row>.
-    Found 1-bit register for signal <hblank_reg>.
-    Found 8-bit register for signal <hcount_reg>.
-    Found 1-bit 16-to-1 multiplexer for signal <hscrol_enabled_next>.
-    Found 1-bit register for signal <hscrol_enabled_reg>.
-    Found 4-bit register for signal <hscrol_reg>.
-    Found 1-bit register for signal <instruction_blank_reg>.
-    Found 4-bit 16-to-1 multiplexer for signal <instruction_final_row_next>.
-    Found 4-bit register for signal <instruction_final_row_reg>.
-    Found 8-bit register for signal <instruction_reg>.
-    Found 5-bit 16-to-1 multiplexer for signal <instruction_type_next>.
-    Found 5-bit register for signal <instruction_type_reg>.
-    Found 4-bit comparator equal for signal <last_line_of_instruction_live$cmp_eq0000> created at line 1205.
-    Found 4-bit comparator equal for signal <last_line_of_instruction_live$cmp_eq0001> created at line 1209.
-    Found 1-bit register for signal <last_line_of_instruction_reg>.
-    Found 1-bit register for signal <map_background_reg>.
-    Found 1-bit register for signal <multi_colour_character_reg>.
-    Found 1-bit register for signal <nmi_reg>.
-    Found 16-bit register for signal <nmi_shiftreg_reg>.
-    Found 2-bit register for signal <nmien_raw_reg>.
-    Found 3-bit register for signal <nmist_reg>.
-    Found 8-bit register for signal <penh_reg>.
-    Found 8-bit register for signal <penv_reg>.
-    Found 1-bit register for signal <playfield_display_active_reg>.
-    Found 8-bit comparator equal for signal <playfield_display_active_reg$cmp_eq0000> created at line 943.
-    Found 8-bit comparator not equal for signal <playfield_display_active_reg$cmp_ne0000> created at line 939.
-    Found 8-bit comparator not equal for signal <playfield_display_active_reg$cmp_ne0001> created at line 943.
-    Found 8-bit 4-to-1 multiplexer for signal <playfield_display_start_cycle>.
-    Found 4-bit comparator greater for signal <playfield_display_start_cycle$cmp_gt0000> created at line 869.
-    Found 8-bit comparator equal for signal <playfield_dma_end$cmp_eq0000> created at line 935.
-    Found 8-bit comparator equal for signal <playfield_dma_start$cmp_eq0000> created at line 930.
-    Found 6-bit register for signal <pmbase_reg>.
-    Found 4-bit comparator less for signal <refresh_fetch_next$cmp_lt0000> created at line 1120.
-    Found 1-bit register for signal <refresh_fetch_reg>.
-    Found 1-bit register for signal <refresh_pending_reg>.
-    Found 4-bit comparator greatequal for signal <refresh_pending_reg$cmp_ge0000> created at line 1120.
-    Found 3-bit register for signal <shift_rate_reg>.
-    Found 1-bit register for signal <shift_twobit_reg>.
-    Found 4-bit register for signal <shiftclock_reg>.
-    Found 1-bit register for signal <single_colour_character_reg>.
-    Found 1-bit 16-to-1 multiplexer for signal <two_part_instruction_next>.
-    Found 1-bit register for signal <two_part_instruction_reg>.
-    Found 1-bit register for signal <twoline_character_reg>.
-    Found 1-bit register for signal <twopixel_reg>.
-    Found 1-bit register for signal <vbi_nmi_reg>.
-    Found 1-bit register for signal <vblank_reg>.
-    Found 9-bit up counter for signal <vcount_reg>.
-    Found 1-bit 16-to-1 multiplexer for signal <vscrol_enabled_next>.
-    Found 1-bit register for signal <vscrol_enabled_reg>.
-    Found 1-bit register for signal <vscrol_last_enabled_reg>.
-    Found 4-bit register for signal <vscrol_raw_reg>.
-    Found 1-bit register for signal <vsync_reg>.
-    Found 1-bit register for signal <wsync_reg>.
-    Summary:
-	inferred   3 ROM(s).
-	inferred   1 Counter(s).
-	inferred 202 D-type flip-flop(s).
-	inferred   3 Adder/Subtractor(s).
-	inferred  12 Comparator(s).
-	inferred  21 Multiplexer(s).
-Unit <antic> synthesized.
-
-
-Synthesizing Unit <pokey>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pokey.vhdl".
-WARNING:Xst:646 - Signal <serout_shift_reg<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <serin_shift_reg<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <addr_decoded<12>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 8x1-bit ROM for signal <clock_input>.
-    Found 1-bit tristate buffer for signal <SIO_CLOCK>.
-    Found 8-bit register for signal <audc0_reg>.
-    Found 8-bit register for signal <audc1_reg>.
-    Found 8-bit register for signal <audc2_reg>.
-    Found 8-bit register for signal <audc3_reg>.
-    Found 8-bit register for signal <audctl_reg>.
-    Found 8-bit register for signal <audf0_reg>.
-    Found 8-bit register for signal <audf1_reg>.
-    Found 8-bit register for signal <audf2_reg>.
-    Found 8-bit register for signal <audf3_reg>.
-    Found 1-bit register for signal <chan0_output_reg>.
-    Found 1-bit register for signal <chan1_output_reg>.
-    Found 1-bit register for signal <chan2_output_reg>.
-    Found 1-bit register for signal <chan3_output_reg>.
-    Found 1-bit register for signal <clock_reg>.
-    Found 1-bit register for signal <clock_sync_reg>.
-    Found 1-bit register for signal <highpass0_reg>.
-    Found 1-bit register for signal <highpass1_reg>.
-    Found 1-bit register for signal <irq_n_reg>.
-    Found 8-bit register for signal <irqen_reg>.
-    Found 8-bit register for signal <irqst_reg>.
-    Found 1-bit register for signal <keyboard_overrun_reg>.
-    Found 8-bit register for signal <pot0_reg>.
-    Found 8-bit register for signal <pot1_reg>.
-    Found 8-bit register for signal <pot2_reg>.
-    Found 8-bit register for signal <pot3_reg>.
-    Found 8-bit register for signal <pot4_reg>.
-    Found 8-bit register for signal <pot5_reg>.
-    Found 8-bit register for signal <pot6_reg>.
-    Found 8-bit register for signal <pot7_reg>.
-    Found 8-bit up counter for signal <pot_counter_reg>.
-    Found 1-bit register for signal <pot_reset_reg>.
-    Found 1-bit register for signal <serial_ip_framing_reg>.
-    Found 1-bit register for signal <serial_ip_overrun_reg>.
-    Found 1-bit register for signal <serial_out_reg>.
-    Found 4-bit register for signal <serin_bitcount_reg>.
-    Found 4-bit subtractor for signal <serin_bitcount_reg$addsub0000> created at line 1082.
-    Found 1-bit register for signal <serin_clock_last_reg>.
-    Found 1-bit register for signal <serin_clock_reg>.
-    Found 1-bit 8-to-1 multiplexer for signal <serin_enable>.
-    Found 8-bit register for signal <serin_reg>.
-    Found 10-bit register for signal <serin_shift_reg>.
-    Found 1-bit register for signal <serout_active_reg>.
-    Found 4-bit register for signal <serout_bitcount_reg>.
-    Found 4-bit subtractor for signal <serout_bitcount_reg$addsub0000> created at line 1003.
-    Found 1-bit register for signal <serout_clock_last_reg>.
-    Found 1-bit register for signal <serout_clock_reg>.
-    Found 1-bit 8-to-1 multiplexer for signal <serout_enable>.
-    Found 1-bit register for signal <serout_holding_full_reg>.
-    Found 8-bit register for signal <serout_holding_reg>.
-    Found 10-bit register for signal <serout_shift_reg>.
-    Found 1-bit register for signal <sio_in_reg>.
-    Found 1-bit register for signal <sio_out_reg>.
-    Found 8-bit register for signal <skctl_reg>.
-    Found 1-bit register for signal <twotone_reg>.
-    Found 1-bit xor2 for signal <volume_channel_0_next$xor0000> created at line 920.
-    Found 4-bit register for signal <volume_channel_0_reg>.
-    Found 1-bit xor2 for signal <volume_channel_1_next$xor0000> created at line 924.
-    Found 4-bit register for signal <volume_channel_1_reg>.
-    Found 4-bit register for signal <volume_channel_2_reg>.
-    Found 4-bit register for signal <volume_channel_3_reg>.
-    Summary:
-	inferred   1 ROM(s).
-	inferred   1 Counter(s).
-	inferred 243 D-type flip-flop(s).
-	inferred   2 Adder/Subtractor(s).
-	inferred   2 Multiplexer(s).
-	inferred   1 Tristate(s).
-Unit <pokey> synthesized.
-
-
-Synthesizing Unit <Replay_JoyPS2_Core_1>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_JoyPS2.vhd".
-WARNING:Xst:647 - Input <i_joy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:1780 - Signal <msy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <msx> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <msb> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <cpu_r_stb> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <cpu_port_id<5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <cpu_int_ack> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 4-bit register for signal <clk_in>.
-    Found 1-bit register for signal <clk_in_falling>.
-    Found 1-bit register for signal <clk_in_r>.
-    Found 1-bit 4-to-1 multiplexer for signal <clk_in_r$mux0000>.
-    Found 8-bit register for signal <cpu_in_port>.
-    Found 4-bit register for signal <data_in>.
-    Found 1-bit register for signal <data_in_r>.
-    Found 1-bit 4-to-1 multiplexer for signal <data_in_r$mux0000>.
-    Found 1-bit register for signal <ps2_drive_clk_low>.
-    Found 1-bit register for signal <ps2_drive_data_low>.
-    Found 1-bit register for signal <rx_data>.
-    Found 1-bit register for signal <rx_falling_int>.
-    Found 1-bit register for signal <rx_falling_int_ack>.
-    Found 1-bit register for signal <rx_falling_int_ena>.
-    Found 2-bit register for signal <status>.
-    Found 1-bit register for signal <timer_int>.
-    Found 1-bit register for signal <timer_int_ack>.
-    Found 1-bit register for signal <timer_int_ena>.
-    Summary:
-	inferred  30 D-type flip-flop(s).
-	inferred   2 Multiplexer(s).
-Unit <Replay_JoyPS2_Core_1> synthesized.
-
-
-Synthesizing Unit <Replay_JoyPS2_Core_2>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_JoyPS2.vhd".
-WARNING:Xst:647 - Input <i_joy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:1780 - Signal <msy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <msx> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <msb> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <cpu_r_stb> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <cpu_port_id<5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <cpu_int_ack> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 4-bit register for signal <clk_in>.
-    Found 1-bit register for signal <clk_in_falling>.
-    Found 1-bit register for signal <clk_in_r>.
-    Found 1-bit 4-to-1 multiplexer for signal <clk_in_r$mux0000>.
-    Found 8-bit register for signal <cpu_in_port>.
-    Found 4-bit register for signal <data_in>.
-    Found 1-bit register for signal <data_in_r>.
-    Found 1-bit 4-to-1 multiplexer for signal <data_in_r$mux0000>.
-    Found 1-bit register for signal <ps2_drive_clk_low>.
-    Found 1-bit register for signal <ps2_drive_data_low>.
-    Found 1-bit register for signal <rx_data>.
-    Found 1-bit register for signal <rx_falling_int>.
-    Found 1-bit register for signal <rx_falling_int_ack>.
-    Found 1-bit register for signal <rx_falling_int_ena>.
-    Found 2-bit register for signal <status>.
-    Found 1-bit register for signal <timer_int>.
-    Found 1-bit register for signal <timer_int_ack>.
-    Found 1-bit register for signal <timer_int_ena>.
-    Summary:
-	inferred  30 D-type flip-flop(s).
-	inferred   2 Multiplexer(s).
-Unit <Replay_JoyPS2_Core_2> synthesized.
-
-
-Synthesizing Unit <Replay_DDRCtrl>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_DDRCtrl.vhd".
-WARNING:Xst:646 - Signal <cur_w_l> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <cur_addr<23:11>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-INFO:Xst:1799 - State 1101 is never reached in FSM <b0_state>.
-INFO:Xst:1799 - State 1100 is never reached in FSM <b0_state>.
-INFO:Xst:1799 - State 1110 is never reached in FSM <b0_state>.
-    Found finite state machine <FSM_8> for signal <b0_state>.
-    -----------------------------------------------------------------------
-    | States             | 11                                             |
-    | Transitions        | 14                                             |
-    | Inputs             | 3                                              |
-    | Outputs            | 3                                              |
-    | Clock              | i_clk                     (rising_edge)        |
-    | Reset              | ram_startup_done          (negative)           |
-    | Reset type         | synchronous                                    |
-    | Reset State        | 1111                                           |
-    | Power Up State     | 0000                                           |
-    | Encoding           | automatic                                      |
-    | Implementation     | automatic                                      |
-    -----------------------------------------------------------------------
-    Found 16x7-bit ROM for signal <ram_startup_cnt$rom0000>.
-    Found 24-bit register for signal <cur_addr>.
-    Found 4-bit register for signal <cur_w_be>.
-    Found 32-bit register for signal <cur_w_data>.
-    Found 1-bit 16-to-1 multiplexer for signal <inc$mux0001> created at line 218.
-    Found 1-bit register for signal <ram_cke_enable>.
-    Found 3-bit register for signal <ram_cmd_s>.
-    Found 4-bit register for signal <ram_mux_s>.
-    Found 4-bit up counter for signal <ram_startup_cnt>.
-    Found 9-bit up counter for signal <ram_startup_delay>.
-    Found 1-bit register for signal <ram_startup_done>.
-    Found 1-bit 16-to-1 multiplexer for signal <ram_startup_done$mux0000> created at line 218.
-    Found 4-bit up accumulator for signal <ref_cnt>.
-    Found 12-bit down counter for signal <ref_div>.
-    Found 1-bit register for signal <ref_req>.
-    Found 16-bit up counter for signal <start_up_cnt>.
-    Found 1-bit register for signal <start_up_wait>.
-    Summary:
-	inferred   1 Finite State Machine(s).
-	inferred   1 ROM(s).
-	inferred   4 Counter(s).
-	inferred   1 Accumulator(s).
-	inferred  71 D-type flip-flop(s).
-	inferred   2 Multiplexer(s).
-Unit <Replay_DDRCtrl> synthesized.
-
-
-Synthesizing Unit <Replay_OSD>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_OSD.vhd".
-WARNING:Xst:1780 - Signal <pix_ena_t> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <pix_active_t<3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <osd_sol> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <font_addr_t1<12:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <char_vid_dout_t1<6:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 8x8-bit ROM for signal <op0$mux0000> created at line 153.
-    Found 8x8-bit ROM for signal <pix_op_0$mux0000> created at line 452.
-    Found 8x8-bit ROM for signal <pix_op_1$mux0000> created at line 452.
-    Found 8x8-bit ROM for signal <pix_op_2$mux0000> created at line 452.
-    Found 24-bit register for signal <o_vid_rgb>.
-    Found 4-bit register for signal <attrib.bg>.
-    Found 4-bit register for signal <attrib.fg>.
-    Found 1-bit register for signal <attrib.invert>.
-    Found 16-bit register for signal <char_vid_dout_t1>.
-    Found 15-bit register for signal <font_addr_t1>.
-    Found 2-bit 4-to-1 multiplexer for signal <font_dout>.
-    Found 10-bit register for signal <osd_cpos>.
-    Found 10-bit adder for signal <osd_cpos$addsub0000> created at line 209.
-    Found 1-bit register for signal <osd_eol>.
-    Found 1-bit register for signal <osd_hactive>.
-    Found 10-bit register for signal <osd_hpos>.
-    Found 10-bit adder for signal <osd_hpos$addsub0000> created at line 208.
-    Found 1-bit register for signal <osd_htog>.
-    Found 1-bit register for signal <osd_vactive>.
-    Found 9-bit register for signal <osd_vpos>.
-    Found 9-bit adder for signal <osd_vpos_8$add0000> created at line 232.
-    Found 4-bit adder for signal <osd_vpos_o>.
-    Found 1-bit register for signal <osd_vtog>.
-    Found 4-bit register for signal <pix_active_t>.
-    Found 2-bit 4-to-1 multiplexer for signal <pix_bg$mux0001> created at line 449.
-    Found 2-bit 4-to-1 multiplexer for signal <pix_bg$mux0002> created at line 449.
-    Found 2-bit 4-to-1 multiplexer for signal <pix_bg$mux0003> created at line 449.
-    Found 4-bit register for signal <pix_h_t1>.
-    Found 24-bit 4-to-1 multiplexer for signal <pix_op>.
-    Found 4-bit register for signal <pix_v_t1>.
-    Found 2-bit register for signal <shifter_data>.
-    Found 4-bit register for signal <voffset>.
-    Found 4-bit register for signal <voffset_sync>.
-    Summary:
-	inferred   4 ROM(s).
-	inferred 120 D-type flip-flop(s).
-	inferred   4 Adder/Subtractor(s).
-	inferred  32 Multiplexer(s).
-Unit <Replay_OSD> synthesized.
-
-
-Synthesizing Unit <Replay_JoyPS2>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_JoyPS2.vhd".
-WARNING:Xst:646 - Signal <status_a> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 3-bit register for signal <o_ms_butn>.
-    Found 1-bit register for signal <o_kb_ps2_we>.
-    Found 8-bit register for signal <o_kb_ps2_data>.
-    Found 12-bit register for signal <o_ms_posx>.
-    Found 12-bit register for signal <o_ms_posy>.
-    Found 1-bit register for signal <o_ms_we>.
-    Found 6-bit register for signal <joy_a_reg>.
-    Found 6-bit register for signal <joy_b_reg>.
-    Summary:
-	inferred  49 D-type flip-flop(s).
-Unit <Replay_JoyPS2> synthesized.
-
-
-Synthesizing Unit <Replay_DDRCtrl_Top>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_DDRCtrl_Top.vhd".
-WARNING:Xst:646 - Signal <start_b> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Register <lp_w_data<16>> equivalent to <lp_w_data<0>> has been removed
-    Register <lp_w_data<24>> equivalent to <lp_w_data<0>> has been removed
-    Register <lp_w_data<8>> equivalent to <lp_w_data<0>> has been removed
-    Register <lp_w_data<18>> equivalent to <lp_w_data<10>> has been removed
-    Register <lp_w_data<26>> equivalent to <lp_w_data<10>> has been removed
-    Register <lp_w_data<2>> equivalent to <lp_w_data<10>> has been removed
-    Register <lp_w_data<19>> equivalent to <lp_w_data<11>> has been removed
-    Register <lp_w_data<27>> equivalent to <lp_w_data<11>> has been removed
-    Register <lp_w_data<3>> equivalent to <lp_w_data<11>> has been removed
-    Register <lp_w_data<20>> equivalent to <lp_w_data<12>> has been removed
-    Register <lp_w_data<28>> equivalent to <lp_w_data<12>> has been removed
-    Register <lp_w_data<4>> equivalent to <lp_w_data<12>> has been removed
-    Register <lp_w_data<21>> equivalent to <lp_w_data<13>> has been removed
-    Register <lp_w_data<29>> equivalent to <lp_w_data<13>> has been removed
-    Register <lp_w_data<5>> equivalent to <lp_w_data<13>> has been removed
-    Register <lp_w_data<22>> equivalent to <lp_w_data<14>> has been removed
-    Register <lp_w_data<30>> equivalent to <lp_w_data<14>> has been removed
-    Register <lp_w_data<6>> equivalent to <lp_w_data<14>> has been removed
-    Register <lp_w_data<23>> equivalent to <lp_w_data<15>> has been removed
-    Register <lp_w_data<31>> equivalent to <lp_w_data<15>> has been removed
-    Register <lp_w_data<7>> equivalent to <lp_w_data<15>> has been removed
-    Register <lp_w_data<1>> equivalent to <lp_w_data<17>> has been removed
-    Register <lp_w_data<25>> equivalent to <lp_w_data<17>> has been removed
-    Register <lp_w_data<9>> equivalent to <lp_w_data<17>> has been removed
-    Found 4x4-bit ROM for signal <lp_w_be$mux0001> created at line 240.
-    Found 8-bit register for signal <o_lp_r_data>.
-    Found 1-bit register for signal <o_lp_r_we>.
-    Found 32-bit register for signal <o_hp_r_data>.
-    Found 1-bit register for signal <o_cfg_ready>.
-    Found 1-bit register for signal <cur_hp>.
-    Found 1-bit register for signal <cur_lp>.
-    Found 1-bit register for signal <cur_read>.
-    Found 1-bit register for signal <ena_sys_t1>.
-    Found 1-bit register for signal <ena_sys_t2>.
-    Found 1-bit register for signal <ena_sys_t3>.
-    Found 24-bit register for signal <hp_addr>.
-    Found 1-bit register for signal <hp_rw_l>.
-    Found 1-bit register for signal <hp_valid>.
-    Found 4-bit register for signal <hp_w_be>.
-    Found 32-bit register for signal <hp_w_data>.
-    Found 24-bit register for signal <lp_addr>.
-    Found 2-bit register for signal <lp_r_sel>.
-    Found 1-bit register for signal <lp_rw_l>.
-    Found 1-bit register for signal <lp_valid>.
-    Found 4-bit register for signal <lp_w_be>.
-    Found 1-bit register for signal <lp_w_data<17>>.
-    Found 6-bit register for signal <lp_w_data<15:10>>.
-    Found 1-bit register for signal <lp_w_data<0>>.
-    Found 8-bit 4-to-1 multiplexer for signal <o_lp_r_data$mux0001> created at line 422.
-    Found 4-bit up counter for signal <phase>.
-    Found 1-bit xor2 for signal <phase$xor0000> created at line 194.
-    Found 1-bit register for signal <r_buf_ena>.
-    Found 1-bit register for signal <r_we_hp>.
-    Found 1-bit register for signal <r_we_lp>.
-    Found 1-bit register for signal <start_a>.
-    Found 1-bit register for signal <sys_cur_hp>.
-    Found 1-bit register for signal <sys_cur_lp>.
-    Found 1-bit register for signal <sys_cur_read>.
-    Found 1-bit register for signal <sys_taken>.
-    Found 1-bit register for signal <sys_taken_meta1>.
-    Summary:
-	inferred   1 ROM(s).
-	inferred   1 Counter(s).
-	inferred 159 D-type flip-flop(s).
-	inferred   8 Multiplexer(s).
-Unit <Replay_DDRCtrl_Top> synthesized.
-
-
-Synthesizing Unit <Replay_Syscon>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Syscon.vhd".
-WARNING:Xst:646 - Signal <spi_rx_cmd<7:4>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <spi_cmd_low<15:9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <spi_cmd_low<7:4>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <spi_cmd_high<15:13>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <spi_cmd_high<11:6>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <spi_cmd_high<4:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <spi_cmd_high<1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <spi_byte_sel<7:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <h_size<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <cs_trig> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <cs_control0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <cs_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-    Register <o_vid_sync.dig_vs> equivalent to <o_vbl> has been removed
-    Found 8-bit register for signal <o_cfg_fileio>.
-    Found 1-bit register for signal <o_vid_sync.ana_vs>.
-    Found 1-bit register for signal <o_vid_sync.ana_de>.
-    Found 1-bit register for signal <o_vbl>.
-    Found 1-bit register for signal <o_vid_sync.ana_hs>.
-    Found 1-bit register for signal <o_vid_sync.dig_de>.
-    Found 32-bit register for signal <o_cfg_static>.
-    Found 1-bit register for signal <o_vid_sync.dig_hs>.
-    Found 11-bit register for signal <char_addr>.
-    Found 11-bit adder for signal <char_addr$add0000> created at line 396.
-    Found 12-bit up counter for signal <h_count>.
-    Found 12-bit register for signal <h_size>.
-    Found 12-bit subtractor for signal <h_start_pos>.
-    Found 12-bit subtractor for signal <h_start_pos$mux0000> created at line 535.
-    Found 2-bit register for signal <hs_t>.
-    Found 1-bit register for signal <osd_ena>.
-    Found 1-bit register for signal <osd_hexp>.
-    Found 1-bit register for signal <osd_hstart>.
-    Found 12-bit comparator equal for signal <osd_hstart$cmp_eq0000> created at line 554.
-    Found 1-bit register for signal <osd_oddline>.
-    Found 1-bit register for signal <osd_prog>.
-    Found 1-bit xor2 for signal <osd_prog$xor0000> created at line 518.
-    Found 1-bit register for signal <osd_vstart>.
-    Found 12-bit comparator equal for signal <osd_vstart$cmp_eq0000> created at line 559.
-    Found 8-bit register for signal <spi_byte_sel>.
-    Found 16-bit register for signal <spi_cmd_high>.
-    Found 16-bit register for signal <spi_cmd_low>.
-    Found 16-bit register for signal <spi_ctrl.cfg_ctrl>.
-    Found 32-bit register for signal <spi_ctrl.cfg_dynamic>.
-    Found 8-bit register for signal <spi_ctrl.cfg_fileio>.
-    Found 32-bit register for signal <spi_ctrl.cfg_static>.
-    Found 1-bit register for signal <spi_ctrl.halt>.
-    Found 1-bit register for signal <spi_ctrl.keyboard_dis>.
-    Found 1-bit register for signal <spi_ctrl.osd_ena>.
-    Found 1-bit register for signal <spi_ctrl.reset>.
-    Found 8-bit register for signal <spi_data>.
-    Found 1-bit register for signal <spi_rx_rdy_meta_1>.
-    Found 1-bit register for signal <spi_rx_rdy_meta_2>.
-    Found 1-bit register for signal <spi_rx_sof_meta_1>.
-    Found 1-bit register for signal <spi_rx_sof_meta_2>.
-    Found 1-bit register for signal <spi_sof>.
-    Found 1-bit register for signal <spi_stb>.
-    Found 8-bit register for signal <spi_tx_cfg_fileio>.
-    Found 16-bit register for signal <spi_tx_cfg_status>.
-    Found 8-bit register for signal <spi_tx_kbd>.
-    Found 8-bit register for signal <spi_tx_status>.
-    Found 12-bit up counter for signal <v_count>.
-    Found 12-bit register for signal <v_size>.
-    Found 12-bit subtractor for signal <v_start_pos>.
-    Found 2-bit register for signal <vs_t>.
-    Summary:
-	inferred   2 Counter(s).
-	inferred 277 D-type flip-flop(s).
-	inferred   4 Adder/Subtractor(s).
-	inferred   2 Comparator(s).
-Unit <Replay_Syscon> synthesized.
-
-
-Synthesizing Unit <zpu_config_regs>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl".
-WARNING:Xst:647 - Input <SWITCH> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:646 - Signal <spi_tx_data> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <spi_speed_reg_integer> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <spi_speed_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:653 - Signal <spi_rx_data> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
-WARNING:Xst:653 - Signal <spi_mosi> is used but never assigned. This sourceless signal will be automatically connected to value 0.
-WARNING:Xst:646 - Signal <spi_miso> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <spi_enable> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:653 - Signal <spi_clk_out> is used but never assigned. This sourceless signal will be automatically connected to value 0.
-WARNING:Xst:653 - Signal <spi_chip_select<0>> is used but never assigned. This sourceless signal will be automatically connected to value 0.
-WARNING:Xst:653 - Signal <spi_busy> is used but never assigned. This sourceless signal will be automatically connected to value 0.
-WARNING:Xst:1780 - Signal <spi_addr_reg_integer> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <spi_addr_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <addr_decoded<15:12>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 8-bit register for signal <config_6502_reg>.
-    Found 1-bit register for signal <gpio_enable_reg>.
-    Found 8-bit register for signal <ledg_reg>.
-    Found 10-bit register for signal <ledr_reg>.
-    Found 32-bit 4-to-1 multiplexer for signal <pause_next>.
-    Found 32-bit subtractor for signal <pause_next$addsub0000> created at line 355.
-    Found 32-bit register for signal <pause_reg>.
-    Found 1-bit register for signal <paused_reg>.
-    Found 3-bit register for signal <ram_select_reg>.
-    Found 1-bit register for signal <reset_6502_cpu_reg>.
-    Found 1-bit register for signal <reset_n_reg>.
-    Found 1-bit register for signal <reset_zpu_reg>.
-    Found 2-bit register for signal <rom_select_reg>.
-    Found 32-bit register for signal <sector_reg>.
-    Found 1-bit register for signal <sector_request_reg>.
-    Found 16-bit register for signal <zpu_hex_reg>.
-    Summary:
-	inferred 117 D-type flip-flop(s).
-	inferred   1 Adder/Subtractor(s).
-	inferred  32 Multiplexer(s).
-Unit <zpu_config_regs> synthesized.
-
-
-Synthesizing Unit <atari800core>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd".
-WARNING:Xst:647 - Input <JOY2_n<5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <matrix_out<15:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <JOY1_n<5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:646 - Signal <vcount_temp> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <mist_switches> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <mist_buttons> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <hcount_temp> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <gtia_blank> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <dummy_sector_request> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <dummy_sector> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:653 - Signal <ZPU_SECTOR_DATA> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
-WARNING:Xst:646 - Signal <ZPU_HEX> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <ZPU_ADDR_ROM_RAM<23:14>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <ZPU_ADDR_ROM_RAM<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <VIRTUAL_TRIGGERS<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <VIRTUAL_STICKS> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <VGA_G_dummy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <VGA_B_dummy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <VGA> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <UART_TXD_dummy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <TRIGGERS> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <SYNC_KEYS> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <SHIFT_PRESSED_DUMMY> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <SHIFT_PRESSED> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <SD_DAT3> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:653 - Signal <SD_DAT0> is used but never assigned. This sourceless signal will be automatically connected to value 0.
-WARNING:Xst:646 - Signal <SD_CMD> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <SD_CLK> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <SDRAM_REFRESH> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <SCANDOUBLER_SHARED_ENABLE_LOW> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <SCANDOUBLER_SHARED_ENABLE_HIGH> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <ROM_SELECT_dummy> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <RAM_SELECT_dummy> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:653 - Signal <RAM_DO<15:8>> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
-WARNING:Xst:646 - Signal <POT_RESET> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:653 - Signal <POT_IN> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
-WARNING:Xst:646 - Signal <PORTB_DIR_OUT> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <PBI_WRITE_ENABLE> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <PBI_ADDR<15:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <LEDR_dummy> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <LEDG_dummy> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <KEY_INTERRUPT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <KEY_HELD> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <KBCODE> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <GREREN_LEDS> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <GREEN_LEDS> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <GPIO_SIO_OUT> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <GPIO_SIO_IN> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <GPIO_ENABLE> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <GPIO_1_OUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <GPIO_1_IN> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <GPIO_1_DIR_OUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <GPIO_0_OUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <GPIO_0_IN> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <GPIO_0_DIR_OUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <CONTROL_PRESSED> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <COMPOSITE_ON_HSYNC> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <CART_S5_N> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <CART_S4_n> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <CART_REQUEST> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <CART_CCTL_N> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <BREAK_PRESSED_DUMMY> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <BREAK_PRESSED> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-Unit <atari800core> synthesized.
-
-
-Synthesizing Unit <Core_Top>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Core_Top.vhd".
-WARNING:Xst:1305 - Output <debug> is never assigned. Tied to value 000000000000000000000000000000000000.
-WARNING:Xst:1305 - Output <o_act_led_n> is never assigned. Tied to value 0.
-WARNING:Xst:647 - Input <I_CART_RO> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <drive_address> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <CONF_WR_1541> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <hp_ddr_wr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <i_Ms_We> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <I_RAM_EXT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <CONF_WR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <floppy_inserted> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:1305 - Output <media_read_o> is never assigned. Tied to value 0.
-WARNING:Xst:647 - Input <i_Ms_Butn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <debugi> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <hp_ddr_taken> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <diskid_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <i_Ena_Sub1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <media_dat_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:1305 - Output <media_adr_o> is never assigned. Tied to value 000000000000000000.
-WARNING:Xst:647 - Input <core_ps2_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <i_Ena_Sub4> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <CONF_AI<15:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <i_Ms_PosX> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <i_Ms_PosY> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <core_ps2_data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <i_Audio_Taken> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <I_CART_EN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <i_RS232_CTS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:647 - Input <write_prot_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:646 - Signal <matrix_out_mix> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <joy_mix> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <fdata_o> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <fclk_o> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <fatn_o> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <data_i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <core_blankn_ds> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <core_blank> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <clk_i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <cdata_o> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <cclk_o> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <catn_o> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <atn_i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <SDRAM_WIDTH_16bit_ACCESS> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <SDRAM_READ_ENABLE> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 24-bit up counter for signal <core_blank_count_reg>.
-    Found 24-bit comparator less for signal <core_blankn_s$cmp_lt0000> created at line 350.
-    Found 1-bit register for signal <ddr_request_pending_reg>.
-    Found 1-bit register for signal <ddr_response_pending_reg>.
-    Found 24-bit 4-to-1 multiplexer for signal <lsample_s>.
-    Found 24-bit 4-to-1 multiplexer for signal <rsample_s>.
-    Found 1-bit register for signal <sh_lock_key>.
-    Found 1-bit register for signal <stat6_del>.
-    Summary:
-	inferred   1 Counter(s).
-	inferred   4 D-type flip-flop(s).
-	inferred   1 Comparator(s).
-	inferred  48 Multiplexer(s).
-Unit <Core_Top> synthesized.
-
-
-Synthesizing Unit <Replay_Top>.
-    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd".
-WARNING:Xst:647 - Input <i_Aux_IP> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-WARNING:Xst:646 - Signal <tick> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <ram_valid> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <ram_r_w_l> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <ram_data> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <ram_addr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <media_read> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:653 - Signal <media_dat> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
-WARNING:Xst:646 - Signal <media_adr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <mch_ram_taken> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <mch_ram_rd_we> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <mch_ram_rd_data> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <led> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <hp_ddr_addr<1:0>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <cs_trig> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <cs_control0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <cs_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <core_vid_timing.v_pix> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <core_vid_timing.v_oddline> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <core_vid_timing.h_pix> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <core_vid_timing.f2> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <core_vid_timing.dig_sol> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <core_vid_timing.dig_sof> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <core_vid_timing.dig_act_v> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <core_vid_timing.dig_act_h> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <core_vid_std.v_active> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <core_vid_std.prog> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <core_vid_std.h_rep> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <core_vid_std.h_active> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:1780 - Signal <conf_taken> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <cfg_static<31:6>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <cfg_fileio_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <cfg_dynamic<31:19>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <cfg_dynamic<15:9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-WARNING:Xst:646 - Signal <cfg_ctrl<15:10>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
-    Found 1-bit tristate buffer for signal <b_Video_SPC>.
-    Found 1-bit tristate buffer for signal <b_Video_SPD>.
-    Found 1-bit tristate buffer for signal <b_PS2A_Clk>.
-    Found 1-bit tristate buffer for signal <b_PS2A_Data>.
-    Found 1-bit tristate buffer for signal <b_PS2B_Clk>.
-    Found 1-bit tristate buffer for signal <b_PS2B_Data>.
-    Found 1-bit tristate buffer for signal <b_SCL>.
-    Found 1-bit tristate buffer for signal <b_SDA>.
-    Found 1-bit tristate buffer for signal <b_FPGA_SPI_MISO>.
-    Found 1-bit tristate buffer for signal <o_Clk_68K>.
-    Found 16-bit register for signal <diskid_s>.
-    Found 1-bit register for signal <ena_sub1>.
-    Found 1-bit register for signal <ena_sub4>.
-    Found 1-bit register for signal <ena_sys>.
-    Found 1-bit register for signal <ena_sys_ddr>.
-    Found 1-bit register for signal <init_diskinsert_s>.
-    Found 19-bit register for signal <inscnt_s>.
-    Found 19-bit subtractor for signal <inscnt_s$addsub0000> created at line 693.
-    Found 16-bit down counter for signal <PreCounter1>.
-    Found 12-bit down counter for signal <PreCounter2>.
-    Found 5-bit up counter for signal <sub_cnt>.
-    Found 2-bit up counter for signal <sys_cnt>.
-    Found 1-bit register for signal <tick_pre1>.
-    Found 1-bit register for signal <writeprotn_s>.
-    Summary:
-	inferred   4 Counter(s).
-	inferred  42 D-type flip-flop(s).
-	inferred   1 Adder/Subtractor(s).
-	inferred  11 Tristate(s).
-Unit <Replay_Top> synthesized.
-
-
-=========================================================================
-HDL Synthesis Report
-
-Macro Statistics
-# RAMs                                                 : 7
- 1024x8-bit single-port RAM                            : 4
- 16384x8-bit single-port RAM                           : 1
- 2048x24-bit dual-port RAM                             : 1
- 512x8-bit dual-port RAM                               : 1
-# ROMs                                                 : 24
- 16384x8-bit ROM                                       : 1
- 16x15-bit ROM                                         : 1
- 16x7-bit ROM                                          : 1
- 256x24-bit ROM                                        : 1
- 256x44-bit ROM                                        : 1
- 32x6-bit ROM                                          : 4
- 4096x32-bit ROM                                       : 1
- 4x1-bit ROM                                           : 1
- 4x12-bit ROM                                          : 1
- 4x4-bit ROM                                           : 1
- 4x8-bit ROM                                           : 1
- 64x16-bit ROM                                         : 2
- 8192x8-bit ROM                                        : 1
- 8x1-bit ROM                                           : 3
- 8x8-bit ROM                                           : 4
-# Multipliers                                          : 2
- 14x14-bit multiplier                                  : 1
- 32x32-bit multiplier                                  : 1
-# Adders/Subtractors                                   : 105
- 10-bit adder                                          : 3
- 10-bit subtractor                                     : 1
- 11-bit adder                                          : 1
- 12-bit adder                                          : 1
- 12-bit subtractor                                     : 3
- 14-bit adder                                          : 10
- 14-bit adder carry out                                : 1
- 14-bit subtractor                                     : 6
- 15-bit subtractor                                     : 2
- 16-bit adder                                          : 7
- 19-bit subtractor                                     : 1
- 22-bit adder                                          : 3
- 22-bit adder carry in                                 : 1
- 22-bit subtractor                                     : 1
- 24-bit adder                                          : 2
- 28-bit adder                                          : 1
- 28-bit subtractor                                     : 1
- 3-bit adder                                           : 1
- 32-bit adder                                          : 3
- 32-bit subtractor                                     : 2
- 4-bit adder                                           : 4
- 4-bit subtractor                                      : 7
- 5-bit adder                                           : 11
- 5-bit subtractor                                      : 1
- 6-bit adder                                           : 5
- 6-bit subtractor                                      : 1
- 7-bit adder                                           : 3
- 8-bit adder                                           : 3
- 8-bit addsub                                          : 1
- 8-bit subtractor                                      : 14
- 9-bit adder                                           : 3
- 9-bit adder carry in                                  : 1
-# Counters                                             : 39
- 11-bit up counter                                     : 2
- 12-bit down counter                                   : 2
- 12-bit up counter                                     : 2
- 14-bit up counter                                     : 2
- 16-bit down counter                                   : 1
- 16-bit up counter                                     : 1
- 2-bit up counter                                      : 1
- 24-bit up counter                                     : 1
- 3-bit up counter                                      : 2
- 4-bit up counter                                      : 9
- 5-bit up counter                                      : 3
- 6-bit up counter                                      : 3
- 8-bit down counter                                    : 2
- 8-bit up counter                                      : 6
- 9-bit up counter                                      : 2
-# Accumulators                                         : 4
- 12-bit up accumulator                                 : 1
- 4-bit up accumulator                                  : 2
- 8-bit up accumulator                                  : 1
-# Registers                                            : 1508
- 1-bit register                                        : 785
- 10-bit register                                       : 9
- 12-bit register                                       : 3
- 13-bit register                                       : 1
- 14-bit register                                       : 15
- 15-bit register                                       : 3
- 16-bit register                                       : 26
- 17-bit register                                       : 3
- 18-bit register                                       : 1
- 19-bit register                                       : 1
- 2-bit register                                        : 64
- 22-bit register                                       : 2
- 24-bit register                                       : 9
- 25-bit register                                       : 1
- 28-bit register                                       : 1
- 3-bit register                                        : 38
- 32-bit register                                       : 17
- 4-bit register                                        : 77
- 44-bit register                                       : 1
- 5-bit register                                        : 8
- 6-bit register                                        : 19
- 7-bit register                                        : 68
- 8-bit register                                        : 355
- 9-bit register                                        : 1
-# Comparators                                          : 68
- 12-bit comparator equal                               : 2
- 14-bit comparator equal                               : 17
- 14-bit comparator lessequal                           : 2
- 14-bit comparator not equal                           : 9
- 24-bit comparator less                                : 1
- 32-bit comparator equal                               : 1
- 32-bit comparator greater                             : 2
- 32-bit comparator less                                : 2
- 32-bit comparator lessequal                           : 2
- 4-bit comparator equal                                : 2
- 4-bit comparator greatequal                           : 2
- 4-bit comparator greater                              : 1
- 4-bit comparator less                                 : 2
- 5-bit comparator greater                              : 4
- 6-bit comparator equal                                : 4
- 8-bit comparator equal                                : 12
- 8-bit comparator greater                              : 1
- 8-bit comparator not equal                            : 2
-# Multiplexers                                         : 62
- 1-bit 16-to-1 multiplexer                             : 6
- 1-bit 4-to-1 multiplexer                              : 11
- 1-bit 8-to-1 multiplexer                              : 16
- 2-bit 4-to-1 multiplexer                              : 4
- 24-bit 4-to-1 multiplexer                             : 2
- 24-bit 8-to-1 multiplexer                             : 1
- 32-bit 4-to-1 multiplexer                             : 1
- 4-bit 16-to-1 multiplexer                             : 1
- 5-bit 16-to-1 multiplexer                             : 1
- 6-bit 4-to-1 multiplexer                              : 1
- 8-bit 4-to-1 multiplexer                              : 18
-# Decoders                                             : 1
- 1-of-16 decoder                                       : 1
-# Tristates                                            : 16
- 1-bit tristate buffer                                 : 16
-# Xors                                                 : 24
- 1-bit xor2                                            : 21
- 3-bit xor2                                            : 2
- 8-bit xor2                                            : 1
-
-=========================================================================
-
-=========================================================================
-*                       Advanced HDL Synthesis                          *
-=========================================================================
-
-Analyzing FSM <FSM_8> for best encoding.
-Optimizing FSM <u_DDRCtrl/u_ddr_ctrl/b0_state/FSM> on signal <b0_state[1:11]> with one-hot encoding.
-----------------------
- State | Encoding
-----------------------
- 0000  | 00000000001
- 0001  | 00000000100
- 0010  | 00000100000
- 0011  | 00000010000
- 0100  | 00001000000
- 0101  | 00010000000
- 0110  | 00100000000
- 0111  | 01000000000
- 1010  | 00000001000
- 1011  | 10000000000
- 1100  | unreached
- 1101  | unreached
- 1110  | unreached
- 1111  | 00000000010
-----------------------
-Analyzing FSM <FSM_7> for best encoding.
-Optimizing FSM <u_Core/atari800core/gtia1/pmg_dma_state_reg/FSM> on signal <pmg_dma_state_reg[1:3]> with gray encoding.
--------------------
- State | Encoding
--------------------
- 000   | 011
- 001   | 010
- 010   | 110
- 011   | 111
- 100   | 101
- 101   | 000
- 110   | 001
--------------------
-Analyzing FSM <FSM_6> for best encoding.
-Optimizing FSM <u_Video/u_I2C/State/FSM> on signal <State[1:3]> with gray encoding.
-------------------------
- State      | Encoding
-------------------------
- s_idle     | 000
- s_devid    | 001
- s_ack1     | 011
- s_rab      | 010
- s_ack2     | 111
- s_data     | 101
- s_read     | 110
- s_ack_read | 100
-------------------------
-Analyzing FSM <FSM_5> for best encoding.
-Optimizing FSM <u_Core/atari800core/gtia1/player0/count_reg/FSM> on signal <count_reg[1:2]> with user encoding.
-Optimizing FSM <u_Core/atari800core/gtia1/player1/count_reg/FSM> on signal <count_reg[1:2]> with user encoding.
-Optimizing FSM <u_Core/atari800core/gtia1/player2/count_reg/FSM> on signal <count_reg[1:2]> with user encoding.
-Optimizing FSM <u_Core/atari800core/gtia1/player3/count_reg/FSM> on signal <count_reg[1:2]> with user encoding.
-Optimizing FSM <u_Core/atari800core/gtia1/missile0/count_reg/FSM> on signal <count_reg[1:2]> with user encoding.
-Optimizing FSM <u_Core/atari800core/gtia1/missile1/count_reg/FSM> on signal <count_reg[1:2]> with user encoding.
-Optimizing FSM <u_Core/atari800core/gtia1/missile2/count_reg/FSM> on signal <count_reg[1:2]> with user encoding.
-Optimizing FSM <u_Core/atari800core/gtia1/missile3/count_reg/FSM> on signal <count_reg[1:2]> with user encoding.
--------------------
- State | Encoding
--------------------
- 00    | 00
- 01    | 01
- 10    | 10
- 11    | 11
--------------------
-Analyzing FSM <FSM_4> for best encoding.
-Optimizing FSM <u_Core/atari800core/zpu_config1/uart1/pokey_keyboard_scanner1/state_reg/FSM> on signal <state_reg[1:2]> with gray encoding.
-Optimizing FSM <u_Core/atari800core/pokey2/pokey_keyboard_scanner1/state_reg/FSM> on signal <state_reg[1:2]> with gray encoding.
-Optimizing FSM <u_Core/atari800core/pokey1/pokey_keyboard_scanner1/state_reg/FSM> on signal <state_reg[1:2]> with gray encoding.
--------------------
- State | Encoding
--------------------
- 00    | 00
- 01    | 01
- 10    | 11
- 11    | 10
--------------------
-Analyzing FSM <FSM_3> for best encoding.
-Optimizing FSM <u_Core/atari800core/zpu_glue1/myzpu/state/FSM> on signal <state[1:4]> with gray encoding.
--------------------------------
- State             | Encoding
--------------------------------
- st_load2          | 1110
- st_popped         | 1111
- st_load_sp2       | 0100
- st_load_sp3       | 1001
- st_add_sp2        | 1101
- st_fetch          | 1100
- st_execute        | 0111
- st_decode         | 0010
- st_decode2        | 0110
- st_resync         | 0000
- st_store_sp2      | 0101
- st_resync2        | 0001
- st_resync3        | 0011
- st_loadb2         | 1011
- st_mult2          | unreached
- st_mult3          | unreached
- st_mult5          | 1010
- st_mult4          | unreached
- st_binary_op_res2 | unreached
- st_binary_op_res  | unreached
- st_idle           | unreached
--------------------------------
-Analyzing FSM <FSM_2> for best encoding.
-Optimizing FSM <u_Core/atari800core/cpu6502/cpu_6502_peter/theCpuCycle/FSM> on signal <theCpuCycle[1:19]> with one-hot encoding.
------------------------------------------
- State            | Encoding
------------------------------------------
- opcodefetch      | 0000000000000000001
- cycle2           | 0000000000000000010
- cycle3           | 0000000000001000000
- cyclepreindirect | 0000000000010000000
- cycleindirect    | 0000000000100000000
- cyclebranchtaken | 0000000000000000100
- cyclebranchpage  | 0000100000000000000
- cyclepreread     | 0000000010000000000
- cycleread        | 0000010000000000000
- cycleread2       | 0000000100000000000
- cyclermw         | 0001000000000000000
- cycleprewrite    | 0000000001000000000
- cyclewrite       | 0000000000000100000
- cyclestack1      | 0000000000000001000
- cyclestack2      | 0000000000000010000
- cyclestack3      | 0010000000000000000
- cyclestack4      | 0100000000000000000
- cyclejump        | 0000001000000000000
- cycleend         | 1000000000000000000
------------------------------------------
-Analyzing FSM <FSM_1> for best encoding.
-Optimizing FSM <u_Core/atari800core/mmu1/state_reg/FSM> on signal <state_reg[1:2]> with sequential encoding.
--------------------
- State | Encoding
--------------------
- 00    | 00
- 01    | 11
- 10    | 10
- 11    | 01
--------------------
-Analyzing FSM <FSM_0> for best encoding.
-Optimizing FSM <u_Core/u_Kbd/key_state/FSM> on signal <key_state[1:13]> with one-hot encoding.
------------------------------
- State      | Encoding
------------------------------
- normal     | 0000000000001
- extended   | 0000000000100
- pending    | 0000000001000
- translate1 | 0010000000000
- translate2 | 0100000000000
- done       | 1000000000000
- pause0     | 0000000000010
- pause1     | 0000000010000
- pause2     | 0000000100000
- pause3     | 0000001000000
- pause4     | 0000010000000
- pause5     | 0000100000000
- pause6     | 0001000000000
------------------------------
-WARNING:Xst:2404 -  FFs/Latches <dbg_o.pc<31:24>> (without init value) have a constant value of 0 in block <ZPUMediumCore>.
-WARNING:Xst:2404 -  FFs/Latches <penv_reg<7:0>> (without init value) have a constant value of 0 in block <antic>.
-WARNING:Xst:2404 -  FFs/Latches <penh_reg<7:0>> (without init value) have a constant value of 0 in block <antic>.
-WARNING:Xst:2404 -  FFs/Latches <spi_fch_tx<7:0>> (without init value) have a constant value of 0 in block <Replay_FileIO>.
-WARNING:Xst:2404 -  FFs/Latches <spi_stat_gen_6<7:0>> (without init value) have a constant value of 0 in block <Replay_FileIO>.
-WARNING:Xst:2404 -  FFs/Latches <spi_tx_status<7:1>> (without init value) have a constant value of 0 in block <Replay_Syscon>.
-WARNING:Xst:2404 -  FFs/Latches <spi_tx_cfg_fileio<7:0>> (without init value) have a constant value of 0 in block <Replay_Syscon>.
-WARNING:Xst:2404 -  FFs/Latches <spi_tx_cfg_status<15:0>> (without init value) have a constant value of 0 in block <Replay_Syscon>.
-WARNING:Xst:2404 -  FFs/Latches <spi_ctrl.cfg_fileio<7:0>> (without init value) have a constant value of 0 in block <Replay_Syscon>.
-WARNING:Xst:2404 -  FFs/Latches <spi_stat_gen_5<7:0>> (without init value) have a constant value of 0 in block <Replay_FileIO>.
-WARNING:Xst:2404 -  FFs/Latches <o_cfg_fileio<7:0>> (without init value) have a constant value of 0 in block <Replay_Syscon>.
-WARNING:Xst:2404 -  FFs/Latches <spi_stat_gen_4<7:0>> (without init value) have a constant value of 0 in block <Replay_FileIO>.
-
-Synthesizing (advanced) Unit <Replay_DDRCtrl_Top>.
-INFO:Xst:3034 - In order to maximize performance and save block RAM resources, the small ROM <Mrom_lp_w_be_mux0001> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
-Unit <Replay_DDRCtrl_Top> synthesized (advanced).
-
-Synthesizing (advanced) Unit <Replay_TranslatePS2>.
-INFO:Xst:3230 - The RAM description <Mram_keylut> will not be implemented on the device block RAM because of limited available resources. If you would like this RAM to be implemented in block RAM, please select a larger device or increase the value specified by the BRAM_Utilization_Ratio constraint.
-    -----------------------------------------------------------------------
-    | ram_type           | Distributed                         |          |
-    -----------------------------------------------------------------------
-    | Port A                                                              |
-    |     aspect ratio   | 512-word x 8-bit                    |          |
-    |     clkA           | connected to signal <i_clk_sys>     | rise     |
-    |     weA            | connected to signal <i_conf_wr>     | high     |
-    |     addrA          | connected to signal <i_conf_adr>    |          |
-    |     diA            | connected to signal <i_conf_dat>    |          |
-    -----------------------------------------------------------------------
-    | Port B                                                              |
-    |     aspect ratio   | 512-word x 8-bit                    |          |
-    |     addrB          | connected to signal <key_opt>       |          |
-    |     doB            | connected to internal node          |          |
-    -----------------------------------------------------------------------
-Unit <Replay_TranslatePS2> synthesized (advanced).
-
-Synthesizing (advanced) Unit <Replay_VideoConverter>.
-INFO:Xst:3230 - The RAM description <Mram_dupo_buf_s> will not be implemented on the device block RAM because of limited available resources. If you would like this RAM to be implemented in block RAM, please select a larger device or increase the value specified by the BRAM_Utilization_Ratio constraint.
-    -----------------------------------------------------------------------
-    | ram_type           | Distributed                         |          |
-    -----------------------------------------------------------------------
-    | Port A                                                              |
-    |     aspect ratio   | 2048-word x 24-bit                  |          |
-    |     clkA           | connected to signal <i_clk_sys>     | rise     |
-    |     weA            | connected to signal <bufin_wr_en_s> | high     |
-    |     addrA          | connected to signal <vidin_hcnt_s>  |          |
-    |     diA            | connected to signal <i_vid_b>       |          |
-    -----------------------------------------------------------------------
-    | Port B                                                              |
-    |     aspect ratio   | 2048-word x 24-bit                  |          |
-    |     addrB          | connected to signal <vidout_hpix_s> |          |
-    |     doB            | connected to internal node          |          |
-    -----------------------------------------------------------------------
-Unit <Replay_VideoConverter> synthesized (advanced).
-
-Synthesizing (advanced) Unit <ZPUMediumCore>.
-	Found pipelined multiplier on signal <mult_res_mult0000>:
-		- 1 pipeline level(s) found in a register connected to the multiplier macro output.
-		Pushing register(s) into the multiplier macro.
-
-		- 1 pipeline level(s) found in a register on signal <b_r>.
-		Pushing register(s) into the multiplier macro.
-INFO:Xst:3034 - In order to maximize performance and save block RAM resources, the small ROM <Mrom_tdecoded_mux0111> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
-INFO:Xst:3034 - In order to maximize performance and save block RAM resources, the small ROM <Mrom_tdecoded_mux0112> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
-INFO:Xst:3034 - In order to maximize performance and save block RAM resources, the small ROM <Mrom_tdecoded_mux0113> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
-INFO:Xst:3034 - In order to maximize performance and save block RAM resources, the small ROM <Mrom_insn_mux0002> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
-INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult_mult_res_mult0000 by adding 2 register level(s).
-Unit <ZPUMediumCore> synthesized (advanced).
-
-Synthesizing (advanced) Unit <basic>.
-INFO:Xst:3044 - The ROM <Mrom_rdata> will be implemented as a read-only BLOCK RAM, absorbing the register: <q>.
-INFO:Xst:3225 - The RAM <Mrom_rdata> will be implemented as BLOCK RAM
-    -----------------------------------------------------------------------
-    | ram_type           | Block                               |          |
-    -----------------------------------------------------------------------
-    | Port A                                                              |
-    |     aspect ratio   | 8192-word x 8-bit                   |          |
-    |     mode           | write-first                         |          |
-    |     clkA           | connected to signal <clock>         | rise     |
-    |     weA            | connected to internal node          | high     |
-    |     addrA          | connected to signal <address>       |          |
-    |     diA            | connected to internal node          |          |
-    |     doA            | connected to signal <q>             |          |
-    -----------------------------------------------------------------------
-    | optimization       | area                                |          |
-    -----------------------------------------------------------------------
-Unit <basic> synthesized (advanced).
-
-Synthesizing (advanced) Unit <cpu_65xx>.
-INFO:Xst:3044 - The ROM <Mrom_nextOpcInfo_rom0000> will be implemented as a read-only BLOCK RAM, absorbing the register: <opcInfo>.
-INFO:Xst:3225 - The RAM <Mrom_nextOpcInfo_rom0000> will be implemented as BLOCK RAM
-    -----------------------------------------------------------------------
-    | ram_type           | Block                               |          |
-    -----------------------------------------------------------------------
-    | Port A                                                              |
-    |     aspect ratio   | 256-word x 44-bit                   |          |
-    |     mode           | write-first                         |          |
-    |     clkA           | connected to signal <clk>           | rise     |
-    |     enA            | connected to signal <opcInfo_not0001> | high     |
-    |     weA            | connected to signal <GND>           | high     |
-    |     addrA          | connected to signal <nextOpcode>    |          |
-    |     diA            | connected to signal <GND>           |          |
-    |     doA            | connected to signal <opcInfo>       |          |
-    -----------------------------------------------------------------------
-    | optimization       | area                                |          |
-    -----------------------------------------------------------------------
-Unit <cpu_65xx> synthesized (advanced).
-
-Synthesizing (advanced) Unit <generic_ram_infer_1>.
-INFO:Xst:3230 - The RAM description <Mram_ram_block> will not be implemented on the device block RAM because of limited available resources. If you would like this RAM to be implemented in block RAM, please select a larger device or increase the value specified by the BRAM_Utilization_Ratio constraint.
-    -----------------------------------------------------------------------
-    | ram_type           | Distributed                         |          |
-    -----------------------------------------------------------------------
-    | Port A                                                              |
-    |     aspect ratio   | 1024-word x 8-bit                   |          |
-    |     clkA           | connected to signal <clock>         | rise     |
-    |     weA            | connected to signal <we>            | high     |
-    |     addrA          | connected to signal <address>       |          |
-    |     diA            | connected to signal <data>          |          |
-    |     doA            | connected to internal node          |          |
-    -----------------------------------------------------------------------
-Unit <generic_ram_infer_1> synthesized (advanced).
-
-Synthesizing (advanced) Unit <generic_ram_infer_2>.
-INFO:Xst:3226 - The RAM <Mram_ram_block> will be implemented as a BLOCK RAM, absorbing the following register(s): <q>
-    -----------------------------------------------------------------------
-    | ram_type           | Block                               |          |
-    -----------------------------------------------------------------------
-    | Port A                                                              |
-    |     aspect ratio   | 16384-word x 8-bit                  |          |
-    |     mode           | read-first                          |          |
-    |     clkA           | connected to signal <clock>         | rise     |
-    |     weA            | connected to signal <we>            | high     |
-    |     addrA          | connected to signal <address>       |          |
-    |     diA            | connected to signal <data>          |          |
-    |     doA            | connected to signal <q>             |          |
-    -----------------------------------------------------------------------
-    | optimization       | area                                |          |
-    -----------------------------------------------------------------------
-Unit <generic_ram_infer_2> synthesized (advanced).
-
-Synthesizing (advanced) Unit <os16>.
-INFO:Xst:3044 - The ROM <Mrom_rdata> will be implemented as a read-only BLOCK RAM, absorbing the register: <q>.
-INFO:Xst:3225 - The RAM <Mrom_rdata> will be implemented as BLOCK RAM
-    -----------------------------------------------------------------------
-    | ram_type           | Block                               |          |
-    -----------------------------------------------------------------------
-    | Port A                                                              |
-    |     aspect ratio   | 16384-word x 8-bit                  |          |
-    |     mode           | write-first                         |          |
-    |     clkA           | connected to signal <clock>         | rise     |
-    |     weA            | connected to internal node          | high     |
-    |     addrA          | connected to signal <address>       |          |
-    |     diA            | connected to internal node          |          |
-    |     doA            | connected to signal <q>             |          |
-    -----------------------------------------------------------------------
-    | optimization       | area                                |          |
-    -----------------------------------------------------------------------
-Unit <os16> synthesized (advanced).
-
-Synthesizing (advanced) Unit <zpu_rom>.
-INFO:Xst:3044 - The ROM <Mrom_rdata> will be implemented as a read-only BLOCK RAM, absorbing the register: <q>.
-INFO:Xst:3225 - The RAM <Mrom_rdata> will be implemented as BLOCK RAM
-    -----------------------------------------------------------------------
-    | ram_type           | Block                               |          |
-    -----------------------------------------------------------------------
-    | Port A                                                              |
-    |     aspect ratio   | 4096-word x 32-bit                  |          |
-    |     mode           | write-first                         |          |
-    |     clkA           | connected to signal <clock>         | rise     |
-    |     weA            | connected to internal node          | high     |
-    |     addrA          | connected to signal <address>       |          |
-    |     diA            | connected to internal node          |          |
-    |     doA            | connected to signal <q>             |          |
-    -----------------------------------------------------------------------
-    | optimization       | area                                |          |
-    -----------------------------------------------------------------------
-Unit <zpu_rom> synthesized (advanced).
-WARNING:Xst:2677 - Node <rpipe_1> of sequential type is unconnected in block <Replay_DDRCtrl_Datapath>.
-WARNING:Xst:2677 - Node <rpipe_2> of sequential type is unconnected in block <Replay_DDRCtrl_Datapath>.
-WARNING:Xst:2677 - Node <wpipe_2> of sequential type is unconnected in block <Replay_DDRCtrl_Datapath>.
-WARNING:Xst:2677 - Node <an_prev2_reg_2> of sequential type is unconnected in block <gtia>.
-WARNING:Xst:2677 - Node <displayed_character_reg_0> of sequential type is unconnected in block <antic>.
-WARNING:Xst:2677 - Node <displayed_character_reg_1> of sequential type is unconnected in block <antic>.
-WARNING:Xst:2677 - Node <displayed_character_reg_2> of sequential type is unconnected in block <antic>.
-WARNING:Xst:2677 - Node <displayed_character_reg_3> of sequential type is unconnected in block <antic>.
-WARNING:Xst:2677 - Node <displayed_character_reg_4> of sequential type is unconnected in block <antic>.
-WARNING:Xst:2677 - Node <cur_addr_11> of sequential type is unconnected in block <Replay_DDRCtrl>.
-WARNING:Xst:2677 - Node <cur_addr_12> of sequential type is unconnected in block <Replay_DDRCtrl>.
-WARNING:Xst:2677 - Node <cur_addr_13> of sequential type is unconnected in block <Replay_DDRCtrl>.
-WARNING:Xst:2677 - Node <cur_addr_14> of sequential type is unconnected in block <Replay_DDRCtrl>.
-WARNING:Xst:2677 - Node <cur_addr_15> of sequential type is unconnected in block <Replay_DDRCtrl>.
-WARNING:Xst:2677 - Node <cur_addr_16> of sequential type is unconnected in block <Replay_DDRCtrl>.
-WARNING:Xst:2677 - Node <cur_addr_17> of sequential type is unconnected in block <Replay_DDRCtrl>.
-WARNING:Xst:2677 - Node <cur_addr_18> of sequential type is unconnected in block <Replay_DDRCtrl>.
-WARNING:Xst:2677 - Node <cur_addr_19> of sequential type is unconnected in block <Replay_DDRCtrl>.
-WARNING:Xst:2677 - Node <cur_addr_20> of sequential type is unconnected in block <Replay_DDRCtrl>.
-WARNING:Xst:2677 - Node <cur_addr_21> of sequential type is unconnected in block <Replay_DDRCtrl>.
-WARNING:Xst:2677 - Node <cur_addr_22> of sequential type is unconnected in block <Replay_DDRCtrl>.
-WARNING:Xst:2677 - Node <cur_addr_23> of sequential type is unconnected in block <Replay_DDRCtrl>.
-WARNING:Xst:2677 - Node <pix_active_t_3> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <char_vid_dout_t1_0> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <char_vid_dout_t1_1> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <char_vid_dout_t1_2> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <char_vid_dout_t1_3> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <char_vid_dout_t1_4> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <char_vid_dout_t1_5> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <char_vid_dout_t1_6> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <font_addr_t1_0> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <font_addr_t1_1> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <font_addr_t1_2> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <font_addr_t1_3> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <font_addr_t1_4> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <font_addr_t1_5> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <font_addr_t1_6> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <font_addr_t1_7> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <font_addr_t1_8> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <font_addr_t1_9> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <font_addr_t1_10> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <font_addr_t1_11> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <font_addr_t1_12> of sequential type is unconnected in block <Replay_OSD>.
-WARNING:Xst:2677 - Node <spi_cmd_low_5> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_low_6> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_low_7> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_low_8> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_low_9> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_low_10> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_low_11> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_low_12> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_low_13> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_low_14> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_low_15> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_high_0> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_high_1> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_high_3> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_high_9> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_high_12> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_high_13> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_high_14> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_high_15> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_byte_sel_5> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_byte_sel_6> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <spi_byte_sel_7> of sequential type is unconnected in block <Replay_FileIO>.
-WARNING:Xst:2677 - Node <serin_shift_reg_0> of sequential type is unconnected in block <pokey>.
-WARNING:Xst:2677 - Node <serin_shift_reg_1> of sequential type is unconnected in block <pokey>.
-WARNING:Xst:2677 - Node <serout_shift_reg_0> of sequential type is unconnected in block <pokey>.
-WARNING:Xst:2677 - Node <spi_cmd_low_2> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_low_4> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_low_5> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_low_6> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_low_7> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_low_9> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_low_10> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_low_11> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_low_12> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_low_13> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_low_14> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_low_15> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_high_1> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_high_3> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_high_4> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_high_6> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_high_7> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_high_8> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_high_9> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_high_10> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_high_11> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_high_13> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_high_14> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_cmd_high_15> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <h_size_0> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_byte_sel_5> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_byte_sel_6> of sequential type is unconnected in block <Replay_Syscon>.
-WARNING:Xst:2677 - Node <spi_byte_sel_7> of sequential type is unconnected in block <Replay_Syscon>.
-
-=========================================================================
-Advanced HDL Synthesis Report
-
-Macro Statistics
-# FSMs                                                 : 9
-# RAMs                                                 : 11
- 1024x8-bit single-port distributed RAM                : 4
- 16384x8-bit single-port block RAM                     : 2
- 2048x24-bit dual-port distributed RAM                 : 1
- 256x44-bit single-port block RAM                      : 1
- 4096x32-bit single-port block RAM                     : 1
- 512x8-bit dual-port distributed RAM                   : 1
- 8192x8-bit single-port block RAM                      : 1
-# ROMs                                                 : 20
- 16x15-bit ROM                                         : 1
- 16x7-bit ROM                                          : 1
- 256x24-bit ROM                                        : 1
- 32x6-bit ROM                                          : 4
- 4x1-bit ROM                                           : 1
- 4x12-bit ROM                                          : 1
- 4x4-bit ROM                                           : 1
- 4x8-bit ROM                                           : 1
- 64x16-bit ROM                                         : 2
- 8x1-bit ROM                                           : 3
- 8x8-bit ROM                                           : 4
-# Multipliers                                          : 2
- 14x14-bit multiplier                                  : 1
- 32x32-bit registered multiplier                       : 1
-# Adders/Subtractors                                   : 104
- 10-bit adder                                          : 3
- 10-bit subtractor                                     : 1
- 11-bit adder                                          : 1
- 12-bit adder                                          : 1
- 12-bit subtractor                                     : 3
- 14-bit adder                                          : 10
- 14-bit adder carry out                                : 1
- 14-bit subtractor                                     : 6
- 14-bit subtractor borrow in                           : 1
- 16-bit adder                                          : 7
- 19-bit subtractor                                     : 1
- 22-bit adder                                          : 3
- 22-bit adder carry in                                 : 1
- 22-bit subtractor                                     : 1
- 24-bit adder                                          : 2
- 28-bit adder                                          : 1
- 28-bit subtractor                                     : 1
- 3-bit adder                                           : 1
- 32-bit adder                                          : 3
- 32-bit subtractor                                     : 2
- 4-bit adder                                           : 5
- 4-bit subtractor                                      : 8
- 5-bit adder                                           : 10
- 6-bit adder                                           : 5
- 6-bit subtractor                                      : 1
- 7-bit adder                                           : 3
- 8-bit adder                                           : 3
- 8-bit addsub                                          : 1
- 8-bit subtractor                                      : 14
- 9-bit adder                                           : 3
- 9-bit adder carry in                                  : 1
-# Counters                                             : 37
- 11-bit up counter                                     : 2
- 12-bit down counter                                   : 1
- 12-bit up counter                                     : 2
- 14-bit up counter                                     : 2
- 16-bit up counter                                     : 1
- 2-bit up counter                                      : 1
- 24-bit up counter                                     : 1
- 3-bit up counter                                      : 2
- 4-bit up counter                                      : 9
- 5-bit up counter                                      : 3
- 6-bit up counter                                      : 3
- 8-bit down counter                                    : 2
- 8-bit up counter                                      : 6
- 9-bit up counter                                      : 2
-# Accumulators                                         : 4
- 12-bit up accumulator                                 : 1
- 4-bit up accumulator                                  : 2
- 8-bit up accumulator                                  : 1
-# Registers                                            : 6488
- Flip-Flops                                            : 6488
-# Comparators                                          : 68
- 12-bit comparator equal                               : 2
- 14-bit comparator equal                               : 17
- 14-bit comparator lessequal                           : 2
- 14-bit comparator not equal                           : 9
- 24-bit comparator less                                : 1
- 32-bit comparator equal                               : 1
- 32-bit comparator greater                             : 2
- 32-bit comparator less                                : 2
- 32-bit comparator lessequal                           : 2
- 4-bit comparator equal                                : 2
- 4-bit comparator greatequal                           : 2
- 4-bit comparator greater                              : 1
- 4-bit comparator less                                 : 2
- 5-bit comparator greater                              : 4
- 6-bit comparator equal                                : 4
- 8-bit comparator equal                                : 12
- 8-bit comparator greater                              : 1
- 8-bit comparator not equal                            : 2
-# Multiplexers                                         : 62
- 1-bit 16-to-1 multiplexer                             : 6
- 1-bit 4-to-1 multiplexer                              : 11
- 1-bit 8-to-1 multiplexer                              : 16
- 2-bit 4-to-1 multiplexer                              : 4
- 24-bit 4-to-1 multiplexer                             : 2
- 24-bit 8-to-1 multiplexer                             : 1
- 32-bit 4-to-1 multiplexer                             : 1
- 4-bit 16-to-1 multiplexer                             : 1
- 5-bit 16-to-1 multiplexer                             : 1
- 6-bit 4-to-1 multiplexer                              : 1
- 8-bit 4-to-1 multiplexer                              : 18
-# Decoders                                             : 1
- 1-of-16 decoder                                       : 1
-# Xors                                                 : 24
- 1-bit xor2                                            : 21
- 3-bit xor2                                            : 2
- 8-bit xor2                                            : 1
-
-=========================================================================
-
-=========================================================================
-*                         Low Level Synthesis                           *
-=========================================================================
-WARNING:Xst:1293 - FF/Latch <halt_dly> has a constant value of 0 in block <cpu_65xx>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <p0pl_reg_0> (without init value) has a constant value of 0 in block <gtia>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <p1pl_reg_1> (without init value) has a constant value of 0 in block <gtia>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <p2pl_reg_2> (without init value) has a constant value of 0 in block <gtia>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <p3pl_reg_3> (without init value) has a constant value of 0 in block <gtia>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <nmist_reg_5> (without init value) has a constant value of 0 in block <antic>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <spi_stat_gen_3_7> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_3_6> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_3_5> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_3_4> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_3_3> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_3_2> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_3_1> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_3_0> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_2_7> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_2_6> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_2_5> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_2_4> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_2_3> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_2_2> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_2_1> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_2_0> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_1_7> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_1_6> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_1_5> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_1_4> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_1_3> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_1_2> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_1_1> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_1_0> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen<0>_7> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen<0>_6> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen<0>_5> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen<0>_4> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen<0>_3> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen<0>_2> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen<0>_1> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen<0>_0> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
-INFO:Xst:2261 - The FF/Latch <wpipe_1> in Unit <Replay_DDRCtrl_Datapath> is equivalent to the following FF/Latch, which will be removed : <dqs_enable> 
-INFO:Xst:2261 - The FF/Latch <ana_vs> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <dig_vs> 
-INFO:Xst:2261 - The FF/Latch <ana_hs> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <dig_hs> 
-INFO:Xst:2261 - The FF/Latch <active_bk_valid_reg_0> in Unit <gtia> is equivalent to the following 3 FFs/Latches, which will be removed : <active_bk_valid_reg_1> <active_bk_valid_reg_2> <active_bk_valid_reg_3> 
-INFO:Xst:2261 - The FF/Latch <active_bk_valid_reg_4> in Unit <gtia> is equivalent to the following 3 FFs/Latches, which will be removed : <active_bk_valid_reg_5> <active_bk_valid_reg_6> <active_bk_valid_reg_7> 
-INFO:Xst:2261 - The FF/Latch <o_vbl> in Unit <Replay_Syscon> is equivalent to the following FF/Latch, which will be removed : <vs_t_0> 
-INFO:Xst:2261 - The FF/Latch <osd_hexp> in Unit <Replay_Syscon> is equivalent to the following FF/Latch, which will be removed : <h_size_10> 
-INFO:Xst:2261 - The FF/Latch <hs_t_0> in Unit <Replay_Syscon> is equivalent to the following FF/Latch, which will be removed : <o_vid_sync.dig_hs> 
-WARNING:Xst:1710 - FF/Latch <volume_reg_15> (without init value) has a constant value of 0 in block <pokey_mixer>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:2677 - Node <Mmult_mult_res_mult0000_submult_11> of sequential type is unconnected in block <ZPUMediumCore>.
-WARNING:Xst:2677 - Node <vidin_vcnt_s_2> of sequential type is unconnected in block <Replay_VideoConverter>.
-WARNING:Xst:2677 - Node <vidin_vcnt_s_3> of sequential type is unconnected in block <Replay_VideoConverter>.
-WARNING:Xst:2677 - Node <vidin_vcnt_s_4> of sequential type is unconnected in block <Replay_VideoConverter>.
-WARNING:Xst:2677 - Node <vidin_vcnt_s_5> of sequential type is unconnected in block <Replay_VideoConverter>.
-WARNING:Xst:2677 - Node <vidin_vcnt_s_6> of sequential type is unconnected in block <Replay_VideoConverter>.
-WARNING:Xst:2677 - Node <vidin_vcnt_s_7> of sequential type is unconnected in block <Replay_VideoConverter>.
-WARNING:Xst:2677 - Node <vidin_vcnt_s_8> of sequential type is unconnected in block <Replay_VideoConverter>.
-WARNING:Xst:2677 - Node <vidin_vcnt_s_9> of sequential type is unconnected in block <Replay_VideoConverter>.
-WARNING:Xst:2677 - Node <vidin_vcnt_s_10> of sequential type is unconnected in block <Replay_VideoConverter>.
-WARNING:Xst:2677 - Node <vidin_vcnt_s_11> of sequential type is unconnected in block <Replay_VideoConverter>.
-WARNING:Xst:2677 - Node <vidin_vcnt_s_12> of sequential type is unconnected in block <Replay_VideoConverter>.
-WARNING:Xst:2677 - Node <vidin_vcnt_s_13> of sequential type is unconnected in block <Replay_VideoConverter>.
-WARNING:Xst:2677 - Node <vidin_hcnt_s_9> of sequential type is unconnected in block <Replay_VideoConverter>.
-WARNING:Xst:2677 - Node <vidin_hcnt_s_10> of sequential type is unconnected in block <Replay_VideoConverter>.
-WARNING:Xst:2677 - Node <vidin_hcnt_s_11> of sequential type is unconnected in block <Replay_VideoConverter>.
-WARNING:Xst:2677 - Node <vidin_hcnt_s_12> of sequential type is unconnected in block <Replay_VideoConverter>.
-WARNING:Xst:2677 - Node <vidin_hcnt_s_13> of sequential type is unconnected in block <Replay_VideoConverter>.
-WARNING:Xst:2677 - Node <instruction_type_reg_4> of sequential type is unconnected in block <antic>.
-WARNING:Xst:2677 - Node <dma_speed_reg_0> of sequential type is unconnected in block <antic>.
-INFO:Xst:2261 - The FF/Latch <param_c.h_start_2nd_0> in Unit <Replay_VideoTiming> is equivalent to the following 2 FFs/Latches, which will be removed : <param_c.h_stop_eq2_0> <param_c.h_stop_bd2_0> 
-INFO:Xst:2261 - The FF/Latch <param_c.h_start_act_0> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <param_c.h_start_ana_0> 
-INFO:Xst:2261 - The FF/Latch <param_c.h_start_2nd_1> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <param_c.h_stop_bd2_1> 
-INFO:Xst:2261 - The FF/Latch <param_c.h_start_2nd_2> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <param_c.h_stop_bd2_2> 
-INFO:Xst:2261 - The FF/Latch <param_c.h_start_2nd_3> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <param_c.h_stop_bd2_3> 
-INFO:Xst:2261 - The FF/Latch <param_c.h_start_2nd_4> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <param_c.h_stop_bd2_4> 
-INFO:Xst:2261 - The FF/Latch <param_c.h_start_sync_0> in Unit <Replay_VideoTiming> is equivalent to the following 2 FFs/Latches, which will be removed : <param_c.h_stop_eq1_0> <param_c.h_stop_bd1_0> 
-INFO:Xst:2261 - The FF/Latch <param_c.h_start_sync_1> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <param_c.h_stop_bd1_1> 
-INFO:Xst:2261 - The FF/Latch <param_c.h_start_sync_2> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <param_c.h_stop_bd1_2> 
-INFO:Xst:2261 - The FF/Latch <param_c.h_start_sync_3> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <param_c.h_stop_bd1_3> 
-INFO:Xst:2261 - The FF/Latch <param_c.h_start_sync_4> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <param_c.h_stop_bd1_4> 
-WARNING:Xst:2039 - Unit Replay_Top: 1 multi-source signal is replaced by logic (pull-up yes): b_FPGA_SPI_MISO_MLTSRCEDGE.
-WARNING:Xst:2041 - Unit pokey: 1 internal tristate is replaced by logic (pull-up yes): SIO_CLOCK.
-
-Optimizing unit <Replay_Top> ...
-
-Optimizing unit <complete_address_decoder_1> ...
-
-Optimizing unit <irq_glue> ...
-
-Optimizing unit <complete_address_decoder_2> ...
-
-Optimizing unit <complete_address_decoder_5> ...
-
-Optimizing unit <pokey_noise_filter> ...
-
-Optimizing unit <complete_address_decoder_3> ...
-
-Optimizing unit <complete_address_decoder_4> ...
-
-Optimizing unit <Replay_Audio> ...
-
-Optimizing unit <Replay_ResetGen> ...
-
-Optimizing unit <Replay_TranslatePS2> ...
-
-Optimizing unit <pokey_mixer> ...
-
-Optimizing unit <address_decoder> ...
-
-Optimizing unit <zpu_rom> ...
-
-Optimizing unit <generic_ram_infer_1> ...
-
-Optimizing unit <gtia_palette> ...
-
-Optimizing unit <cpu_65xx> ...
-
-Optimizing unit <antic_counter_1> ...
-
-Optimizing unit <antic_counter_2> ...
-
-Optimizing unit <simple_counter_1> ...
-
-Optimizing unit <simple_counter_2> ...
-
-Optimizing unit <wide_delay_line_1> ...
-
-Optimizing unit <antic_dma_clock> ...
-
-Optimizing unit <wide_delay_line_2> ...
-
-Optimizing unit <wide_delay_line_3> ...
-
-Optimizing unit <delay_line_1> ...
-
-Optimizing unit <ZPUMediumCore> ...
-
-Optimizing unit <delay_line_2> ...
-
-Optimizing unit <syncreset_enable_divider_1> ...
-
-Optimizing unit <syncreset_enable_divider_2> ...
-
-Optimizing unit <delay_line_3> ...
-
-Optimizing unit <synchronizer> ...
-
-Optimizing unit <pokey_keyboard_scanner> ...
-
-Optimizing unit <enable_divider_1> ...
-
-Optimizing unit <enable_divider_2> ...
-
-Optimizing unit <delay_line_4> ...
-
-Optimizing unit <delay_line_5> ...
-
-Optimizing unit <gtia_player> ...
-
-Optimizing unit <gtia_priority> ...
-
-Optimizing unit <wide_delay_line_4> ...
-
-Optimizing unit <wide_delay_line_5> ...
-
-Optimizing unit <wide_delay_line_6> ...
-
-Optimizing unit <wide_delay_line_7> ...
-
-Optimizing unit <wide_delay_line_8> ...
-
-Optimizing unit <wide_delay_line_9> ...
-
-Optimizing unit <basic> ...
-
-Optimizing unit <os16> ...
-
-Optimizing unit <generic_ram_infer_2> ...
-
-Optimizing unit <pia> ...
-
-Optimizing unit <reg_file_1> ...
-
-Optimizing unit <reg_file_2> ...
-
-Optimizing unit <covox> ...
-
-Optimizing unit <reg_file_3> ...
-
-Optimizing unit <ps2_rom> ...
-
-Optimizing unit <kcpsm3> ...
-
-Optimizing unit <Replay_DDRCtrl_Datapath> ...
-
-Optimizing unit <FIFO_SyncSRL_D16> ...
-
-Optimizing unit <FONT0> ...
-
-Optimizing unit <FONT1> ...
-
-Optimizing unit <FONT2> ...
-
-Optimizing unit <FIFO_SyncBlock_D2048_W8> ...
-
-Optimizing unit <poly_17_9> ...
-
-Optimizing unit <poly_5> ...
-
-Optimizing unit <poly_4> ...
-
-Optimizing unit <Replay_VideoTiming> ...
-
-Optimizing unit <Replay_SPI8> ...
-
-Optimizing unit <Replay_I2C> ...
-
-Optimizing unit <Replay_ClockGen> ...
-
-Optimizing unit <cpu> ...
-
-Optimizing unit <zpu_glue> ...
-
-Optimizing unit <shared_enable> ...
-
-Optimizing unit <gtia> ...
-
-Optimizing unit <internalromram> ...
-
-Optimizing unit <pokey_countdown_timer> ...
-
-Optimizing unit <antic> ...
-
-Optimizing unit <Replay_JoyPS2_Core_1> ...
-
-Optimizing unit <Replay_JoyPS2_Core_2> ...
-
-Optimizing unit <Replay_DDRCtrl> ...
-
-Optimizing unit <Replay_OSD> ...
-
-Optimizing unit <Replay_Video> ...
-
-Optimizing unit <Replay_VideoConverter> ...
-
-Optimizing unit <Replay_FileIO> ...
-
-Optimizing unit <pokey> ...
-
-Optimizing unit <Replay_JoyPS2> ...
-
-Optimizing unit <Replay_DDRCtrl_Top> ...
-
-Optimizing unit <Replay_Syscon> ...
-
-Optimizing unit <zpu_config_regs> ...
-
-Optimizing unit <atari800core> ...
-
-Optimizing unit <Core_Top> ...
-WARNING:Xst:1710 - FF/Latch <shift_reg_2> (without init value) has a constant value of 0 in block <missile1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_1> (without init value) has a constant value of 0 in block <missile1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_0> (without init value) has a constant value of 0 in block <missile1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_5> (without init value) has a constant value of 0 in block <missile2>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_4> (without init value) has a constant value of 0 in block <missile2>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_3> (without init value) has a constant value of 0 in block <missile2>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_2> (without init value) has a constant value of 0 in block <missile2>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_1> (without init value) has a constant value of 0 in block <missile2>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_0> (without init value) has a constant value of 0 in block <missile2>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_5> (without init value) has a constant value of 0 in block <missile3>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_4> (without init value) has a constant value of 0 in block <missile3>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_3> (without init value) has a constant value of 0 in block <missile3>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_2> (without init value) has a constant value of 0 in block <missile3>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_1> (without init value) has a constant value of 0 in block <missile3>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_0> (without init value) has a constant value of 0 in block <missile3>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <trig2_reg> (without init value) has a constant value of 0 in block <gtia1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <trig3_reg> (without init value) has a constant value of 0 in block <gtia1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq2_1> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_sync_0> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_ana_3> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_ana_2> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_ana_1> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_bd1_13> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_bd1_12> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_bd1_11> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_bd1_10> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_bd1_9> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <state_reg_FSM_FFd2> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <state_reg_FSM_FFd1> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <compare_latch_reg_5> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <compare_latch_reg_4> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <compare_latch_reg_3> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <compare_latch_reg_2> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <compare_latch_reg_1> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <compare_latch_reg_0> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <break_pressed_reg> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <control_pressed_reg> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <irq_reg> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <key_held_reg> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_pressed_reg> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ff_reg_2> (without init value) has a constant value of 1 in block <sio_in2_synchronizer>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ff_reg_2> (without init value) has a constant value of 1 in block <sio_in3_synchronizer>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ff_reg_2> (without init value) has a constant value of 1 in block <sio_in1_synchronizer>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ff_reg_2> (without init value) has a constant value of 1 in block <sio_in2_synchronizer>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ff_reg_2> (without init value) has a constant value of 1 in block <sio_in3_synchronizer>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <ff_reg_2> (without init value) has a constant value of 1 in block <sio_in2_synchronizer>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_5> (without init value) has a constant value of 0 in block <missile0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_4> (without init value) has a constant value of 0 in block <missile0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_3> (without init value) has a constant value of 0 in block <missile0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_2> (without init value) has a constant value of 0 in block <missile0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_1> (without init value) has a constant value of 0 in block <missile0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_0> (without init value) has a constant value of 0 in block <missile0>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_5> (without init value) has a constant value of 0 in block <missile1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_4> (without init value) has a constant value of 0 in block <missile1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shift_reg_3> (without init value) has a constant value of 0 in block <missile1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_10> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_9> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_8> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_7> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_6> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_5> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_1> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_0> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_act_3> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_act_2> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_act_1> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_act_0> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_len_13> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_len_12> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_len_11> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_len_9> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_len_4> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_len_3> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_len_2> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_len_1> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_len_0> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <hp_addr_25> (without init value) has a constant value of 0 in block <u_DDRCtrl>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <hp_addr_24> (without init value) has a constant value of 0 in block <u_DDRCtrl>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <hp_addr_23> (without init value) has a constant value of 0 in block <u_DDRCtrl>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <cpu_in_port_6> (without init value) has a constant value of 0 in block <u_PSB>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <cpu_in_port_6> (without init value) has a constant value of 0 in block <u_PSA>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <shifter_0> (without init value) has a constant value of 0 in block <u_Audio>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_ana_13> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_1> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_5> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_6> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_7> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_8> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_9> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_10> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_11> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_12> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_13> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_2nd_0> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_2nd_1> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_bd1_5> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_bd1_6> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_bd1_7> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_bd1_8> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_11> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_12> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_13> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_ana_0> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_ana_1> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_ana_2> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_ana_3> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_ana_4> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_ana_9> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_ana_11> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1710 - FF/Latch <param_c.h_stop_ana_12> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_1> (without init value) has a constant value of 1 in block <sio_in2_synchronizer>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_1> (without init value) has a constant value of 1 in block <sio_in3_synchronizer>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_1> (without init value) has a constant value of 1 in block <sio_in2_synchronizer>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_1> (without init value) has a constant value of 1 in block <sio_in2_synchronizer>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <keycode_latch_reg_5> (without init value) has a constant value of 1 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_1> (without init value) has a constant value of 1 in block <sio_in3_synchronizer>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <keycode_latch_reg_4> (without init value) has a constant value of 1 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <keycode_latch_reg_3> (without init value) has a constant value of 1 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_1> (without init value) has a constant value of 1 in block <sio_in1_synchronizer>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <keycode_latch_reg_0> (without init value) has a constant value of 1 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <keycode_latch_reg_1> (without init value) has a constant value of 1 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <keycode_latch_reg_2> (without init value) has a constant value of 1 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_0> (without init value) has a constant value of 1 in block <sio_in1_synchronizer>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_0> (without init value) has a constant value of 1 in block <sio_in2_synchronizer>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_0> (without init value) has a constant value of 1 in block <sio_in3_synchronizer>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_0> (without init value) has a constant value of 1 in block <sio_in2_synchronizer>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_0> (without init value) has a constant value of 1 in block <sio_in2_synchronizer>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_0> (without init value) has a constant value of 1 in block <sio_in3_synchronizer>. This FF/Latch will be trimmed during the optimization process.
-WARNING:Xst:2677 - Node <writeprotn_s> of sequential type is unconnected in block <Replay_Top>.
-WARNING:Xst:2677 - Node <ena_sub4> of sequential type is unconnected in block <Replay_Top>.
-WARNING:Xst:2677 - Node <diskid_s_2> of sequential type is unconnected in block <Replay_Top>.
-WARNING:Xst:2677 - Node <diskid_s_0> of sequential type is unconnected in block <Replay_Top>.
-WARNING:Xst:2677 - Node <diskid_s_1> of sequential type is unconnected in block <Replay_Top>.
-WARNING:Xst:2677 - Node <diskid_s_3> of sequential type is unconnected in block <Replay_Top>.
-WARNING:Xst:2677 - Node <diskid_s_4> of sequential type is unconnected in block <Replay_Top>.
-WARNING:Xst:2677 - Node <diskid_s_5> of sequential type is unconnected in block <Replay_Top>.
-WARNING:Xst:2677 - Node <diskid_s_6> of sequential type is unconnected in block <Replay_Top>.
-WARNING:Xst:2677 - Node <diskid_s_7> of sequential type is unconnected in block <Replay_Top>.
-WARNING:Xst:2677 - Node <diskid_s_8> of sequential type is unconnected in block <Replay_Top>.
-WARNING:Xst:2677 - Node <diskid_s_9> of sequential type is unconnected in block <Replay_Top>.
-WARNING:Xst:2677 - Node <diskid_s_10> of sequential type is unconnected in block <Replay_Top>.
-WARNING:Xst:2677 - Node <diskid_s_11> of sequential type is unconnected in block <Replay_Top>.
-WARNING:Xst:2677 - Node <diskid_s_12> of sequential type is unconnected in block <Replay_Top>.
-WARNING:Xst:2677 - Node <diskid_s_13> of sequential type is unconnected in block <Replay_Top>.
-WARNING:Xst:2677 - Node <diskid_s_14> of sequential type is unconnected in block <Replay_Top>.
-WARNING:Xst:2677 - Node <diskid_s_15> of sequential type is unconnected in block <Replay_Top>.
-WARNING:Xst:2677 - Node <o_sample_taken> of sequential type is unconnected in block <u_Audio>.
-WARNING:Xst:2677 - Node <ps_eq> of sequential type is unconnected in block <u_ClockGen>.
-WARNING:Xst:2677 - Node <ps_eq_meta> of sequential type is unconnected in block <u_ClockGen>.
-WARNING:Xst:2677 - Node <o_rst_ram_capture> of sequential type is unconnected in block <u_ClockGen>.
-WARNING:Xst:2677 - Node <write_ena> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <write_data_0> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <write_data_1> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <write_data_2> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <write_data_3> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <write_data_4> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <write_data_5> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <write_data_6> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <write_data_7> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <devid_0> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <devid_1> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <devid_2> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <devid_3> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <devid_4> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <devid_5> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <devid_6> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <rab_0> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <rab_1> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <rab_2> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <rab_3> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <rab_4> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <rab_5> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <rab_6> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <rab_7> of sequential type is unconnected in block <u_I2C>.
-WARNING:Xst:2677 - Node <o_fch_to_core.data_we> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.cmd_ack> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.cmd_done> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.data_taken> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.cmd_done> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_low_2> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_low_3> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.status_we> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <spi_cs_meta_0> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <spi_cs_meta_1> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <spi_cs_meta_2> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <spi_cs_meta_3> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.cmd_err> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.cmd_ack> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.data_we> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.cmd_err> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.data_taken> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_high_2> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_high_4> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_high_5> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_high_6> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <spi_cmd_high_7> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.update> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <spi_done> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.writable_3> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.writable_2> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.status_0> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.status_1> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.status_2> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.status_3> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.status_4> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.status_5> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.status_6> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.status_7> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.data_0> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.data_1> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.data_2> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.data_3> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.data_4> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.data_5> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.data_6> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.data_7> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.data_0> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.data_1> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.data_2> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.data_3> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.data_4> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.data_5> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.data_6> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_hch_to_core.data_7> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.inserted_0> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.inserted_1> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.inserted_2> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.inserted_3> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.writable_0> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.writable_1> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.pos_0> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.pos_1> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.pos_2> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_fch_to_core.pos_3> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <spi_pos_cnt_0> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <spi_pos_cnt_1> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <spi_pos_cnt_2> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <spi_pos_cnt_3> of sequential type is unconnected in block <u_FileIO>.
-WARNING:Xst:2677 - Node <o_rxbytesel_5> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxbytesel_6> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxbytesel_7> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxbytecnt_0> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxbytecnt_1> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxbytecnt_2> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxbytecnt_3> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxcmd_0> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxcmd_1> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxcmd_2> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxcmd_3> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <byte_cnt_0> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <byte_cnt_1> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <byte_cnt_2> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <byte_cnt_3> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <byte_7> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <byte_6> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <byte_5> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <joy_b_reg_0> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <joy_b_reg_1> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <joy_b_reg_2> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <joy_b_reg_3> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <joy_b_reg_4> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <joy_b_reg_5> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posy_0> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posy_1> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posy_2> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posy_3> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posy_4> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posy_5> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posy_6> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posy_7> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posy_8> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posy_9> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posx_0> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posx_1> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posx_2> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posx_3> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posx_4> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_butn_0> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_butn_1> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_butn_2> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posx_10> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posx_5> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posx_11> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posx_6> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posx_7> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posx_8> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posx_9> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posy_10> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <joy_a_reg_0> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <joy_a_reg_1> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <joy_a_reg_2> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <joy_a_reg_3> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <joy_a_reg_4> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <joy_a_reg_5> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_posy_11> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <o_ms_we> of sequential type is unconnected in block <u_JoyPS2>.
-WARNING:Xst:2677 - Node <status_0> of sequential type is unconnected in block <u_PSA>.
-WARNING:Xst:2677 - Node <status_1> of sequential type is unconnected in block <u_PSA>.
-WARNING:Xst:2677 - Node <status_0> of sequential type is unconnected in block <u_PSB>.
-WARNING:Xst:2677 - Node <status_1> of sequential type is unconnected in block <u_PSB>.
-WARNING:Xst:2677 - Node <r_we_hp> of sequential type is unconnected in block <u_DDRCtrl>.
-WARNING:Xst:2677 - Node <cur_hp> of sequential type is unconnected in block <u_DDRCtrl>.
-WARNING:Xst:2677 - Node <o_cfg_ready> of sequential type is unconnected in block <u_DDRCtrl>.
-WARNING:Xst:2677 - Node <sys_cur_hp> of sequential type is unconnected in block <u_DDRCtrl>.
-WARNING:Xst:2677 - Node <spi_rx_sof_meta_1> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_rx_sof_meta_2> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_byte_sel_4> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_24> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_19> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_30> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_25> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_31> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_26> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_27> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_28> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_29> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_10> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_11> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_12> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_13> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_14> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_9> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_20> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_15> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_21> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_22> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_23> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_24> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_19> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_0> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_30> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_ctrl_10> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_25> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_1> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_ctrl_11> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_31> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_26> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_2> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_27> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_ctrl_12> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_3> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_28> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_ctrl_13> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_10> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_4> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_29> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_ctrl_14> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_11> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_5> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_ctrl_15> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_12> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_6> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_13> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_7> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_8> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_14> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_20> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_9> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_15> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_21> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_16> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_22> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_17> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_23> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_18> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_0> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_1> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_2> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_3> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_4> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_5> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_6> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_7> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_8> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_9> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_10> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_11> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_12> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_13> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_14> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_15> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_16> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_17> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_18> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_19> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_20> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_21> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_22> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_23> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_24> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_25> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_26> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_27> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_28> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_29> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_30> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_cfg_static_31> of sequential type is unconnected in block <u_Syscon>.
-WARNING:Xst:2677 - Node <o_sof> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxbytesel_4> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxbytesel_5> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxbytesel_6> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxbytesel_7> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxbytecnt_0> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxbytecnt_1> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxbytecnt_2> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxbytecnt_3> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxcmd_4> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxcmd_5> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxcmd_6> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <o_rxcmd_7> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <byte_cnt_0> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <byte_cnt_1> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <byte_cnt_2> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <byte_cnt_3> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <byte_7> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <byte_6> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <byte_5> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <byte_4> of sequential type is unconnected in block <u_spi>.
-WARNING:Xst:2677 - Node <matrix_0_8> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_0_9> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_0_10> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_0_11> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_0_12> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_0_13> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_0_14> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_0_15> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_1_8> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_1_9> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_1_10> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_1_11> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_1_12> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_1_13> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_1_14> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_1_15> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_2_8> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_2_9> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_2_10> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_2_11> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_2_12> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_2_13> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_2_14> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_2_15> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_3_8> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_3_9> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_3_10> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_3_11> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_3_12> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_3_13> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_3_14> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_3_15> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_4_8> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_4_9> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_4_10> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_4_11> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_4_12> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_4_13> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_4_14> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_4_15> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_7_8> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_7_9> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_7_10> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_7_11> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_7_12> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_7_13> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_7_14> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_7_15> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_5_8> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_5_9> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_5_10> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_5_11> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_5_12> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_5_13> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_5_14> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_5_15> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_6_8> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_6_9> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_6_10> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_6_11> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_6_12> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_6_13> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_6_14> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <matrix_6_15> of sequential type is unconnected in block <u_Kbd>.
-WARNING:Xst:2677 - Node <dig_sof> of sequential type is unconnected in block <u_VideoTiming>.
-WARNING:Xst:2677 - Node <dig_sol> of sequential type is unconnected in block <u_VideoTiming>.
-WARNING:Xst:2677 - Node <dig_ha> of sequential type is unconnected in block <u_VideoTiming>.
-WARNING:Xst:2677 - Node <dig_va> of sequential type is unconnected in block <u_VideoTiming>.
-WARNING:Xst:2677 - Node <width_16bit_reg> of sequential type is unconnected in block <mmu1>.
-WARNING:Xst:2677 - Node <theOpcode_0> of sequential type is unconnected in block <cpu_6502_peter>.
-WARNING:Xst:2677 - Node <theOpcode_1> of sequential type is unconnected in block <cpu_6502_peter>.
-WARNING:Xst:2677 - Node <theOpcode_2> of sequential type is unconnected in block <cpu_6502_peter>.
-WARNING:Xst:2677 - Node <theOpcode_3> of sequential type is unconnected in block <cpu_6502_peter>.
-WARNING:Xst:2677 - Node <theOpcode_4> of sequential type is unconnected in block <cpu_6502_peter>.
-WARNING:Xst:2677 - Node <ZPU_16BIT_WRITE_ENABLE_reg> of sequential type is unconnected in block <zpu_glue1>.
-WARNING:Xst:2677 - Node <dbg_o.b_inst> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <break_o> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <not_lshr> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <opcode_r_0_7> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <opcode_r_1_7> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <opcode_r_2_7> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <opcode_r_3_7> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_2> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_10> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_0> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_1> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_2> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_3> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_4> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_5> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_6> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_7> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_8> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_9> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_10> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_11> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_12> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_13> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_14> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_15> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_16> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_17> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_18> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_19> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_20> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_21> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_22> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_23> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_24> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_25> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_26> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_27> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_28> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_29> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_30> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_a_31> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_3> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_0> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_1> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_2> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_3> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_4> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_5> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_6> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_7> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_8> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_9> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_10> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_11> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_12> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_13> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_14> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_15> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_16> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_17> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_18> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_19> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_20> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_21> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_22> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_23> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_24> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_25> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_26> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_27> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_28> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_29> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_30> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.stk_b_31> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_11> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_4> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_12> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_5> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_13> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_6> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_14> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_7> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_20> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_15> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_8> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_16> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_21> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_9> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_22> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_17> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_23> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_18> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.sp_19> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_0> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_1> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_2> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_3> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_4> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_5> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_6> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_7> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_8> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_9> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_10> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_11> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_12> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_13> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_14> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_15> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_16> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_17> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_18> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_19> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_20> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_21> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_22> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.pc_23> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.opcode_0> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.opcode_1> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.opcode_2> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.opcode_3> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.opcode_4> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.opcode_5> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.opcode_6> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:2677 - Node <dbg_o.opcode_7> of sequential type is unconnected in block <myzpu>.
-WARNING:Xst:1290 - Hierarchical block <sl_enable_colour_clock_div> is unconnected in block <enables>.
-   It will be removed from the design.
-WARNING:Xst:2677 - Node <value_reg_6> of sequential type is unconnected in block <antic_counter_line_buffer>.
-WARNING:Xst:2677 - Node <value_reg_7> of sequential type is unconnected in block <antic_counter_line_buffer>.
-WARNING:Xst:2677 - Node <twotone_reg> of sequential type is unconnected in block <pokey2>.
-WARNING:Xst:2677 - Node <irq_n_reg> of sequential type is unconnected in block <pokey2>.
-WARNING:Xst:2677 - Node <sio_out_reg> of sequential type is unconnected in block <pokey2>.
-WARNING:Xst:2677 - Node <irqen_reg_3> of sequential type is unconnected in block <pokey2>.
-WARNING:Xst:2677 - Node <skctl_reg_7> of sequential type is unconnected in block <pokey2>.
-WARNING:Xst:2677 - Node <sector_reg_0> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_1> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_2> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_3> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_4> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_5> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_6> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_7> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_8> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_9> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_10> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_11> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_12> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_13> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_14> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_15> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_16> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_17> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_18> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_19> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_20> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_21> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_22> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_23> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_24> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_25> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_26> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_27> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_28> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_29> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_30> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <sector_reg_31> of sequential type is unconnected in block <zpu_config1>.
-WARNING:Xst:2677 - Node <volume_channel_0_reg_0> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <volume_channel_0_reg_1> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <volume_channel_0_reg_2> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <volume_channel_0_reg_3> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc1_reg_0> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc1_reg_1> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc1_reg_2> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc1_reg_3> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc1_reg_4> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc1_reg_5> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc1_reg_6> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc1_reg_7> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <volume_channel_1_reg_0> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <volume_channel_1_reg_1> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <volume_channel_1_reg_2> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <volume_channel_1_reg_3> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <highpass0_reg> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc2_reg_0> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc2_reg_1> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc2_reg_2> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc2_reg_3> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc2_reg_4> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc2_reg_5> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc2_reg_6> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc2_reg_7> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <volume_channel_2_reg_0> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <volume_channel_2_reg_1> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <volume_channel_2_reg_2> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <volume_channel_2_reg_3> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <highpass1_reg> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc3_reg_0> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc3_reg_1> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc3_reg_2> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc3_reg_3> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc3_reg_4> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc3_reg_5> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc3_reg_6> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc3_reg_7> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <volume_channel_3_reg_0> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <volume_channel_3_reg_1> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <volume_channel_3_reg_2> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <volume_channel_3_reg_3> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <irq_n_reg> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audctl_reg_1> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audctl_reg_2> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <irqen_reg_3> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc0_reg_0> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc0_reg_1> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc0_reg_2> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc0_reg_3> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc0_reg_4> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc0_reg_5> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc0_reg_6> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <audc0_reg_7> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <chan1_output_reg> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <chan2_output_reg> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <chan0_output_reg> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:2677 - Node <chan3_output_reg> of sequential type is unconnected in block <uart1>.
-WARNING:Xst:1290 - Hierarchical block <pokey_noise_filter3> is unconnected in block <uart1>.
-   It will be removed from the design.
-WARNING:Xst:1290 - Hierarchical block <pokey_noise_filter2> is unconnected in block <uart1>.
-   It will be removed from the design.
-WARNING:Xst:1290 - Hierarchical block <pokey_noise_filter1> is unconnected in block <uart1>.
-   It will be removed from the design.
-WARNING:Xst:1290 - Hierarchical block <pokey_noise_filter0> is unconnected in block <uart1>.
-   It will be removed from the design.
-WARNING:Xst:1290 - Hierarchical block <poly_5_lfsr> is unconnected in block <uart1>.
-   It will be removed from the design.
-WARNING:Xst:1290 - Hierarchical block <poly_4_lfsr> is unconnected in block <uart1>.
-   It will be removed from the design.
-WARNING:Xst:2677 - Node <result_reg_17> of sequential type is unconnected in block <zpu_glue1>.
-WARNING:Xst:2677 - Node <result_reg_16> of sequential type is unconnected in block <zpu_glue1>.
-WARNING:Xst:2677 - Node <result_reg_15> of sequential type is unconnected in block <zpu_glue1>.
-WARNING:Xst:2677 - Node <result_reg_14> of sequential type is unconnected in block <zpu_glue1>.
-WARNING:Xst:2677 - Node <result_reg_13> of sequential type is unconnected in block <zpu_glue1>.
-WARNING:Xst:1290 - Hierarchical block <sio_in3_synchronizer> is unconnected in block <pokey2>.
-   It will be removed from the design.
-WARNING:Xst:1290 - Hierarchical block <sio_in2_synchronizer> is unconnected in block <pokey2>.
-   It will be removed from the design.
-WARNING:Xst:1290 - Hierarchical block <sio_in1_synchronizer> is unconnected in block <pokey2>.
-   It will be removed from the design.
-WARNING:Xst:2677 - Node <bincnt_reg_0> of sequential type is unconnected in block <pokey_keyboard_scanner1>.
-WARNING:Xst:2677 - Node <bincnt_reg_1> of sequential type is unconnected in block <pokey_keyboard_scanner1>.
-WARNING:Xst:2677 - Node <bincnt_reg_2> of sequential type is unconnected in block <pokey_keyboard_scanner1>.
-WARNING:Xst:2677 - Node <bincnt_reg_3> of sequential type is unconnected in block <pokey_keyboard_scanner1>.
-WARNING:Xst:2677 - Node <bincnt_reg_4> of sequential type is unconnected in block <pokey_keyboard_scanner1>.
-WARNING:Xst:2677 - Node <bincnt_reg_5> of sequential type is unconnected in block <pokey_keyboard_scanner1>.
-
-Mapping all equations...
-Building and optimizing final netlist ...
-INFO:Xst:2260 - The FF/Latch <gen_dq_oe_l_t1[0].fdp_dq_oe1_l> in Unit <u_datapath> is equivalent to the following 15 FFs/Latches : <gen_dq_oe_l_t1[1].fdp_dq_oe1_l> <gen_dq_oe_l_t1[2].fdp_dq_oe1_l> <gen_dq_oe_l_t1[3].fdp_dq_oe1_l> <gen_dq_oe_l_t1[4].fdp_dq_oe1_l> <gen_dq_oe_l_t1[5].fdp_dq_oe1_l> <gen_dq_oe_l_t1[6].fdp_dq_oe1_l> <gen_dq_oe_l_t1[7].fdp_dq_oe1_l> <gen_dq_oe_l_t1[8].fdp_dq_oe1_l> <gen_dq_oe_l_t1[9].fdp_dq_oe1_l> <gen_dq_oe_l_t1[10].fdp_dq_oe1_l> <gen_dq_oe_l_t1[11].fdp_dq_oe1_l> <gen_dq_oe_l_t1[12].fdp_dq_oe1_l> <gen_dq_oe_l_t1[13].fdp_dq_oe1_l> <gen_dq_oe_l_t1[14].fdp_dq_oe1_l> <gen_dq_oe_l_t1[15].fdp_dq_oe1_l> 
-INFO:Xst:2260 - The FF/Latch <gen_dq_oe_l_t1[0].fdp_dq_oe0_l> in Unit <u_datapath> is equivalent to the following 15 FFs/Latches : <gen_dq_oe_l_t1[1].fdp_dq_oe0_l> <gen_dq_oe_l_t1[2].fdp_dq_oe0_l> <gen_dq_oe_l_t1[3].fdp_dq_oe0_l> <gen_dq_oe_l_t1[4].fdp_dq_oe0_l> <gen_dq_oe_l_t1[5].fdp_dq_oe0_l> <gen_dq_oe_l_t1[6].fdp_dq_oe0_l> <gen_dq_oe_l_t1[7].fdp_dq_oe0_l> <gen_dq_oe_l_t1[8].fdp_dq_oe0_l> <gen_dq_oe_l_t1[9].fdp_dq_oe0_l> <gen_dq_oe_l_t1[10].fdp_dq_oe0_l> <gen_dq_oe_l_t1[11].fdp_dq_oe0_l> <gen_dq_oe_l_t1[12].fdp_dq_oe0_l> <gen_dq_oe_l_t1[13].fdp_dq_oe0_l> <gen_dq_oe_l_t1[14].fdp_dq_oe0_l> <gen_dq_oe_l_t1[15].fdp_dq_oe0_l> 
-INFO:Xst:2260 - The FF/Latch <gen_dq_oe_l_t1[0].fdp_dq_oe1_l> in Unit <u_datapath> is equivalent to the following 15 FFs/Latches : <gen_dq_oe_l_t1[1].fdp_dq_oe1_l> <gen_dq_oe_l_t1[2].fdp_dq_oe1_l> <gen_dq_oe_l_t1[3].fdp_dq_oe1_l> <gen_dq_oe_l_t1[4].fdp_dq_oe1_l> <gen_dq_oe_l_t1[5].fdp_dq_oe1_l> <gen_dq_oe_l_t1[6].fdp_dq_oe1_l> <gen_dq_oe_l_t1[7].fdp_dq_oe1_l> <gen_dq_oe_l_t1[8].fdp_dq_oe1_l> <gen_dq_oe_l_t1[9].fdp_dq_oe1_l> <gen_dq_oe_l_t1[10].fdp_dq_oe1_l> <gen_dq_oe_l_t1[11].fdp_dq_oe1_l> <gen_dq_oe_l_t1[12].fdp_dq_oe1_l> <gen_dq_oe_l_t1[13].fdp_dq_oe1_l> <gen_dq_oe_l_t1[14].fdp_dq_oe1_l> <gen_dq_oe_l_t1[15].fdp_dq_oe1_l> 
-INFO:Xst:2260 - The FF/Latch <gen_dq_oe_l_t1[0].fdp_dq_oe0_l> in Unit <u_datapath> is equivalent to the following 15 FFs/Latches : <gen_dq_oe_l_t1[1].fdp_dq_oe0_l> <gen_dq_oe_l_t1[2].fdp_dq_oe0_l> <gen_dq_oe_l_t1[3].fdp_dq_oe0_l> <gen_dq_oe_l_t1[4].fdp_dq_oe0_l> <gen_dq_oe_l_t1[5].fdp_dq_oe0_l> <gen_dq_oe_l_t1[6].fdp_dq_oe0_l> <gen_dq_oe_l_t1[7].fdp_dq_oe0_l> <gen_dq_oe_l_t1[8].fdp_dq_oe0_l> <gen_dq_oe_l_t1[9].fdp_dq_oe0_l> <gen_dq_oe_l_t1[10].fdp_dq_oe0_l> <gen_dq_oe_l_t1[11].fdp_dq_oe0_l> <gen_dq_oe_l_t1[12].fdp_dq_oe0_l> <gen_dq_oe_l_t1[13].fdp_dq_oe0_l> <gen_dq_oe_l_t1[14].fdp_dq_oe0_l> <gen_dq_oe_l_t1[15].fdp_dq_oe0_l> 
-FlipFlop u_Core/vconv/vidin_hcnt_s_0 has been replicated 18 time(s)
-FlipFlop u_Core/vconv/vidin_hcnt_s_1 has been replicated 18 time(s)
-FlipFlop u_Core/vconv/vidin_hcnt_s_2 has been replicated 18 time(s)
-FlipFlop u_Core/vconv/vidin_hcnt_s_3 has been replicated 18 time(s)
-FlipFlop u_FileIO/mem_addr_0 has been replicated 1 time(s)
-FlipFlop u_FileIO/mem_addr_1 has been replicated 1 time(s)
-FlipFlop u_FileIO/mem_addr_2 has been replicated 1 time(s)
-FlipFlop u_FileIO/mem_addr_3 has been replicated 1 time(s)
-
-Final Macro Processing ...
-
-Processing Unit <antic1> :
-	Found 16-bit shift register for signal <nmi_shiftreg_reg_0>.
-	Found 5-bit shift register for signal <delay_display_shift_reg_0>.
-	Found 5-bit shift register for signal <delay_display_shift_reg_1>.
-	Found 5-bit shift register for signal <delay_display_shift_reg_2>.
-	Found 5-bit shift register for signal <delay_display_shift_reg_3>.
-	Found 5-bit shift register for signal <delay_display_shift_reg_4>.
-Unit <antic1> processed.
-
-Processing Unit <chbase_delay> :
-	Found 32-bit shift register for signal <shift_reg_0_0>.
-	Found 32-bit shift register for signal <shift_reg_0_1>.
-	Found 32-bit shift register for signal <shift_reg_0_2>.
-	Found 32-bit shift register for signal <shift_reg_0_3>.
-	Found 32-bit shift register for signal <shift_reg_0_4>.
-	Found 32-bit shift register for signal <shift_reg_0_5>.
-	Found 32-bit shift register for signal <shift_reg_0_6>.
-Unit <chbase_delay> processed.
-
-Processing Unit <delay_line_phase> :
-INFO:Xst:741 - HDL ADVISOR - A 15-bit shift register was found for signal <shift_reg_0> and currently occupies 15 logic cells (7 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
-Unit <delay_line_phase> processed.
-
-Processing Unit <delay_line_phase2> :
-INFO:Xst:741 - HDL ADVISOR - A 8-bit shift register was found for signal <shift_reg_0> and currently occupies 8 logic cells (4 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
-Unit <delay_line_phase2> processed.
-
-Processing Unit <hposm0_delay> :
-	Found 5-bit shift register for signal <shift_reg_0_0>.
-	Found 5-bit shift register for signal <shift_reg_0_1>.
-	Found 5-bit shift register for signal <shift_reg_0_2>.
-	Found 5-bit shift register for signal <shift_reg_0_3>.
-	Found 5-bit shift register for signal <shift_reg_0_4>.
-	Found 5-bit shift register for signal <shift_reg_0_5>.
-	Found 5-bit shift register for signal <shift_reg_0_6>.
-	Found 5-bit shift register for signal <shift_reg_0_7>.
-Unit <hposm0_delay> processed.
-
-Processing Unit <hposm1_delay> :
-	Found 5-bit shift register for signal <shift_reg_0_0>.
-	Found 5-bit shift register for signal <shift_reg_0_1>.
-	Found 5-bit shift register for signal <shift_reg_0_2>.
-	Found 5-bit shift register for signal <shift_reg_0_3>.
-	Found 5-bit shift register for signal <shift_reg_0_4>.
-	Found 5-bit shift register for signal <shift_reg_0_5>.
-	Found 5-bit shift register for signal <shift_reg_0_6>.
-	Found 5-bit shift register for signal <shift_reg_0_7>.
-Unit <hposm1_delay> processed.
-
-Processing Unit <hposm2_delay> :
-	Found 5-bit shift register for signal <shift_reg_0_0>.
-	Found 5-bit shift register for signal <shift_reg_0_1>.
-	Found 5-bit shift register for signal <shift_reg_0_2>.
-	Found 5-bit shift register for signal <shift_reg_0_3>.
-	Found 5-bit shift register for signal <shift_reg_0_4>.
-	Found 5-bit shift register for signal <shift_reg_0_5>.
-	Found 5-bit shift register for signal <shift_reg_0_6>.
-	Found 5-bit shift register for signal <shift_reg_0_7>.
-Unit <hposm2_delay> processed.
-
-Processing Unit <hposm3_delay> :
-	Found 5-bit shift register for signal <shift_reg_0_0>.
-	Found 5-bit shift register for signal <shift_reg_0_1>.
-	Found 5-bit shift register for signal <shift_reg_0_2>.
-	Found 5-bit shift register for signal <shift_reg_0_3>.
-	Found 5-bit shift register for signal <shift_reg_0_4>.
-	Found 5-bit shift register for signal <shift_reg_0_5>.
-	Found 5-bit shift register for signal <shift_reg_0_6>.
-	Found 5-bit shift register for signal <shift_reg_0_7>.
-Unit <hposm3_delay> processed.
-
-Processing Unit <hposp0_delay> :
-	Found 5-bit shift register for signal <shift_reg_0_0>.
-	Found 5-bit shift register for signal <shift_reg_0_1>.
-	Found 5-bit shift register for signal <shift_reg_0_2>.
-	Found 5-bit shift register for signal <shift_reg_0_3>.
-	Found 5-bit shift register for signal <shift_reg_0_4>.
-	Found 5-bit shift register for signal <shift_reg_0_5>.
-	Found 5-bit shift register for signal <shift_reg_0_6>.
-	Found 5-bit shift register for signal <shift_reg_0_7>.
-Unit <hposp0_delay> processed.
-
-Processing Unit <hposp1_delay> :
-	Found 5-bit shift register for signal <shift_reg_0_0>.
-	Found 5-bit shift register for signal <shift_reg_0_1>.
-	Found 5-bit shift register for signal <shift_reg_0_2>.
-	Found 5-bit shift register for signal <shift_reg_0_3>.
-	Found 5-bit shift register for signal <shift_reg_0_4>.
-	Found 5-bit shift register for signal <shift_reg_0_5>.
-	Found 5-bit shift register for signal <shift_reg_0_6>.
-	Found 5-bit shift register for signal <shift_reg_0_7>.
-Unit <hposp1_delay> processed.
-
-Processing Unit <hposp2_delay> :
-	Found 5-bit shift register for signal <shift_reg_0_0>.
-	Found 5-bit shift register for signal <shift_reg_0_1>.
-	Found 5-bit shift register for signal <shift_reg_0_2>.
-	Found 5-bit shift register for signal <shift_reg_0_3>.
-	Found 5-bit shift register for signal <shift_reg_0_4>.
-	Found 5-bit shift register for signal <shift_reg_0_5>.
-	Found 5-bit shift register for signal <shift_reg_0_6>.
-	Found 5-bit shift register for signal <shift_reg_0_7>.
-Unit <hposp2_delay> processed.
-
-Processing Unit <hposp3_delay> :
-	Found 5-bit shift register for signal <shift_reg_0_0>.
-	Found 5-bit shift register for signal <shift_reg_0_1>.
-	Found 5-bit shift register for signal <shift_reg_0_2>.
-	Found 5-bit shift register for signal <shift_reg_0_3>.
-	Found 5-bit shift register for signal <shift_reg_0_4>.
-	Found 5-bit shift register for signal <shift_reg_0_5>.
-	Found 5-bit shift register for signal <shift_reg_0_6>.
-	Found 5-bit shift register for signal <shift_reg_0_7>.
-Unit <hposp3_delay> processed.
-
-Processing Unit <hsync_delay> :
-INFO:Xst:741 - HDL ADVISOR - A 15-bit shift register was found for signal <shift_reg_0> and currently occupies 15 logic cells (7 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
-Unit <hsync_delay> processed.
-
-Processing Unit <nmien_delay> :
-	Found 16-bit shift register for signal <shift_reg_0_0>.
-	Found 16-bit shift register for signal <shift_reg_0_1>.
-Unit <nmien_delay> processed.
-
-Processing Unit <prior_longer_delay> :
-	Found 4-bit shift register for signal <shift_reg_0_0>.
-	Found 4-bit shift register for signal <shift_reg_0_1>.
-Unit <prior_longer_delay> processed.
-
-Processing Unit <sio_in1_synchronizer> :
-	Found 3-bit shift register for signal <ff_reg_0>.
-	Found 3-bit shift register for signal <ff_reg_0>.
-Unit <sio_in1_synchronizer> processed.
-
-Processing Unit <sio_in3_synchronizer> :
-	Found 3-bit shift register for signal <ff_reg_0>.
-Unit <sio_in3_synchronizer> processed.
-
-Processing Unit <sizem_delay> :
-	Found 4-bit shift register for signal <shift_reg_0_0>.
-	Found 4-bit shift register for signal <shift_reg_0_1>.
-	Found 4-bit shift register for signal <shift_reg_0_2>.
-	Found 4-bit shift register for signal <shift_reg_0_3>.
-	Found 4-bit shift register for signal <shift_reg_0_4>.
-	Found 4-bit shift register for signal <shift_reg_0_5>.
-	Found 4-bit shift register for signal <shift_reg_0_6>.
-	Found 4-bit shift register for signal <shift_reg_0_7>.
-Unit <sizem_delay> processed.
-
-Processing Unit <sizep0_delay> :
-	Found 4-bit shift register for signal <shift_reg_0_0>.
-	Found 4-bit shift register for signal <shift_reg_0_1>.
-Unit <sizep0_delay> processed.
-
-Processing Unit <sizep1_delay> :
-	Found 4-bit shift register for signal <shift_reg_0_0>.
-	Found 4-bit shift register for signal <shift_reg_0_1>.
-Unit <sizep1_delay> processed.
-
-Processing Unit <sizep2_delay> :
-	Found 4-bit shift register for signal <shift_reg_0_0>.
-	Found 4-bit shift register for signal <shift_reg_0_1>.
-Unit <sizep2_delay> processed.
-
-Processing Unit <sizep3_delay> :
-	Found 4-bit shift register for signal <shift_reg_0_0>.
-	Found 4-bit shift register for signal <shift_reg_0_1>.
-Unit <sizep3_delay> processed.
-
-Processing Unit <u_DDRCtrl> :
-	Found 2-bit shift register for signal <ena_sys_t3>.
-Unit <u_DDRCtrl> processed.
-
-Processing Unit <u_FileIO> :
-	Found 2-bit shift register for signal <spi_rx_rdy_meta_2>.
-	Found 2-bit shift register for signal <spi_rx_sof_meta_2>.
-Unit <u_FileIO> processed.
-
-Processing Unit <u_I2C> :
-	Found 2-bit shift register for signal <scl_in_2>.
-	Found 2-bit shift register for signal <sda_in_2>.
-Unit <u_I2C> processed.
-
-Processing Unit <u_Kbd> :
-	Found 7-bit shift register for signal <key_state_FSM_FFd4>.
-Unit <u_Kbd> processed.
-
-Processing Unit <u_OSD> :
-	Found 2-bit shift register for signal <pix_active_t_2>.
-Unit <u_OSD> processed.
-
-Processing Unit <u_PSA> :
-	Found 2-bit shift register for signal <data_in_2>.
-	Found 2-bit shift register for signal <clk_in_2>.
-Unit <u_PSA> processed.
-
-Processing Unit <u_PSB> :
-	Found 2-bit shift register for signal <data_in_2>.
-	Found 2-bit shift register for signal <clk_in_2>.
-Unit <u_PSB> processed.
-
-Processing Unit <u_Syscon> :
-	Found 2-bit shift register for signal <spi_rx_rdy_meta_2>.
-Unit <u_Syscon> processed.
-
-Processing Unit <u_Video> :
-	Found 5-bit shift register for signal <o_video_hsync>.
-	Found 5-bit shift register for signal <o_video_vsync>.
-Unit <u_Video> processed.
-
-Processing Unit <u_ddr_ctrl> :
-	Found 4-bit shift register for signal <b0_state_FSM_FFd2>.
-Unit <u_ddr_ctrl> processed.
-
-Processing Unit <u_reset> :
-	Found 2-bit shift register for signal <por_l_meta2>.
-Unit <u_reset> processed.
-
-Processing Unit <vconv> :
-	Found 2-bit shift register for signal <o_vid_sync.dig_vs>.
-	Found 2-bit shift register for signal <o_vid_sync.ana_de>.
-	Found 2-bit shift register for signal <o_vid_sync.ana_hs>.
-	Found 2-bit shift register for signal <o_vid_sync.dig_de>.
-	Found 2-bit shift register for signal <o_vid_sync.dig_hs>.
-	Found 2-bit shift register for signal <o_vid_sync.ana_vs>.
-Unit <vconv> processed.
-
-Processing Unit <vscrol_delay> :
-	Found 16-bit shift register for signal <shift_reg_0_0>.
-	Found 16-bit shift register for signal <shift_reg_0_1>.
-	Found 16-bit shift register for signal <shift_reg_0_2>.
-	Found 16-bit shift register for signal <shift_reg_0_3>.
-Unit <vscrol_delay> processed.
-
-Processing Unit <wsync_delay> :
-INFO:Xst:741 - HDL ADVISOR - A 24-bit shift register was found for signal <shift_reg_0> and currently occupies 24 logic cells (12 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
-Unit <wsync_delay> processed.
-
-=========================================================================
-Final Register Report
-
-Macro Statistics
-# Registers                                            : 5346
- Flip-Flops                                            : 5346
-# Shift Registers                                      : 126
- 16-bit shift register                                 : 7
- 2-bit shift register                                  : 18
- 3-bit shift register                                  : 3
- 32-bit shift register                                 : 7
- 4-bit shift register                                  : 19
- 5-bit shift register                                  : 71
- 7-bit shift register                                  : 1
-
-=========================================================================
-
-=========================================================================
-*                           Partition Report                            *
-=========================================================================
-
-Partition Implementation Status
--------------------------------
-
-  No Partitions were found in this design.
-
--------------------------------
-
-=========================================================================
-*                            Final Report                               *
-=========================================================================
-Final Results
-Top Level Output File Name         : Replay.ngc
-Output Format                      : NGC
-Optimization Goal                  : Area
-Keep Hierarchy                     : yes
-
-Design Statistics
-# IOs                              : 227
-
-Cell Usage :
-# BELS                             : 18452
-#      BUF                         : 57
-#      GND                         : 76
-#      INV                         : 466
-#      LUT1                        : 340
-#      LUT2                        : 1570
-#      LUT3                        : 4230
-#      LUT4                        : 6145
-#      MUXCY                       : 1341
-#      MUXF5                       : 2137
-#      MUXF6                       : 592
-#      MUXF7                       : 278
-#      MUXF8                       : 136
-#      VCC                         : 65
-#      XORCY                       : 1019
-# FlipFlops/Latches                : 5786
-#      FD                          : 394
-#      FD_1                        : 2
-#      FDC                         : 648
-#      FDCE                        : 2175
-#      FDE                         : 1817
-#      FDP                         : 105
-#      FDPE                        : 126
-#      FDR                         : 192
-#      FDR_1                       : 16
-#      FDRE                        : 112
-#      FDRS                        : 32
-#      FDRSE                       : 21
-#      FDS                         : 60
-#      FDSE                        : 14
-#      IDDR2                       : 18
-#      ODDR2                       : 54
-# RAMS                             : 4482
-#      RAM16X1D                    : 3386
-#      RAM32X1S                    : 1060
-#      RAMB16_S1                   : 16
-#      RAMB16_S18_S18              : 1
-#      RAMB16_S2                   : 7
-#      RAMB16_S36                  : 1
-#      RAMB16_S4                   : 8
-#      RAMB16_S9                   : 1
-#      RAMB16_S9_S18               : 1
-#      RAMB16_S9_S9                : 1
-# Shift Registers                  : 141
-#      SRL16                       : 34
-#      SRL16E                      : 100
-#      SRLC16                      : 7
-# Clock Buffers                    : 8
-#      BUFG                        : 8
-# IO Buffers                       : 156
-#      IBUF                        : 33
-#      IBUFG                       : 4
-#      IOBUF                       : 7
-#      OBUF                        : 89
-#      OBUFT                       : 23
-# DCMs                             : 4
-#      DCM_SP                      : 4
-# MULTs                            : 4
-#      MULT18X18SIO                : 4
-# Others                           : 94
-#      PULLUP                      : 94
-=========================================================================
-
-Device utilization summary:
----------------------------
-
-Selected Device : 3s1600efg320-4 
-
- Number of Slices:                     8867  out of  14752    60%  
- Number of Slice Flip Flops:           5766  out of  29504    19%  
- Number of 4 input LUTs:              21784  out of  29504    73%  
-    Number used as logic:             12751
-    Number used as Shift registers:     141
-    Number used as RAMs:               8892
- Number of IOs:                         227
- Number of bonded IOBs:                 135  out of    250    54%  
-    IOB Flip Flops:                      20
- Number of BRAMs:                        36  out of     36   100%  
- Number of MULT18X18SIOs:                 4  out of     36    11%  
- Number of GCLKs:                         8  out of     24    33%  
- Number of DCMs:                          4  out of      8    50%  
-
----------------------------
-Partition Resource Summary:
----------------------------
-
-  No Partitions were found in this design.
-
----------------------------
-
-
-=========================================================================
-TIMING REPORT
-
-NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
-      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
-      GENERATED AFTER PLACE-and-ROUTE.
-
-Clock Information:
-------------------
------------------------------------+-------------------------+-------+
-Clock Signal                       | Clock buffer(FF name)   | Load  |
------------------------------------+-------------------------+-------+
-ClK_A                              | u_a_dcm:CLKDV           | 9393  |
-ClK_B                              | u_b_dcm:CLK0            | 36    |
-ClK_A                              | phase_ctrl.u_a2_dcm:CLK0| 367   |
-ClK_C                              | u_c_dcm:CLK0            | 479   |
-ClK_C                              | u_c_dcm:CLK90           | 4     |
-i_FPGA_SPI_Clk                     | IBUFG+BUFG              | 101   |
-ClK_A                              | u_a_dcm:CLK90           | 104   |
------------------------------------+-------------------------+-------+
-
-Asynchronous Control Signals Information:
-----------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------+
-Control Signal                                                                                                                                               | Buffer(FF name)                                                                | Load  |
--------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------+
-u_Core/atari800core/gtia1/RESET_N_inv(u_Core/atari800core/gtia1/RESET_N_inv631_INV_0:O)                                                                      | NONE(u_Core/atari800core/gtia1/COLOUR_REG_0)                                   | 309   |
-u_Core/atari800core/pokey1/RESET_N_inv(u_Core/atari800core/pokey1/RESET_N_inv531_INV_0:O)                                                                    | NONE(u_Core/atari800core/pokey1/audc0_reg_0)                                   | 244   |
-u_Core/atari800core/pokey2/RESET_N_inv(u_Core/atari800core/pokey2/RESET_N_inv531_INV_0:O)                                                                    | NONE(u_Core/atari800core/pokey2/audc0_reg_0)                                   | 239   |
-u_ClockGen/rst_ctl(u_ClockGen/rst_ctl:Q)                                                                                                                     | NONE(init_diskinsert_s)                                                        | 231   |
-u_Core/atari800core/antic1/RESET_N_inv(u_Core/atari800core/antic1/RESET_N_inv491_INV_0:O)                                                                    | NONE(u_Core/atari800core/antic1/RESET_N_inv_shift1)                            | 187   |
-u_Core/atari800core/zpu_config1/uart1/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/RESET_N_inv531_INV_0:O)                                              | NONE(u_Core/atari800core/zpu_config1/uart1/audctl_reg_0)                       | 186   |
-u_ClockGen/rst_ram(u_ClockGen/rst_ram:Q)                                                                                                                     | NONE(u_DDRCtrl/cur_lp)                                                         | 174   |
-u_ClockGen/rst_video(u_ClockGen/rst_video:Q)                                                                                                                 | NONE(u_Core/vconv/u_VideoTiming/act_h_cnt_0)                                   | 159   |
-u_Core/atari800core/zpu_config1/reset_zpu_reg(u_Core/atari800core/zpu_config1/reset_zpu_reg:Q)                                                               | NONE(u_Core/atari800core/zpu_glue1/ZPU_32BIT_WRITE_ENABLE_reg)                 | 106   |
-u_Core/u_Kbd/key_state_or0000(u_Core/u_Kbd/key_state_or00001:O)                                                                                              | NONE(u_Core/u_Kbd/key_break)                                                   | 95    |
-u_Core/atari800core/pia1/RESET_N_inv(u_Core/atari800core/pia1/RESET_N_inv1_INV_0:O)                                                                          | NONE(u_Core/atari800core/pia1/CA1_reg)                                         | 73    |
-u_Core/atari800core/mmu1/reset_n_inv(u_Core/atari800core/mmu1/reset_n_inv1_INV_0:O)                                                                          | NONE(u_Core/atari800core/mmu1/ADDR_reg_0)                                      | 63    |
-u_ClockGen/rst_ctl_hard(u_ClockGen/rst_ctl_hard:Q)                                                                                                           | NONE(u_Syscon/char_addr_0)                                                     | 45    |
-u_Core/atari800core/antic1/chbase_delay/RESET_N_inv(u_Core/atari800core/antic1/chbase_delay/RESET_N_inv321_INV_0:O)                                          | NONE(u_Core/atari800core/antic1/chbase_delay/RESET_N_inv_shift1)               | 38    |
-u_ClockGen/rst_aux(u_ClockGen/rst_aux:Q)                                                                                                                     | NONE(u_Audio/cnt_0)                                                            | 35    |
-u_Core/atari800core/pokey1/pokey_keyboard_scanner1/reset_n_inv(u_Core/atari800core/pokey1/pokey_keyboard_scanner1/reset_n_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey1/pokey_keyboard_scanner1/bincnt_reg_0)          | 25    |
-u_Core/atari800core/pokey2/pokey_keyboard_scanner1/reset_n_inv(u_Core/atari800core/pokey2/pokey_keyboard_scanner1/reset_n_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey2/pokey_keyboard_scanner1/bincnt_reg_0)          | 25    |
-u_Core/atari800core/antic1/wsync_delay/RESET_N_inv(u_Core/atari800core/antic1/wsync_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/antic1/wsync_delay/shift_reg_0)                       | 24    |
-u_Core/atari800core/antic1/vscrol_delay/RESET_N_inv(u_Core/atari800core/antic1/vscrol_delay/RESET_N_inv1_INV_0:O)                                            | NONE(u_Core/atari800core/antic1/vscrol_delay/RESET_N_inv_shift1)               | 19    |
-u_Core/atari800core/antic1/nmien_delay/RESET_N_inv(u_Core/atari800core/antic1/nmien_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/antic1/nmien_delay/RESET_N_inv_shift1)                | 17    |
-u_Core/atari800core/pokey1/poly_17_19_lfsr/shift_reg_Acst_inv(u_Core/atari800core/pokey1/poly_17_19_lfsr/shift_reg_Acst_inv1_INV_0:O)                        | NONE(u_Core/atari800core/pokey1/poly_17_19_lfsr/shift_reg_0)                   | 17    |
-u_Core/atari800core/pokey2/poly_17_19_lfsr/shift_reg_Acst_inv(u_Core/atari800core/pokey2/poly_17_19_lfsr/shift_reg_Acst_inv1_INV_0:O)                        | NONE(u_Core/atari800core/pokey2/poly_17_19_lfsr/shift_reg_0)                   | 17    |
-u_Core/atari800core/zpu_config1/uart1/poly_17_19_lfsr/shift_reg_Acst_inv(u_Core/atari800core/zpu_config1/uart1/poly_17_19_lfsr/shift_reg_Acst_inv1_INV_0:O)  | NONE(u_Core/atari800core/zpu_config1/uart1/poly_17_19_lfsr/shift_reg_0)        | 17    |
-u_Core/atari800core/antic1/antic_counter_display_list/RESET_n_inv(u_Core/atari800core/antic1/antic_counter_display_list/RESET_n_inv1_INV_0:O)                | NONE(u_Core/atari800core/antic1/antic_counter_display_list/value_reg_0)        | 16    |
-u_Core/atari800core/antic1/antic_counter_memory_scan/RESET_n_inv(u_Core/atari800core/antic1/antic_counter_memory_scan/RESET_n_inv1_INV_0:O)                  | NONE(u_Core/atari800core/antic1/antic_counter_memory_scan/value_reg_0)         | 16    |
-u_Core/atari800core/enables/delay_line_phase/RESET_N_inv(u_Core/atari800core/enables/delay_line_phase/RESET_N_inv1_INV_0:O)                                  | NONE(u_Core/atari800core/enables/delay_line_phase/shift_reg_0)                 | 15    |
-u_Core/atari800core/gtia1/hsync_delay/RESET_N_inv(u_Core/atari800core/gtia1/hsync_delay/RESET_N_inv1_INV_0:O)                                                | NONE(u_Core/atari800core/gtia1/hsync_delay/shift_reg_0)                        | 15    |
-u_ClockGen/u_reset/o_rst(u_ClockGen/u_reset/o_rst:Q)                                                                                                         | NONE(u_ClockGen/ps_en)                                                         | 14    |
-u_Core/atari800core/gtia1/colbk_delay/RESET_N_inv(u_Core/atari800core/gtia1/colbk_delay/RESET_N_inv1_INV_0:O)                                                | NONE(u_Core/atari800core/gtia1/colbk_delay/shift_reg_0_0)                      | 14    |
-u_Core/atari800core/gtia1/colpf0_delay/RESET_N_inv(u_Core/atari800core/gtia1/colpf0_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/colpf0_delay/shift_reg_0_0)                     | 14    |
-u_Core/atari800core/gtia1/colpf1_delay/RESET_N_inv(u_Core/atari800core/gtia1/colpf1_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/colpf1_delay/shift_reg_0_0)                     | 14    |
-u_Core/atari800core/gtia1/colpf2_delay/RESET_N_inv(u_Core/atari800core/gtia1/colpf2_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/colpf2_delay/shift_reg_0_0)                     | 14    |
-u_Core/atari800core/gtia1/colpf3_delay/RESET_N_inv(u_Core/atari800core/gtia1/colpf3_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/colpf3_delay/shift_reg_0_0)                     | 14    |
-u_Core/atari800core/gtia1/colpm0_delay/RESET_N_inv(u_Core/atari800core/gtia1/colpm0_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/colpm0_delay/shift_reg_0_0)                     | 14    |
-u_Core/atari800core/gtia1/colpm1_delay/RESET_N_inv(u_Core/atari800core/gtia1/colpm1_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/colpm1_delay/shift_reg_0_0)                     | 14    |
-u_Core/atari800core/gtia1/colpm2_delay/RESET_N_inv(u_Core/atari800core/gtia1/colpm2_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/colpm2_delay/shift_reg_0_0)                     | 14    |
-u_Core/atari800core/gtia1/colpm3_delay/RESET_N_inv(u_Core/atari800core/gtia1/colpm3_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/colpm3_delay/shift_reg_0_0)                     | 14    |
-u_Core/atari800core/gtia1/hposm0_delay/RESET_N_inv(u_Core/atari800core/gtia1/hposm0_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/hposm0_delay/RESET_N_inv_shift1)                | 12    |
-u_Core/atari800core/gtia1/hposm1_delay/RESET_N_inv(u_Core/atari800core/gtia1/hposm1_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/hposm1_delay/RESET_N_inv_shift1)                | 12    |
-u_Core/atari800core/gtia1/hposm2_delay/RESET_N_inv(u_Core/atari800core/gtia1/hposm2_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/hposm2_delay/RESET_N_inv_shift1)                | 12    |
-u_Core/atari800core/gtia1/hposm3_delay/RESET_N_inv(u_Core/atari800core/gtia1/hposm3_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/hposm3_delay/RESET_N_inv_shift1)                | 12    |
-u_Core/atari800core/gtia1/hposp0_delay/RESET_N_inv(u_Core/atari800core/gtia1/hposp0_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/hposp0_delay/RESET_N_inv_shift1)                | 12    |
-u_Core/atari800core/gtia1/hposp1_delay/RESET_N_inv(u_Core/atari800core/gtia1/hposp1_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/hposp1_delay/RESET_N_inv_shift1)                | 12    |
-u_Core/atari800core/gtia1/hposp2_delay/RESET_N_inv(u_Core/atari800core/gtia1/hposp2_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/hposp2_delay/RESET_N_inv_shift1)                | 12    |
-u_Core/atari800core/gtia1/hposp3_delay/RESET_N_inv(u_Core/atari800core/gtia1/hposp3_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/hposp3_delay/RESET_N_inv_shift1)                | 12    |
-u_Core/atari800core/gtia1/prior_short_delay/RESET_N_inv(u_Core/atari800core/gtia1/prior_short_delay/RESET_N_inv1_INV_0:O)                                    | NONE(u_Core/atari800core/gtia1/prior_short_delay/shift_reg_0_0)                | 12    |
-u_Core/atari800core/gtia1/sizem_delay/RESET_N_inv(u_Core/atari800core/gtia1/sizem_delay/RESET_N_inv1_INV_0:O)                                                | NONE(u_Core/atari800core/gtia1/sizem_delay/RESET_N_inv_shift1)                 | 11    |
-u_Core/atari800core/gtia1/player0/RESET_N_inv(u_Core/atari800core/gtia1/player0/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/gtia1/player0/count_reg_FSM_FFd1)                     | 10    |
-u_Core/atari800core/gtia1/player1/RESET_N_inv(u_Core/atari800core/gtia1/player1/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/gtia1/player1/count_reg_FSM_FFd1)                     | 10    |
-u_Core/atari800core/gtia1/player2/RESET_N_inv(u_Core/atari800core/gtia1/player2/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/gtia1/player2/count_reg_FSM_FFd1)                     | 10    |
-u_Core/atari800core/gtia1/player3/RESET_N_inv(u_Core/atari800core/gtia1/player3/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/gtia1/player3/count_reg_FSM_FFd1)                     | 10    |
-u_Core/atari800core/enables/RESET_N_inv(u_Core/atari800core/enables/RESET_N_inv1_INV_0:O)                                                                    | NONE(u_Core/atari800core/enables/cpu_extra_enable_reg)                         | 9     |
-i_FPGA_Ctrl0                                                                                                                                                 | IBUF                                                                           | 8     |
-u_Core/atari800core/antic1/antic_dma_clock1/RESET_n_inv(u_Core/atari800core/antic1/antic_dma_clock1/RESET_n_inv1_INV_0:O)                                    | NONE(u_Core/atari800core/antic1/antic_dma_clock1/dma_shiftreg_reg_0)           | 8     |
-u_Core/atari800core/enables/delay_line_phase2/RESET_N_inv(u_Core/atari800core/enables/delay_line_phase2/RESET_N_inv1_INV_0:O)                                | NONE(u_Core/atari800core/enables/delay_line_phase2/shift_reg_0)                | 8     |
-u_Core/atari800core/gtia1/counter_hpos/RESET_n_inv(u_Core/atari800core/gtia1/counter_hpos/RESET_n_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/counter_hpos/value_reg_0)                       | 8     |
-u_Core/atari800core/pokey1/enable_15_div/RESET_N_inv(u_Core/atari800core/pokey1/enable_15_div/RESET_N_inv1_INV_0:O)                                          | NONE(u_Core/atari800core/pokey1/enable_15_div/count_reg_0)                     | 8     |
-u_Core/atari800core/pokey1/timer0/RESET_N_inv(u_Core/atari800core/pokey1/timer0/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/pokey1/timer0/count_reg_0)                            | 8     |
-u_Core/atari800core/pokey1/timer1/RESET_N_inv(u_Core/atari800core/pokey1/timer1/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/pokey1/timer1/count_reg_0)                            | 8     |
-u_Core/atari800core/pokey1/timer2/RESET_N_inv(u_Core/atari800core/pokey1/timer2/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/pokey1/timer2/count_reg_0)                            | 8     |
-u_Core/atari800core/pokey1/timer3/RESET_N_inv(u_Core/atari800core/pokey1/timer3/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/pokey1/timer3/count_reg_0)                            | 8     |
-u_Core/atari800core/pokey2/enable_15_div/RESET_N_inv(u_Core/atari800core/pokey2/enable_15_div/RESET_N_inv1_INV_0:O)                                          | NONE(u_Core/atari800core/pokey2/enable_15_div/count_reg_0)                     | 8     |
-u_Core/atari800core/pokey2/timer0/RESET_N_inv(u_Core/atari800core/pokey2/timer0/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/pokey2/timer0/count_reg_0)                            | 8     |
-u_Core/atari800core/pokey2/timer1/RESET_N_inv(u_Core/atari800core/pokey2/timer1/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/pokey2/timer1/count_reg_0)                            | 8     |
-u_Core/atari800core/pokey2/timer2/RESET_N_inv(u_Core/atari800core/pokey2/timer2/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/pokey2/timer2/count_reg_0)                            | 8     |
-u_Core/atari800core/pokey2/timer3/RESET_N_inv(u_Core/atari800core/pokey2/timer3/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/pokey2/timer3/count_reg_0)                            | 8     |
-u_Core/atari800core/zpu_config1/uart1/enable_15_div/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/enable_15_div/RESET_N_inv1_INV_0:O)                    | NONE(u_Core/atari800core/zpu_config1/uart1/enable_15_div/count_reg_0)          | 8     |
-u_Core/atari800core/zpu_config1/uart1/timer0/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/timer0/RESET_N_inv1_INV_0:O)                                  | NONE(u_Core/atari800core/zpu_config1/uart1/timer0/count_reg_0)                 | 8     |
-u_Core/atari800core/zpu_config1/uart1/timer1/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/timer1/RESET_N_inv1_INV_0:O)                                  | NONE(u_Core/atari800core/zpu_config1/uart1/timer1/count_reg_0)                 | 8     |
-u_Core/atari800core/zpu_config1/uart1/timer2/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/timer2/RESET_N_inv1_INV_0:O)                                  | NONE(u_Core/atari800core/zpu_config1/uart1/timer2/count_reg_0)                 | 8     |
-u_Core/atari800core/zpu_config1/uart1/timer3/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/timer3/RESET_N_inv1_INV_0:O)                                  | NONE(u_Core/atari800core/zpu_config1/uart1/timer3/count_reg_0)                 | 8     |
-i_FPGA_Ctrl1                                                                                                                                                 | IBUF                                                                           | 7     |
-u_ClockGen/u_reset/o_rst_soft_or0000(u_ClockGen/u_reset/o_rst_soft_or00001:O)                                                                                | NONE(u_ClockGen/u_reset/o_rst_soft)                                            | 6     |
-u_ClockGen/u_reset/por_l_meta2_inv(u_ClockGen/u_reset/por_l_meta2_inv1_INV_0:O)                                                                              | NONE(u_ClockGen/u_reset/o_rst)                                                 | 6     |
-u_Core/atari800core/antic1/antic_counter_line_buffer/RESET_n_inv(u_Core/atari800core/antic1/antic_counter_line_buffer/RESET_n_inv1_INV_0:O)                  | NONE(u_Core/atari800core/antic1/antic_counter_line_buffer/value_reg_0)         | 6     |
-u_Core/atari800core/gtia1/prior_long_delay/RESET_N_inv(u_Core/atari800core/gtia1/prior_long_delay/RESET_N_inv1_INV_0:O)                                      | NONE(u_Core/atari800core/gtia1/prior_long_delay/shift_reg_0_0)                 | 6     |
-u_Core/atari800core/pokey1/enable_64_div/RESET_N_inv(u_Core/atari800core/pokey1/enable_64_div/RESET_N_inv1_INV_0:O)                                          | NONE(u_Core/atari800core/pokey1/enable_64_div/count_reg_0)                     | 6     |
-u_Core/atari800core/pokey2/enable_64_div/RESET_N_inv(u_Core/atari800core/pokey2/enable_64_div/RESET_N_inv1_INV_0:O)                                          | NONE(u_Core/atari800core/pokey2/enable_64_div/count_reg_0)                     | 6     |
-u_Core/atari800core/zpu_config1/uart1/enable_64_div/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/enable_64_div/RESET_N_inv1_INV_0:O)                    | NONE(u_Core/atari800core/zpu_config1/uart1/enable_64_div/count_reg_0)          | 6     |
-u_Core/atari800core/enables/enable_179_clock_div/RESET_N_inv(u_Core/atari800core/enables/enable_179_clock_div/RESET_N_inv1_INV_0:O)                          | NONE(u_Core/atari800core/enables/enable_179_clock_div/count_reg_0)             | 5     |
-u_Core/atari800core/gtia1/prior_longer_delay/RESET_N_inv(u_Core/atari800core/gtia1/prior_longer_delay/RESET_N_inv1_INV_0:O)                                  | NONE(u_Core/atari800core/gtia1/prior_longer_delay/RESET_N_inv_shift1)          | 5     |
-u_Core/atari800core/gtia1/sizep0_delay/RESET_N_inv(u_Core/atari800core/gtia1/sizep0_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/sizep0_delay/RESET_N_inv_shift1)                | 5     |
-u_Core/atari800core/gtia1/sizep1_delay/RESET_N_inv(u_Core/atari800core/gtia1/sizep1_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/sizep1_delay/RESET_N_inv_shift1)                | 5     |
-u_Core/atari800core/gtia1/sizep2_delay/RESET_N_inv(u_Core/atari800core/gtia1/sizep2_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/sizep2_delay/RESET_N_inv_shift1)                | 5     |
-u_Core/atari800core/gtia1/sizep3_delay/RESET_N_inv(u_Core/atari800core/gtia1/sizep3_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/sizep3_delay/RESET_N_inv_shift1)                | 5     |
-u_Core/atari800core/pokey1/poly_5_lfsr/shift_reg_Acst_inv(u_Core/atari800core/pokey1/poly_5_lfsr/shift_reg_Acst_inv1_INV_0:O)                                | NONE(u_Core/atari800core/pokey1/poly_5_lfsr/shift_reg_0)                       | 5     |
-u_Core/atari800core/pokey2/poly_5_lfsr/shift_reg_Acst_inv(u_Core/atari800core/pokey2/poly_5_lfsr/shift_reg_Acst_inv1_INV_0:O)                                | NONE(u_Core/atari800core/pokey2/poly_5_lfsr/shift_reg_0)                       | 5     |
-u_Core/atari800core/antic1/antic_counter_refresh_count/RESET_n_inv(u_Core/atari800core/antic1/antic_counter_refresh_count/RESET_n_inv1_INV_0:O)              | NONE(u_Core/atari800core/antic1/antic_counter_refresh_count/value_reg_0)       | 4     |
-u_Core/atari800core/antic1/antic_counter_row_count/RESET_n_inv(u_Core/atari800core/antic1/antic_counter_row_count/RESET_n_inv1_INV_0:O)                      | NONE(u_Core/atari800core/antic1/antic_counter_row_count/value_reg_0)           | 4     |
-u_Core/atari800core/gtia1/missile0/RESET_N_inv(u_Core/atari800core/gtia1/missile0/RESET_N_inv1_INV_0:O)                                                      | NONE(u_Core/atari800core/gtia1/missile0/count_reg_FSM_FFd1)                    | 4     |
-u_Core/atari800core/gtia1/missile1/RESET_N_inv(u_Core/atari800core/gtia1/missile1/RESET_N_inv1_INV_0:O)                                                      | NONE(u_Core/atari800core/gtia1/missile1/count_reg_FSM_FFd1)                    | 4     |
-u_Core/atari800core/gtia1/missile2/RESET_N_inv(u_Core/atari800core/gtia1/missile2/RESET_N_inv1_INV_0:O)                                                      | NONE(u_Core/atari800core/gtia1/missile2/count_reg_FSM_FFd1)                    | 4     |
-u_Core/atari800core/gtia1/missile3/RESET_N_inv(u_Core/atari800core/gtia1/missile3/RESET_N_inv1_INV_0:O)                                                      | NONE(u_Core/atari800core/gtia1/missile3/count_reg_FSM_FFd1)                    | 4     |
-u_Core/atari800core/pokey1/poly_4_lfsr/shift_reg_Acst_inv(u_Core/atari800core/pokey1/poly_4_lfsr/shift_reg_Acst_inv1_INV_0:O)                                | NONE(u_Core/atari800core/pokey1/poly_4_lfsr/shift_reg_0)                       | 4     |
-u_Core/atari800core/pokey2/poly_4_lfsr/shift_reg_Acst_inv(u_Core/atari800core/pokey2/poly_4_lfsr/shift_reg_Acst_inv1_INV_0:O)                                | NONE(u_Core/atari800core/pokey2/poly_4_lfsr/shift_reg_0)                       | 4     |
-u_ClockGen/u_reset/o_rst_soft(u_ClockGen/u_reset/o_rst_soft:Q)                                                                                               | NONE(u_ClockGen/rst_aux)                                                       | 3     |
-u_Core/atari800core/pokey1/stimer_delay/RESET_N_inv(u_Core/atari800core/pokey1/stimer_delay/RESET_N_inv1_INV_0:O)                                            | NONE(u_Core/atari800core/pokey1/stimer_delay/shift_reg_0)                      | 3     |
-u_Core/atari800core/pokey1/timer0/underflow0_delay/RESET_N_inv(u_Core/atari800core/pokey1/timer0/underflow0_delay/RESET_N_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey1/timer0/underflow0_delay/shift_reg_0)           | 3     |
-u_Core/atari800core/pokey1/timer1/underflow0_delay/RESET_N_inv(u_Core/atari800core/pokey1/timer1/underflow0_delay/RESET_N_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey1/timer1/underflow0_delay/shift_reg_0)           | 3     |
-u_Core/atari800core/pokey1/timer2/underflow0_delay/RESET_N_inv(u_Core/atari800core/pokey1/timer2/underflow0_delay/RESET_N_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey1/timer2/underflow0_delay/shift_reg_0)           | 3     |
-u_Core/atari800core/pokey1/timer3/underflow0_delay/RESET_N_inv(u_Core/atari800core/pokey1/timer3/underflow0_delay/RESET_N_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey1/timer3/underflow0_delay/shift_reg_0)           | 3     |
-u_Core/atari800core/pokey2/stimer_delay/RESET_N_inv(u_Core/atari800core/pokey2/stimer_delay/RESET_N_inv1_INV_0:O)                                            | NONE(u_Core/atari800core/pokey2/stimer_delay/shift_reg_0)                      | 3     |
-u_Core/atari800core/pokey2/timer0/underflow0_delay/RESET_N_inv(u_Core/atari800core/pokey2/timer0/underflow0_delay/RESET_N_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey2/timer0/underflow0_delay/shift_reg_0)           | 3     |
-u_Core/atari800core/pokey2/timer1/underflow0_delay/RESET_N_inv(u_Core/atari800core/pokey2/timer1/underflow0_delay/RESET_N_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey2/timer1/underflow0_delay/shift_reg_0)           | 3     |
-u_Core/atari800core/pokey2/timer2/underflow0_delay/RESET_N_inv(u_Core/atari800core/pokey2/timer2/underflow0_delay/RESET_N_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey2/timer2/underflow0_delay/shift_reg_0)           | 3     |
-u_Core/atari800core/pokey2/timer3/underflow0_delay/RESET_N_inv(u_Core/atari800core/pokey2/timer3/underflow0_delay/RESET_N_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey2/timer3/underflow0_delay/shift_reg_0)           | 3     |
-u_Core/atari800core/zpu_config1/uart1/stimer_delay/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/stimer_delay/RESET_N_inv1_INV_0:O)                      | NONE(u_Core/atari800core/zpu_config1/uart1/stimer_delay/shift_reg_0)           | 3     |
-u_Core/atari800core/zpu_config1/uart1/timer0/underflow0_delay/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/timer0/underflow0_delay/RESET_N_inv1_INV_0:O)| NONE(u_Core/atari800core/zpu_config1/uart1/timer0/underflow0_delay/shift_reg_0)| 3     |
-u_Core/atari800core/zpu_config1/uart1/timer1/underflow0_delay/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/timer1/underflow0_delay/RESET_N_inv1_INV_0:O)| NONE(u_Core/atari800core/zpu_config1/uart1/timer1/underflow0_delay/shift_reg_0)| 3     |
-u_Core/atari800core/zpu_config1/uart1/timer2/underflow0_delay/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/timer2/underflow0_delay/RESET_N_inv1_INV_0:O)| NONE(u_Core/atari800core/zpu_config1/uart1/timer2/underflow0_delay/shift_reg_0)| 3     |
-u_Core/atari800core/zpu_config1/uart1/timer3/underflow0_delay/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/timer3/underflow0_delay/RESET_N_inv1_INV_0:O)| NONE(u_Core/atari800core/zpu_config1/uart1/timer3/underflow0_delay/shift_reg_0)| 3     |
-u_ClockGen/rst_video_hard(u_ClockGen/rst_video_hard:Q)                                                                                                       | NONE(u_Video/o_video_rst_l)                                                    | 2     |
-u_Core/atari800core/internalromram1/reset_n_inv(u_Core/atari800core/internalromram1/reset_n_inv1_INV_0:O)                                                    | NONE(u_Core/atari800core/internalromram1/ram_request_reg)                      | 2     |
-u_Core/atari800core/pokey1/serout_clock_delay/RESET_N_inv(u_Core/atari800core/pokey1/serout_clock_delay/RESET_N_inv1_INV_0:O)                                | NONE(u_Core/atari800core/pokey1/serout_clock_delay/shift_reg_0)                | 2     |
-u_Core/atari800core/pokey2/serout_clock_delay/RESET_N_inv(u_Core/atari800core/pokey2/serout_clock_delay/RESET_N_inv1_INV_0:O)                                | NONE(u_Core/atari800core/pokey2/serout_clock_delay/shift_reg_0)                | 2     |
-u_Core/atari800core/zpu_config1/reset_6502_cpu_reg(u_Core/atari800core/zpu_config1/reset_6502_cpu_reg:Q)                                                     | NONE(u_Core/atari800core/cpu6502/nmi_n_reg)                                    | 2     |
-u_Core/atari800core/zpu_config1/uart1/serout_clock_delay/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/serout_clock_delay/RESET_N_inv1_INV_0:O)          | NONE(u_Core/atari800core/zpu_config1/uart1/serout_clock_delay/shift_reg_0)     | 2     |
-u_DDRCtrl/u_ddr_ctrl/o_taken(u_DDRCtrl/u_ddr_ctrl/u_ack_reg:Q)                                                                                               | NONE(u_DDRCtrl/sys_taken_meta1)                                                | 1     |
-u_DDRCtrl/u_ddr_ctrl/u_datapath/dq_st(u_DDRCtrl/u_ddr_ctrl/u_datapath/fd_dq_st:Q)                                                                            | NONE(u_DDRCtrl/u_ddr_ctrl/u_datapath/dq_st_hold)                               | 1     |
-u_FileIO/spi_rx_rdy_meta_2(u_FileIO/spi_rx_rdy_meta_2:Q)                                                                                                     | NONE(u_FileIO/u_spi/o_rdy)                                                     | 1     |
-u_FileIO/spi_rx_sof_meta_2(u_FileIO/spi_rx_sof_meta_2:Q)                                                                                                     | NONE(u_FileIO/u_spi/o_sof)                                                     | 1     |
-u_Syscon/spi_ctrl.reset(u_Syscon/spi_ctrl.reset:Q)                                                                                                           | NONE(u_ClockGen/u_reset/rst_soft)                                              | 1     |
-u_Syscon/spi_rx_rdy_meta_2(u_Syscon/spi_rx_rdy_meta_2:Q)                                                                                                     | NONE(u_Syscon/u_spi/o_rdy)                                                     | 1     |
--------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------+
-
-Timing Summary:
----------------
-Speed Grade: -4
-
-   Minimum period: 11.410ns (Maximum Frequency: 87.640MHz)
-   Minimum input arrival time before clock: 3.673ns
-   Maximum output required time after clock: 11.067ns
-   Maximum combinational path delay: 6.671ns
-
-Timing Detail:
---------------
-All values displayed in nanoseconds (ns)
-
-=========================================================================
-Timing constraint: Default period analysis for Clock 'ClK_A'
-  Clock period: 11.410ns (frequency: 87.640MHz)
-  Total number of paths / destination ports: 16152102 / 51567
--------------------------------------------------------------------------
-Delay:               2.853ns (Levels of Logic = 2)
-  Source:            u_ClockGen/rst_ram (FF)
-  Destination:       u_DDRCtrl/u_ddr_ctrl/u_datapath/gen_dm[0].oddr_dm (FF)
-  Source Clock:      ClK_A rising
-  Destination Clock: ClK_A rising +90
-
-  Data Path: u_ClockGen/rst_ram to u_DDRCtrl/u_ddr_ctrl/u_datapath/gen_dm[0].oddr_dm
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDPE:C->Q           182   0.591   1.310  rst_ram (rst_ram)
-     end scope: 'u_ClockGen'
-     begin scope: 'u_DDRCtrl'
-     begin scope: 'u_ddr_ctrl'
-     begin scope: 'u_datapath'
-     ODDR2:S                   0.952          gen_dm[0].oddr_dm
-    ----------------------------------------
-    Total                      2.853ns (1.543ns logic, 1.310ns route)
-                                       (54.1% logic, 45.9% route)
-
-=========================================================================
-Timing constraint: Default period analysis for Clock 'ClK_B'
-  Clock period: 5.012ns (frequency: 199.534MHz)
-  Total number of paths / destination ports: 364 / 58
--------------------------------------------------------------------------
-Delay:               5.012ns (Levels of Logic = 4)
-  Source:            u_Audio/cnt_3 (FF)
-  Destination:       u_Audio/shifter_2 (FF)
-  Source Clock:      ClK_B rising
-  Destination Clock: ClK_B rising
-
-  Data Path: u_Audio/cnt_3 to u_Audio/shifter_2
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDC:C->Q              2   0.591   0.622  cnt_3 (cnt_3)
-     LUT4:I0->O            1   0.704   0.000  o_sample_taken_cmp_eq00001 (o_sample_taken_cmp_eq00001)
-     MUXF5:I0->O          43   0.321   1.441  o_sample_taken_cmp_eq0000_f5 (o_sample_taken_cmp_eq0000)
-     LUT4:I0->O            1   0.704   0.000  shifter_mux0002<9>2 (shifter_mux0002<9>2)
-     MUXF5:I0->O           1   0.321   0.000  shifter_mux0002<9>_f5 (shifter_mux0002<9>)
-     FDCE:D                    0.308          shifter_9
-    ----------------------------------------
-    Total                      5.012ns (2.949ns logic, 2.063ns route)
-                                       (58.8% logic, 41.2% route)
-
-=========================================================================
-Timing constraint: Default period analysis for Clock 'ClK_C'
-  Clock period: 10.700ns (frequency: 93.458MHz)
-  Total number of paths / destination ports: 40688 / 677
--------------------------------------------------------------------------
-Delay:               10.700ns (Levels of Logic = 8)
-  Source:            u_Core/vconv/u_VideoTiming/v_cnt_9 (FF)
-  Destination:       u_Core/vconv/u_VideoTiming/cs_gate_2 (FF)
-  Source Clock:      ClK_C rising
-  Destination Clock: ClK_C rising
-
-  Data Path: u_Core/vconv/u_VideoTiming/v_cnt_9 to u_Core/vconv/u_VideoTiming/cs_gate_2
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDCE:C->Q            25   0.591   1.435  v_cnt_9 (v_cnt_9)
-     LUT3:I0->O            2   0.704   0.526  cs_gate_or0000311 (N57)
-     LUT3:I1->O            1   0.704   0.424  cs_gate_or00002_SW0 (N72)
-     LUT4:I3->O            4   0.704   0.666  cs_gate_or00002 (N8)
-     LUT4:I1->O            1   0.704   0.000  cs_gate_or00004112 (cs_gate_or00004111)
-     MUXF5:I0->O           2   0.321   0.622  cs_gate_or0000411_f5 (cs_gate_or000041)
-     LUT4:I0->O            1   0.704   0.424  cs_gate_mux0036<2>12_SW0 (N161)
-     LUT4:I3->O            1   0.704   0.455  cs_gate_mux0036<2>12 (cs_gate_mux0036<2>12)
-     LUT3:I2->O            1   0.704   0.000  cs_gate_mux0036<2>35 (cs_gate_mux0036<2>)
-     FDCE:D                    0.308          cs_gate_2
-    ----------------------------------------
-    Total                     10.700ns (6.148ns logic, 4.552ns route)
-                                       (57.5% logic, 42.5% route)
-
-=========================================================================
-Timing constraint: Default period analysis for Clock 'i_FPGA_SPI_Clk'
-  Clock period: 11.320ns (frequency: 88.339MHz)
-  Total number of paths / destination ports: 397 / 132
--------------------------------------------------------------------------
-Delay:               5.660ns (Levels of Logic = 6)
-  Source:            u_Syscon/u_spi/o_rxcmd_0 (FF)
-  Destination:       u_Syscon/u_spi/dout_0 (FF)
-  Source Clock:      i_FPGA_SPI_Clk rising
-  Destination Clock: i_FPGA_SPI_Clk falling
-
-  Data Path: u_Syscon/u_spi/o_rxcmd_0 to u_Syscon/u_spi/dout_0
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDE:C->Q             10   0.591   1.057  o_rxcmd_0 (o_rxcmd_0)
-     end scope: 'u_spi'
-     LUT4:I0->O            1   0.704   0.000  spi_tx_data<0>82_SW02 (spi_tx_data<0>82_SW01)
-     MUXF5:I0->O           2   0.321   0.526  spi_tx_data<0>82_SW0_f5 (N12)
-     LUT4:I1->O            1   0.704   0.000  spi_tx_data<0>82_F (N18)
-     MUXF5:I0->O           1   0.321   0.424  spi_tx_data<0>82 (spi_tx_data<0>)
-     begin scope: 'u_spi'
-     LUT4:I3->O            1   0.704   0.000  dout_mux0002<0>1 (dout_mux0002<0>)
-     FDR_1:D                   0.308          dout_0
-    ----------------------------------------
-    Total                      5.660ns (3.653ns logic, 2.007ns route)
-                                       (64.5% logic, 35.5% route)
-
-=========================================================================
-Timing constraint: Default OFFSET IN BEFORE for Clock 'ClK_C'
-  Total number of paths / destination ports: 1 / 1
--------------------------------------------------------------------------
-Offset:              2.059ns (Levels of Logic = 2)
-  Source:            i_Ext_Rst_L (PAD)
-  Destination:       u_ClockGen/u_reset/Mshreg_por_l_meta2 (FF)
-  Destination Clock: ClK_C rising
-
-  Data Path: i_Ext_Rst_L to u_ClockGen/u_reset/Mshreg_por_l_meta2
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     IBUF:I->O             1   1.218   0.420  i_Ext_Rst_L_IBUF (i_Ext_Rst_L_IBUF)
-     begin scope: 'u_ClockGen'
-     begin scope: 'u_reset'
-     SRL16:D                   0.421          Mshreg_por_l_meta2
-    ----------------------------------------
-    Total                      2.059ns (1.639ns logic, 0.420ns route)
-                                       (79.6% logic, 20.4% route)
-
-=========================================================================
-Timing constraint: Default OFFSET IN BEFORE for Clock 'ClK_A'
-  Total number of paths / destination ports: 18 / 18
--------------------------------------------------------------------------
-Offset:              3.673ns (Levels of Logic = 3)
-  Source:            b_Video_SPD (PAD)
-  Destination:       u_Video/u_I2C/spd_in_0 (FF)
-  Destination Clock: ClK_A rising 0.2X
-
-  Data Path: b_Video_SPD to u_Video/u_I2C/spd_in_0
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     IOBUF:IO->O           1   1.218   0.420  b_Video_SPD_IOBUF (N9)
-     begin scope: 'u_Video'
-     begin scope: 'u_I2C'
-     INV:I->O              1   0.704   0.420  i_spd_inv1_INV_0 (i_spd_inv)
-     FDR:R                     0.911          spd_in_0
-    ----------------------------------------
-    Total                      3.673ns (2.833ns logic, 0.840ns route)
-                                       (77.1% logic, 22.9% route)
-
-=========================================================================
-Timing constraint: Default OFFSET IN BEFORE for Clock 'i_FPGA_SPI_Clk'
-  Total number of paths / destination ports: 5 / 5
--------------------------------------------------------------------------
-Offset:              2.159ns (Levels of Logic = 2)
-  Source:            b_FPGA_SPI_MOSI (PAD)
-  Destination:       u_FileIO/u_spi/din_0 (FF)
-  Destination Clock: i_FPGA_SPI_Clk rising
-
-  Data Path: b_FPGA_SPI_MOSI to u_FileIO/u_spi/din_0
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     IBUF:I->O             5   1.218   0.633  b_FPGA_SPI_MOSI_IBUF (b_FPGA_SPI_MOSI_IBUF)
-     begin scope: 'u_FileIO'
-     begin scope: 'u_spi'
-     FD:D                      0.308          din_0
-    ----------------------------------------
-    Total                      2.159ns (1.526ns logic, 0.633ns route)
-                                       (70.7% logic, 29.3% route)
-
-=========================================================================
-Timing constraint: Default OFFSET OUT AFTER for Clock 'ClK_A'
-  Total number of paths / destination ports: 143 / 65
--------------------------------------------------------------------------
-Offset:              11.067ns (Levels of Logic = 7)
-  Source:            u_FileIO/u_mem_FIFO/level_11 (FF)
-  Destination:       b_Aux_IO<10> (PAD)
-  Source Clock:      ClK_A rising 0.2X
-
-  Data Path: u_FileIO/u_mem_FIFO/level_11 to b_Aux_IO<10>
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDR:C->Q              6   0.591   0.844  level_11 (level_11)
-     end scope: 'u_mem_FIFO'
-     LUT2:I0->O            2   0.704   0.482  mem_fifo_hfull1 (mem_fifo_hfull)
-     LUT4:I2->O            3   0.704   0.706  o_mch_valid1 (o_mch_valid)
-     end scope: 'u_FileIO'
-     LUT4:I0->O            3   0.704   0.566  writeprotn_s_not0001163 (N0)
-     LUT4:I2->O            4   0.704   0.666  conf_wr_core11 (b_Aux_IO_8_OBUF)
-     LUT2:I1->O            1   0.704   0.420  conf_wr_15411 (b_Aux_IO_11_OBUF)
-     OBUF:I->O                 3.272          b_Aux_IO_11_OBUF (b_Aux_IO<11>)
-    ----------------------------------------
-    Total                     11.067ns (7.383ns logic, 3.684ns route)
-                                       (66.7% logic, 33.3% route)
-
-=========================================================================
-Timing constraint: Default OFFSET OUT AFTER for Clock 'i_FPGA_SPI_Clk'
-  Total number of paths / destination ports: 2 / 1
--------------------------------------------------------------------------
-Offset:              5.486ns (Levels of Logic = 3)
-  Source:            u_Syscon/u_spi/dout_7 (FF)
-  Destination:       b_FPGA_SPI_MISO (PAD)
-  Source Clock:      i_FPGA_SPI_Clk falling
-
-  Data Path: u_Syscon/u_spi/dout_7 to b_FPGA_SPI_MISO
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDR_1:C->Q            1   0.591   0.499  dout_7 (dout_7)
-     end scope: 'u_spi'
-     end scope: 'u_Syscon'
-     LUT4:I1->O            1   0.704   0.420  b_FPGA_SPI_MISO_MLTSRCEDGELogicTrst1 (b_FPGA_SPI_MISO_MLTSRCEDGE)
-     OBUFT:I->O                3.272          b_FPGA_SPI_MISO_OBUFT (b_FPGA_SPI_MISO)
-    ----------------------------------------
-    Total                      5.486ns (4.567ns logic, 0.919ns route)
-                                       (83.2% logic, 16.8% route)
-
-=========================================================================
-Timing constraint: Default OFFSET OUT AFTER for Clock 'ClK_C'
-  Total number of paths / destination ports: 7 / 7
--------------------------------------------------------------------------
-Offset:              4.450ns (Levels of Logic = 2)
-  Source:            u_Syscon/o_vbl (FF)
-  Destination:       o_SSC_RD (PAD)
-  Source Clock:      ClK_C rising
-
-  Data Path: u_Syscon/o_vbl to o_SSC_RD
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FD:C->Q               4   0.591   0.587  o_vbl (o_vbl)
-     end scope: 'u_Syscon'
-     OBUF:I->O                 3.272          o_SSC_RD_OBUF (o_SSC_RD)
-    ----------------------------------------
-    Total                      4.450ns (3.863ns logic, 0.587ns route)
-                                       (86.8% logic, 13.2% route)
-
-=========================================================================
-Timing constraint: Default OFFSET OUT AFTER for Clock 'ClK_B'
-  Total number of paths / destination ports: 4 / 4
--------------------------------------------------------------------------
-Offset:              4.283ns (Levels of Logic = 2)
-  Source:            u_Audio/o_audio_din (FF)
-  Destination:       o_Audio_DIN (PAD)
-  Source Clock:      ClK_B rising
-
-  Data Path: u_Audio/o_audio_din to o_Audio_DIN
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     FDC:C->Q              1   0.591   0.420  o_audio_din (o_audio_din)
-     end scope: 'u_Audio'
-     OBUF:I->O                 3.272          o_Audio_DIN_OBUF (o_Audio_DIN)
-    ----------------------------------------
-    Total                      4.283ns (3.863ns logic, 0.420ns route)
-                                       (90.2% logic, 9.8% route)
-
-=========================================================================
-Timing constraint: Default path analysis
-  Total number of paths / destination ports: 4 / 1
--------------------------------------------------------------------------
-Delay:               6.671ns (Levels of Logic = 3)
-  Source:            i_FPGA_Ctrl0 (PAD)
-  Destination:       b_FPGA_SPI_MISO (PAD)
-
-  Data Path: i_FPGA_Ctrl0 to b_FPGA_SPI_MISO
-                                Gate     Net
-    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
-    ----------------------------------------  ------------
-     IBUF:I->O            10   1.218   1.057  i_FPGA_Ctrl0_IBUF (b_FPGA_SPI_MISO_spi_fileio_miso_not0000_inv)
-     LUT2:I0->O            1   0.704   0.420  b_FPGA_SPI_MISOControl1 (N5)
-     OBUFT:T->O                3.272          b_FPGA_SPI_MISO_OBUFT (b_FPGA_SPI_MISO)
-    ----------------------------------------
-    Total                      6.671ns (5.194ns logic, 1.477ns route)
-                                       (77.9% logic, 22.1% route)
-
-=========================================================================
-
-
-Total REAL time to Xst completion: 461.00 secs
-Total CPU time to Xst completion: 458.88 secs
- 
---> 
-
-
-Total memory usage is 506540 kilobytes
-
-Number of errors   :    0 (   0 filtered)
-Number of warnings : 1376 (   0 filtered)
-Number of infos    :  154 (   0 filtered)
-
-Starting Translate...
-Release 14.7 - ngdbuild P.20131013 (lin)
-Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
-
-Command Line:
-/home/markw/altera/xilinx/ise/14.7/ISE_DS/ISE/bin/lin/unwrapped/ngdbuild -nt on
--uc Replay.ucf Replay.ngc Replay.ngd
-
-Reading NGO file
-"/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay.ngc" ...
-Gathering constraint information from source properties...
-Done.
-
-Annotating constraints to design from ucf file "Replay.ucf" ...
-Resolving constraint associations...
-Checking Constraint Associations...
-WARNING:ConstraintSystem:119 - Constraint <NET "b_Aux_IO(37)"              LOC =
-   "C3"  |> [Replay.ucf(79)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_Aux_IO(37)"' because those design objects do
-   not contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_Aux_IO(37)"              LOC = "C3"  |> [Replay.ucf(79)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(79)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_Aux_IO(37)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(79)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_Aux_IO(37)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_Aux_IO(38)"              LOC =
-   "B6"  |> [Replay.ucf(101)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_Aux_IO(38)"' because those design objects do
-   not contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_Aux_IO(38)"              LOC = "B6"  |> [Replay.ucf(101)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(101)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_Aux_IO(38)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(101)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_Aux_IO(38)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_Aux_IO(36)"              LOC =
-   "F11" |> [Replay.ucf(128)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_Aux_IO(36)"' because those design objects do
-   not contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_Aux_IO(36)"              LOC = "F11" |> [Replay.ucf(128)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(128)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_Aux_IO(36)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(128)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_Aux_IO(36)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_2V5_IO_1"                LOC =
-   "E16" |> [Replay.ucf(160)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_2V5_IO_1"' because those design objects do
-   not contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_2V5_IO_1"                LOC = "E16" |> [Replay.ucf(160)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVCMOS25;>
-   [Replay.ucf(160)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_2V5_IO_1"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_2V5_IO_0"                LOC =
-   "E15" |> [Replay.ucf(161)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_2V5_IO_0"' because those design objects do
-   not contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_2V5_IO_0"                LOC = "E15" |> [Replay.ucf(161)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVCMOS25;>
-   [Replay.ucf(161)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_2V5_IO_0"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_Clk_Aux"                 LOC =
-   "N9"  |> [Replay.ucf(258)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_Clk_Aux"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_Clk_Aux"                 LOC = "N9"  |> [Replay.ucf(258)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(258)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_Clk_Aux"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(258)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_Clk_Aux"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(15)"                  LOC =
-   "N7"  |> [Replay.ucf(272)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(15)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(15)"                  LOC = "N7"  |> [Replay.ucf(272)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(272)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(15)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(272)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(15)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(3)"                   LOC =
-   "V5"  |> [Replay.ucf(277)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(3)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(3)"                   LOC = "V5"  |> [Replay.ucf(277)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(277)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(3)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(277)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(3)"' because those design objects do not contain or drive any instances
-   of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(4)"                   LOC =
-   "U5"  |> [Replay.ucf(278)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(4)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(4)"                   LOC = "U5"  |> [Replay.ucf(278)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(278)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(4)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(278)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(4)"' because those design objects do not contain or drive any instances
-   of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(5)"                   LOC =
-   "T5"  |> [Replay.ucf(279)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(5)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(5)"                   LOC = "T5"  |> [Replay.ucf(279)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(279)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(5)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(279)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(5)"' because those design objects do not contain or drive any instances
-   of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(6)"                   LOC =
-   "R5"  |> [Replay.ucf(281)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(6)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(6)"                   LOC = "R5"  |> [Replay.ucf(281)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(281)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(6)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(281)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(6)"' because those design objects do not contain or drive any instances
-   of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(7)"                   LOC =
-   "T4"  |> [Replay.ucf(283)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(7)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(7)"                   LOC = "T4"  |> [Replay.ucf(283)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(283)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(7)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(283)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(7)"' because those design objects do not contain or drive any instances
-   of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(8)"                   LOC =
-   "U3"  |> [Replay.ucf(285)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(8)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(8)"                   LOC = "U3"  |> [Replay.ucf(285)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(285)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(8)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(285)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(8)"' because those design objects do not contain or drive any instances
-   of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(9)"                   LOC =
-   "T1"  |> [Replay.ucf(291)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(9)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(9)"                   LOC = "T1"  |> [Replay.ucf(291)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(291)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(9)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(291)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(9)"' because those design objects do not contain or drive any instances
-   of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(10)"                  LOC =
-   "T2"  |> [Replay.ucf(292)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(10)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(10)"                  LOC = "T2"  |> [Replay.ucf(292)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(292)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(10)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(292)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(10)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(11)"                  LOC =
-   "R2"  |> [Replay.ucf(294)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(11)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(11)"                  LOC = "R2"  |> [Replay.ucf(294)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(294)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(11)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(294)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(11)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(12)"                  LOC =
-   "R3"  |> [Replay.ucf(295)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(12)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(12)"                  LOC = "R3"  |> [Replay.ucf(295)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(295)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(12)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(295)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(12)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(13)"                  LOC =
-   "P1"  |> [Replay.ucf(297)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(13)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(13)"                  LOC = "P1"  |> [Replay.ucf(297)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(297)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(13)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(297)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(13)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(14)"                  LOC =
-   "P2"  |> [Replay.ucf(299)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(14)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(14)"                  LOC = "P2"  |> [Replay.ucf(299)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(299)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(14)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(299)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(14)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(43)"                  LOC =
-   "P4"  |> [Replay.ucf(301)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(43)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(43)"                  LOC = "P4"  |> [Replay.ucf(301)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(301)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(43)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(301)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(43)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(42)"                  LOC =
-   "N4"  |> [Replay.ucf(304)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(42)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(42)"                  LOC = "N4"  |> [Replay.ucf(304)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(304)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(42)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(304)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(42)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(41)"                  LOC =
-   "N5"  |> [Replay.ucf(305)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(41)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(41)"                  LOC = "N5"  |> [Replay.ucf(305)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(305)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(41)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(305)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(41)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(40)"                  LOC =
-   "M3"  |> [Replay.ucf(308)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(40)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(40)"                  LOC = "M3"  |> [Replay.ucf(308)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(308)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(40)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(308)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(40)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(27)"                  LOC =
-   "M4"  |> [Replay.ucf(309)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(27)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(27)"                  LOC = "M4"  |> [Replay.ucf(309)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(309)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(27)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(309)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(27)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(26)"                  LOC =
-   "M5"  |> [Replay.ucf(310)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(26)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(26)"                  LOC = "M5"  |> [Replay.ucf(310)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(310)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(26)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(310)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(26)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(25)"                  LOC =
-   "M6"  |> [Replay.ucf(311)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(25)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(25)"                  LOC = "M6"  |> [Replay.ucf(311)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(311)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(25)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(311)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(25)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(24)"                  LOC =
-   "L1"  |> [Replay.ucf(312)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(24)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(24)"                  LOC = "L1"  |> [Replay.ucf(312)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(312)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(24)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(312)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(24)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(23)"                  LOC =
-   "L2"  |> [Replay.ucf(313)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(23)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(23)"                  LOC = "L2"  |> [Replay.ucf(313)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(313)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(23)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(313)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(23)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(22)"                  LOC =
-   "L3"  |> [Replay.ucf(314)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(22)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(22)"                  LOC = "L3"  |> [Replay.ucf(314)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(314)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(22)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(314)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(22)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(21)"                  LOC =
-   "L4"  |> [Replay.ucf(315)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(21)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(21)"                  LOC = "L4"  |> [Replay.ucf(315)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(315)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(21)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(315)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(21)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(20)"                  LOC =
-   "L5"  |> [Replay.ucf(317)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(20)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(20)"                  LOC = "L5"  |> [Replay.ucf(317)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(317)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(20)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(317)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(20)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(19)"                  LOC =
-   "L6"  |> [Replay.ucf(318)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(19)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(19)"                  LOC = "L6"  |> [Replay.ucf(318)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(318)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(19)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(318)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(19)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(18)"                  LOC =
-   "K3"  |> [Replay.ucf(320)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(18)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(18)"                  LOC = "K3"  |> [Replay.ucf(320)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(320)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(18)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(320)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(18)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(17)"                  LOC =
-   "K4"  |> [Replay.ucf(321)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(17)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(17)"                  LOC = "K4"  |> [Replay.ucf(321)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(321)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(17)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(321)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(17)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(16)"                  LOC =
-   "K5"  |> [Replay.ucf(322)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(16)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(16)"                  LOC = "K5"  |> [Replay.ucf(322)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(322)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(16)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(322)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(16)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(44)"                  LOC =
-   "K6"  |> [Replay.ucf(323)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(44)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(44)"                  LOC = "K6"  |> [Replay.ucf(323)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(323)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(44)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(323)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(44)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(45)"                  LOC =
-   "J1"  |> [Replay.ucf(326)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(45)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(45)"                  LOC = "J1"  |> [Replay.ucf(326)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(326)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(45)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(326)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(45)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(46)"                  LOC =
-   "J2"  |> [Replay.ucf(327)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(46)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(46)"                  LOC = "J2"  |> [Replay.ucf(327)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(327)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(46)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(327)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(46)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(47)"                  LOC =
-   "J4"  |> [Replay.ucf(328)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(47)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(47)"                  LOC = "J4"  |> [Replay.ucf(328)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(328)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(47)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(328)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(47)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(48)"                  LOC =
-   "J5"  |> [Replay.ucf(329)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(48)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(48)"                  LOC = "J5"  |> [Replay.ucf(329)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(329)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(48)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(329)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(48)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(49)"                  LOC =
-   "H1"  |> [Replay.ucf(332)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(49)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(49)"                  LOC = "H1"  |> [Replay.ucf(332)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(332)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(49)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(332)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(49)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(50)"                  LOC =
-   "H2"  |> [Replay.ucf(333)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(50)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(50)"                  LOC = "H2"  |> [Replay.ucf(333)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(333)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(50)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(333)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(50)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(51)"                  LOC =
-   "H3"  |> [Replay.ucf(335)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(51)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(51)"                  LOC = "H3"  |> [Replay.ucf(335)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(335)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(51)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(335)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(51)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(52)"                  LOC =
-   "H4"  |> [Replay.ucf(336)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(52)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(52)"                  LOC = "H4"  |> [Replay.ucf(336)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(336)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(52)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(336)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(52)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(53)"                  LOC =
-   "H5"  |> [Replay.ucf(337)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(53)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(53)"                  LOC = "H5"  |> [Replay.ucf(337)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(337)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(53)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(337)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(53)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(54)"                  LOC =
-   "H6"  |> [Replay.ucf(338)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(54)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(54)"                  LOC = "H6"  |> [Replay.ucf(338)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(338)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(54)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(338)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(54)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(39)"                  LOC =
-   "G3"  |> [Replay.ucf(340)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(39)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(39)"                  LOC = "G3"  |> [Replay.ucf(340)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(340)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(39)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(340)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(39)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(38)"                  LOC =
-   "G4"  |> [Replay.ucf(341)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(38)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(38)"                  LOC = "G4"  |> [Replay.ucf(341)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(341)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(38)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(341)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(38)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(37)"                  LOC =
-   "G5"  |> [Replay.ucf(342)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(37)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(37)"                  LOC = "G5"  |> [Replay.ucf(342)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(342)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(37)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(342)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(37)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(36)"                  LOC =
-   "G6"  |> [Replay.ucf(344)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(36)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(36)"                  LOC = "G6"  |> [Replay.ucf(344)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(344)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(36)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(344)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(36)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(35)"                  LOC =
-   "F1"  |> [Replay.ucf(345)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(35)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(35)"                  LOC = "F1"  |> [Replay.ucf(345)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(345)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(35)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(345)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(35)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(34)"                  LOC =
-   "F2"  |> [Replay.ucf(346)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(34)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(34)"                  LOC = "F2"  |> [Replay.ucf(346)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(346)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(34)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(346)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(34)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(33)"                  LOC =
-   "E1"  |> [Replay.ucf(349)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(33)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(33)"                  LOC = "E1"  |> [Replay.ucf(349)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(349)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(33)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(349)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(33)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(32)"                  LOC =
-   "E2"  |> [Replay.ucf(350)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(32)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(32)"                  LOC = "E2"  |> [Replay.ucf(350)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(350)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(32)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(350)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(32)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(31)"                  LOC =
-   "E3"  |> [Replay.ucf(351)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(31)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(31)"                  LOC = "E3"  |> [Replay.ucf(351)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(351)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(31)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(351)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(31)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(30)"                  LOC =
-   "E4"  |> [Replay.ucf(353)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(30)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(30)"                  LOC = "E4"  |> [Replay.ucf(353)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(353)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(30)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(353)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(30)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(29)"                  LOC =
-   "D1"  |> [Replay.ucf(354)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(29)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(29)"                  LOC = "D1"  |> [Replay.ucf(354)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(354)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(29)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(354)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(29)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(28)"                  LOC =
-   "D2"  |> [Replay.ucf(355)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_IO(28)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_IO(28)"                  LOC = "D2"  |> [Replay.ucf(355)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(355)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_IO(28)"' because those design objects do not contain
-   or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(355)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_IO(28)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <NET "b_Aux_IO(39)"              LOC =
-   "C1"  |> [Replay.ucf(358)]: This constraint cannot be distributed from the
-   design objects matching 'NET "b_Aux_IO(39)"' because those design objects do
-   not contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem - A target design object for the Locate constraint
-   '<NET "b_Aux_IO(39)"              LOC = "C1"  |> [Replay.ucf(358)]' could not
-   be found and so the Locate constraint will be removed.
-
-WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
-   [Replay.ucf(358)]: This constraint cannot be distributed from the design
-   objects matching 'NET "b_Aux_IO(39)"' because those design objects do not
-   contain or drive any instances of the correct type.
-
-WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(358)]: This
-   constraint cannot be distributed from the design objects matching 'NET
-   "b_Aux_IO(39)"' because those design objects do not contain or drive any
-   instances of the correct type.
-
-INFO:ConstraintSystem:178 - TNM 'clk_a_grp', used in period specification
-   'TS03', was traced into DCM_SP instance u_a_dcm. The following new TNM groups
-   and period specifications were generated at the DCM_SP output(s): 
-   CLK0: <TIMESPEC TS_u_ClockGen_clk_a_dcm_0 = PERIOD "u_ClockGen_clk_a_dcm_0"
-   TS03 HIGH 50%>
-
-INFO:ConstraintSystem:178 - TNM 'clk_a_grp', used in period specification
-   'TS03', was traced into DCM_SP instance u_a_dcm. The following new TNM groups
-   and period specifications were generated at the DCM_SP output(s): 
-   CLK90: <TIMESPEC TS_u_ClockGen_clk_a_dcm_90 = PERIOD
-   "u_ClockGen_clk_a_dcm_90" TS03 PHASE 2.3475 ns HIGH 50%>
-
-INFO:ConstraintSystem:178 - TNM 'clk_a_grp', used in period specification
-   'TS03', was traced into DCM_SP instance u_a_dcm. The following new TNM groups
-   and period specifications were generated at the DCM_SP output(s): 
-   CLKDV: <TIMESPEC TS_u_ClockGen_clk_a_dcm_div = PERIOD
-   "u_ClockGen_clk_a_dcm_div" TS03 * 4 HIGH 50%>
-
-INFO:ConstraintSystem:178 - TNM 'clk_a_grp', used in period specification
-   'TS03', was traced into DCM_SP instance phase_ctrl.u_a2_dcm. The following
-   new TNM groups and period specifications were generated at the DCM_SP
-   output(s): 
-   CLK0: <TIMESPEC TS_u_ClockGen_clk_a2_dcm_0 = PERIOD "u_ClockGen_clk_a2_dcm_0"
-   TS03 HIGH 50%>
-
-INFO:ConstraintSystem:178 - TNM 'clk_b_grp', used in period specification
-   'TS02', was traced into DCM_SP instance u_b_dcm. The following new TNM groups
-   and period specifications were generated at the DCM_SP output(s): 
-   CLK0: <TIMESPEC TS_u_ClockGen_clk_b_dcm_0 = PERIOD "u_ClockGen_clk_b_dcm_0"
-   TS02 HIGH 50%>
-
-INFO:ConstraintSystem:178 - TNM 'clk_c_grp', used in period specification
-   'TS01', was traced into DCM_SP instance u_c_dcm. The following new TNM groups
-   and period specifications were generated at the DCM_SP output(s): 
-   CLK0: <TIMESPEC TS_u_ClockGen_clk_c_dcm_0 = PERIOD "u_ClockGen_clk_c_dcm_0"
-   TS01 HIGH 50%>
-
-INFO:ConstraintSystem:178 - TNM 'clk_c_grp', used in period specification
-   'TS01', was traced into DCM_SP instance u_c_dcm. The following new TNM groups
-   and period specifications were generated at the DCM_SP output(s): 
-   CLK90: <TIMESPEC TS_u_ClockGen_clk_c_dcm_90 = PERIOD
-   "u_ClockGen_clk_c_dcm_90" TS01 PHASE 9.245 ns HIGH 50%>
-
-Done...
-
-INFO:NgdBuild:1222 - Setting CLKIN_PERIOD attribute associated with DCM instance
-   u_a_dcm to 9.390000 ns based on the period specification (<TIMESPEC TS03 =
-   PERIOD : clk_a_grp :  9.39 ;> [Replay.ucf(16)]).
-INFO:NgdBuild:1222 - Setting CLKIN_PERIOD attribute associated with DCM instance
-   u_b_dcm to 20.130000 ns based on the period specification (<TIMESPEC TS02 =
-   PERIOD : clk_b_grp : 20.13 ;> [Replay.ucf(17)]).
-INFO:NgdBuild:1222 - Setting CLKIN_PERIOD attribute associated with DCM instance
-   u_c_dcm to 36.980000 ns based on the period specification (<TIMESPEC TS01 =
-   PERIOD : clk_c_grp : 36.98 ;> [Replay.ucf(18)]).
-INFO:NgdBuild:1222 - Setting CLKIN_PERIOD attribute associated with DCM instance
-   phase_ctrl.u_a2_dcm to 9.390000 ns based on the period specification
-   (<TIMESPEC TS03 = PERIOD : clk_a_grp :  9.39 ;> [Replay.ucf(16)]).
-Checking expanded design ...
-WARNING:NgdBuild:452 - logical net 'N207' has no driver
-WARNING:NgdBuild:452 - logical net 'N228' has no driver
-WARNING:NgdBuild:452 - logical net 'N252' has no driver
-WARNING:NgdBuild:452 - logical net 'N253' has no driver
-WARNING:NgdBuild:452 - logical net 'N254' has no driver
-WARNING:NgdBuild:452 - logical net 'N255' has no driver
-WARNING:NgdBuild:452 - logical net 'N256' has no driver
-WARNING:NgdBuild:452 - logical net 'N257' has no driver
-WARNING:NgdBuild:452 - logical net 'N258' has no driver
-WARNING:NgdBuild:452 - logical net 'N259' has no driver
-WARNING:NgdBuild:452 - logical net 'N260' has no driver
-WARNING:NgdBuild:452 - logical net 'N261' has no driver
-WARNING:NgdBuild:452 - logical net 'N262' has no driver
-WARNING:NgdBuild:452 - logical net 'N263' has no driver
-WARNING:NgdBuild:452 - logical net 'N264' has no driver
-WARNING:NgdBuild:452 - logical net 'N265' has no driver
-WARNING:NgdBuild:452 - logical net 'N266' has no driver
-WARNING:NgdBuild:452 - logical net 'N267' has no driver
-WARNING:NgdBuild:452 - logical net 'cfg_static<0>' has no driver
-WARNING:NgdBuild:452 - logical net 'cfg_static<1>' has no driver
-WARNING:NgdBuild:452 - logical net 'cfg_static<2>' has no driver
-WARNING:NgdBuild:452 - logical net 'cfg_static<3>' has no driver
-WARNING:NgdBuild:452 - logical net 'cfg_static<4>' has no driver
-WARNING:NgdBuild:452 - logical net 'cfg_static<5>' has no driver
-WARNING:NgdBuild:452 - logical net 'hp_ddr_taken' has no driver
-WARNING:NgdBuild:452 - logical net 'hp_ddr_we' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_butn<0>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_butn<1>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_butn<2>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posx<0>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posx<10>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posx<11>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posx<1>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posx<2>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posx<3>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posx<4>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posx<5>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posx<6>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posx<7>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posx<8>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posx<9>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posy<0>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posy<10>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posy<11>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posy<1>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posy<2>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posy<3>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posy<4>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posy<5>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posy<6>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posy<7>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posy<8>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_posy<9>' has no driver
-WARNING:NgdBuild:452 - logical net 'ms_we' has no driver
-WARNING:NgdBuild:452 - logical net 'phy_audio_taken' has no driver
-WARNING:NgdBuild:452 - logical net 'rst_capture' has no driver
-WARNING:NgdBuild:452 - logical net 'u_Video/o_drive_scl_low' has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/i_Joy_A<5>' has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/i_Joy_B<5>' has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/matrix_out<10>' has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/matrix_out<11>' has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/matrix_out<12>' has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/matrix_out<13>' has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/matrix_out<14>' has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/matrix_out<15>' has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/matrix_out<8>' has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/matrix_out<9>' has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/o_Vid_Timing_dig_act_h' has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/o_Vid_Timing_dig_act_v' has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/o_Vid_Timing_dig_sof' has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/o_Vid_Timing_dig_sol' has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/o_Vid_Timing_v_oddline' has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/o_Vid_Timing_v_pix<0>' has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/RAM_ADDR<16>' has no
-   driver
-WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/RAM_ADDR<17>' has no
-   driver
-WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/RAM_ADDR<18>' has no
-   driver
-WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/ROM_ADDR<14>' has no
-   driver
-WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/ROM_ADDR<16>' has no
-   driver
-WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/ROM_ADDR<17>' has no
-   driver
-WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/ROM_ADDR<18>' has no
-   driver
-WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/ROM_ADDR<19>' has no
-   driver
-WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/ROM_ADDR<20>' has no
-   driver
-WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/ROM_ADDR<21>' has no
-   driver
-WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/SDRAM_READ_ENABLE' has
-   no driver
-WARNING:NgdBuild:452 - logical net
-   'u_Core/atari800core/SDRAM_WIDTH_16bit_ACCESS' has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/ZPU_16BIT_WRITE_ENABLE'
-   has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/pokey2/keyboard_scan<1>'
-   has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/pokey2/keyboard_scan<2>'
-   has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/pokey2/keyboard_scan<3>'
-   has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/pokey2/keyboard_scan<4>'
-   has no driver
-WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/pokey2/keyboard_scan<5>'
-   has no driver
-WARNING:NgdBuild:452 - logical net
-   'u_Core/atari800core/zpu_config1/uart1/keyboard_scan<0>' has no driver
-WARNING:NgdBuild:452 - logical net
-   'u_Core/atari800core/zpu_config1/uart1/keyboard_scan<1>' has no driver
-WARNING:NgdBuild:452 - logical net
-   'u_Core/atari800core/zpu_config1/uart1/keyboard_scan<2>' has no driver
-WARNING:NgdBuild:452 - logical net
-   'u_Core/atari800core/zpu_config1/uart1/keyboard_scan<3>' has no driver
-WARNING:NgdBuild:452 - logical net
-   'u_Core/atari800core/zpu_config1/uart1/keyboard_scan<4>' has no driver
-WARNING:NgdBuild:452 - logical net
-   'u_Core/atari800core/zpu_config1/uart1/keyboard_scan<5>' has no driver
-WARNING:NgdBuild:470 - bidirect pad net 'b_IO<0>' has no legal driver
-WARNING:NgdBuild:470 - bidirect pad net 'b_IO<1>' has no legal driver
-WARNING:NgdBuild:470 - bidirect pad net 'b_IO<2>' has no legal driver
-
-Partition Implementation Status
--------------------------------
-
-  No Partitions were found in this design.
-
--------------------------------
-
-NGDBUILD Design Results Summary:
-  Number of errors:     0
-  Number of warnings: 334
-
-Writing NGD file "Replay.ngd" ...
-Total REAL time to NGDBUILD completion:  46 sec
-Total CPU time to NGDBUILD completion:   46 sec
-
-Writing NGDBUILD log file "Replay.bld"...
-
-NGDBUILD done.
-Starting Map...
-Release 14.7 - Map P.20131013 (lin)
-Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
-Using target part "3s1600efg320-4".
-Mapping design into LUTs...
-WARNING:MapLib:701 - Signal b_Video_SPC connected to top level port b_Video_SPC
-   has been removed.
-WARNING:MapLib:701 - Signal b_IO<3> connected to top level port b_IO<3> has been
-   removed.
-WARNING:MapLib:701 - Signal b_IO<4> connected to top level port b_IO<4> has been
-   removed.
-WARNING:MapLib:701 - Signal b_IO<5> connected to top level port b_IO<5> has been
-   removed.
-WARNING:MapLib:701 - Signal b_IO<6> connected to top level port b_IO<6> has been
-   removed.
-WARNING:MapLib:701 - Signal b_IO<7> connected to top level port b_IO<7> has been
-   removed.
-WARNING:MapLib:701 - Signal b_IO<8> connected to top level port b_IO<8> has been
-   removed.
-WARNING:MapLib:701 - Signal b_IO<9> connected to top level port b_IO<9> has been
-   removed.
-WARNING:MapLib:701 - Signal b_IO<10> connected to top level port b_IO<10> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<11> connected to top level port b_IO<11> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<12> connected to top level port b_IO<12> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<13> connected to top level port b_IO<13> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<14> connected to top level port b_IO<14> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<15> connected to top level port b_IO<15> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<16> connected to top level port b_IO<16> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<17> connected to top level port b_IO<17> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<18> connected to top level port b_IO<18> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<19> connected to top level port b_IO<19> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<20> connected to top level port b_IO<20> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<21> connected to top level port b_IO<21> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<22> connected to top level port b_IO<22> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<23> connected to top level port b_IO<23> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<24> connected to top level port b_IO<24> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<25> connected to top level port b_IO<25> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<26> connected to top level port b_IO<26> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<27> connected to top level port b_IO<27> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<28> connected to top level port b_IO<28> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<29> connected to top level port b_IO<29> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<30> connected to top level port b_IO<30> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<31> connected to top level port b_IO<31> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<32> connected to top level port b_IO<32> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<33> connected to top level port b_IO<33> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<34> connected to top level port b_IO<34> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<35> connected to top level port b_IO<35> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<36> connected to top level port b_IO<36> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<37> connected to top level port b_IO<37> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<38> connected to top level port b_IO<38> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<39> connected to top level port b_IO<39> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<40> connected to top level port b_IO<40> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<41> connected to top level port b_IO<41> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<42> connected to top level port b_IO<42> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<43> connected to top level port b_IO<43> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<44> connected to top level port b_IO<44> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<45> connected to top level port b_IO<45> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<46> connected to top level port b_IO<46> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<47> connected to top level port b_IO<47> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<48> connected to top level port b_IO<48> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<49> connected to top level port b_IO<49> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<50> connected to top level port b_IO<50> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<51> connected to top level port b_IO<51> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<52> connected to top level port b_IO<52> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<53> connected to top level port b_IO<53> has
-   been removed.
-WARNING:MapLib:701 - Signal b_IO<54> connected to top level port b_IO<54> has
-   been removed.
-WARNING:MapLib:701 - Signal b_Aux_IO<36> connected to top level port
-   b_Aux_IO<36> has been removed.
-WARNING:MapLib:701 - Signal b_Aux_IO<37> connected to top level port
-   b_Aux_IO<37> has been removed.
-WARNING:MapLib:701 - Signal b_Aux_IO<38> connected to top level port
-   b_Aux_IO<38> has been removed.
-WARNING:MapLib:701 - Signal b_Aux_IO<39> connected to top level port
-   b_Aux_IO<39> has been removed.
-WARNING:MapLib:701 - Signal b_Clk_Aux connected to top level port b_Clk_Aux has
-   been removed.
-WARNING:MapLib:701 - Signal b_2V5_IO_1 connected to top level port b_2V5_IO_1
-   has been removed.
-WARNING:MapLib:701 - Signal b_2V5_IO_0 connected to top level port b_2V5_IO_0
-   has been removed.
-WARNING:MapLib:701 - Signal o_Clk_68K connected to top level port o_Clk_68K has
-   been removed.
-WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
-   symbol "u_ClockGen/physical_group_o_clk_ctl/u_dcm_a_clk_div_bufg" (output
-   signal=clk_ctl) has a mix of clock and non-clock loads. The non-clock loads
-   are:
-   Pin PSCLK of u_ClockGen/physical_group_clk_a2_dcm_0/phase_ctrl.u_a2_dcm
-Writing file Replay.ngm...
-Running directed packing...
-WARNING:Pack:1237 - The register u_Core/atari800core/pia1/CB2_output_reg failed
-   to join the output side of an I/O component. Symbol
-   u_Core/atari800core/pia1/CB2_output_reg is not under the same hierarchy
-   region as symbol o_RS232_RTS_OBUF. There are three ways to fix the problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_Core/atari800core/pia1 in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_Video/u_I2C/o_drive_sda_low failed to join
-   the output side of an I/O component. Symbol u_Video/u_I2C/o_drive_sda_low is
-   not under the same hierarchy region as symbol b_SDA_IOBUF/OBUFT. There are
-   three ways to fix the problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_Video/u_I2C in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_addr_0_1 failed to join the output
-   side of an I/O component. Symbol u_FileIO/mem_addr_0_1 is not under the same
-   hierarchy region as symbol b_Aux_IO_0_OBUF. There are three ways to fix the
-   problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_addr_1_1 failed to join the output
-   side of an I/O component. Symbol u_FileIO/mem_addr_1_1 is not under the same
-   hierarchy region as symbol b_Aux_IO_1_OBUF. There are three ways to fix the
-   problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_rd failed to join the output side
-   of an I/O component. Symbol u_FileIO/mem_rd is not under the same hierarchy
-   region as symbol b_Aux_IO_2_OBUF. There are three ways to fix the problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_rd failed to join the output side
-   of an I/O component. Symbol u_FileIO/mem_rd is not under the same hierarchy
-   region as symbol b_Aux_IO_3_OBUF. There are three ways to fix the problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_addr_18 failed to join the output
-   side of an I/O component. Symbol u_FileIO/mem_addr_18 is not under the same
-   hierarchy region as symbol b_Aux_IO_6_OBUF. There are three ways to fix the
-   problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1239 - The register u_FileIO/u_spi/din_0 failed to join the input
-   side of an I/O component. Symbol u_FileIO/u_spi/din_0 is not under the same
-   hierarchy region as symbol b_FPGA_SPI_MOSI_IBUF. There are three ways to fix
-   the problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO/u_spi in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1239 - The register u_FileIO/u_spi/o_rxdata_0 failed to join the
-   input side of an I/O component. Symbol u_FileIO/u_spi/o_rxdata_0 is not under
-   the same hierarchy region as symbol b_FPGA_SPI_MOSI_IBUF. There are three
-   ways to fix the problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO/u_spi in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1239 - The register u_Syscon/u_spi/din_0 failed to join the input
-   side of an I/O component. Symbol u_Syscon/u_spi/din_0 is not under the same
-   hierarchy region as symbol b_FPGA_SPI_MOSI_IBUF. There are three ways to fix
-   the problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_Syscon/u_spi in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1239 - The register u_Syscon/u_spi/o_rxdata_0 failed to join the
-   input side of an I/O component. Symbol u_Syscon/u_spi/o_rxdata_0 is not under
-   the same hierarchy region as symbol b_FPGA_SPI_MOSI_IBUF. There are three
-   ways to fix the problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_Syscon/u_spi in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1239 - The register u_Syscon/u_spi/o_rxcmd_0 failed to join the
-   input side of an I/O component. Symbol u_Syscon/u_spi/o_rxcmd_0 is not under
-   the same hierarchy region as symbol b_FPGA_SPI_MOSI_IBUF. There are three
-   ways to fix the problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_Syscon/u_spi in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_JoyPS2/u_PSA/ps2_drive_clk_low failed to join
-   the output side of an I/O component. Symbol u_JoyPS2/u_PSA/ps2_drive_clk_low
-   is not under the same hierarchy region as symbol b_PS2A_Clk_IOBUF/OBUFT.
-   There are three ways to fix the problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_JoyPS2/u_PSA in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_JoyPS2/u_PSB/ps2_drive_clk_low failed to join
-   the output side of an I/O component. Symbol u_JoyPS2/u_PSB/ps2_drive_clk_low
-   is not under the same hierarchy region as symbol b_PS2B_Clk_IOBUF/OBUFT.
-   There are three ways to fix the problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_JoyPS2/u_PSB in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_Syscon/o_vbl failed to join the output side
-   of an I/O component. Symbol u_Syscon/o_vbl is not under the same hierarchy
-   region as symbol o_SSC_RD_OBUF. There are three ways to fix the problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_Syscon in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_addr_8 failed to join the output
-   side of an I/O component. Symbol u_FileIO/mem_addr_8 is not under the same
-   hierarchy region as symbol b_Aux_IO_20_OBUF. There are three ways to fix the
-   problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_addr_0_1 failed to join the output
-   side of an I/O component. Symbol u_FileIO/mem_addr_0_1 is not under the same
-   hierarchy region as symbol b_Aux_IO_12_OBUF. There are three ways to fix the
-   problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_addr_9 failed to join the output
-   side of an I/O component. Symbol u_FileIO/mem_addr_9 is not under the same
-   hierarchy region as symbol b_Aux_IO_21_OBUF. There are three ways to fix the
-   problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_addr_1_1 failed to join the output
-   side of an I/O component. Symbol u_FileIO/mem_addr_1_1 is not under the same
-   hierarchy region as symbol b_Aux_IO_13_OBUF. There are three ways to fix the
-   problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_addr_10 failed to join the output
-   side of an I/O component. Symbol u_FileIO/mem_addr_10 is not under the same
-   hierarchy region as symbol b_Aux_IO_22_OBUF. There are three ways to fix the
-   problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_addr_2_1 failed to join the output
-   side of an I/O component. Symbol u_FileIO/mem_addr_2_1 is not under the same
-   hierarchy region as symbol b_Aux_IO_14_OBUF. There are three ways to fix the
-   problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_addr_11 failed to join the output
-   side of an I/O component. Symbol u_FileIO/mem_addr_11 is not under the same
-   hierarchy region as symbol b_Aux_IO_23_OBUF. There are three ways to fix the
-   problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_addr_3_1 failed to join the output
-   side of an I/O component. Symbol u_FileIO/mem_addr_3_1 is not under the same
-   hierarchy region as symbol b_Aux_IO_15_OBUF. There are three ways to fix the
-   problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_addr_12 failed to join the output
-   side of an I/O component. Symbol u_FileIO/mem_addr_12 is not under the same
-   hierarchy region as symbol b_Aux_IO_24_OBUF. There are three ways to fix the
-   problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_addr_4 failed to join the output
-   side of an I/O component. Symbol u_FileIO/mem_addr_4 is not under the same
-   hierarchy region as symbol b_Aux_IO_16_OBUF. There are three ways to fix the
-   problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_addr_13 failed to join the output
-   side of an I/O component. Symbol u_FileIO/mem_addr_13 is not under the same
-   hierarchy region as symbol b_Aux_IO_25_OBUF. There are three ways to fix the
-   problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_addr_5 failed to join the output
-   side of an I/O component. Symbol u_FileIO/mem_addr_5 is not under the same
-   hierarchy region as symbol b_Aux_IO_17_OBUF. There are three ways to fix the
-   problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_addr_14 failed to join the output
-   side of an I/O component. Symbol u_FileIO/mem_addr_14 is not under the same
-   hierarchy region as symbol b_Aux_IO_26_OBUF. There are three ways to fix the
-   problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_addr_6 failed to join the output
-   side of an I/O component. Symbol u_FileIO/mem_addr_6 is not under the same
-   hierarchy region as symbol b_Aux_IO_18_OBUF. There are three ways to fix the
-   problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_addr_15 failed to join the output
-   side of an I/O component. Symbol u_FileIO/mem_addr_15 is not under the same
-   hierarchy region as symbol b_Aux_IO_27_OBUF. There are three ways to fix the
-   problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_FileIO/mem_addr_7 failed to join the output
-   side of an I/O component. Symbol u_FileIO/mem_addr_7 is not under the same
-   hierarchy region as symbol b_Aux_IO_19_OBUF. There are three ways to fix the
-   problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_FileIO in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_Video/u_I2C/o_drive_spc_low failed to join
-   the output side of an I/O component. Symbol u_Video/u_I2C/o_drive_spc_low is
-   not under the same hierarchy region as symbol b_Video_SPC_OBUFT. There are
-   three ways to fix the problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_Video/u_I2C in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_Video/u_I2C/o_drive_spd_low failed to join
-   the output side of an I/O component. Symbol u_Video/u_I2C/o_drive_spd_low is
-   not under the same hierarchy region as symbol b_Video_SPD_IOBUF/OBUFT. There
-   are three ways to fix the problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_Video/u_I2C in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_JoyPS2/u_PSA/ps2_drive_data_low failed to
-   join the output side of an I/O component. Symbol
-   u_JoyPS2/u_PSA/ps2_drive_data_low is not under the same hierarchy region as
-   symbol b_PS2A_Data_IOBUF/OBUFT. There are three ways to fix the problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_JoyPS2/u_PSA in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:1237 - The register u_JoyPS2/u_PSB/ps2_drive_data_low failed to
-   join the output side of an I/O component. Symbol
-   u_JoyPS2/u_PSB/ps2_drive_data_low is not under the same hierarchy region as
-   symbol b_PS2B_Data_IOBUF/OBUFT. There are three ways to fix the problem:
-   1. Put both symbols under the same hierarchy region and process the design.
-   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
-   code I/O registers on the top level of code. If this can not be done, it is
-   suggested to instantiate the proper I/O buffer in the lower level of code and
-   disable I/O buffer inference for that port in the design.
-   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
-   u_JoyPS2/u_PSB in the UCF file.
-   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
-   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
-   will dissolve all hierarchy in the design.
-
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey2/audf2_next<5>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey2/timer2/Mmux_count_next18_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/zpu_config1/uart1/audf1_next<1>11 failed to merge with F5
-   multiplexer u_Core/atari800core/zpu_config1/uart1/timer1/Mmux_count_next6_f5.
-    Two or more symbols belong to different KEEP_HIERARCHY boundaries and can
-   not be merged into the same component.  The design will exhibit suboptimal
-   timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/zpu_config1/uart1/audf1_next<2>11 failed to merge with F5
-   multiplexer u_Core/atari800core/zpu_config1/uart1/timer1/Mmux_count_next9_f5.
-    Two or more symbols belong to different KEEP_HIERARCHY boundaries and can
-   not be merged into the same component.  The design will exhibit suboptimal
-   timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/zpu_config1/uart1/audf1_next<5>11 failed to merge with F5
-   multiplexer
-   u_Core/atari800core/zpu_config1/uart1/timer1/Mmux_count_next18_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey1/audf2_next<1>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey1/timer2/Mmux_count_next6_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey1/audf2_next<2>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey1/timer2/Mmux_count_next9_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey1/audf0_next<5>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey1/timer0/Mmux_count_next18_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom00001081 failed to merge
-   with F5 multiplexer
-   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom0000651_7_f5_f5.  There is
-   a conflict for the FXMUX.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/cpu6502/CPU_ENABLE_RDY1 failed to merge with F5
-   multiplexer u_Core/atari800core/cpu6502/cpu_6502_peter/nmiReg_not0001_f5. 
-   Two or more symbols belong to different KEEP_HIERARCHY boundaries and can not
-   be merged into the same component.  The design will exhibit suboptimal
-   timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/zpu_config1/uart1/audf3_next<5>11 failed to merge with F5
-   multiplexer
-   u_Core/atari800core/zpu_config1/uart1/timer3/Mmux_count_next18_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/zpu_config1/uart1/audf0_next<1>11 failed to merge with F5
-   multiplexer u_Core/atari800core/zpu_config1/uart1/timer0/Mmux_count_next6_f5.
-    Two or more symbols belong to different KEEP_HIERARCHY boundaries and can
-   not be merged into the same component.  The design will exhibit suboptimal
-   timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/zpu_config1/uart1/audf0_next<2>11 failed to merge with F5
-   multiplexer u_Core/atari800core/zpu_config1/uart1/timer0/Mmux_count_next9_f5.
-    Two or more symbols belong to different KEEP_HIERARCHY boundaries and can
-   not be merged into the same component.  The design will exhibit suboptimal
-   timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey1/audf2_next<5>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey1/timer2/Mmux_count_next18_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey2/audf3_next<1>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey2/timer3/Mmux_count_next6_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey2/audf3_next<2>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey2/timer3/Mmux_count_next9_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey1/audf1_next<1>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey1/timer1/Mmux_count_next6_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey1/audf1_next<2>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey1/timer1/Mmux_count_next9_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom00001631 failed to merge
-   with F5 multiplexer
-   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom00002451_8_f5_0_f5.  There
-   is a conflict for the FXMUX.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey2/audf1_next<5>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey2/timer1/Mmux_count_next18_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/antic1/row_count_next<3>1 failed to merge with F5
-   multiplexer
-   u_Core/atari800core/antic1/antic_counter_row_count/Mcount_value_reg_xor<3>1_f
-   5.  Two or more symbols belong to different KEEP_HIERARCHY boundaries and can
-   not be merged into the same component.  The design will exhibit suboptimal
-   timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/antic1/refresh_count_next<0>1 failed to merge with F5
-   multiplexer
-   u_Core/atari800core/antic1/antic_counter_refresh_count/Mcount_value_reg_xor<3
-   >1_f5.  Two or more symbols belong to different KEEP_HIERARCHY boundaries and
-   can not be merged into the same component.  The design will exhibit
-   suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey2/audf2_next<1>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey2/timer2/Mmux_count_next6_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey2/audf2_next<2>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey2/timer2/Mmux_count_next9_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/zpu_config1/uart1/audf0_next<5>11 failed to merge with F5
-   multiplexer
-   u_Core/atari800core/zpu_config1/uart1/timer0/Mmux_count_next18_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey1/audf0_next<1>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey1/timer0/Mmux_count_next6_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey1/audf0_next<2>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey1/timer0/Mmux_count_next9_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey2/audf3_next<5>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey2/timer3/Mmux_count_next18_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/zpu_config1/uart1/audf3_next<1>11 failed to merge with F5
-   multiplexer u_Core/atari800core/zpu_config1/uart1/timer3/Mmux_count_next6_f5.
-    Two or more symbols belong to different KEEP_HIERARCHY boundaries and can
-   not be merged into the same component.  The design will exhibit suboptimal
-   timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/zpu_config1/uart1/audf3_next<2>11 failed to merge with F5
-   multiplexer u_Core/atari800core/zpu_config1/uart1/timer3/Mmux_count_next9_f5.
-    Two or more symbols belong to different KEEP_HIERARCHY boundaries and can
-   not be merged into the same component.  The design will exhibit suboptimal
-   timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/cpu6502/cpu_6502_peter/nineBits_mux0000<0>42 failed to
-   merge with F5 multiplexer
-   u_Core/atari800core/cpu6502/cpu_6502_peter/varZ_mux000128_f5.  There is a
-   conflict for the FXMUX.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/zpu_config1/uart1/audf2_next<5>11 failed to merge with F5
-   multiplexer
-   u_Core/atari800core/zpu_config1/uart1/timer2/Mmux_count_next18_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom0000105 failed to merge
-   with F5 multiplexer
-   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom00001811_5_f5_f5.  There is
-   a conflict for the FXMUX.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey1/audf1_next<5>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey1/timer1/Mmux_count_next18_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey2/audf1_next<1>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey2/timer1/Mmux_count_next6_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey2/audf1_next<2>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey2/timer1/Mmux_count_next9_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/zpu_config1/uart1/audf2_next<1>11 failed to merge with F5
-   multiplexer u_Core/atari800core/zpu_config1/uart1/timer2/Mmux_count_next6_f5.
-    Two or more symbols belong to different KEEP_HIERARCHY boundaries and can
-   not be merged into the same component.  The design will exhibit suboptimal
-   timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/zpu_config1/uart1/audf2_next<2>11 failed to merge with F5
-   multiplexer u_Core/atari800core/zpu_config1/uart1/timer2/Mmux_count_next9_f5.
-    Two or more symbols belong to different KEEP_HIERARCHY boundaries and can
-   not be merged into the same component.  The design will exhibit suboptimal
-   timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey1/audf3_next<5>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey1/timer3/Mmux_count_next18_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom00001551 failed to merge
-   with F5 multiplexer
-   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom00001921_5_f5_f5.  There is
-   a conflict for the FXMUX.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom0000571 failed to merge
-   with F5 multiplexer
-   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom00001001_5_f5_1.  There is
-   a conflict for the FXMUX.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey2/audf0_next<5>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey2/timer0/Mmux_count_next18_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey1/audf3_next<1>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey1/timer3/Mmux_count_next6_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey1/audf3_next<2>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey1/timer3/Mmux_count_next9_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey2/audf0_next<1>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey2/timer0/Mmux_count_next6_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-WARNING:Pack:266 - The function generator
-   u_Core/atari800core/pokey2/audf0_next<2>11 failed to merge with F5
-   multiplexer u_Core/atari800core/pokey2/timer0/Mmux_count_next9_f5.  Two or
-   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
-   merged into the same component.  The design will exhibit suboptimal timing.
-Running delay-based LUT packing...
-Running related packing...
-Updating timing models...
-Writing design file "Replay.ncd"...
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<0>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<1>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<2>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<3>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<4>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<5>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<6>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<7>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<8>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<9>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Joy_A<5>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Joy_B<5>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<10>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<11>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<12>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<20>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<13>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<21>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<14>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<22>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<15>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<16>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<17>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<18>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<19>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <b_IO<0>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <b_IO<1>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <b_IO<2>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Video_Int_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_RS232_CTS_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
-   <u_Core/atari800core/gtia1/counter_hpos/GLOBAL_LOGIC0> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
-   <u_Core/atari800core/antic1/antic_counter_line_buffer/GLOBAL_LOGIC0> is
-   incomplete. The signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
-   <u_Core/atari800core/pokey1/GLOBAL_LOGIC0> is incomplete. The signal does not
-   drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
-   <u_Core/atari800core/pokey2/GLOBAL_LOGIC0> is incomplete. The signal does not
-   drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
-   <u_Core/atari800core/zpu_config1/uart1/GLOBAL_LOGIC0> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<0> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<1> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<2> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<3> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<20> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<12> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<21> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<13> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<30> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<22> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<14> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<31> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<23> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<15> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<32> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<24> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<16> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<33> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<25> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<17> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<34> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<26> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<18> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<35> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<27> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<19> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<28> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<29> is set but the tri state is not configured. 
-
-Design Summary:
-Number of errors:      0
-Number of warnings:  205
-Logic Utilization:
-  Number of Slice Flip Flops:         5,682 out of  29,504   19%
-  Number of 4 input LUTs:            21,508 out of  29,504   72%
-Logic Distribution:
-  Number of occupied Slices:         13,191 out of  14,752   89%
-    Number of Slices containing only related logic:  13,191 out of  13,191 100%
-    Number of Slices containing unrelated logic:          0 out of  13,191   0%
-      *See NOTES below for an explanation of the effects of unrelated logic.
-  Total Number of 4 input LUTs:      22,011 out of  29,504   74%
-    Number used as logic:            12,475
-    Number used as a route-thru:        503
-    Number used for Dual Port RAMs:   6,772
-      (Two LUTs used per Dual Port RAM)
-    Number used for 32x1 RAMs:        2,120
-      (Two LUTs used per 32x1 RAM)
-    Number used as Shift registers:     141
-
-  The Slice Logic Distribution report is not meaningful if the design is
-  over-mapped for a non-slice resource or if Placement fails.
-
-  Number of bonded IOBs:                167 out of     250   66%
-    IOB Flip Flops:                      30
-  Number of IDDR2s used:                 16
-    Number of DDR_ALIGNMENT = NONE       16
-    Number of DDR_ALIGNMENT = C0          0
-    Number of DDR_ALIGNMENT = C1          0
-  Number of ODDR2s used:                 54
-    Number of DDR_ALIGNMENT = NONE       54
-    Number of DDR_ALIGNMENT = C0          0
-    Number of DDR_ALIGNMENT = C1          0
-  Number of RAMB16s:                     36 out of      36  100%
-  Number of BUFGMUXs:                     8 out of      24   33%
-  Number of DCMs:                         4 out of       8   50%
-  Number of MULT18X18SIOs:                4 out of      36   11%
-
-  Number of RPM macros:            1
-Average Fanout of Non-Clock Nets:                4.87
-
-Peak Memory Usage:  312 MB
-Total REAL time to MAP completion:  44 secs 
-Total CPU time to MAP completion:   44 secs 
-
-NOTES:
-
-   Related logic is defined as being logic that shares connectivity - e.g. two
-   LUTs are "related" if they share common inputs.  When assembling slices,
-   Map gives priority to combine logic that is related.  Doing so results in
-   the best timing performance.
-
-   Unrelated logic shares no connectivity.  Map will only begin packing
-   unrelated logic into a slice once 99% of the slices are occupied through
-   related logic packing.
-
-   Note that once logic distribution reaches the 99% level through related
-   logic packing, this does not mean the device is completely utilized.
-   Unrelated logic packing will then begin, continuing until all usable LUTs
-   and FFs are occupied.  Depending on your timing budget, increased levels of
-   unrelated logic packing may adversely affect the overall timing performance
-   of your design.
-
-Mapping completed.
-See MAP report file "Replay.mrp" for details.
-Starting Place & Route...
-Release 14.7 - par P.20131013 (lin)
-Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
-
-
-
-Constraints file: Replay.pcf.
-Loading device for application Rf_Device from file '3s1600e.nph' in environment
-/home/markw/altera/xilinx/ise/14.7/ISE_DS/ISE/.
-   "Replay_Top" is an NCD, version 3.2, device xc3s1600e, package fg320, speed -4
-INFO:Par:469 - Although the Overall Effort Level (-ol) for this implementation has been set to Standard, Placer will run
-   at effort level High. To override this, please set the Placer Effort Level (-pl) to Standard.
-
-Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
-Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)
-
-
-Device speed data version:  "PRODUCTION 1.27 2013-10-13".
-
-
-Design Summary Report:
-
- Number of External IOBs                         167 out of 250    66%
-
-   Number of External Input IOBs                 50
-
-      Number of External Input IBUFs             50
-        Number of LOCed External Input IBUFs     50 out of 50    100%
-
-
-   Number of External Output IOBs                93
-
-      Number of External Output IOBs             93
-        Number of LOCed External Output IOBs     93 out of 93    100%
-
-
-   Number of External Bidir IOBs                 24
-
-      Number of External Bidir IOBs              24
-        Number of LOCed External Bidir IOBs      24 out of 24    100%
-
-
-   Number of BUFGMUXs                        8 out of 24     33%
-      Number of LOCed BUFGMUXs               7 out of 8      87%
-
-   Number of DCMs                            4 out of 8      50%
-      Number of LOCed DCMs                   4 out of 4     100%
-
-   Number of MULT18X18SIOs                   4 out of 36     11%
-   Number of RAMB16s                        36 out of 36    100%
-   Number of Slices                      13191 out of 14752  89%
-      Number of SLICEMs                   5087 out of 7376   68%
-
-
-
-Overall effort level (-ol):   Standard 
-Placer effort level (-pl):    High 
-Placer cost table entry (-t): 1
-Router effort level (-rl):    Standard 
-
-WARNING:Timing:3223 - Timing constraint PATH "TS_20_path" TIG; ignored during timing analysis.
-INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please
-   consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.
-Starting initial Timing Analysis.  REAL time: 20 secs 
-Finished initial Timing Analysis.  REAL time: 23 secs 
-
-WARNING:Par:288 - The signal i_Aux_IP<0>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<1>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<2>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<3>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<4>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<5>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<6>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<7>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<8>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<9>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Joy_A<5>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Joy_B<5>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<10>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<11>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<12>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<20>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<13>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<21>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<14>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<22>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<15>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<16>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<17>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<18>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Aux_IP<19>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal b_IO<0>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal b_IO<1>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal b_IO<2>_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_Video_Int_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal i_RS232_CTS_IBUF has no load.  PAR will not attempt to route this signal.
-WARNING:Par:288 - The signal u_DDRCtrl/u_ddr_ctrl/u_datapath/dqs_ip<0> has no load.  PAR will not attempt to route this
-   signal.
-WARNING:Par:288 - The signal u_DDRCtrl/u_ddr_ctrl/u_datapath/dqs_ip<1> has no load.  PAR will not attempt to route this
-   signal.
-
-Starting Placer
-Total REAL time at the beginning of Placer: 23 secs 
-Total CPU  time at the beginning of Placer: 23 secs 
-
-Phase 1.1  Initial Placement Analysis
-Phase 1.1  Initial Placement Analysis (Checksum:6f14fc81) REAL time: 28 secs 
-
-Phase 2.7  Design Feasibility Check
-Phase 2.7  Design Feasibility Check (Checksum:6f14fc81) REAL time: 28 secs 
-
-Phase 3.31  Local Placement Optimization
-Phase 3.31  Local Placement Optimization (Checksum:6f14fc81) REAL time: 28 secs 
-
-Phase 4.2  Initial Clock and IO Placement
-
-..........
-WARNING:Place:1013 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM
-   site pair.  The clock component <u_ClockGen/u_c_dcm> is placed at site <DCM_X1Y3>.  The clock IO/DCM site can be
-   paired if they are placed/locked in the same quadrant.  The IO component <ClK_C> is placed at site <D10>.  This will
-   not allow the use of the fast path between the IO and the Clock buffer. This is normally an ERROR but the
-   CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <u_ClockGen/ClK_C.PAD> allowing your design to continue.
-   This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly
-   discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in
-   the design.
-WARNING:Place:1013 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM
-   site pair.  The clock component <u_ClockGen/phase_ctrl.u_a2_dcm> is placed at site <DCM_X1Y0>.  The clock IO/DCM site
-   can be paired if they are placed/locked in the same quadrant.  The IO component <ClK_A> is placed at site <IPAD244>. 
-   This will not allow the use of the fast path between the IO and the Clock buffer. This is normally an ERROR but the
-   CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <u_ClockGen/ClK_A.PAD> allowing your design to continue.
-   This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly
-   discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in
-   the design.
-Phase 4.2  Initial Clock and IO Placement (Checksum:675a3311) REAL time: 38 secs 
-
-Phase 5.30  Global Clock Region Assignment
-Phase 5.30  Global Clock Region Assignment (Checksum:675a3311) REAL time: 38 secs 
-
-Phase 6.36  Local Placement Optimization
-Phase 6.36  Local Placement Optimization (Checksum:675a3311) REAL time: 38 secs 
-
-Phase 7.8  Global Placement
-................................
-..........................................................................................................................
-.....................................
-..................................................................................................................
-.................................................
-................................................
-.................................
-..........................................
-Phase 7.8  Global Placement (Checksum:5eee4f94) REAL time: 4 mins 35 secs 
-
-Phase 8.5  Local Placement Optimization
-Phase 8.5  Local Placement Optimization (Checksum:5eee4f94) REAL time: 4 mins 36 secs 
-
-Phase 9.18  Placement Optimization
-Phase 9.18  Placement Optimization (Checksum:355031c8) REAL time: 5 mins 39 secs 
-
-Phase 10.5  Local Placement Optimization
-Phase 10.5  Local Placement Optimization (Checksum:355031c8) REAL time: 5 mins 40 secs 
-
-Total REAL time to Placer completion: 5 mins 43 secs 
-Total CPU  time to Placer completion: 5 mins 42 secs 
-Writing design to file Replay.ncd
-
-
-
-Starting Router
-
-
-Phase  1  : 108359 unrouted;      REAL time: 6 mins 23 secs 
-
-Phase  2  : 99316 unrouted;      REAL time: 6 mins 34 secs 
-
-Phase  3  : 30271 unrouted;      REAL time: 7 mins 10 secs 
-
-Phase  4  : 30355 unrouted; (Setup:5838, Hold:0, Component Switching Limit:0)     REAL time: 7 mins 33 secs 
-
-Phase  5  : 0 unrouted; (Setup:7081, Hold:0, Component Switching Limit:0)     REAL time: 8 mins 43 secs 
-
-Updating file: Replay.ncd with current fully routed design.
-
-Phase  6  : 0 unrouted; (Setup:7081, Hold:0, Component Switching Limit:0)     REAL time: 9 mins 11 secs 
-
-Phase  7  : 0 unrouted; (Setup:7081, Hold:0, Component Switching Limit:0)     REAL time: 9 mins 57 secs 
-
-Phase  8  : 0 unrouted; (Setup:7081, Hold:0, Component Switching Limit:0)     REAL time: 10 mins 10 secs 
-
-Phase  9  : 0 unrouted; (Setup:7081, Hold:0, Component Switching Limit:0)     REAL time: 10 mins 10 secs 
-
-Phase 10  : 0 unrouted; (Setup:6386, Hold:0, Component Switching Limit:0)     REAL time: 10 mins 20 secs 
-WARNING:Route:455 - CLK Net:u_ClockGen/clk_c_ibuf may have excessive skew because 
-      1 CLK pins and 0 NON_CLK pins failed to route using a CLK template.
-
-Total REAL time to Router completion: 10 mins 21 secs 
-Total CPU time to Router completion: 10 mins 20 secs 
-
-Partition Implementation Status
--------------------------------
-
-  No Partitions were found in this design.
-
--------------------------------
-
-Generating "PAR" statistics.
-
-**************************
-Generating Clock Report
-**************************
-
-+---------------------+--------------+------+------+------------+-------------+
-|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
-+---------------------+--------------+------+------+------------+-------------+
-|             clk_aud | BUFGMUX_X1Y10| No   |   32 |  0.192     |  0.549      |
-+---------------------+--------------+------+------+------------+-------------+
-|             clk_ctl |  BUFGMUX_X1Y1|Yes   | 7403 |  0.507     |  0.768      |
-+---------------------+--------------+------+------+------------+-------------+
-|             clk_vid | BUFGMUX_X2Y10|Yes   |  307 |  0.280     |  0.549      |
-+---------------------+--------------+------+------+------------+-------------+
-|             clk_ram |  BUFGMUX_X2Y1|Yes   |  193 |  0.289     |  0.549      |
-+---------------------+--------------+------+------+------------+-------------+
-|          clk_vid_90 | BUFGMUX_X2Y11|Yes   |    4 |  0.000     |  0.552      |
-+---------------------+--------------+------+------+------------+-------------+
-|         clk_capture |  BUFGMUX_X2Y0|Yes   |   70 |  0.179     |  0.552      |
-+---------------------+--------------+------+------+------------+-------------+
-|          clk_ram_90 |  BUFGMUX_X1Y0|Yes   |   54 |  0.179     |  0.552      |
-+---------------------+--------------+------+------+------------+-------------+
-|             clk_spi | BUFGMUX_X1Y11|Yes   |   59 |  0.115     |  0.535      |
-+---------------------+--------------+------+------+------------+-------------+
-|u_ClockGen/clk_c_ibu |              |      |      |            |             |
-|                   f |         Local|      |   11 |  0.150     |  1.839      |
-+---------------------+--------------+------+------+------------+-------------+
-
-* Net Skew is the difference between the minimum and maximum routing
-only delays for the net. Note this is different from Clock Skew which
-is reported in TRCE timing report. Clock Skew is the difference between
-the minimum and maximum path delays which includes logic delays.
-
-* The fanout is the number of component pins not the individual BEL loads,
-for example SLICE loads not FF loads.
-
-Timing Score: 6386 (Setup: 6386, Hold: 0, Component Switching Limit: 0)
-
-WARNING:Par:468 - Your design did not meet timing.  The following are some suggestions to assist you to meet timing in
-   your design.
-
-   Review the timing report using Timing Analyzer (In ISE select "Post-Place &
-   Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
-
-   Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to
-   ensure the best options are set in the tools for timing closure.
-
-   Increase the PAR Effort Level setting to "high"
-
-   Use the Xilinx "SmartXplorer" script to try special combinations of
-   options known to produce very good results.
-
-   Visit the Xilinx technical support web at http://support.xilinx.com and go to
-   either "Troubleshoot->Tech Tips->Timing & Constraints" or "
-   TechXclusives->Timing Closure" for tips and suggestions for meeting timing
-   in your design.
-
-Number of Timing Constraints that were not applied: 4
-
-Asterisk (*) preceding a constraint indicates it was not met.
-   This may be due to a setup or hold violation.
-
-----------------------------------------------------------------------------------------------------------
-  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
-                                            |             |    Slack   | Achievable | Errors |    Score   
-----------------------------------------------------------------------------------------------------------
-* TS_u_ClockGen_clk_a_dcm_div = PERIOD TIME | SETUP       |    -0.436ns|    39.304ns|      32|        6386
-  GRP "u_ClockGen_clk_a_dcm_div" TS03 *     | HOLD        |     0.678ns|            |       0|           0
-       4 HIGH 50%                           |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  NET "u_ClockGen/clk_a_ibuf" MAXSKEW = 0.3 | NETSKEW     |     0.064ns|     0.236ns|       0|           0
-   ns                                       |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  TS_u_ClockGen_clk_a_dcm_90 = PERIOD TIMEG | SETUP       |     0.236ns|     8.445ns|       0|           0
-  RP "u_ClockGen_clk_a_dcm_90" TS03         | HOLD        |     1.240ns|            |       0|           0
-   PHASE 2.3475 ns HIGH 50%                 |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  TS_u_ClockGen_clk_a_dcm_0 = PERIOD TIMEGR | SETUP       |     0.278ns|     9.112ns|       0|           0
-  P "u_ClockGen_clk_a_dcm_0" TS03 HIGH      | HOLD        |     0.917ns|            |       0|           0
-      50%                                   |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  TS_u_ClockGen_clk_a2_dcm_0 = PERIOD TIMEG | SETUP       |     0.606ns|     8.178ns|       0|           0
-  RP "u_ClockGen_clk_a2_dcm_0" TS03         | HOLD        |     0.928ns|            |       0|           0
-   HIGH 50%                                 |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  TS03 = PERIOD TIMEGRP "clk_a_grp" 9.39 ns | MINLOWPULSE |     4.590ns|     4.800ns|       0|           0
-   HIGH 50%                                 |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  TS_i_FPGA_SPI_Clk = PERIOD TIMEGRP "i_FPG | SETUP       |     8.508ns|    12.984ns|       0|           0
-  A_SPI_Clk" 30 ns HIGH 50%                 | HOLD        |     0.960ns|            |       0|           0
-----------------------------------------------------------------------------------------------------------
-  TS02 = PERIOD TIMEGRP "clk_b_grp" 20.13 n | MINLOWPULSE |    10.130ns|    10.000ns|       0|           0
-  s HIGH 50%                                |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  TS_u_ClockGen_clk_b_dcm_0 = PERIOD TIMEGR | SETUP       |    13.229ns|     6.901ns|       0|           0
-  P "u_ClockGen_clk_b_dcm_0" TS02 HIGH      | HOLD        |     1.367ns|            |       0|           0
-      50%                                   |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  TS_u_ClockGen_clk_c_dcm_0 = PERIOD TIMEGR | SETUP       |    14.051ns|    21.023ns|       0|           0
-  P "u_ClockGen_clk_c_dcm_0" TS01 HIGH      | HOLD        |     0.761ns|            |       0|           0
-      50%                                   |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  TS12 = MAXDELAY FROM TIMEGRP "FFS" TO TIM | MAXDELAY    |    15.749ns|    14.251ns|       0|           0
-  EGRP "PADS" 30 ns                         |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  TS11 = MAXDELAY FROM TIMEGRP "PADS" TO TI | SETUP       |    22.188ns|     7.812ns|       0|           0
-  MEGRP "FFS" 30 ns                         |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  TS01 = PERIOD TIMEGRP "clk_c_grp" 36.98 n | SETUP       |    33.315ns|     3.665ns|       0|           0
-  s HIGH 50%                                | HOLD        |     0.973ns|            |       0|           0
-                                            | MINLOWPULSE |    26.980ns|    10.000ns|       0|           0
-----------------------------------------------------------------------------------------------------------
-  TS_u_ClockGen_clk_c_dcm_90 = PERIOD TIMEG | MINPERIOD   |    35.384ns|     1.596ns|       0|           0
-  RP "u_ClockGen_clk_c_dcm_90" TS01         |             |            |            |        |            
-   PHASE 9.245 ns HIGH 50%                  |             |            |            |        |            
-----------------------------------------------------------------------------------------------------------
-  PATH "TS_22_path" TIG                     | SETUP       |         N/A|     6.220ns|     N/A|           0
-----------------------------------------------------------------------------------------------------------
-  PATH "TS_21_path" TIG                     | MAXDELAY    |         N/A|     5.001ns|     N/A|           0
-----------------------------------------------------------------------------------------------------------
-  PATH "TS_20_path" TIG                     | N/A         |         N/A|         N/A|     N/A|         N/A
-----------------------------------------------------------------------------------------------------------
-
-
-Derived Constraint Report
-Review Timing Report for more details on the following derived constraints.
-To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
-or "Run Timing Analysis" from Timing Analyzer (timingan).
-Derived Constraints for TS03
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
-|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS03                           |      9.390ns|      4.800ns|      9.826ns|            0|           32|            0|     16440849|
-| TS_u_ClockGen_clk_a_dcm_0     |      9.390ns|      9.112ns|          N/A|            0|            0|         3628|            0|
-| TS_u_ClockGen_clk_a_dcm_90    |      9.390ns|      8.445ns|          N/A|            0|            0|          104|            0|
-| TS_u_ClockGen_clk_a_dcm_div   |     37.560ns|     39.304ns|          N/A|           32|            0|     16436746|            0|
-| TS_u_ClockGen_clk_a2_dcm_0    |      9.390ns|      8.178ns|          N/A|            0|            0|          371|            0|
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-Derived Constraints for TS02
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
-|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS02                           |     20.130ns|     10.000ns|      6.901ns|            0|            0|            0|          364|
-| TS_u_ClockGen_clk_b_dcm_0     |     20.130ns|      6.901ns|          N/A|            0|            0|          364|            0|
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-Derived Constraints for TS01
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
-|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
-|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-|TS01                           |     36.980ns|     10.000ns|     21.023ns|            0|            0|           50|        40640|
-| TS_u_ClockGen_clk_c_dcm_0     |     36.980ns|     21.023ns|          N/A|            0|            0|        40640|            0|
-| TS_u_ClockGen_clk_c_dcm_90    |     36.980ns|      1.596ns|          N/A|            0|            0|            0|            0|
-+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
-
-1 constraint not met.
-INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 
-   constraint is not analyzed due to the following: No paths covered by this 
-   constraint; Other constraints intersect with this constraint; or This 
-   constraint was disabled by a Path Tracing Control. Please run the Timespec 
-   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
-
-
-Generating Pad Report.
-
-All signals are completely routed.
-
-WARNING:Par:283 - There are 32 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
-
-Total REAL time to PAR completion: 10 mins 31 secs 
-Total CPU time to PAR completion: 10 mins 29 secs 
-
-Peak Memory Usage:  455 MB
-
-Placement: Completed - No errors found.
-Routing: Completed - No errors found.
-Timing: Completed - 32 errors found.
-
-Number of error messages: 0
-Number of warning messages: 39
-Number of info messages: 2
-
-Writing design to file Replay.ncd
-
-
-
-PAR done!
-Starting Timing Analysis...
-Release 14.7 - Trace  (lin)
-Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
-
-
-Loading device for application Rf_Device from file '3s1600e.nph' in environment
-/home/markw/altera/xilinx/ise/14.7/ISE_DS/ISE/.
-   "Replay_Top" is an NCD, version 3.2, device xc3s1600e, package fg320, speed
--4
-WARNING:Timing:3223 - Timing constraint PATH "TS_20_path" TIG; ignored during
-   timing analysis.
-INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more
-   information, see the TSI report.  Please consult the Xilinx Command Line
-   Tools User Guide for information on generating a TSI report.
---------------------------------------------------------------------------------
-Release 14.7 Trace  (lin)
-Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
-
-/home/markw/altera/xilinx/ise/14.7/ISE_DS/ISE/bin/lin/unwrapped/trce -v 10 -o
-Replay.twr Replay.ncd Replay.pcf
-
-
-Design file:              Replay.ncd
-Physical constraint file: Replay.pcf
-Device,speed:             xc3s1600e,-4 (PRODUCTION 1.27 2013-10-13)
-Report level:             verbose report, limited to 10 items per constraint
---------------------------------------------------------------------------------
-
-INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
-INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
-   option. All paths that are not constrained will be reported in the
-   unconstrained paths section(s) of the report.
-INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a
-   50 Ohm transmission line loading model.  For the details of this model, and
-   for more information on accounting for different loading conditions, please
-   see the device datasheet.
-INFO:Timing:3390 - This architecture does not support a default System Jitter
-   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
-   Uncertainty calculation.
-INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
-   'Phase Error' calculations, these terms will be zero in the Clock Uncertainty
-   calculation.  Please make appropriate modification to SYSTEM_JITTER to
-   account for the unsupported Discrete Jitter and Phase Error.
-
-
-Timing summary:
----------------
-
-Timing errors: 32  Score: 6386 (Setup/Max: 6386, Hold: 0)
-
-Constraints cover 16489089 paths, 1 nets, and 106512 connections
-
-Design statistics:
-   Minimum period:  39.304ns (Maximum frequency:  25.443MHz)
-   Maximum path delay from/to any node:  14.251ns
-   Maximum net skew:   0.236ns
-
-
-Analysis completed Fri Mar 21 21:39:00 2014
---------------------------------------------------------------------------------
-
-Generating Report ...
-
-Number of warnings: 1
-Number of info messages: 6
-Total time: 1 mins 4 secs 
-Starting Bitgen...
-Release 14.7 - Bitgen P.20131013 (lin)
-Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
-Loading device for application Rf_Device from file '3s1600e.nph' in environment
-/home/markw/altera/xilinx/ise/14.7/ISE_DS/ISE/.
-   "Replay_Top" is an NCD, version 3.2, device xc3s1600e, package fg320, speed
--4
-Opened constraints file Replay.pcf.
-
-Fri Mar 21 21:39:14 2014
-
-Running DRC.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<0>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<1>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<2>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<3>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<4>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<5>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<6>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<7>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<8>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<9>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Joy_A<5>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Joy_B<5>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<10>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<11>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<12>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<20>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<13>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<21>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<14>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<22>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<15>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<16>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<17>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<18>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<19>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <b_IO<0>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <b_IO<1>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <b_IO<2>_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_Video_Int_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal <i_RS232_CTS_IBUF> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
-   <u_Core/atari800core/gtia1/counter_hpos/GLOBAL_LOGIC0> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
-   <u_Core/atari800core/antic1/antic_counter_line_buffer/GLOBAL_LOGIC0> is
-   incomplete. The signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
-   <u_Core/atari800core/pokey1/GLOBAL_LOGIC0> is incomplete. The signal does not
-   drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
-   <u_Core/atari800core/pokey2/GLOBAL_LOGIC0> is incomplete. The signal does not
-   drive any load pins in the design.
-WARNING:PhysDesignRules:367 - The signal
-   <u_Core/atari800core/zpu_config1/uart1/GLOBAL_LOGIC0> is incomplete. The
-   signal does not drive any load pins in the design.
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<0> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<1> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<2> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<3> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<20> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<12> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<21> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<13> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<30> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<22> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<14> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<31> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<23> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<15> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<32> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<24> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<16> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<33> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<25> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<17> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<34> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<26> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<18> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<35> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<27> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<19> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<28> is set but the tri state is not configured. 
-WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
-   b_Aux_IO<29> is set but the tri state is not configured. 
-DRC detected 0 errors and 63 warnings.  Please see the previously displayed
-individual error or warning messages for more details.
-Creating bit map...
-Saving bit stream in "Replay.bit".
-Saving bit stream in "Replay.bin".
-Bitstream generation is complete.
-~/altera/replay/src/hw/replay/cores/atari_800xl
Index: replay/Replay.prj
===================================================================
--- replay/Replay.prj	(revision 17)
+++ replay/Replay.prj	(revision 18)
@@ -35,7 +35,6 @@
 antic_dma_clock.vhdl
 antic.vhdl
 complete_address_decoder.vhdl
-countdown_timer.vhdl
 cpu_65xx_e.vhd
 cpu_65xx_a.vhd
 cpu_6510.vhd
@@ -50,13 +49,14 @@
 internalromram.vhd
 irq_glue.vhdl
 pia.vhdl
+pokey_countdown_timer.vhdl
 pokey_keyboard_scanner.vhdl
 pokey_mixer.vhdl
 pokey_noise_filter.vhdl
 pokey.vhdl
-poly_17_9.vhdl
-poly_4.vhdl
-poly_5.vhdl
+pokey_poly_17_9.vhdl
+pokey_poly_4.vhdl
+pokey_poly_5.vhdl
 reg_file.vhdl
 shared_enable.vhdl
 simple_counter.vhdl
@@ -63,14 +63,10 @@
 synchronizer.vhdl
 syncreset_enable_divider.vhd
 wide_delay_line.vhdl
-zpupkg.vhd
-zpu_config_regs.vhdl
-zpu_core.vhd
-zpu_glue.vhdl
-zpu_rom.vhdl
 basic.vhdl
 os16.vhdl
 covox.vhd
 atari800core.vhd
+atari800core_simple_sdram.vhd
 Core_Top.vhd
 Replay_Top.vhd
Index: replay/build.sh
===================================================================
--- replay/build.sh	(revision 17)
+++ replay/build.sh	(revision 18)
@@ -6,8 +6,9 @@
 
 embed_roms=0
 
+REPLAY_BASE=/home/markw/fpga/svn/replay/src/hw/replay/cores/replay_lib/
 
-. /home/markw/altera/xilinx/ise/14.7/ISE_DS/settings32.sh
+. /home/markw/fpga/xilinx/14.7/ISE_DS/settings64.sh
 
 if [ $embed_roms = 1 ]; then
     pushd sdcard
@@ -24,8 +25,14 @@
 mkdir -p build
 pushd build
 
-cp -p ../../replay_lib/rtl/*.vhd .
-cp -p ../source/*.v* .
+# copy source files
+cp -p ${REPLAY_BASE}/rtl/*.vhd .
+cp -p ../source/*.vhd .
+cp -p ../source/*.vhdl .
+cp -p ../../common/a8core/*.vhd .
+cp -p ../../common/a8core/*.vhdl .
+cp -p ../../common/components/*.vhd .
+cp -p ../../common/components/*.vhdl .
 
 cp -p ../$name.ucf .
 cp -p ../$name.ut .
Index: replay/sdcard/atari800.bin
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: replay/simulate.sh
===================================================================
--- replay/simulate.sh	(revision 17)
+++ replay/simulate.sh	(revision 18)
@@ -7,9 +7,10 @@
 
 name=Replay
 
+REPLAY_BASE=/home/markw/fpga/svn/replay/src/hw/replay/cores/replay_lib/
 
 
-. /home/markw/altera/xilinx/ise/14.7/ISE_DS/settings32.sh
+. /home/markw/fpga/xilinx/14.7/ISE_DS/settings64.sh
 
 mkdir -p sim
 pushd sim
@@ -26,14 +27,18 @@
 
         # copy testbench files
         cp -p ../tb/Replay_tb.vhd .
-        cp -p ../../replay_lib/tb/ddr.v .
-        cp -p ../../replay_lib/tb/ddr_parameters.vh .
-        cp -p ../../replay_lib/tb/Replay_I2C_CH7301.vhd .
+        cp -p ${REPLAY_BASE}/tb/ddr.v .
+        cp -p ${REPLAY_BASE}/tb/ddr_parameters.vh .
+        cp -p ${REPLAY_BASE}/tb/Replay_I2C_CH7301.vhd .
 
         # copy source files
-        cp -p ../../replay_lib/rtl/*.vhd .
+        cp -p ${REPLAY_BASE}/rtl/*.vhd .
         cp -p ../source/*.vhd .
         cp -p ../source/*.vhdl .
+	cp -p ../../common/a8core/*.vhd .
+	cp -p ../../common/a8core/*.vhdl .
+	cp -p ../../common/components/*.vhd .
+	cp -p ../../common/components/*.vhdl .
 
 
         # set up project definition file
Index: replay/source/Core_Top.vhd
===================================================================
--- replay/source/Core_Top.vhd	(revision 17)
+++ replay/source/Core_Top.vhd	(revision 18)
@@ -53,6 +53,7 @@
   use ieee.std_logic_1164.all;
   use ieee.std_logic_unsigned.all;
   use ieee.numeric_std.all;
+  use IEEE.STD_LOGIC_MISC.all;
 
   use work.Replay_Pack.all;
   use work.Replay_VideoTiming_Pack.all;
@@ -215,17 +216,80 @@
   signal core_blank_count_next : std_logic_vector(23 downto 0);
   signal core_blank_count_reg : std_logic_vector(23 downto 0);
 
+  SIGNAL	THROTTLE_COUNT_6502 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+
+  SIGNAL	CONSOL_OPTION :  STD_LOGIC;
+  SIGNAL	CONSOL_SELECT :  STD_LOGIC;
+  SIGNAL	CONSOL_START :  STD_LOGIC;
+
+  SIGNAL	KEYBOARD_RESPONSE :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+  SIGNAL	KEYBOARD_SCAN :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+
+  signal keyboard_scan_inv : std_logic_vector(5 downto 0);
+  signal matrix_out_match : std_logic_vector(7 downto 0);
+
 begin
   -- core control
   res_s <= i_Rst_Core;
   core_en_s <= i_Ena_Sys and not i_Halt_Core and not pause_key;
 
-PLL_LOCKED <= not(i_rst_sys or i_Rst_Core);
-atari800core : entity work.atari800core
-	PORT map
+  -- atari keyboard
+	keyboard_scan_inv <= not(keyboard_scan);
+
+a4051: entity work.complete_address_decoder
+	generic map (width => 3)
+	PORT map ( addr_in => keyboard_scan_inv(5 downto 3), addr_decoded => matrix_in ); 
+
+b4051: entity work.complete_address_decoder
+	generic map (width => 3)
+	PORT map ( addr_in => keyboard_scan_inv(2 downto 0), addr_decoded => matrix_out_match ); 
+
+	process(matrix_out, matrix_out_match)
+	begin
+		keyboard_response(0) <= '1';
+
+		if (or_reduce(matrix_out(7 downto 0) and matrix_out_match(7 downto 0)) = '1') then
+			keyboard_response(0) <= '0';
+		end if;
+	end process;
+
+	process(static_keys, pause_key)
+	begin
+		keyboard_response(1) <= '1';
+
+		if (keyboard_scan(5 downto 4)="00" and pause_key = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+		
+		if (keyboard_scan(5 downto 4)="10" and static_keys(0) = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+
+		if (keyboard_scan(5 downto 4)="11" and static_keys(1) = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+	end process;
+
+	CONSOL_START <= static_keys(6);
+	CONSOL_SELECT <= static_keys(5);
+	CONSOL_OPTION <= static_keys(4);
+--	system_reset_request <= static_keys(3);
+
+	PLL_LOCKED <= not(i_rst_sys or i_Rst_Core);
+	
+	THROTTLE_COUNT_6502 <= std_logic_vector(to_unsigned(16-1,6));
+
+atarixl_simple_sdram1 : entity work.atari800core_simple_sdram
+	GENERIC MAP
 	(
+		cycle_length => 16,
+		internal_rom => 0,
+		internal_ram => 0
+	)
+	PORT MAP
+	(
 		CLK => i_clk_sys,
-		PLL_LOCKED => PLL_LOCKED,
+		RESET_N => PLL_LOCKED,
 
 		VGA_VS => core_vsync,
 		VGA_HS => core_hsync,
@@ -233,17 +297,23 @@
 		VGA_G => core_g_s,
 		VGA_R => core_r_s,
 
-		matrix_out => matrix_out,
-		matrix_in => matrix_in,
-		static_keys => static_keys,
-		pause_key => pause_key,
-
-		JOY1_n => i_Joy_A,
-		JOY2_n => i_Joy_B,
-		
 		AUDIO_L => lsound_s,
 		AUDIO_R => rsound_s,
 
+		JOY1_n => i_Joy_B(4 downto 0),
+		JOY2_n => i_Joy_A(4 downto 0),
+
+		KEYBOARD_RESPONSE => KEYBOARD_RESPONSE,
+		KEYBOARD_SCAN => KEYBOARD_SCAN,
+
+		SIO_COMMAND => o_RS232_RTS,
+		SIO_RXD => i_RS232_RXD,
+		SIO_TXD => o_RS232_TXD,
+
+		CONSOL_OPTION => CONSOL_OPTION,
+		CONSOL_SELECT => CONSOL_SELECT,
+		CONSOL_START => CONSOL_START,
+
 		SDRAM_REQUEST => SDRAM_REQUEST,
 		SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
 		SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,
@@ -251,20 +321,72 @@
 		SDRAM_ADDR => SDRAM_ADDR,
 		SDRAM_DO => SDRAM_DO,
 		SDRAM_DI => SDRAM_DI,
-		SDRAM_WIDTH_8bit_ACCESS => SDRAM_WIDTH_8bit_ACCESS,
-		SDRAM_WIDTH_16bit_ACCESS => SDRAM_WIDTH_16bit_ACCESS,
-		SDRAM_WIDTH_32bit_ACCESS => SDRAM_WIDTH_32bit_ACCESS,
+		SDRAM_32BIT_WRITE_ENABLE => SDRAM_WIDTH_32bit_ACCESS,
+		SDRAM_16BIT_WRITE_ENABLE => SDRAM_WIDTH_16bit_ACCESS,
+		SDRAM_8BIT_WRITE_ENABLE => SDRAM_WIDTH_8bit_ACCESS,
 
-		SIO_RXD => i_RS232_RXD,
-		SIO_TXD => o_RS232_TXD,
-		SIO_COMMAND_TX => o_RS232_RTS,
+		-- TODO, these sdram signals should come from PBI, not from DMA...
+		-- TODO, review what I can share form PBI/DMA...
+		DMA_FETCH => '0',
+		DMA_READ_ENABLE => '0',
+		DMA_32BIT_WRITE_ENABLE => '0',
+		DMA_16BIT_WRITE_ENABLE => '0',
+		DMA_8BIT_WRITE_ENABLE => '0',
+		DMA_ADDR => (others=>'1'),
+		DMA_WRITE_DATA => (others=>'0'),
+		MEMORY_READY_DMA => open,
 
-		ram_select => ram_select,
-		rom_select => rom_select,
-
-		halt => i_Halt_Core
+   		RAM_SELECT => ram_select,
+    		ROM_SELECT => rom_select,
+		PAL => '1',
+		HALT => i_Halt_Core,
+		THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502
 	);
 
+--atari800core : entity work.atari800core
+--	PORT map
+--	(
+--		CLK => i_clk_sys,
+--		PLL_LOCKED => PLL_LOCKED,
+--
+--		VGA_VS => core_vsync,
+--		VGA_HS => core_hsync,
+--		VGA_B => core_b_s,
+--		VGA_G => core_g_s,
+--		VGA_R => core_r_s,
+--
+--		matrix_out => matrix_out,
+--		matrix_in => matrix_in,
+--		static_keys => static_keys,
+--		pause_key => pause_key,
+--
+--		JOY1_n => i_Joy_A,
+--		JOY2_n => i_Joy_B,
+--		
+--		AUDIO_L => lsound_s,
+--		AUDIO_R => rsound_s,
+--
+--		SDRAM_REQUEST => SDRAM_REQUEST,
+--		SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
+--		SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,
+--		SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,
+--		SDRAM_ADDR => SDRAM_ADDR,
+--		SDRAM_DO => SDRAM_DO,
+--		SDRAM_DI => SDRAM_DI,
+--		SDRAM_WIDTH_8bit_ACCESS => SDRAM_WIDTH_8bit_ACCESS,
+--		SDRAM_WIDTH_16bit_ACCESS => SDRAM_WIDTH_16bit_ACCESS,
+--		SDRAM_WIDTH_32bit_ACCESS => SDRAM_WIDTH_32bit_ACCESS,
+--
+--		SIO_RXD => i_RS232_RXD,
+--		SIO_TXD => o_RS232_TXD,
+--		SIO_COMMAND_TX => o_RS232_RTS,
+--
+--		ram_select => ram_select,
+--		rom_select => rom_select,
+--
+--		halt => i_Halt_Core
+--	);
+
   ----------------------------------------------------------
   -- KEYBOARD MAPPER
   ----------------------------------------------------------
