Index: aeon_lite/Aeon.prj
===================================================================
--- aeon_lite/Aeon.prj	(nonexistent)
+++ aeon_lite/Aeon.prj	(revision 149)
@@ -0,0 +1,58 @@
+address_decoder.vhdl
+antic_counter.vhdl
+antic_dma_clock.vhdl
+antic.vhdl
+complete_address_decoder.vhdl
+cpu_65xx_e.vhd
+cpu_65xx_a.vhd
+cpu_6510.vhd
+cpu.vhd
+delay_line.vhdl
+enable_divider.vhdl
+generic_ram_infer.vhdl
+gtia_palette.vhdl
+gtia_player.vhdl
+gtia_priority.vhdl
+gtia.vhdl
+irq_glue.vhdl
+pia.vhdl
+pokey_countdown_timer.vhdl
+pokey_keyboard_scanner.vhdl
+pokey_mixer.vhdl
+pokey_noise_filter.vhdl
+pokey.vhdl
+pokey_poly_17_9.vhdl
+pokey_poly_4.vhdl
+pokey_poly_5.vhdl
+reg_file.vhdl
+shared_enable.vhdl
+simple_counter.vhdl
+synchronizer.vhdl
+syncreset_enable_divider.vhd
+wide_delay_line.vhdl
+basic.vhdl
+os16.vhdl
+os2.vhdl
+os8.vhdl
+os16_loop.vhdl
+internalromram.vhd
+covox.vhd
+ps2_keyboard.vhdl
+ps2_to_atari800.vhdl
+atari800core.vhd
+atari800core_simple_sdram.vhd
+dac.vhd
+nes_gamepad.vhd
+sram_statemachine.vhd
+zpu_rom.vhdl
+pll.xco
+pll.xise
+scandouble_ram_infer.vhdl
+scandoubler.vhdl
+spi_master.vhd
+zpupkg.vhd
+zpu_config_regs.vhdl
+zpu_glue.vhdl
+zpu_core.vhd
+zpucore.vhd
+atari.vhd
Index: aeon_lite/Aeon.scr
===================================================================
--- aeon_lite/Aeon.scr	(nonexistent)
+++ aeon_lite/Aeon.scr	(revision 149)
@@ -0,0 +1,10 @@
+run
+-ifn Aeon.prj
+-ifmt VHDL
+-ofn Aeon.ngc
+-ofmt NGC
+-p XC3S1600E-FG320-4
+-opt_mode Area
+-opt_level 1
+-keep_hierarchy yes
+-top ATARI
Index: aeon_lite/Aeon.ucf
===================================================================
--- aeon_lite/Aeon.ucf	(nonexistent)
+++ aeon_lite/Aeon.ucf	(revision 149)
@@ -0,0 +1,124 @@
+# 50NHz Clock
+NET "CLK_50"      LOC = P123  |  IOSTANDARD = LVTTL;
+NET "CLK_50"      TNM_NET = "CLK_50";
+TIMESPEC TS_CLK_50 = PERIOD "CLK_50" 50 MHz HIGH 50 %;
+
+# VGA
+NET "VGA_R[3]"    LOC = P83   |  IOSTANDARD = LVTTL;
+NET "VGA_R[2]"    LOC = P82   |  IOSTANDARD = LVTTL;
+NET "VGA_R[1]"    LOC = P81   |  IOSTANDARD = LVTTL;
+NET "VGA_R[0]"    LOC = P80   |  IOSTANDARD = LVTTL;
+NET "VGA_G[3]"    LOC = P79   |  IOSTANDARD = LVTTL;
+NET "VGA_G[2]"    LOC = P78   |  IOSTANDARD = LVTTL;
+NET "VGA_G[1]"    LOC = P75   |  IOSTANDARD = LVTTL;
+NET "VGA_G[0]"    LOC = P74   |  IOSTANDARD = LVTTL;
+NET "VGA_B[3]"    LOC = P67   |  IOSTANDARD = LVTTL;
+NET "VGA_B[2]"    LOC = P66   |  IOSTANDARD = LVTTL;
+NET "VGA_B[1]"    LOC = P64   |  IOSTANDARD = LVTTL;
+NET "VGA_B[0]"    LOC = P62   |  IOSTANDARD = LVTTL;
+NET "VGA_VSYNC"   LOC = P61   |  IOSTANDARD = LVTTL;
+NET "VGA_HSYNC"   LOC = P59   |  IOSTANDARD = LVTTL;
+
+#NET "BTN_RST"     LOC = P114  |  IOSTANDARD = LVTTL;
+#NET "BTN_NMI"     LOC = P115  |  IOSTANDARD = LVTTL;
+
+# Sound
+NET "SOUND_L"     LOC = P84   |  IOSTANDARD = LVTTL;
+NET "SOUND_R"     LOC = P85   |  IOSTANDARD = LVTTL;
+
+# SPI Communication
+#NET "COMM_CSA"    LOC = P69   |  IOSTANDARD = LVTTL;
+#NET "COMM_CSD"    LOC = P60   |  IOSTANDARD = LVTTL;
+#NET "COMM_MISO"   LOC = P50   |  IOSTANDARD = LVTTL;
+#NET "COMM_MOSI"   LOC = P65   |  IOSTANDARD = LVTTL;
+#NET "COMM_SCK"    LOC = P70   |  IOSTANDARD = LVTTL   | CLOCK_DEDICATED_ROUTE = FALSE;
+#NET "COMM_RDY"    LOC = P39   |  IOSTANDARD = LVTTL;
+
+# SD-Card & SPI-Flash
+NET "SD_MOSI"     LOC = P41   |  IOSTANDARD = LVTTL;
+NET "SD_MISO"     LOC = P38   |  IOSTANDARD = LVTTL;
+NET "SD_SCK"      LOC = P40   |  IOSTANDARD = LVTTL;
+NET "SD_CS"       LOC = P44   |  IOSTANDARD = LVTTL;
+#NET "FL_CS"       LOC = P43   |  IOSTANDARD = LVTTL;
+
+# SRAM
+NET "SRAM_A[0]"   LOC = P21   |  IOSTANDARD = LVTTL;
+NET "SRAM_A[1]"   LOC = P17   |  IOSTANDARD = LVTTL;
+NET "SRAM_A[2]"   LOC = P16   |  IOSTANDARD = LVTTL;
+NET "SRAM_A[3]"   LOC = P15   |  IOSTANDARD = LVTTL;
+NET "SRAM_A[4]"   LOC = P14   |  IOSTANDARD = LVTTL;
+NET "SRAM_A[5]"   LOC = P144  |  IOSTANDARD = LVTTL;
+NET "SRAM_A[6]"   LOC = P143  |  IOSTANDARD = LVTTL;
+NET "SRAM_A[7]"   LOC = P142  |  IOSTANDARD = LVTTL;
+NET "SRAM_A[8]"   LOC = P141  |  IOSTANDARD = LVTTL;
+NET "SRAM_A[9]"   LOC = P140  |  IOSTANDARD = LVTTL;
+NET "SRAM_A[10]"  LOC = P124  |  IOSTANDARD = LVTTL;
+NET "SRAM_A[11]"  LOC = P126  |  IOSTANDARD = LVTTL;
+NET "SRAM_A[12]"  LOC = P127  |  IOSTANDARD = LVTTL;
+NET "SRAM_A[13]"  LOC = P131  |  IOSTANDARD = LVTTL;
+NET "SRAM_A[14]"  LOC = P132  |  IOSTANDARD = LVTTL;
+NET "SRAM_A[15]"  LOC = P32   |  IOSTANDARD = LVTTL;
+NET "SRAM_A[16]"  LOC = P33   |  IOSTANDARD = LVTTL;
+NET "SRAM_A[17]"  LOC = P34   |  IOSTANDARD = LVTTL;
+#NET "SRAM_A[18]"  LOC = P133  |  IOSTANDARD = LVTTL;
+NET "SRAM_D[0]"   LOC = P11   |  IOSTANDARD = LVTTL;
+NET "SRAM_D[1]"   LOC = P10   |  IOSTANDARD = LVTTL;
+NET "SRAM_D[2]"   LOC = P9    |  IOSTANDARD = LVTTL;
+NET "SRAM_D[3]"   LOC = P8    |  IOSTANDARD = LVTTL;
+NET "SRAM_D[4]"   LOC = P7    |  IOSTANDARD = LVTTL;
+NET "SRAM_D[5]"   LOC = P6    |  IOSTANDARD = LVTTL;
+NET "SRAM_D[6]"   LOC = P5    |  IOSTANDARD = LVTTL;
+NET "SRAM_D[7]"   LOC = P2    |  IOSTANDARD = LVTTL;
+NET "SRAM_D[8]"   LOC = P134  |  IOSTANDARD = LVTTL;
+NET "SRAM_D[9]"   LOC = P137  |  IOSTANDARD = LVTTL;
+NET "SRAM_D[10]"  LOC = P138  |  IOSTANDARD = LVTTL;
+NET "SRAM_D[11]"  LOC = P139  |  IOSTANDARD = LVTTL;
+NET "SRAM_D[12]"  LOC = P22   |  IOSTANDARD = LVTTL;
+NET "SRAM_D[13]"  LOC = P23   |  IOSTANDARD = LVTTL;
+NET "SRAM_D[14]"  LOC = P24   |  IOSTANDARD = LVTTL;
+NET "SRAM_D[15]"  LOC = P26   |  IOSTANDARD = LVTTL;
+NET "SRAM_CE0"    LOC = P12   |  IOSTANDARD = LVTTL;
+NET "SRAM_CE1"    LOC = P35   |  IOSTANDARD = LVTTL;
+NET "SRAM_LB"     LOC = P27   |  IOSTANDARD = LVTTL;
+NET "SRAM_OE"     LOC = P30   |  IOSTANDARD = LVTTL;
+NET "SRAM_UB"     LOC = P29   |  IOSTANDARD = LVTTL;
+NET "SRAM_WE"     LOC = P1    |  IOSTANDARD = LVTTL;
+
+# Gamepads
+NET "JOY_LOAD"    LOC = P118  |  IOSTANDARD = LVTTL;
+NET "JOY_CLK"     LOC = P119  |  IOSTANDARD = LVTTL;
+NET "JOY_DATA0"   LOC = P120  |  IOSTANDARD = LVTTL;
+NET "JOY_DATA1"   LOC = P121  |  IOSTANDARD = LVTTL;
+
+# Keyboard & Mouse
+NET "KB_CLK"      LOC = P58   |  IOSTANDARD = LVTTL;
+NET "KB_DAT"      LOC = P57   |  IOSTANDARD = LVTTL;
+#NET "MOUSE_CLK"   LOC = P55   |  IOSTANDARD = LVTTL;
+#NET "MOUSE_DATA"  LOC = P56   |  IOSTANDARD = LVTTL;
+
+##############################################################
+#NET "IO[0]"       LOC = P117  |  IOSTANDARD = LVTTL;
+#NET "IO[1]"       LOC = P116  |  IOSTANDARD = LVTTL;
+#NET "IO[2]"       LOC = P115  |  IOSTANDARD = LVTTL;
+#NET "IO[3]"       LOC = P114  |  IOSTANDARD = LVTTL;
+#NET "IO[4]"       LOC = P112  |  IOSTANDARD = LVTTL;
+#NET "IO[5]"       LOC = P111  |  IOSTANDARD = LVTTL;
+#NET "IO[6]"       LOC = P105  |  IOSTANDARD = LVTTL;
+#NET "IO[7]"       LOC = P104  |  IOSTANDARD = LVTTL;
+#NET "IO[8]"       LOC = P102  |  IOSTANDARD = LVTTL;
+#NET "IO[9]"       LOC = P101  |  IOSTANDARD = LVTTL;
+#NET "IO[10]"      LOC = P100  |  IOSTANDARD = LVTTL;
+#NET "IO[11]"      LOC = P99   |  IOSTANDARD = LVTTL;
+#NET "IO[12]"      LOC = P98   |  IOSTANDARD = LVTTL;
+#NET "IO[13]"      LOC = P97   |  IOSTANDARD = LVTTL;
+#NET "IO[14]"      LOC = P95   |  IOSTANDARD = LVTTL;
+#NET "IO[15]"      LOC = P94   |  IOSTANDARD = LVTTL;
+#NET "IO[16]"      LOC = P93   |  IOSTANDARD = LVTTL;
+#NET "IO[17]"      LOC = P92   |  IOSTANDARD = LVTTL;
+#NET "IO[18]"      LOC = P88   |  IOSTANDARD = LVTTL;
+#NET "IO[19]"      LOC = P87   |  IOSTANDARD = LVTTL;
+#NET "COMM[6]"     LOC = P45   |  IOSTANDARD = LVTTL;
+#NET "COMM[7]"     LOC = P44   |  IOSTANDARD = LVTTL;
+#NET "COMM[8]"     LOC = P43   |  IOSTANDARD = LVTTL;
+#NET "COMM[9]"     LOC = P41   |  IOSTANDARD = LVTTL;
+#NET "COMM[10]"    LOC = P40   |  IOSTANDARD = LVTTL;
Index: aeon_lite/Aeon.ut
===================================================================
--- aeon_lite/Aeon.ut	(nonexistent)
+++ aeon_lite/Aeon.ut	(revision 149)
@@ -0,0 +1,8 @@
+-g DonePin:PULLUP
+-g TdoPin:PULLNONE
+-g M0Pin:PULLUP
+-g M1Pin:PULLUP
+-g M2Pin:PULLUP
+-g StartUpClk:CCLK
+-g DriveDone:Yes
+-g Binary:Yes
Index: aeon_lite/atari.vhd
===================================================================
--- aeon_lite/atari.vhd	(nonexistent)
+++ aeon_lite/atari.vhd	(revision 149)
@@ -0,0 +1,423 @@
+---------------------------------------------------------------------------
+-- Atari800-Core wrapper
+---------------------------------------------------------------------------
+-- This file is a part of "Aeon Lite" project
+-- Dmitriy Schapotschkin aka ILoveSpeccy '2014
+-- ilovespeccy@speccyland.net
+-- Project homepage: www.speccyland.net
+---------------------------------------------------------------------------
+
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+
+-- New Files:
+-- DAC.VHD                 - Delta-Sigma-DAC from Xilinx Appnotes
+-- NES-GAMEPAD.VHD         - NES-Gamepad controller
+-- SRAM-STATEMACHINE.VHD   - SRAM (2 x 256KB x 16bit) Controller
+
+-- Changed Files:
+-- PS2_TO_ATARI800.VHD     - Added PS2_KEYS Output
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity ATARI is
+port (
+   CLK_50         : in    std_logic;
+
+   SRAM_A         : out   std_logic_vector(17 downto 0);
+   SRAM_D         : inout std_logic_vector(15 downto 0);
+   SRAM_WE        : out   std_logic;
+   SRAM_OE        : out   std_logic;
+   SRAM_UB        : out   std_logic;
+   SRAM_LB        : out   std_logic;
+   SRAM_CE0       : out   std_logic; 
+   SRAM_CE1       : out   std_logic; 
+
+   KB_CLK         : in    std_logic;
+   KB_DAT         : in    std_logic;
+
+   JOY_CLK        : out   std_logic;
+   JOY_LOAD       : out   std_logic;
+   JOY_DATA0      : in    std_logic;
+   JOY_DATA1      : in    std_logic;
+   
+   SD_MOSI        : out   std_logic;
+   SD_MISO        : in    std_logic;
+   SD_SCK         : out   std_logic;
+   SD_CS          : out   std_logic; 
+
+   SOUND_L        : out    std_logic;
+   SOUND_R        : out    std_logic;
+
+   VGA_R          : out   std_logic_vector(3 downto 0);
+   VGA_G          : out   std_logic_vector(3 downto 0);
+   VGA_B          : out   std_logic_vector(3 downto 0);
+   VGA_HSYNC      : out   std_logic;
+   VGA_VSYNC      : out   std_logic );
+end ATARI;
+
+architecture rtl of ATARI is
+
+   signal CLK                 : std_logic;
+   signal LOCKED              : std_logic;
+   signal RESET_N             : std_logic;
+   
+   -- Pokey Keyboard
+   signal KEYBOARD_SCAN       : std_logic_vector(5 downto 0);
+   signal KEYBOARD_RESPONSE   : std_logic_vector(1 downto 0);
+
+   -- GTIA Consol Keys
+   signal CONSOL_START        : std_logic;
+   signal CONSOL_SELECT       : std_logic;
+   signal CONSOL_OPTION       : std_logic;
+   signal FKEYS               : std_logic_vector(11 downto 0); 
+   signal PS2_KEYS            : std_logic_vector(511 downto 0);
+   
+   -- Gamepads
+   signal GAMEPAD0            : std_logic_vector(7 downto 0);
+   signal GAMEPAD1            : std_logic_vector(7 downto 0);
+   signal JOY1_n              : std_logic_vector(4 downto 0);
+   signal JOY2_n              : std_logic_vector(4 downto 0);
+
+   -- Video
+   signal VIDEO_R             : std_logic_vector(7 downto 0);
+   signal VIDEO_G             : std_logic_vector(7 downto 0);
+   signal VIDEO_B             : std_logic_vector(7 downto 0);
+   signal VIDEO_VS            : std_logic;
+   signal VIDEO_HS            : std_logic;
+
+   signal PAL                 : std_logic := '0';
+   signal VGA                 : std_logic := '1';
+   signal SCANLINES           : std_logic := '0';
+
+   -- Scandoubler
+   signal SCANDOUBLE_CLK      : std_logic;
+   signal HALF_SCANDOUBLE_ENABLE_REG : std_logic;
+	signal HALF_SCANDOUBLE_ENABLE_NEXT : std_logic;
+
+   -- Audio
+   signal AUDIO_L_PCM         : std_logic_vector(15 downto 0);
+   signal AUDIO_R_PCM         : std_logic_vector(15 downto 0); 
+
+   -- SDRAM (SRAM)
+   signal SDRAM_REQUEST       : std_logic;
+   signal SDRAM_REQUEST_COMPLETE : std_logic;
+   signal SDRAM_WRITE_ENABLE  : std_logic;
+   signal SDRAM_ADDR          : std_logic_vector(22 DOWNTO 0);
+   signal SDRAM_DO            : std_logic_vector(31 DOWNTO 0);
+   signal SDRAM_DI            : std_logic_vector(31 DOWNTO 0);
+   signal SDRAM_WIDTH_8BIT_ACCESS : std_logic;
+   signal SDRAM_WIDTH_16BIT_ACCESS : std_logic;
+   signal SDRAM_WIDTH_32BIT_ACCESS : std_logic; 
+   
+   -- DMA/Virtual Drive
+   signal DMA_ADDR_FETCH      : std_logic_vector(23 downto 0);
+   signal DMA_WRITE_DATA      : std_logic_vector(31 downto 0);
+   signal DMA_FETCH           : std_logic;
+   signal DMA_32BIT_WRITE_ENABLE : std_logic;
+   signal DMA_16BIT_WRITE_ENABLE : std_logic;
+   signal DMA_8BIT_WRITE_ENABLE : std_logic;
+   signal DMA_READ_ENABLE     : std_logic;
+   signal DMA_MEMORY_READY    : std_logic;
+   signal DMA_MEMORY_DATA     : std_logic_vector(31 downto 0);
+
+   signal ZPU_ADDR_ROM        : std_logic_vector(15 downto 0);
+   signal ZPU_ROM_DATA        : std_logic_vector(31 downto 0);
+   signal ZPU_OUT1            : std_logic_vector(31 downto 0);
+
+   -- System Control from ZPU
+   signal ZPU_POKEY_ENABLE    : std_logic;
+
+   signal ZPU_SIO_TXD         : std_logic;
+   signal ZPU_SIO_RXD         : std_logic;
+   signal ZPU_SIO_COMMAND     : std_logic;
+
+   alias  PAUSE_ATARI         : std_logic                    is ZPU_OUT1(0);
+   alias  RESET_ATARI         : std_logic                    is ZPU_OUT1(1);
+   alias  SPEED_6502          : std_logic_vector(5 downto 0) is ZPU_OUT1(7 downto 2);
+   alias  RAM_SELECT          : std_logic_vector(2 downto 0) is ZPU_OUT1(10 downto 8);
+   alias  ROM_SELECT          : std_logic_vector(5 downto 0) is ZPU_OUT1(16 downto 11);
+
+   signal reset_n_inc_zpu : std_logic;
+   signal zpu_in1 : std_logic_vector(31 downto 0);
+
+begin 
+
+u_PLL : entity work.PLL
+port map (
+   CLKIN                      => CLK_50,
+   CLKOUT                     => CLK,
+   CLKOUT2                    => SCANDOUBLE_CLK,
+   LOCKED                     => LOCKED );
+   
+u_DAC_L : entity work.dac
+port map (
+   CLK_I                      => CLK,
+   RES_N_I                    => RESET_N,
+   DAC_I                      => AUDIO_L_PCM,
+   DAC_O                      => SOUND_L );
+
+u_DAC_R : entity work.dac
+port map (
+   CLK_I                      => CLK,
+   RES_N_I                    => RESET_N,
+   DAC_I                      => AUDIO_R_PCM,
+   DAC_O                      => SOUND_R );
+
+u_KEYBOARD : entity work.ps2_to_atari800
+port map(
+   CLK                        => CLK,
+   RESET_N                    => RESET_N,
+   PS2_CLK                    => KB_CLK,
+   PS2_DAT                    => KB_DAT,
+   KEYBOARD_SCAN              => KEYBOARD_SCAN,
+   KEYBOARD_RESPONSE          => KEYBOARD_RESPONSE,
+   CONSOL_START               => CONSOL_START,
+   CONSOL_SELECT              => CONSOL_SELECT,
+   CONSOL_OPTION              => CONSOL_OPTION,
+   FKEYS                      => FKEYS,
+   PS2_KEYS                   => PS2_KEYS );
+
+u_JOYSTICKS : entity work.nes_gamepad
+port map( 
+   CLK                        => CLK,
+   RESET                      => not RESET_N,
+   JOY_CLK                    => JOY_CLK,
+   JOY_LOAD                   => JOY_LOAD,
+   JOY_DATA0                  => JOY_DATA0,
+   JOY_DATA1                  => JOY_DATA1,
+   JOY0_BUTTONS               => GAMEPAD0,
+   JOY1_BUTTONS               => GAMEPAD1,
+   JOY0_CONNECTED             => OPEN,
+   JOY1_CONNECTED             => OPEN );
+
+reset_n_inc_zpu <= RESET_N and not (RESET_ATARI);
+u_ATARI800_CORE : entity work.atari800core_simple_sdram
+generic map(
+   CYCLE_LENGTH               => 16,
+   INTERNAL_ROM               => 0,
+   INTERNAL_RAM               => 0,
+   PALETTE                    => 0,
+   VIDEO_BITS                 => 8,
+   LOW_MEMORY                 => 1 )
+port map(
+   CLK                        => CLK,
+   RESET_N                    => reset_n_inc_zpu,
+
+   VIDEO_VS                   => VIDEO_VS,
+   VIDEO_HS                   => VIDEO_HS,
+   VIDEO_B                    => VIDEO_B,
+   VIDEO_G                    => VIDEO_G,
+   VIDEO_R                    => VIDEO_R,
+   VIDEO_BLANK                => OPEN,
+   VIDEO_BURST                => OPEN,
+   VIDEO_START_OF_FIELD       => OPEN,
+   VIDEO_ODD_LINE             => OPEN,
+
+   AUDIO_L                    => AUDIO_L_PCM,
+   AUDIO_R                    => AUDIO_R_PCM,
+   
+   JOY1_n                     => JOY1_n, 
+   JOY2_n                     => JOY2_n, 
+
+   KEYBOARD_RESPONSE          => KEYBOARD_RESPONSE,
+   KEYBOARD_SCAN              => KEYBOARD_SCAN,
+
+   SIO_COMMAND                => ZPU_SIO_COMMAND,
+   SIO_RXD                    => ZPU_SIO_TXD,
+   SIO_TXD                    => ZPU_SIO_RXD,
+
+   CONSOL_OPTION              => CONSOL_OPTION,
+   CONSOL_SELECT              => CONSOL_SELECT,
+   CONSOL_START               => CONSOL_START,
+
+   SDRAM_REQUEST              => SDRAM_REQUEST,
+   SDRAM_REQUEST_COMPLETE     => SDRAM_REQUEST_COMPLETE,
+   SDRAM_READ_ENABLE          => OPEN,
+   SDRAM_WRITE_ENABLE         => SDRAM_WRITE_ENABLE,
+   SDRAM_ADDR                 => SDRAM_ADDR,
+   SDRAM_DO                   => SDRAM_DO,
+   SDRAM_DI                   => SDRAM_DI,
+   SDRAM_32BIT_WRITE_ENABLE   => SDRAM_WIDTH_32BIT_ACCESS,
+   SDRAM_16BIT_WRITE_ENABLE   => SDRAM_WIDTH_16BIT_ACCESS,
+   SDRAM_8BIT_WRITE_ENABLE    => SDRAM_WIDTH_8BIT_ACCESS,
+   SDRAM_REFRESH              => OPEN,
+
+   DMA_FETCH                  => DMA_FETCH,
+   DMA_READ_ENABLE            => DMA_READ_ENABLE,
+   DMA_32BIT_WRITE_ENABLE     => DMA_32BIT_WRITE_ENABLE,
+   DMA_16BIT_WRITE_ENABLE     => DMA_16BIT_WRITE_ENABLE,
+   DMA_8BIT_WRITE_ENABLE      => DMA_8BIT_WRITE_ENABLE,
+   DMA_ADDR                   => DMA_ADDR_FETCH,
+   DMA_WRITE_DATA             => DMA_WRITE_DATA,
+   MEMORY_READY_DMA           => DMA_MEMORY_READY,
+   DMA_MEMORY_DATA            => DMA_MEMORY_DATA, 
+
+   RAM_SELECT                 => RAM_SELECT,
+   ROM_SELECT                 => ROM_SELECT,
+   PAL                        => PAL,
+   HALT                       => PAUSE_ATARI,
+   THROTTLE_COUNT_6502        => SPEED_6502 );
+
+u_SRAM : entity work.sram_statemachine
+
+port map (
+   CLK                        => CLK,
+   RESET_N                    => reset_n_inc_zpu,
+
+   ADDRESS_IN                 => SDRAM_ADDR,
+   DATA_IN                    => SDRAM_DI,
+   DATA_OUT                   => SDRAM_DO,
+   WRITE_EN                   => SDRAM_WRITE_ENABLE,
+   REQUEST                    => SDRAM_REQUEST,
+   BYTE_ACCESS                => SDRAM_WIDTH_8BIT_ACCESS,
+   WORD_ACCESS                => SDRAM_WIDTH_16BIT_ACCESS,
+   LONGWORD_ACCESS            => SDRAM_WIDTH_32BIT_ACCESS,
+   COMPLETE                   => SDRAM_REQUEST_COMPLETE,
+
+   SRAM_ADDR                  => SRAM_A,
+   SRAM_DQ                    => SRAM_D,
+   SRAM_CE0_N                 => SRAM_CE0,
+   SRAM_CE1_N                 => SRAM_CE1,
+   SRAM_OE_N                  => SRAM_OE,
+   SRAM_WE_N                  => SRAM_WE,
+   SRAM_UB_N                  => SRAM_UB,
+   SRAM_LB_N                  => SRAM_LB );
+
+u_ZPU : entity work.zpucore
+generic map (
+   PLATFORM                   => 1,
+   SPI_CLOCK_DIV              => 1 )
+port map (
+   CLK                        => CLK,
+   RESET_N                    => RESET_N,
+
+   ZPU_ADDR_FETCH             => DMA_ADDR_FETCH,
+   ZPU_DATA_OUT               => DMA_WRITE_DATA,
+   ZPU_FETCH                  => DMA_FETCH,
+   ZPU_32BIT_WRITE_ENABLE     => DMA_32BIT_WRITE_ENABLE,
+   ZPU_16BIT_WRITE_ENABLE     => DMA_16BIT_WRITE_ENABLE,
+   ZPU_8BIT_WRITE_ENABLE      => DMA_8BIT_WRITE_ENABLE,
+   ZPU_READ_ENABLE            => DMA_READ_ENABLE,
+   ZPU_MEMORY_READY           => DMA_MEMORY_READY,
+   ZPU_MEMORY_DATA            => DMA_MEMORY_DATA, 
+
+   ZPU_ADDR_ROM               => ZPU_ADDR_ROM,
+   ZPU_ROM_DATA               => ZPU_ROM_DATA,
+
+   ZPU_SD_DAT0                => SD_MISO,
+   ZPU_SD_CLK                 => SD_SCK,
+   ZPU_SD_CMD                 => SD_MOSI,
+   ZPU_SD_DAT3                => SD_CS,
+
+   ZPU_POKEY_ENABLE           => ZPU_POKEY_ENABLE,
+   ZPU_SIO_TXD                => ZPU_SIO_TXD,
+   ZPU_SIO_RXD                => ZPU_SIO_RXD,
+   ZPU_SIO_COMMAND            => ZPU_SIO_COMMAND,
+
+   ZPU_IN1                    => zpu_in1,
+   ZPU_IN2                    => X"00000000",
+   ZPU_IN3                    => X"00000000",
+   ZPU_IN4                    => X"00000000",
+
+   ZPU_OUT1                   => ZPU_OUT1,
+   ZPU_OUT2                   => OPEN,
+   ZPU_OUT3                   => OPEN,
+   ZPU_OUT4                   => OPEN );
+zpu_in1 <= X"00000" & FKEYS;
+
+u_ZPUROM : entity work.zpu_rom
+port map (
+   CLOCK                      => CLK,
+   ADDRESS                    => ZPU_ADDR_ROM(13 downto 2),
+   Q                          => ZPU_ROM_DATA );
+
+u_ZPUPOKEY : entity work.enable_divider
+generic map (
+   COUNT                      => 16 )
+port map (
+   CLK                        => CLK,
+   RESET_N                    => RESET_N,
+   ENABLE_IN                  => '1',
+   ENABLE_OUT                 => ZPU_POKEY_ENABLE);
+
+-- Scandoubler
+process(SCANDOUBLE_CLK, RESET_N, RESET_ATARI)
+begin
+   if ((RESET_N and not (RESET_ATARI)) = '0') then
+      HALF_SCANDOUBLE_ENABLE_REG <= '0';
+   elsif (SCANDOUBLE_CLK'event and SCANDOUBLE_CLK = '1') then
+      HALF_SCANDOUBLE_ENABLE_REG <= HALF_SCANDOUBLE_ENABLE_NEXT;
+   end if;
+end process;
+
+HALF_SCANDOUBLE_ENABLE_NEXT <= not(HALF_SCANDOUBLE_ENABLE_REG);
+
+u_SCANDOUBLER : entity work.scandoubler
+port map (
+   CLK                        => SCANDOUBLE_CLK,
+   RESET_N                    => reset_n_inc_zpu,
+   VGA                        => VGA,
+   COMPOSITE_ON_HSYNC         => not VGA,
+
+   COLOUR_ENABLE              => HALF_SCANDOUBLE_ENABLE_REG,
+   DOUBLED_ENABLE             => VGA,
+   
+   SCANLINES_ON               => SCANLINES,
+			
+   COLOUR_IN                  => VIDEO_B,
+   VSYNC_IN                   => VIDEO_VS,
+   HSYNC_IN                   => VIDEO_HS,
+			
+   R                          => VGA_R,
+   G                          => VGA_G,
+   B                          => VGA_B,
+			
+   VSYNC                      => VGA_VSYNC,
+   HSYNC                      => VGA_HSYNC );
+
+RESET_N <= LOCKED;
+
+-- NES Gamepad 1 & Cursor keys on keyboard
+JOY1_n <= (not GAMEPAD0(7) and not GAMEPAD0(6) and not PS2_KEYS(16#014#)) & 
+                              (not GAMEPAD0(0) and not PS2_KEYS(16#174#)) & 
+                              (not GAMEPAD0(1) and not PS2_KEYS(16#16B#)) & 
+                              (not GAMEPAD0(2) and not PS2_KEYS(16#172#)) & 
+                              (not GAMEPAD0(3) and not PS2_KEYS(16#175#)) ;
+
+-- NES Gamepad 2
+JOY2_n <= (not GAMEPAD1(7) and not GAMEPAD1(6)) & not GAMEPAD1(0) & not GAMEPAD1(1) & not GAMEPAD1(2) & not GAMEPAD1(3);
+
+-- Switch video mode
+-- VGA/TV (Ins)
+process(PS2_KEYS)
+begin
+   if rising_edge(PS2_KEYS(16#170#)) then
+      VGA <= not VGA;
+   end if;
+end process;
+
+-- PAL/NTSC (Home)
+process(PS2_KEYS)
+begin
+   if rising_edge(PS2_KEYS(16#16C#)) then
+      PAL <= not PAL;
+   end if;
+end process;
+
+-- Scanlines on/off (Page Up)
+process(PS2_KEYS)
+begin
+   if rising_edge(PS2_KEYS(16#17D#)) then
+      SCANLINES <= not SCANLINES;
+   end if;
+end process;
+
+end rtl;
Index: aeon_lite/build.sh
===================================================================
--- aeon_lite/build.sh	(nonexistent)
+++ aeon_lite/build.sh	(revision 149)
@@ -0,0 +1,51 @@
+#!/bin/bash
+
+name=Aeon
+args=$@
+shift
+
+. /home/markw/fpga/xilinx/14.7/ISE_DS/settings64.sh
+
+mkdir -p build
+pushd build
+
+# copy source files
+cp -p ../*.vhd .
+cp -p ../*.vhdl .
+cp -p ../pll/* .
+cp -p ../../common/a8core/*.vhd .
+cp -p ../../common/a8core/*.vhdl .
+cp -p ../../common/components/*.vhd .
+cp -p ../../common/components/*.vhdl .
+cp -p ../../common/zpu/*.vhd .
+cp -p ../../common/zpu/*.vhdl .
+
+cp -p ../$name.ucf .
+cp -p ../$name.ut .
+cp -p ../$name.scr .
+cp -p ../$name.prj .
+
+if [ "${args[0]}" != "-xil" ]; then
+
+    echo "Starting Synthesis..."
+    xst -ifn $name.scr -ofn $name.srp || exit 1
+
+fi
+
+echo "Starting Translate..."
+ngdbuild -nt on -uc $name.ucf $name.ngc $name.ngd || exit 1
+
+echo "Starting Map..."
+map -pr b $name.ngd -o $name.ncd $name.pcf || exit 1
+
+echo "Starting Place & Route..."
+par -w -ol std $name.ncd $name.ncd $name.pcf || exit 1
+
+echo "Starting Timing Analysis..."
+trce -v 10 -o $name.twr $name.ncd $name.pcf || exit 1
+
+echo "Starting Bitgen..."
+bitgen $name.ncd $name.bit -w -f $name.ut || exit 1
+
+popd
+cp build/$name.bin core/atari800.bin

Property changes on: aeon_lite/build.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: aeon_lite/dac.vhd
===================================================================
--- aeon_lite/dac.vhd	(nonexistent)
+++ aeon_lite/dac.vhd	(revision 149)
@@ -0,0 +1,53 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity dac is
+
+  generic (
+    msbi_g : integer := 15
+  );
+  port (
+    clk_i   : in  std_logic;
+    res_n_i : in  std_logic;
+    dac_i   : in  std_logic_vector(msbi_g downto 0);
+    dac_o   : out std_logic
+  );
+
+end dac;
+
+library ieee;
+use ieee.numeric_std.all;
+
+architecture rtl of dac is
+
+  signal DACout_q      : std_logic;
+  signal DeltaAdder_s,
+         SigmaAdder_s,
+         SigmaLatch_q,
+         DeltaB_s      : unsigned(msbi_g+2 downto 0);
+
+begin
+
+  DeltaB_s(msbi_g+2 downto msbi_g+1) <= SigmaLatch_q(msbi_g+2) &
+                                        SigmaLatch_q(msbi_g+2);
+  DeltaB_s(msbi_g   downto        0) <= (others => '0');
+
+  DeltaAdder_s <= unsigned('0' & '0' & dac_i) + DeltaB_s;
+
+  SigmaAdder_s <= DeltaAdder_s + SigmaLatch_q;
+
+  seq: process (clk_i, res_n_i)
+  begin
+    if res_n_i = '0' then
+      SigmaLatch_q <= to_unsigned(2**(msbi_g+1), SigmaLatch_q'length);
+      DACout_q     <= '0';
+
+    elsif clk_i'event and clk_i = '1' then
+      SigmaLatch_q <= SigmaAdder_s;
+      DACout_q     <= SigmaLatch_q(msbi_g+2);
+    end if;
+  end process seq;
+
+  dac_o <= DACout_q;
+
+end rtl;
Index: aeon_lite/pll/pll/simulation/functional/simulate_mti.do
===================================================================
--- aeon_lite/pll/pll/simulation/functional/simulate_mti.do	(nonexistent)
+++ aeon_lite/pll/pll/simulation/functional/simulate_mti.do	(revision 149)
@@ -0,0 +1,65 @@
+# file: simulate_mti.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vcom -work work ../../../pll.vhd
+vcom -work work ../../example_design/pll_exdes.vhd
+vcom -work work ../pll_tb.vhd
+
+# run the simulation
+vsim  -t ps -voptargs="+acc" -L unisim work.pll_tb 
+do wave.do
+when {end_of_sim} {echo "End of Simulation"; stop} 
+log pll_tb/dut/counter
+log -r /*
+run 50000ns
Index: aeon_lite/pll/pll/simulation/functional/simulate_vcs.sh
===================================================================
--- aeon_lite/pll/pll/simulation/functional/simulate_vcs.sh	(nonexistent)
+++ aeon_lite/pll/pll/simulation/functional/simulate_vcs.sh	(revision 149)
@@ -0,0 +1,70 @@
+#!/bin/sh
+# file: simulate_vcs.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# remove old files
+rm -rf simv* csrc DVEfiles AN.DB 
+
+# compile all of the files
+# Note that -sverilog is not strictly required- You can
+#   remove the -sverilog if you change the type of the
+#   localparam for the periods in the testbench file to 
+#   [63:0] from time
+vhdlan -xlrm ../../../pll.vhd \
+      ../../example_design/pll_exdes.vhd \
+      ../pll_tb.vhd
+
+# prepare the simulation 
+vcs +vcs+lic+wait -xlrm -debug pll_tb
+
+# run the simulation
+./simv -xlrm -ucli -i ucli_commands.key
+
+# launch the viewer
+#dve -vpd vcdplus.vpd -session vcs_session.tcl
Index: aeon_lite/pll/pll/simulation/pll_tb.vhd
===================================================================
--- aeon_lite/pll/pll/simulation/pll_tb.vhd	(nonexistent)
+++ aeon_lite/pll/pll/simulation/pll_tb.vhd	(revision 149)
@@ -0,0 +1,191 @@
+-- file: pll_tb.vhd
+-- 
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+
+------------------------------------------------------------------------------
+-- Clocking wizard demonstration testbench
+------------------------------------------------------------------------------
+-- This demonstration testbench instantiates the example design for the 
+--   clocking wizard. Input clocks are toggled, which cause the clocking
+--   network to lock and the counters to increment.
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+
+library std;
+use std.textio.all;
+
+library work;
+use work.all;
+
+entity pll_tb is
+end pll_tb;
+
+architecture test of pll_tb is
+
+  -- Clock to Q delay of 100 ps
+  constant TCQ               : time := 100 ps;
+  -- timescale is 1ps
+  constant ONE_NS      : time := 1 ns;
+  -- how many cycles to run
+  constant COUNT_PHASE : integer := 1024 + 1;
+
+
+  -- we'll be using the period in many locations
+  constant PER1        : time := 20.000 ns;
+
+
+  -- Declare the input clock signals
+  signal CLK_IN1       : std_logic := '1';
+  -- The high bits of the sampling counters
+  signal COUNT         : std_logic_vector(2 downto 1);
+  -- Status and control signals
+  signal LOCKED        : std_logic;
+  signal COUNTER_RESET : std_logic := '0';
+--  signal defined to stop mti simulation without severity failure in the report
+  signal end_of_sim : std_logic := '0';
+  signal CLK_OUT : std_logic_vector(2 downto 1);
+--Freq Check using the M & D values setting and actual Frequency generated
+
+component pll_exdes
+generic (
+  TCQ               : in time := 100 ps);
+port
+ (-- Clock in ports
+  CLK_IN1           : in  std_logic;
+  -- Reset that only drives logic in example design
+  COUNTER_RESET     : in  std_logic;
+  CLK_OUT           : out std_logic_vector(2 downto 1) ;
+  -- High bits of counters driven by clocks
+  COUNT             : out std_logic_vector(2 downto 1);
+  -- Status and control signals
+  LOCKED            : out std_logic
+ );
+end component;
+
+begin
+
+  -- Input clock generation
+  --------------------------------------
+  process begin
+    CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
+  end process;
+
+  -- Test sequence
+  process 
+
+    procedure simtimeprint is
+      variable outline : line;
+    begin
+      write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
+      write(outline, NOW/PER1);
+      write(outline, string'(" ns"));
+      writeline(output,outline);
+    end simtimeprint;
+
+    procedure simfreqprint (period : time; clk_num : integer) is
+       variable outputline : LINE;
+       variable str1 : string(1 to 16);
+       variable str2 : integer;
+       variable str3 : string(1 to 2);
+       variable str4 : integer;
+       variable str5 : string(1 to 4);
+    begin
+       str1 := "Freq of CLK_OUT(";
+       str2 :=  clk_num;
+       str3 :=  ") ";
+       str4 :=  1000000 ps/period ;
+       str5 :=  " MHz" ;
+       write(outputline, str1 );
+       write(outputline, str2);
+       write(outputline, str3);
+       write(outputline, str4);
+       write(outputline, str5);
+       writeline(output, outputline);
+    end simfreqprint;
+
+  begin
+    wait until LOCKED = '1';
+    COUNTER_RESET <= '1';
+    wait for (PER1*20);
+    COUNTER_RESET <= '0';
+    wait for (PER1*COUNT_PHASE);
+
+
+    simtimeprint;
+    end_of_sim <= '1';
+    wait for 1 ps;
+    report "Simulation Stopped." severity failure;
+    wait;
+  end process;
+
+  -- Instantiation of the example design containing the clock
+  --    network and sampling counters
+  -----------------------------------------------------------
+  dut : pll_exdes
+  generic map (
+    TCQ                => TCQ)
+  port map
+   (-- Clock in ports
+    CLK_IN1            => CLK_IN1,
+    -- Reset for logic in example design
+    COUNTER_RESET      => COUNTER_RESET,
+    CLK_OUT            => CLK_OUT,
+    -- High bits of the counters
+    COUNT              => COUNT,
+    -- Status and control signals
+    LOCKED             => LOCKED);
+
+-- Freq Check 
+
+end test;
Index: aeon_lite/pll/pll/implement/planAhead_rdn.bat
===================================================================
--- aeon_lite/pll/pll/implement/planAhead_rdn.bat	(nonexistent)
+++ aeon_lite/pll/pll/implement/planAhead_rdn.bat	(revision 149)
@@ -0,0 +1,58 @@
+REM file: planAhead_rdn.sh
+REM 
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM 
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM 
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM 
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM 
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM 
+
+REM-----------------------------------------------------------------------------
+REM Script to synthesize and implement the RTL provided for the XADC wizard
+REM-----------------------------------------------------------------------------
+
+del \f results
+mkdir results
+cd results
+
+planAhead -mode batch -source ..\planAhead_rdn.tcl
Index: aeon_lite/pll/pll/implement/planAhead_rdn.tcl
===================================================================
--- aeon_lite/pll/pll/implement/planAhead_rdn.tcl	(nonexistent)
+++ aeon_lite/pll/pll/implement/planAhead_rdn.tcl	(revision 149)
@@ -0,0 +1,69 @@
+# file : planAhead_rdn.tcl
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+set device xc6slx9tqg144-3
+set projName pll
+set design pll
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module pll_exdes
+set_property top pll_exdes [get_property srcset [current_run]]
+add_files -norecurse {../../../pll.vhd}
+add_files -norecurse {../../example_design/pll_exdes.vhd}
+import_files -fileset [get_filesets constrs_1 ] -force -norecurse {../../example_design/pll_exdes.xdc}
+synth_design
+opt_design 
+place_design 
+route_design 
+write_sdf -rename_top_module pll_exdes -file routed.sdf 
+write_vhdl -file routed.vhd
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file report.drc
+write_bitstream -bitgen_options {-g UnconstrainedPins:Allow} -file routed.bit
Index: aeon_lite/pll/pll/implement/xst.scr
===================================================================
--- aeon_lite/pll/pll/implement/xst.scr	(nonexistent)
+++ aeon_lite/pll/pll/implement/xst.scr	(revision 149)
@@ -0,0 +1,9 @@
+run
+-ifmt MIXED
+-top pll_exdes
+-p xc6slx9-tqg144-3
+-ifn xst.prj
+-ofn pll_exdes
+-keep_hierarchy soft 
+-equivalent_register_removal no 
+-max_fanout 65535
Index: aeon_lite/pll/pll/simulation/functional/simulate_isim.bat
===================================================================
--- aeon_lite/pll/pll/simulation/functional/simulate_isim.bat	(nonexistent)
+++ aeon_lite/pll/pll/simulation/functional/simulate_isim.bat	(revision 149)
@@ -0,0 +1,58 @@
+REM file: simulate_isim.bat
+REM  
+REM  (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM  
+REM  This file contains confidential and proprietary information
+REM  of Xilinx, Inc. and is protected under U.S. and
+REM  international copyright and other intellectual property
+REM  laws.
+REM  
+REM  DISCLAIMER
+REM  This disclaimer is not a license and does not grant any
+REM  rights to the materials distributed herewith. Except as
+REM  otherwise provided in a valid license issued to you by
+REM  Xilinx, and to the maximum extent permitted by applicable
+REM  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM  (2) Xilinx shall not be liable (whether in contract or tort,
+REM  including negligence, or under any other theory of
+REM  liability) for any loss or damage of any kind or nature
+REM  related to, arising under or in connection with these
+REM  materials, including for any direct, or any indirect,
+REM  special, incidental, or consequential loss or damage
+REM  (including loss of data, profits, goodwill, or any type of
+REM  loss or damage suffered as a result of any action brought
+REM  by a third party) even if such damage or loss was
+REM  reasonably foreseeable or Xilinx had been advised of the
+REM  possibility of the same.
+REM  
+REM  CRITICAL APPLICATIONS
+REM  Xilinx products are not designed or intended to be fail-
+REM  safe, or for use in any application requiring fail-safe
+REM  performance, such as life-support or safety devices or
+REM  systems, Class III medical devices, nuclear facilities,
+REM  applications related to the deployment of airbags, or any
+REM  other applications that could lead to death, personal
+REM  injury, or severe property or environmental damage
+REM  (individually and collectively, "Critical
+REM  Applications"). Customer assumes the sole risk and
+REM  liability of any use of Xilinx products in Critical
+REM  Applications, subject only to applicable laws and
+REM  regulations governing limitations on product liability.
+REM  
+REM  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM  PART OF THIS FILE AT ALL TIMES.
+REM  
+
+vhpcomp -work work ..\..\..\pll.vhd
+vhpcomp -work work ..\..\example_design\pll_exdes.vhd
+vhpcomp -work work ..\pll_tb.vhd
+
+REM compile the project
+fuse work.pll_tb  -L unisim -o pll_isim.exe
+
+REM run the simulation script
+.\pll_isim.exe -gui -tclbatch simcmds.tcl
Index: aeon_lite/pll/pll/simulation/functional/simulate_mti.bat
===================================================================
--- aeon_lite/pll/pll/simulation/functional/simulate_mti.bat	(nonexistent)
+++ aeon_lite/pll/pll/simulation/functional/simulate_mti.bat	(revision 149)
@@ -0,0 +1,60 @@
+REM file: simulate_mti.bat
+REM  
+REM  (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM  
+REM  This file contains confidential and proprietary information
+REM  of Xilinx, Inc. and is protected under U.S. and
+REM  international copyright and other intellectual property
+REM  laws.
+REM  
+REM  DISCLAIMER
+REM  This disclaimer is not a license and does not grant any
+REM  rights to the materials distributed herewith. Except as
+REM  otherwise provided in a valid license issued to you by
+REM  Xilinx, and to the maximum extent permitted by applicable
+REM  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM  (2) Xilinx shall not be liable (whether in contract or tort,
+REM  including negligence, or under any other theory of
+REM  liability) for any loss or damage of any kind or nature
+REM  related to, arising under or in connection with these
+REM  materials, including for any direct, or any indirect,
+REM  special, incidental, or consequential loss or damage
+REM  (including loss of data, profits, goodwill, or any type of
+REM  loss or damage suffered as a result of any action brought
+REM  by a third party) even if such damage or loss was
+REM  reasonably foreseeable or Xilinx had been advised of the
+REM  possibility of the same.
+REM  
+REM  CRITICAL APPLICATIONS
+REM  Xilinx products are not designed or intended to be fail-
+REM  safe, or for use in any application requiring fail-safe
+REM  performance, such as life-support or safety devices or
+REM  systems, Class III medical devices, nuclear facilities,
+REM  applications related to the deployment of airbags, or any
+REM  other applications that could lead to death, personal
+REM  injury, or severe property or environmental damage
+REM  (individually and collectively, "Critical
+REM  Applications"). Customer assumes the sole risk and
+REM  liability of any use of Xilinx products in Critical
+REM  Applications, subject only to applicable laws and
+REM  regulations governing limitations on product liability.
+REM  
+REM  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM  PART OF THIS FILE AT ALL TIMES.
+REM  
+
+REM set up the working directory
+vlib work
+
+REM compile all of the files
+vcom -work work ..\..\..\pll.vhd
+vcom -work work ..\..\example_design\pll_exdes.vhd
+vcom -work work ..\pll_tb.vhd
+
+REM run the simulation
+vsim -c -t ps -voptargs="+acc" -L secureip -L unisim work.pll_tb 
+
Index: aeon_lite/pll/pll/simulation/functional/simulate_ncsim.sh
===================================================================
--- aeon_lite/pll/pll/simulation/functional/simulate_ncsim.sh	(nonexistent)
+++ aeon_lite/pll/pll/simulation/functional/simulate_ncsim.sh	(revision 149)
@@ -0,0 +1,61 @@
+#/bin/sh
+# file: simulate_ncsim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+mkdir work
+
+# compile all of the files
+ncvhdl -v93 -work work ../../../pll.vhd
+ncvhdl -v93 -work work ../../example_design/pll_exdes.vhd
+ncvhdl -v93 -work work ../pll_tb.vhd
+
+# elaborate and run the simulation
+ncelab -work work -access +wc work.pll_tb 
+ncsim -input  "@database -open -shm nc; probe -create -database nc -all -depth all; probe dut.counter; run 50000ns; exit" work.pll_tb
Index: aeon_lite/pll/pll/simulation/functional/wave.sv
===================================================================
--- aeon_lite/pll/pll/simulation/functional/wave.sv	(nonexistent)
+++ aeon_lite/pll/pll/simulation/functional/wave.sv	(revision 149)
@@ -0,0 +1,119 @@
+# file: wave.sv
+# 
+# (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+# Get the windows set up
+#
+if {[catch {window new WatchList -name "Design Browser 1" -geometry 1054x819+536+322}] != ""} {
+    window geometry "Design Browser 1" 1054x819+536+322
+}
+window target "Design Browser 1" on
+browser using {Design Browser 1}
+browser set \
+    -scope nc::pll_tb
+browser yview see nc::pll_tb
+browser timecontrol set -lock 0
+
+if {[catch {window new WaveWindow -name "Waveform 1" -geometry 1010x600+0+541}] != ""} {
+    window geometry "Waveform 1" 1010x600+0+541
+}
+window target "Waveform 1" on
+waveform using {Waveform 1}
+waveform sidebar visibility partial
+waveform set \
+    -primarycursor TimeA \
+    -signalnames name \
+    -signalwidth 175 \
+    -units ns \
+    -valuewidth 75
+cursor set -using TimeA -time 0
+waveform baseline set -time 0
+waveform xview limits 0 20000n
+
+#
+# Define signal groups
+#
+catch {group new -name {Output clocks} -overlay 0}
+catch {group new -name {Status/control} -overlay 0}
+catch {group new -name {Counters} -overlay 0}
+
+set id [waveform add -signals [list {nc::pll_tb.CLK_IN1}]]
+
+group using {Output clocks}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+    {pll_tb.dut.clk[1]} \
+    {pll_tb.dut.clk[2]} 
+group using {Counters}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+    {pll_tb.dut.counter[1]} \
+    {pll_tb.dut.counter[2]} 
+group using {Status/control}
+group set -overlay 0
+group set -comment {}
+group clear 0 end
+
+group insert \
+   {nc::pll_tb.LOCKED}
+
+
+set id [waveform add -signals [list {nc::pll_tb.COUNT} ]]
+
+set id [waveform add -signals [list {nc::pll_tb.test_phase} ]]
+waveform format $id -radix %a
+
+set groupId [waveform add -groups {{Input clocks}}]
+set groupId [waveform add -groups {{Output clocks}}]
+set groupId [waveform add -groups {{Status/control}}]
+set groupId [waveform add -groups {{Counters}}]
Index: aeon_lite/pll/pll/simulation/timing/sdf_cmd_file
===================================================================
--- aeon_lite/pll/pll/simulation/timing/sdf_cmd_file	(nonexistent)
+++ aeon_lite/pll/pll/simulation/timing/sdf_cmd_file	(revision 149)
@@ -0,0 +1,2 @@
+COMPILED_SDF_FILE = "../../implement/results/routed.sdf.X",
+SCOPE = :dut;
Index: aeon_lite/nes_gamepad.vhd
===================================================================
--- aeon_lite/nes_gamepad.vhd	(nonexistent)
+++ aeon_lite/nes_gamepad.vhd	(revision 149)
@@ -0,0 +1,150 @@
+---------------------------------------------------------------------------
+-- NES-Controller Module
+---------------------------------------------------------------------------
+-- This file is a part of "Aeon Lite" project
+-- Dmitriy Schapotschkin aka ILoveSpeccy '2014
+-- ilovespeccy@speccyland.net
+-- Project homepage: www.speccyland.net
+---------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+------------------
+-- Bit - Button --
+-- (1 = pressed)
+------------------
+--  7     A
+--  6     B
+--  5     Select
+--  4     Start
+--  3     Up
+--  2     Down
+--  1     Left
+--  0     Right
+------------------
+
+entity nes_gamepad is
+generic (
+    CLK_FREQ        : integer   := 25000000;
+    TICK_FREQ       : integer   := 20000 );
+port ( 
+    CLK             : in     std_logic;
+    RESET           : in     std_logic;
+    
+    JOY_CLK         : out    std_logic;
+    JOY_LOAD        : out    std_logic;
+    JOY_DATA0       : in     std_logic;
+    JOY_DATA1       : in     std_logic;
+   
+    JOY0_BUTTONS    : out    std_logic_vector(7 downto 0);
+    JOY1_BUTTONS    : out    std_logic_vector(7 downto 0);
+    
+    JOY0_CONNECTED  : out    std_logic; -- 1 when gamepad connected
+    JOY1_CONNECTED  : out    std_logic );
+end nes_gamepad;
+
+architecture RTL of nes_gamepad is
+
+    signal TICK     : integer range 0 to (CLK_FREQ / TICK_FREQ);
+    signal STATE    : integer range 0 to 17;
+    signal DATA0    : std_logic_vector(7 downto 0); 
+    signal DATA1    : std_logic_vector(7 downto 0); 
+   
+begin
+
+process (CLK)
+begin
+    if rising_edge(CLK) then
+        if RESET = '1' then
+            STATE <= 0;
+            JOY_CLK <= '0';
+            JOY_LOAD <= '0';
+            TICK <= 0;
+            JOY0_BUTTONS <= "00000000";
+            JOY0_BUTTONS <= "00000000";
+            JOY0_CONNECTED <= '0';
+            JOY1_CONNECTED <= '0';
+        else
+            TICK <= TICK + 1;
+            if TICK = (CLK_FREQ / TICK_FREQ) then
+                TICK <= 0;
+                STATE <= STATE + 1;
+            
+                case STATE is
+               
+                    when 0 =>
+                        JOY_LOAD <= '1';
+
+                    when 1 => 
+                        JOY_LOAD <= '0';
+                        DATA0(7) <= JOY_DATA0;
+                        DATA1(7) <= JOY_DATA1;
+
+                    when 2 | 4 | 6 | 8 | 10 | 12 | 14 | 16 => 
+                        JOY_CLK <= '1';
+                  
+                    when 3 =>
+                        JOY_CLK <= '0';
+                        DATA0(6) <= JOY_DATA0;
+                        DATA1(6) <= JOY_DATA1;
+                              
+                    when 5 =>
+                        JOY_CLK <= '0';
+                        DATA0(5) <= JOY_DATA0;
+                        DATA1(5) <= JOY_DATA1;
+            
+                    when 7 =>
+                        JOY_CLK <= '0';
+                        DATA0(4) <= JOY_DATA0;
+                        DATA1(4) <= JOY_DATA1;
+
+                    when 9 =>
+                        JOY_CLK <= '0';
+                        DATA0(3) <= JOY_DATA0;
+                        DATA1(3) <= JOY_DATA1;
+                  
+                    when 11 =>
+                        JOY_CLK <= '0';
+                        DATA0(2) <= JOY_DATA0;
+                        DATA1(2) <= JOY_DATA1;
+            
+                    when 13 =>
+                        JOY_CLK <= '0';
+                        DATA0(1) <= JOY_DATA0;
+                        DATA1(1) <= JOY_DATA1;
+                  
+                    when 15 =>
+                        JOY_CLK <= '0';
+                        DATA0(0) <= JOY_DATA0;
+                        DATA1(0) <= JOY_DATA1;
+
+                    when 17 =>
+                        JOY_CLK <= '0';
+                        JOY0_BUTTONS <= "00000000";
+                        JOY1_BUTTONS <= "00000000";
+                        JOY0_CONNECTED <= '0';
+                        JOY1_CONNECTED <= '0';
+                        STATE <= 0;
+
+                        if DATA0 /= "00000000" then -- gamepad connected
+                            JOY0_BUTTONS <= not DATA0;
+                            JOY0_CONNECTED <= '1';
+                        end if;
+
+                        if DATA1 /= "00000000" then -- gamepad connected
+                            JOY1_BUTTONS <= not DATA1;
+                            JOY1_CONNECTED <= '1';
+                        end if;
+
+                    when OTHERS =>
+                        NULL;
+                  
+                end case;
+            end if;
+        end if;
+    end if;
+end process; 
+   
+end RTL;
Index: aeon_lite/pll/_xmsgs/cg.xmsgs
===================================================================
--- aeon_lite/pll/_xmsgs/cg.xmsgs	(nonexistent)
+++ aeon_lite/pll/_xmsgs/cg.xmsgs	(revision 149)
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="sim" num="172" delta="old" >Generating IP...
+</msg>
+
+<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;pll&apos; already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+
+<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;pll&apos; already exists in the project. Output products for this core may be overwritten.</arg>
+</msg>
+
+<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Component clk_wiz_v3_6 does not have a valid model name for VHDL synthesis</arg>
+</msg>
+
+<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
+</msg>
+
+<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
+</msg>
+
+</messages>
+
Index: aeon_lite/pll/_xmsgs/pn_parser.xmsgs
===================================================================
--- aeon_lite/pll/_xmsgs/pn_parser.xmsgs	(nonexistent)
+++ aeon_lite/pll/_xmsgs/pn_parser.xmsgs	(revision 149)
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated   -->
+<!--     by the Xilinx ISE software.  Any direct editing or        -->
+<!--     changes made to this file may result in unpredictable     -->
+<!--     behavior or data corruption.  It is strongly advised that -->
+<!--     users do not edit the contents of this file.              -->
+<!--                                                               -->
+<!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.    -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;D:/Projects/Aeon Lite/cores/Atari_800/src/pll/pll.vhd&quot; into library work</arg>
+</msg>
+
+</messages>
+
Index: aeon_lite/pll/coregen.cgp
===================================================================
--- aeon_lite/pll/coregen.cgp	(nonexistent)
+++ aeon_lite/pll/coregen.cgp	(revision 149)
@@ -0,0 +1,9 @@
+SET busformat = BusFormatAngleBracketNotRipped
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET package = tqg144
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
Index: aeon_lite/pll/create_pll.tcl
===================================================================
--- aeon_lite/pll/create_pll.tcl	(nonexistent)
+++ aeon_lite/pll/create_pll.tcl	(revision 149)
@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator create command
+##
+
+proc findRtfPath { relativePath } {
+   set xilenv ""
+   if { [info exists ::env(XILINX) ] } {
+      if { [info exists ::env(MYXILINX)] } {
+         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+      } else {
+         set xilenv $::env(XILINX)
+      }
+   }
+   foreach path [ split $xilenv $::xilinx::path_sep ] {
+      set fullPath [ file join $path $relativePath ]
+      if { [ file exists $fullPath ] } {
+         return $fullPath
+      }
+   }
+   return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_create "xilinx.com:ip:clk_wiz:3.6" "pll" "Clocking Wizard" "Clocking Wizard (xilinx.com:ip:clk_wiz:3.6) generated by Project Navigator" xc6slx9-3tqg144 VHDL ]
+
+if { $result == 0 } {
+   puts "Core Generator create command completed successfully."
+} elseif { $result == 1 } {
+   puts "Core Generator create command failed."
+} elseif { $result == 3 || $result == 4 } {
+   # convert 'version check' result to real return range, bypassing any messages.
+   set result [ expr $result - 3 ]
+} else {
+   puts "Core Generator create cancelled."
+}
+exit $result
Index: aeon_lite/pll/edit_pll.tcl
===================================================================
--- aeon_lite/pll/edit_pll.tcl	(nonexistent)
+++ aeon_lite/pll/edit_pll.tcl	(revision 149)
@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator edit command
+##
+
+proc findRtfPath { relativePath } {
+   set xilenv ""
+   if { [info exists ::env(XILINX) ] } {
+      if { [info exists ::env(MYXILINX)] } {
+         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+      } else {
+         set xilenv $::env(XILINX)
+      }
+   }
+   foreach path [ split $xilenv $::xilinx::path_sep ] {
+      set fullPath [ file join $path $relativePath ]
+      if { [ file exists $fullPath ] } {
+         return $fullPath
+      }
+   }
+   return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_edit "pll" xc6slx9-3tqg144 VHDL ]
+
+if { $result == 0 } {
+   puts "Core Generator edit command completed successfully."
+} elseif { $result == 1 } {
+   puts "Core Generator edit command failed."
+} elseif { $result == 3 || $result == 4 } {
+   # convert 'version check' result to real return range, bypassing any messages.
+   set result [ expr $result - 3 ]
+} else {
+   puts "Core Generator edit cancelled."
+}
+exit $result
Index: aeon_lite/pll/pll/clk_wiz_v3_6_readme.txt
===================================================================
--- aeon_lite/pll/pll/clk_wiz_v3_6_readme.txt	(nonexistent)
+++ aeon_lite/pll/pll/clk_wiz_v3_6_readme.txt	(revision 149)
@@ -0,0 +1,184 @@
+CHANGE LOG for LogiCORE Clocking Wizard V3.6 
+
+                    Release Date: June 19, 2013
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+   http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+3. NEW FEATURE HISTORY 
+
+
+  3.1 ISE 
+  
+    - Spread Spectrum support for 7 series MMCME2
+
+    - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+      Resolved issue with example design becoming core top in planAhead
+
+      Resolved issue with Virtex6 MMCM instantiation for VHDL project
+      Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+06/19/2013  Xilinx, Inc.  3.6(Rev3)    ISE 14.6 support
+10/16/2012  Xilinx, Inc.  3.6(Rev2)    ISE 14.3 support
+07/25/2012  Xilinx, Inc.  3.6          ISE 14.2 support
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
Index: aeon_lite/pll/pll/doc/clk_wiz_v3_6_readme.txt
===================================================================
--- aeon_lite/pll/pll/doc/clk_wiz_v3_6_readme.txt	(nonexistent)
+++ aeon_lite/pll/pll/doc/clk_wiz_v3_6_readme.txt	(revision 149)
@@ -0,0 +1,184 @@
+CHANGE LOG for LogiCORE Clocking Wizard V3.6 
+
+                    Release Date: June 19, 2013
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+   http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+3. NEW FEATURE HISTORY 
+
+
+  3.1 ISE 
+  
+    - Spread Spectrum support for 7 series MMCME2
+
+    - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+      Resolved issue with example design becoming core top in planAhead
+
+      Resolved issue with Virtex6 MMCM instantiation for VHDL project
+      Please refer to AR 50719 - http://www.xilinx.com/support/answers/50719.htm
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+06/19/2013  Xilinx, Inc.  3.6(Rev3)    ISE 14.6 support
+10/16/2012  Xilinx, Inc.  3.6(Rev2)    ISE 14.3 support
+07/25/2012  Xilinx, Inc.  3.6          ISE 14.2 support
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
Index: aeon_lite/pll/pll/doc/clk_wiz_v3_6_vinfo.html
===================================================================
--- aeon_lite/pll/pll/doc/clk_wiz_v3_6_vinfo.html	(nonexistent)
+++ aeon_lite/pll/pll/doc/clk_wiz_v3_6_vinfo.html	(revision 149)
@@ -0,0 +1,195 @@
+<HTML>
+<HEAD>
+<TITLE>clk_wiz_v3_6_vinfo</TITLE>
+<META HTTP-EQUIV="Content-Type" CONTENT="text/plain;CHARSET=iso-8859-1">
+</HEAD>
+<BODY>
+<PRE><FONT face="Arial, Helvetica, sans-serif" size="-1">
+CHANGE LOG for LogiCORE Clocking Wizard V3.6 
+
+                    Release Date: June 19, 2013
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+  <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>
+
+For system requirements:
+
+   <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>
+
+This file contains release notes for the Xilinx LogiCORE IP Clocking Wizard v3.6
+solution. For the latest core updates, see the product page at:
+
+   <A HREF="http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/">www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/</A>
+
+................................................................................
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+  
+  The following device families are supported by the core for this release.
+  
+  All 7 Series devices
+
+
+  Zynq-7000 devices
+    Zynq-7000
+    Defense Grade Zynq-7000Q (XQ)
+
+
+  All Virtex-6 devices
+  
+  
+  All Spartan-6 devices
+  
+  
+................................................................................
+
+3. NEW FEATURE HISTORY 
+
+
+  3.1 ISE 
+  
+    - Spread Spectrum support for 7 series MMCME2
+
+    - ISE 14.2 software support
+
+................................................................................
+
+4. RESOLVED ISSUES
+
+
+  4.1 ISE 
+  
+      Resolved issue with example design becoming core top in planAhead
+
+      Resolved issue with Virtex6 MMCM instantiation for VHDL project
+      Please refer to AR 50719 - <A HREF="http://www.xilinx.com/support/answers/50719.htm">www.xilinx.com/support/answers/50719.htm</A>
+
+................................................................................
+
+5. KNOWN ISSUES & LIMITATIONS
+
+
+  5.1 ISE 
+  
+  
+  The most recent information, including known issues, workarounds, and
+  resolutions for this version is provided in the IP Release Notes Guide
+  located at
+
+   <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>
+  
+  
+................................................................................
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+
+To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>
+Questions are routed to a team with expertise using this product.
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+
+................................................................................
+
+7. CORE RELEASE HISTORY
+
+
+Date        By            Version      Description
+================================================================================
+06/19/2013  Xilinx, Inc.  3.6(Rev3)    ISE 14.6 support
+10/16/2012  Xilinx, Inc.  3.6(Rev2)    ISE 14.3 support
+07/25/2012  Xilinx, Inc.  3.6          ISE 14.2 support
+04/24/2012  Xilinx, Inc.  3.5          ISE 14.1 support
+01/18/2012  Xilinx, Inc.  3.3          ISE 13.4 support
+06/22/2011  Xilinx, Inc.  3.2          ISE 13.2 support
+03/01/2011  Xilinx, Inc.  3.1          ISE 13.1 support
+12/14/2010  Xilinx, Inc.  1.8          ISE 12.4 support
+09/21/2010  Xilinx, Inc.  1.7          ISE 12.3 support
+07/23/2010  Xilinx, Inc.  1.6          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  1.5          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  1.4          ISE 11.4 support
+09/16/2009  Xilinx, Inc.  1.3          ISE 11.3 support
+06/24/2009  Xilinx, Inc.  1.2          ISE 11.2 support
+04/24/2009  Xilinx, Inc.  1.1          Initial release; 11.1 support
+================================================================================
+                          
+................................................................................
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
+liability of any use of Xilinx products in Critical
+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
+
+</FONT>
+</PRE>
+</BODY>
+</HTML>
Index: aeon_lite/pll/pll/simulation/timing/simcmds.tcl
===================================================================
--- aeon_lite/pll/pll/simulation/timing/simcmds.tcl	(nonexistent)
+++ aeon_lite/pll/pll/simulation/timing/simcmds.tcl	(revision 149)
@@ -0,0 +1,9 @@
+# file: simcmds.tcl
+
+# create the simulation script
+vcd dumpfile isim.vcd
+vcd dumpvars -m /pll_tb -l 0
+wave add /
+run 50000ns
+quit
+
Index: aeon_lite/pll/pll/simulation/timing/simulate_mti.sh
===================================================================
--- aeon_lite/pll/pll/simulation/timing/simulate_mti.sh	(nonexistent)
+++ aeon_lite/pll/pll/simulation/timing/simulate_mti.sh	(revision 149)
@@ -0,0 +1,60 @@
+#/bin/sh
+# file: simulate_mti.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vcom -work work ../../implement/results/routed.vhd
+vcom -work work pll_tb.vhd
+
+# run the simulation
+vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprim -sdfmax pll_tb/dut=../../implement/results/routed.sdf +no_notifier work.pll_tb 
Index: aeon_lite/pll/pll/simulation/timing/vcs_session.tcl
===================================================================
--- aeon_lite/pll/pll/simulation/timing/vcs_session.tcl	(nonexistent)
+++ aeon_lite/pll/pll/simulation/timing/vcs_session.tcl	(revision 149)
@@ -0,0 +1 @@
+gui_open_window Wave
Index: aeon_lite/pll/pll.ncf
===================================================================
--- aeon_lite/pll/pll.ncf	(nonexistent)
+++ aeon_lite/pll/pll.ncf	(revision 149)
@@ -0,0 +1,59 @@
+# file: pll.ucf
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.000 ns HIGH 50% INPUT_JITTER 200.0ps;
+
+
+# FALSE PATH constraints 
+
+
Index: aeon_lite/pll/pll/simulation/timing/simulate_mti.do
===================================================================
--- aeon_lite/pll/pll/simulation/timing/simulate_mti.do	(nonexistent)
+++ aeon_lite/pll/pll/simulation/timing/simulate_mti.do	(revision 149)
@@ -0,0 +1,65 @@
+# file: simulate_mti.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vcom -work work ../../implement/results/routed.vhd
+vcom -work work pll_tb.vhd
+
+# run the simulation
+vsim -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprim -sdfmax pll_tb/dut=../../implement/results/routed.sdf +no_notifier work.pll_tb 
+when {end_of_sim} {echo "End of Simulation"; stop} 
+#do wave.do
+#log -r /*
+run 50000ns
+
+
Index: aeon_lite/pll/pll/simulation/timing/ucli_commands.key
===================================================================
--- aeon_lite/pll/pll/simulation/timing/ucli_commands.key	(nonexistent)
+++ aeon_lite/pll/pll/simulation/timing/ucli_commands.key	(revision 149)
@@ -0,0 +1,3 @@
+
+run 50000ns
+quit
Index: aeon_lite/pll/pll.gise
===================================================================
--- aeon_lite/pll/pll.gise	(nonexistent)
+++ aeon_lite/pll/pll.gise	(revision 149)
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="pll.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_ASY" xil_pn:name="pll.asy" xil_pn:origination="imported"/>
+    <file xil_pn:fileType="FILE_VHO" xil_pn:name="pll.vho" xil_pn:origination="imported"/>
+  </files>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>
Index: aeon_lite/pll/pll/doc/pg065_clk_wiz.pdf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: aeon_lite/pll/pll/doc/pg065_clk_wiz.pdf
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: aeon_lite/pll/pll/example_design/pll_exdes.ucf
===================================================================
--- aeon_lite/pll/pll/example_design/pll_exdes.ucf	(nonexistent)
+++ aeon_lite/pll/pll/example_design/pll_exdes.ucf	(revision 149)
@@ -0,0 +1,59 @@
+# file: pll_exdes.ucf
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.000 ns HIGH 50% INPUT_JITTER 200.0ps;
+
+
+# FALSE PATH constraints 
+PIN "COUNTER_RESET" TIG;
+
Index: aeon_lite/pll/pll/example_design/pll_exdes.vhd
===================================================================
--- aeon_lite/pll/pll/example_design/pll_exdes.vhd	(nonexistent)
+++ aeon_lite/pll/pll/example_design/pll_exdes.vhd	(revision 149)
@@ -0,0 +1,198 @@
+-- file: pll_exdes.vhd
+-- 
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+
+------------------------------------------------------------------------------
+-- Clocking wizard example design
+------------------------------------------------------------------------------
+-- This example design instantiates the created clocking network, where each
+--   output clock drives a counter. The high bit of each counter is ported.
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity pll_exdes is
+generic (
+  TCQ               : in time := 100 ps);
+port
+ (-- Clock in ports
+  CLK_IN1           : in  std_logic;
+  -- Reset that only drives logic in example design
+  COUNTER_RESET     : in  std_logic;
+  CLK_OUT           : out std_logic_vector(2 downto 1) ;
+  -- High bits of counters driven by clocks
+  COUNT             : out std_logic_vector(2 downto 1);
+  -- Status and control signals
+  LOCKED            : out std_logic
+ );
+end pll_exdes;
+
+architecture xilinx of pll_exdes is
+
+  -- Parameters for the counters
+  ---------------------------------
+  -- Counter width
+  constant C_W        : integer := 16;
+
+  -- Number of counters
+  constant NUM_C      : integer := 2;
+  -- Array typedef
+  type ctrarr is array (1 to NUM_C) of std_logic_vector(C_W-1 downto 0);
+
+  -- When the clock goes out of lock, reset the counters
+  signal   locked_int : std_logic;
+  signal   reset_int  : std_logic                     := '0';
+  -- Declare the clocks and counters
+  signal   clk        : std_logic_vector(NUM_C downto 1);
+ 
+  signal   clk_int    : std_logic_vector(NUM_C downto 1);
+  signal   clk_n  : std_logic_vector(NUM_C downto 1);
+  signal   counter    : ctrarr := (( others => (others => '0')));
+  signal rst_sync : std_logic_vector(NUM_C downto 1);
+  signal rst_sync_int : std_logic_vector(NUM_C downto 1);
+  signal rst_sync_int1 : std_logic_vector(NUM_C downto 1);
+  signal rst_sync_int2 : std_logic_vector(NUM_C downto 1);
+
+
+component pll is
+port
+ (-- Clock in ports
+  CLKIN           : in     std_logic;
+  -- Clock out ports
+  CLKOUT          : out    std_logic;
+  CLKOUT2          : out    std_logic;
+  -- Status and control signals
+  LOCKED            : out    std_logic
+ );
+end component;
+
+begin
+  -- Alias output to internally used signal
+  LOCKED    <= locked_int;
+
+  -- When the clock goes out of lock, reset the counters
+  reset_int <= (not locked_int) or COUNTER_RESET;
+
+
+  counters_1: for count_gen in 1 to NUM_C generate begin
+ process (clk(count_gen), reset_int) begin
+   if (reset_int = '1') then
+       rst_sync(count_gen) <= '1';
+       rst_sync_int(count_gen) <= '1';
+       rst_sync_int1(count_gen) <= '1';
+       rst_sync_int2(count_gen) <= '1';
+   elsif (clk(count_gen) 'event and clk(count_gen)='1') then
+       rst_sync(count_gen) <= '0';
+       rst_sync_int(count_gen) <= rst_sync(count_gen);
+       rst_sync_int1(count_gen) <= rst_sync_int(count_gen);
+       rst_sync_int2(count_gen) <= rst_sync_int1(count_gen);
+   end if;
+ end process;
+end generate counters_1;
+
+
+  -- Instantiation of the clocking network
+  ----------------------------------------
+  clknetwork : pll
+  port map
+   (-- Clock in ports
+    CLKIN            => CLK_IN1,
+    -- Clock out ports
+    CLKOUT           => clk_int(1),
+    CLKOUT2           => clk_int(2),
+    -- Status and control signals
+    LOCKED             => locked_int);
+
+  gen_outclk_oddr: 
+  for clk_out_pins in 1 to NUM_C generate 
+  begin
+  clk_n(clk_out_pins) <= not clk(clk_out_pins);
+  clkout_oddr : ODDR2
+  port map
+   (Q  => CLK_OUT(clk_out_pins),
+    C0 => clk(clk_out_pins),
+    C1 => clk_n(clk_out_pins),
+    CE => '1',
+    D0 => '1',
+    D1 => '0',
+    R  => '0',
+    S  => '0');
+   end generate;
+
+  -- Connect the output clocks to the design
+  -------------------------------------------
+  clk(1) <= clk_int(1);
+  clk(2) <= clk_int(2);
+
+  -- Output clock sampling
+  -------------------------------------
+  counters: for count_gen in 1 to NUM_C generate begin
+    process (clk(count_gen), rst_sync_int2(count_gen)) begin
+        if (rst_sync_int2(count_gen) = '1') then
+          counter(count_gen) <= (others => '0') after TCQ;
+        elsif (rising_edge (clk(count_gen))) then
+          counter(count_gen) <= counter(count_gen) + 1 after TCQ;
+        end if;
+    end process;
+
+    -- alias the high bit of each counter to the corresponding
+    --   bit in the output bus
+    COUNT(count_gen) <= counter(count_gen)(C_W-1);
+
+  end generate counters;
+
+
+
+end xilinx;
Index: aeon_lite/pll/pll/example_design/pll_exdes.xdc
===================================================================
--- aeon_lite/pll/pll/example_design/pll_exdes.xdc	(nonexistent)
+++ aeon_lite/pll/pll/example_design/pll_exdes.xdc	(revision 149)
@@ -0,0 +1,68 @@
+# file: pll_exdes.xdc
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+create_clock -name CLK_IN1 -period 20.000 [get_ports CLK_IN1]
+set_propagated_clock CLK_IN1
+set_input_jitter CLK_IN1 0.2
+
+# FALSE PATH constraint added on COUNTER_RESET 
+set_false_path -from [get_ports "COUNTER_RESET"]
+
+# Derived clock periods. These are commented out because they are 
+#   automatically propogated by the tools
+# However, if you'd like to use them for module level testing, you 
+#   can copy them into your module level timing checks
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
Index: aeon_lite/pll/pll/implement/implement.bat
===================================================================
--- aeon_lite/pll/pll/implement/implement.bat	(nonexistent)
+++ aeon_lite/pll/pll/implement/implement.bat	(revision 149)
@@ -0,0 +1,90 @@
+REM file: implement.bat
+REM 
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM 
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM 
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM 
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM 
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM 
+
+REM -----------------------------------------------------------------------------
+REM  Script to synthesize and implement the RTL provided for the clocking wizard
+REM -----------------------------------------------------------------------------
+
+REM Clean up the results directory
+rmdir /S /Q results
+mkdir results
+
+REM Copy unisim_comp.v file to results directory
+copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\
+
+REM Synthesize the Verilog Wrapper Files
+echo 'Synthesizing Clocking Wizard design with XST'
+xst -ifn xst.scr
+move pll_exdes.ngc results\
+
+REM  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+copy ..\example_design\pll_exdes.ucf results\
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -uc pll_exdes.ucf pll_exdes
+
+echo 'Running map'
+map -timing -pr b pll_exdes -o mapped.ncd
+
+echo 'Running par'
+par -w mapped.ncd routed mapped.pcf
+
+echo 'Running trce'
+trce -e 10 routed -o routed mapped.pcf
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level model for the clocking wizard example design'
+netgen -ofmt vhdl -sim -tm pll_exdes -w routed.ncd routed.vhd
+cd ..
+
Index: aeon_lite/pll/pll/implement/implement.sh
===================================================================
--- aeon_lite/pll/pll/implement/implement.sh	(nonexistent)
+++ aeon_lite/pll/pll/implement/implement.sh	(revision 149)
@@ -0,0 +1,91 @@
+#!/bin/sh
+# file: implement.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the clocking wizard
+#-----------------------------------------------------------------------------
+
+# Clean up the results directory
+rm -rf results
+mkdir results
+
+# Copy unisim_comp.v file to results directory
+cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
+
+# Synthesize the Verilog Wrapper Files
+echo 'Synthesizing Clocking Wizard design with XST'
+xst -ifn xst.scr
+mv pll_exdes.ngc results/
+
+#  Copy the constraints files generated by Coregen
+echo 'Copying files from constraints directory to results directory'
+cp ../example_design/pll_exdes.ucf results/
+
+cd results
+
+echo 'Running ngdbuild'
+ngdbuild -uc pll_exdes.ucf pll_exdes
+
+echo 'Running map'
+map -timing pll_exdes -o mapped.ncd
+
+echo 'Running par'
+par -w mapped.ncd routed mapped.pcf
+
+echo 'Running trce'
+trce -e 10 routed -o routed mapped.pcf
+
+echo 'Running design through bitgen'
+bitgen -w routed
+
+echo 'Running netgen to create gate level model for the clocking wizard example design'
+netgen -ofmt vhdl -sim -tm pll_exdes -w routed.ncd routed.vhd
+
+cd ..
Index: aeon_lite/pll/pll/implement/planAhead_ise.bat
===================================================================
--- aeon_lite/pll/pll/implement/planAhead_ise.bat	(nonexistent)
+++ aeon_lite/pll/pll/implement/planAhead_ise.bat	(revision 149)
@@ -0,0 +1,58 @@
+REM file: planAhead_ise.bat
+REM 
+REM (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM 
+REM This file contains confidential and proprietary information
+REM of Xilinx, Inc. and is protected under U.S. and
+REM international copyright and other intellectual property
+REM laws.
+REM 
+REM DISCLAIMER
+REM This disclaimer is not a license and does not grant any
+REM rights to the materials distributed herewith. Except as
+REM otherwise provided in a valid license issued to you by
+REM Xilinx, and to the maximum extent permitted by applicable
+REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM (2) Xilinx shall not be liable (whether in contract or tort,
+REM including negligence, or under any other theory of
+REM liability) for any loss or damage of any kind or nature
+REM related to, arising under or in connection with these
+REM materials, including for any direct, or any indirect,
+REM special, incidental, or consequential loss or damage
+REM (including loss of data, profits, goodwill, or any type of
+REM loss or damage suffered as a result of any action brought
+REM by a third party) even if such damage or loss was
+REM reasonably foreseeable or Xilinx had been advised of the
+REM possibility of the same.
+REM 
+REM CRITICAL APPLICATIONS
+REM Xilinx products are not designed or intended to be fail-
+REM safe, or for use in any application requiring fail-safe
+REM performance, such as life-support or safety devices or
+REM systems, Class III medical devices, nuclear facilities,
+REM applications related to the deployment of airbags, or any
+REM other applications that could lead to death, personal
+REM injury, or severe property or environmental damage
+REM (individually and collectively, "Critical
+REM Applications"). Customer assumes the sole risk and
+REM liability of any use of Xilinx products in Critical
+REM Applications, subject only to applicable laws and
+REM regulations governing limitations on product liability.
+REM 
+REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM PART OF THIS FILE AT ALL TIMES.
+REM 
+
+REM-----------------------------------------------------------------------------
+REM Script to synthesize and implement the RTL provided for the clocking wizard
+REM-----------------------------------------------------------------------------
+
+del \f results
+mkdir results
+cd results
+
+planAhead -mode batch -source ..\planAhead_ise.tcl
Index: aeon_lite/pll/pll/implement/planAhead_ise.sh
===================================================================
--- aeon_lite/pll/pll/implement/planAhead_ise.sh	(nonexistent)
+++ aeon_lite/pll/pll/implement/planAhead_ise.sh	(revision 149)
@@ -0,0 +1,59 @@
+#!/bin/sh
+# file: planAhead_ise.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the clocking wizard
+#-----------------------------------------------------------------------------
+
+rm -rf results
+mkdir results
+cd results
+
+planAhead -mode batch -source ../planAhead_ise.tcl
Index: aeon_lite/pll/pll/implement/planAhead_ise.tcl
===================================================================
--- aeon_lite/pll/pll/implement/planAhead_ise.tcl	(nonexistent)
+++ aeon_lite/pll/pll/implement/planAhead_ise.tcl	(revision 149)
@@ -0,0 +1,78 @@
+# file: planAhead_ise.tcl
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+set projDir [file dirname [info script]]
+set projName pll
+set topName pll_exdes
+set device xc6slx9tqg144-3
+
+create_project $projName $projDir/results/$projName -part $device
+
+set_property design_mode RTL [get_filesets sources_1]
+
+## Source files
+#set verilogSources [glob $srcDir/*.v]
+import_files -fileset [get_filesets sources_1] -force -norecurse ../../example_design/pll_exdes.vhd
+import_files -fileset [get_filesets sources_1] -force -norecurse ../../../pll.vhd
+
+
+#UCF file
+import_files -fileset [get_filesets constrs_1] -force -norecurse ../../example_design/pll_exdes.ucf
+
+set_property top $topName [get_property srcset [current_run]]
+
+launch_runs -runs synth_1
+wait_on_run synth_1
+
+set_property add_step Bitgen [get_runs impl_1]
+launch_runs -runs impl_1
+wait_on_run impl_1
+
+
+
Index: aeon_lite/pll/pll/implement/planAhead_rdn.sh
===================================================================
--- aeon_lite/pll/pll/implement/planAhead_rdn.sh	(nonexistent)
+++ aeon_lite/pll/pll/implement/planAhead_rdn.sh	(revision 149)
@@ -0,0 +1,57 @@
+#!/bin/sh
+# file: planAhead_rdn.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+#-----------------------------------------------------------------------------
+# Script to synthesize and implement the RTL provided for the XADC wizard
+#-----------------------------------------------------------------------------
+rm -rf results
+mkdir results
+cd results
+planAhead -mode batch -source ../planAhead_rdn.tcl
Index: aeon_lite/pll/pll/implement/xst.prj
===================================================================
--- aeon_lite/pll/pll/implement/xst.prj	(nonexistent)
+++ aeon_lite/pll/pll/implement/xst.prj	(revision 149)
@@ -0,0 +1,2 @@
+vhdl work ../../pll.vhd
+vhdl work ../example_design/pll_exdes.vhd
Index: aeon_lite/pll/pll/simulation/functional/simcmds.tcl
===================================================================
--- aeon_lite/pll/pll/simulation/functional/simcmds.tcl	(nonexistent)
+++ aeon_lite/pll/pll/simulation/functional/simcmds.tcl	(revision 149)
@@ -0,0 +1,8 @@
+# file: simcmds.tcl
+
+# create the simulation script
+vcd dumpfile isim.vcd
+vcd dumpvars -m /pll_tb -l 0
+wave add /
+run 50000ns
+quit
Index: aeon_lite/pll/pll/simulation/functional/simulate_isim.sh
===================================================================
--- aeon_lite/pll/pll/simulation/functional/simulate_isim.sh	(nonexistent)
+++ aeon_lite/pll/pll/simulation/functional/simulate_isim.sh	(revision 149)
@@ -0,0 +1,60 @@
+# file: simulate_isim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# nt64
+# create the project
+vhpcomp -work work ../../../pll.vhd
+vhpcomp -work work ../../example_design/pll_exdes.vhd
+vhpcomp -work work ../pll_tb.vhd
+
+# compile the project
+fuse work.pll_tb  -L unisim -o pll_isim.exe
+
+# run the simulation script
+./pll_isim.exe -gui -tclbatch simcmds.tcl
Index: aeon_lite/pll/pll/simulation/functional/simulate_mti.sh
===================================================================
--- aeon_lite/pll/pll/simulation/functional/simulate_mti.sh	(nonexistent)
+++ aeon_lite/pll/pll/simulation/functional/simulate_mti.sh	(revision 149)
@@ -0,0 +1,60 @@
+#/bin/sh
+# file: simulate_mti.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+# set up the working directory
+set work work
+vlib work
+
+# compile all of the files
+vcom -work work ../../../pll.vhd
+vcom -work work ../../example_design/pll_exdes.vhd
+vcom -work work ../pll_tb.vhd
+
+# run the simulation
+vsim -c -t ps -voptargs="+acc" -L secureip -L unisim work.pll_tb 
Index: aeon_lite/pll/pll/simulation/functional/wave.do
===================================================================
--- aeon_lite/pll/pll/simulation/functional/wave.do	(nonexistent)
+++ aeon_lite/pll/pll/simulation/functional/wave.do	(revision 149)
@@ -0,0 +1,58 @@
+# file: wave.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+add wave -noupdate -divider {Input clocks}
+add wave -noupdate -format Logic /pll_tb/CLK_IN1
+add wave -noupdate -divider {Output clocks}
+add wave -noupdate -format Literal -expand /pll_tb/dut/clk
+add wave -noupdate -divider Status/control
+add wave -noupdate -format Logic /pll_tb/LOCKED
+add wave -noupdate -divider Counters
+add wave -noupdate -format Literal -radix hexadecimal /pll_tb/COUNT
+add wave -noupdate -format Literal -radix hexadecimal -expand /pll_tb/dut/counter
Index: aeon_lite/pll/pll/simulation/timing/pll_tb.vhd
===================================================================
--- aeon_lite/pll/pll/simulation/timing/pll_tb.vhd	(nonexistent)
+++ aeon_lite/pll/pll/simulation/timing/pll_tb.vhd	(revision 149)
@@ -0,0 +1,214 @@
+-- file: pll_tb.vhd
+-- 
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+
+------------------------------------------------------------------------------
+-- Clocking wizard demonstration testbench
+------------------------------------------------------------------------------
+-- This demonstration testbench instantiates the example design for the 
+--   clocking wizard. Input clocks are toggled, which cause the clocking
+--   network to lock and the counters to increment.
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+
+library std;
+use std.textio.all;
+
+library work;
+use work.all;
+
+entity pll_tb is
+end pll_tb;
+
+architecture test of pll_tb is
+
+  -- Clock to Q delay of 100 ps
+  constant TCQ               : time := 100 ps;
+  -- timescale is 1ps
+  constant ONE_NS      : time := 1 ns;
+  -- how many cycles to run
+  constant COUNT_PHASE : integer := 1024 + 1;
+
+
+  -- we'll be using the period in many locations
+  constant PER1        : time := 20.000 ns;
+
+
+  -- Declare the input clock signals
+  signal CLK_IN1       : std_logic := '1';
+  -- The high bits of the sampling counters
+  signal COUNT         : std_logic_vector(2 downto 1);
+  -- Status and control signals
+  signal LOCKED        : std_logic;
+  signal COUNTER_RESET : std_logic := '0';
+  signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
+--  signal defined to stop mti simulation without severity failure in the report
+  signal end_of_sim : std_logic := '0';
+  signal CLK_OUT : std_logic_vector(2 downto 1);
+--Freq Check using the M & D values setting and actual Frequency generated
+
+component pll_exdes
+port
+ (-- Clock in ports
+  CLK_IN1           : in  std_logic;
+  -- Reset that only drives logic in example design
+  COUNTER_RESET     : in  std_logic;
+  CLK_OUT           : out std_logic_vector(2 downto 1) ;
+  -- High bits of counters driven by clocks
+  COUNT             : out std_logic_vector(2 downto 1);
+  -- Status and control signals
+  LOCKED            : out std_logic
+ );
+end component;
+
+begin
+
+  -- Input clock generation
+  --------------------------------------
+  process begin
+    CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
+  end process;
+
+  -- Test sequence
+  process 
+
+    procedure simtimeprint is
+      variable outline : line;
+    begin
+      write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
+      write(outline, NOW/PER1);
+      write(outline, string'(" ns"));
+      writeline(output,outline);
+    end simtimeprint;
+
+    procedure simfreqprint (period : time; clk_num : integer) is
+       variable outputline : LINE;
+       variable str1 : string(1 to 16);
+       variable str2 : integer;
+       variable str3 : string(1 to 2);
+       variable str4 : integer;
+       variable str5 : string(1 to 4);
+    begin
+       str1 := "Freq of CLK_OUT(";
+       str2 :=  clk_num;
+       str3 :=  ") ";
+       str4 :=  1000000 ps/period ;
+       str5 :=  " MHz" ;
+       write(outputline, str1 );
+       write(outputline, str2);
+       write(outputline, str3);
+       write(outputline, str4);
+       write(outputline, str5);
+       writeline(output, outputline);
+    end simfreqprint;
+
+  begin
+   report "Timing checks are not valid" severity note;
+    wait until LOCKED = '1';
+    wait for (PER1*20);
+    COUNTER_RESET <= '1';
+    wait for (PER1*19.5);
+    COUNTER_RESET <= '0';
+    wait for (PER1*1);
+    report "Timing checks are valid" severity note;
+    wait for (PER1*COUNT_PHASE);
+
+
+    simtimeprint;
+    end_of_sim <= '1';
+    wait for 1 ps;
+    report "Simulation Stopped." severity failure;
+    wait;
+  end process;
+
+ process (CLK_IN1)
+    procedure simtimeprint is
+      variable outline : line;
+    begin
+      write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
+      write(outline, NOW/PER1);
+      write(outline, string'(" ns"));
+      writeline(output,outline);
+    end simtimeprint;
+   begin
+     if (CLK_IN1'event and CLK_IN1='1') then
+         timeout_counter <= timeout_counter + '1';
+       if (timeout_counter = "10000000000000") then
+          if (LOCKED /= '1') then
+            simtimeprint;
+            report "NO LOCK signal" severity failure;
+          end if;
+       end if;
+     end if;
+ end process; 
+
+
+  -- Instantiation of the example design containing the clock
+  --    network and sampling counters
+  -----------------------------------------------------------
+  dut : pll_exdes
+  port map
+   (-- Clock in ports
+    CLK_IN1            => CLK_IN1,
+    -- Reset for logic in example design
+    COUNTER_RESET      => COUNTER_RESET,
+    CLK_OUT            => CLK_OUT,
+    -- High bits of the counters
+    COUNT              => COUNT,
+    -- Status and control signals
+    LOCKED             => LOCKED);
+
+-- Freq Check 
+
+end test;
Index: aeon_lite/pll/pll/simulation/timing/simulate_mti.bat
===================================================================
--- aeon_lite/pll/pll/simulation/timing/simulate_mti.bat	(nonexistent)
+++ aeon_lite/pll/pll/simulation/timing/simulate_mti.bat	(revision 149)
@@ -0,0 +1,58 @@
+REM file: simulate_mti.bat
+REM  
+REM  (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+REM  
+REM  This file contains confidential and proprietary information
+REM  of Xilinx, Inc. and is protected under U.S. and
+REM  international copyright and other intellectual property
+REM  laws.
+REM  
+REM  DISCLAIMER
+REM  This disclaimer is not a license and does not grant any
+REM  rights to the materials distributed herewith. Except as
+REM  otherwise provided in a valid license issued to you by
+REM  Xilinx, and to the maximum extent permitted by applicable
+REM  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+REM  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+REM  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+REM  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+REM  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+REM  (2) Xilinx shall not be liable (whether in contract or tort,
+REM  including negligence, or under any other theory of
+REM  liability) for any loss or damage of any kind or nature
+REM  related to, arising under or in connection with these
+REM  materials, including for any direct, or any indirect,
+REM  special, incidental, or consequential loss or damage
+REM  (including loss of data, profits, goodwill, or any type of
+REM  loss or damage suffered as a result of any action brought
+REM  by a third party) even if such damage or loss was
+REM  reasonably foreseeable or Xilinx had been advised of the
+REM  possibility of the same.
+REM  
+REM  CRITICAL APPLICATIONS
+REM  Xilinx products are not designed or intended to be fail-
+REM  safe, or for use in any application requiring fail-safe
+REM  performance, such as life-support or safety devices or
+REM  systems, Class III medical devices, nuclear facilities,
+REM  applications related to the deployment of airbags, or any
+REM  other applications that could lead to death, personal
+REM  injury, or severe property or environmental damage
+REM  (individually and collectively, "Critical
+REM  Applications"). Customer assumes the sole risk and
+REM  liability of any use of Xilinx products in Critical
+REM  Applications, subject only to applicable laws and
+REM  regulations governing limitations on product liability.
+REM  
+REM  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+REM  PART OF THIS FILE AT ALL TIMES.
+REM  
+# set up the working directory
+set work work
+vlib work
+
+REM compile all of the files
+vcom -work work ..\..\implement\results\routed.vhd
+vcom -work work pll_tb.vhd
+
+REM run the simulation
+vsim -c -t ps +transport_int_delays -voptargs="+acc" -L secureip -L simprim -sdfmax pll_tb\dut=..\..\implement\results\routed.sdf +no_notifier work.pll_tb 
Index: aeon_lite/pll/pll/simulation/timing/simulate_vcs.sh
===================================================================
--- aeon_lite/pll/pll/simulation/timing/simulate_vcs.sh	(nonexistent)
+++ aeon_lite/pll/pll/simulation/timing/simulate_vcs.sh	(revision 149)
@@ -0,0 +1,70 @@
+#!/bin/sh
+# file: simulate_vcs.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+
+# remove old files
+rm -rf simv* csrc DVEfiles AN.DB 
+
+# compile all of the files
+# Note that -sverilog is not strictly required- You can
+#   remove the -sverilog if you change the type of the
+#   localparam for the periods in the testbench file to 
+#   [63:0] from time
+vhdlan -xlrm ../../implement/results/routed.vhd \
+      pll_tb.vhd
+
+# prepare the simulation 
+vcs +vcs+lic+wait -xlrm -sdf max:pll_exdes:../../implement/results/routed.sdf -debug pll_tb.vhd ../../implement/results/routed.vhd
+
+# run the simulation
+./simv -xlrm -ucli -i ucli_commands.key
+
+# launch the viewer
+#dve -vpd vcdplus.vpd -session vcs_session.tcl
Index: aeon_lite/pll/pll.asy
===================================================================
--- aeon_lite/pll/pll.asy	(nonexistent)
+++ aeon_lite/pll/pll.asy	(revision 149)
@@ -0,0 +1,21 @@
+Version 4
+SymbolType BLOCK
+TEXT 32 32 LEFT 4 pll
+RECTANGLE Normal 32 32 576 1088
+LINE Normal 0 80 32 80
+PIN 0 80 LEFT 36
+PINATTR PinName clk_in1
+PINATTR Polarity IN
+LINE Normal 608 80 576 80
+PIN 608 80 RIGHT 36
+PINATTR PinName clk_out1
+PINATTR Polarity OUT
+LINE Normal 608 176 576 176
+PIN 608 176 RIGHT 36
+PINATTR PinName clk_out2
+PINATTR Polarity OUT
+LINE Normal 608 976 576 976
+PIN 608 976 RIGHT 36
+PINATTR PinName locked
+PINATTR Polarity OUT
+
Index: aeon_lite/pll/pll.ucf
===================================================================
--- aeon_lite/pll/pll.ucf	(nonexistent)
+++ aeon_lite/pll/pll.ucf	(revision 149)
@@ -0,0 +1,58 @@
+# file: pll.ucf
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+NET "CLK_IN1" TNM_NET = "CLK_IN1";
+TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 20.000 ns HIGH 50% INPUT_JITTER 200.0ps;
+
+
+# FALSE PATH constraints 
+
Index: aeon_lite/pll/pll.xdc
===================================================================
--- aeon_lite/pll/pll.xdc	(nonexistent)
+++ aeon_lite/pll/pll.xdc	(revision 149)
@@ -0,0 +1,66 @@
+# file: pll.xdc
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# Input clock periods. These duplicate the values entered for the
+#  input clocks. You can use these to time your system
+#----------------------------------------------------------------
+create_clock -name CLK_IN1 -period 20.000 [get_ports CLK_IN1]
+set_propagated_clock CLK_IN1
+set_input_jitter CLK_IN1 0.2
+
+
+# Derived clock periods. These are commented out because they are 
+#   automatically propogated by the tools
+# However, if you'd like to use them for module level testing, you 
+#   can copy them into your module level timing checks
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
+
+#-----------------------------------------------------------------
Index: aeon_lite/sram_statemachine.vhd
===================================================================
--- aeon_lite/sram_statemachine.vhd	(nonexistent)
+++ aeon_lite/sram_statemachine.vhd	(revision 149)
@@ -0,0 +1,165 @@
+---------------------------------------------------------------------------
+-- SRAM memory controller
+---------------------------------------------------------------------------
+-- This file is a part of "Aeon Lite" project
+-- Dmitriy Schapotschkin aka ILoveSpeccy '2014
+-- ilovespeccy@speccyland.net
+-- Project homepage: www.speccyland.net
+---------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.numeric_std.all;
+
+ENTITY sram_statemachine IS
+PORT ( 
+   CLK               : in     std_logic;
+   RESET_N           : in     std_logic;
+	
+   DATA_IN           : in     std_logic_vector(31 downto 0);
+   ADDRESS_IN        : in     std_logic_vector(22 downto 0);
+   WRITE_EN          : in     std_logic;
+   REQUEST           : in     std_logic;
+   BYTE_ACCESS       : in     std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+   WORD_ACCESS       : in     std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+   LONGWORD_ACCESS   : in     std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+   COMPLETE          : out    std_logic;
+   DATA_OUT          : out    std_logic_vector(31 downto 0);
+
+   SRAM_ADDR         : out    std_logic_vector(17 downto 0);
+   SRAM_DQ           : inout  std_logic_vector(15 downto 0);
+   SRAM_WE_N         : out    std_logic;
+   SRAM_OE_N         : out    std_logic;
+   SRAM_UB_N         : out    std_logic;
+   SRAM_LB_N         : out    std_logic;
+   SRAM_CE0_N        : out    std_logic;
+   SRAM_CE1_N        : out    std_logic );
+END sram_statemachine;
+
+ARCHITECTURE vhdl OF sram_statemachine IS
+
+	function REPEAT(N: natural; B: std_logic) 
+      return std_logic_vector
+	is
+      variable RESULT: std_logic_vector(1 to N);
+	begin
+      for i in 1 to N loop
+         RESULT(i) := B;
+      end loop;
+      return RESULT;
+	end;
+   
+   signal SRAM_DI          : std_logic_vector(15 downto 0);
+   signal SRAM_DO          : std_logic_vector(15 downto 0);
+   signal DATA_OUT_REG     : std_logic_vector(31 downto 0);
+   signal MASK             : std_logic_vector(3 downto 0);
+   signal ADDRESS_IN_NEXT  : std_logic_vector(18 downto 0);
+   
+   type STATES is (ST_IDLE, ST_READ0, ST_READ1, ST_READ2, ST_WRITE0, ST_WRITE1, ST_WRITE2);
+   signal STATE : STATES;
+
+BEGIN
+
+   SRAM_DQ <= SRAM_DI;
+   SRAM_DO <= SRAM_DQ;
+
+   DATA_OUT <= DATA_OUT_REG;
+   ADDRESS_IN_NEXT <= std_logic_vector(unsigned(ADDRESS_IN(19 downto 1)) + 1);
+   
+   COMPLETE <= '1' when STATE = ST_IDLE and REQUEST = '0' else '0';
+
+   process(CLK, RESET_N)
+   begin
+      if RESET_N = '0' then
+         SRAM_DI <= (OTHERS=>'Z');
+         SRAM_WE_N <= '1';
+         SRAM_OE_N <= '1';
+         SRAM_CE0_N <= '1';
+         SRAM_CE1_N <= '1';
+         SRAM_LB_N <= '1';
+         SRAM_UB_N <= '1';
+         STATE <= ST_IDLE;
+      else
+         if rising_edge(CLK) then
+         
+            case STATE is
+               when ST_IDLE =>
+
+                  SRAM_DI <= (OTHERS=>'Z');
+                  SRAM_WE_N <= '1';
+                  SRAM_OE_N <= '1';
+                  SRAM_LB_N <= '1';
+                  SRAM_UB_N <= '1';
+
+                  if REQUEST = '1' then
+                  
+                     MASK(0) <= (BYTE_ACCESS or WORD_ACCESS) and ADDRESS_IN(0);      -- masked on misaligned byte or word
+                     MASK(1) <= (BYTE_ACCESS) and not(address_in(0));                -- masked on aligned byte only
+                     MASK(2) <= BYTE_ACCESS or (WORD_ACCESS and not(ADDRESS_IN(0))); -- masked on aligned word or byte
+                     MASK(3) <= not(LONGWORD_ACCESS);                                -- masked for everything except long word access                     
+
+                     SRAM_ADDR <= ADDRESS_IN(18 downto 1);
+                     
+                     SRAM_CE0_N <= ADDRESS_IN(19);
+                     SRAM_CE1_N <= not ADDRESS_IN(19);
+
+                     if WRITE_EN = '1' then
+                        STATE <= ST_WRITE0;
+                     else
+                        STATE <= ST_READ0;
+                     end if;
+                  end if;  
+
+               when ST_WRITE0 =>
+                  SRAM_LB_N <= MASK(0);
+                  SRAM_UB_N <= MASK(1);
+                  SRAM_DI(7 downto 0) <= DATA_IN(7 downto 0);
+                  SRAM_DI(15 downto 8) <= (DATA_IN(15 downto 8) and not(repeat(8,MASK(0)))) or (DATA_IN(7 downto 0) and repeat(8,MASK(0)));
+                  SRAM_WE_N <= '0';
+                  STATE <= ST_WRITE1;             
+
+               when ST_WRITE1 =>
+                  SRAM_WE_N <= '1';
+                  STATE <= ST_WRITE2;             
+
+               when ST_WRITE2 =>
+                  SRAM_ADDR <= ADDRESS_IN_NEXT(17 downto 0);
+                  SRAM_CE0_N <= ADDRESS_IN_NEXT(18);
+                  SRAM_CE1_N <= not ADDRESS_IN_NEXT(18);
+                  SRAM_DI(7 downto 0) <= (DATA_IN(23 downto 16) and not(repeat(8,MASK(0)))) or (DATA_IN(15 downto 8) and repeat(8,MASK(0)));
+                  SRAM_DI(15 downto 8) <= DATA_IN(31 downto 24);
+                  SRAM_LB_N <= MASK(2);
+                  SRAM_UB_N <= MASK(3);
+                  SRAM_WE_N <= '0';
+                  STATE <= ST_IDLE;
+   
+               when ST_READ0 =>
+                  SRAM_LB_N <= MASK(0);
+                  SRAM_UB_N <= MASK(1);
+                  SRAM_OE_N <= '0';
+                  STATE <= ST_READ1;
+
+               when ST_READ1 =>
+                  DATA_OUT_REG(7 downto 0) <= (SRAM_DO(7 downto 0) and not(repeat(8,MASK(0)))) or (SRAM_DO(15 downto 8) and repeat(8,MASK(0)));
+                  DATA_OUT_REG(15 downto 8) <= SRAM_DO(15 downto 8); 
+                  SRAM_ADDR <= ADDRESS_IN_NEXT(17 downto 0);
+                  SRAM_CE0_N <= ADDRESS_IN_NEXT(18);
+                  SRAM_CE1_N <= not ADDRESS_IN_NEXT(18);
+                  SRAM_LB_N <= MASK(2);
+                  SRAM_UB_N <= MASK(3);
+                  STATE <= ST_READ2;
+
+               when ST_READ2 =>
+                  DATA_OUT_REG(15 downto 8 ) <= (SRAM_DO(7 downto 0) and repeat(8,MASK(0))) or (DATA_OUT_REG(15 downto 8) and not(repeat(8,MASK(0))));
+                  DATA_OUT_REG(31 downto 16) <= SRAM_DO(15 downto 0);
+                  STATE <= ST_IDLE;
+
+               when OTHERS =>
+                  STATE <= ST_IDLE;
+               
+            end case;
+         end if;
+      end if;
+   end process;
+
+END vhdl;
Index: aeon_lite/pll/pll/simulation/timing/simulate_isim.sh
===================================================================
--- aeon_lite/pll/pll/simulation/timing/simulate_isim.sh	(nonexistent)
+++ aeon_lite/pll/pll/simulation/timing/simulate_isim.sh	(revision 149)
@@ -0,0 +1,61 @@
+# file: simulate_isim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# create the project
+vhpcomp -work work ../../implement/results/routed.vhd
+vhpcomp -work work pll_tb.vhd
+
+# compile the project
+fuse work.pll_tb  -L secureip -L simprim -o pll_isim.exe
+
+# run the simulation script
+./pll_isim.exe -tclbatch simcmds.tcl -sdfmax /pll_tb/dut=../../implement/results/routed.sdf
+
+# run the simulation script
+#./pll_isim.exe -gui -tclbatch simcmds.tcl
Index: aeon_lite/pll/pll/simulation/timing/simulate_ncsim.sh
===================================================================
--- aeon_lite/pll/pll/simulation/timing/simulate_ncsim.sh	(nonexistent)
+++ aeon_lite/pll/pll/simulation/timing/simulate_ncsim.sh	(revision 149)
@@ -0,0 +1,63 @@
+#!/bin/sh
+# file: simulate_ncsim.sh
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+# set up the working directory
+mkdir work
+
+# compile all of the files
+ncvhdl -v93 -work work ../../implement/results/routed.vhd
+ncvhdl -v93 -work work pll_tb.vhd
+
+# elaborate and run the simulation
+ncsdfc ../../implement/results/routed.sdf
+
+ncelab -work work -access +wc -pulse_r 10 -nonotifier work.pll_tb -sdf_cmd_file sdf_cmd_file
+ncsim -input  "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.pll_tb
+
Index: aeon_lite/pll/pll/simulation/timing/wave.do
===================================================================
--- aeon_lite/pll/pll/simulation/timing/wave.do	(nonexistent)
+++ aeon_lite/pll/pll/simulation/timing/wave.do	(revision 149)
@@ -0,0 +1,74 @@
+# file: wave.do
+# 
+# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# 
+
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate -divider {Input clocks}
+add wave -noupdate /pll_tb/clk_in1
+add wave -noupdate -divider {Output clocks}
+add wave -noupdate /pll_tb/clk_in1
+add wave -noupdate /pll_tb/count
+add wave -noupdate /pll_tb/counter_reset
+add wave -noupdate /pll_tb/locked
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {3223025 ps} 0}
+configure wave -namecolwidth 238
+configure wave -valuecolwidth 107
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
Index: aeon_lite/pll/pll.sym
===================================================================
--- aeon_lite/pll/pll.sym	(nonexistent)
+++ aeon_lite/pll/pll.sym	(revision 149)
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<symbol version="7" name="pll">
+    <symboltype>BLOCK</symboltype>
+    <timestamp>2014-7-23T19:14:8</timestamp>
+    <pin polarity="Input" x="0" y="80" name="clk_in1" />
+    <pin polarity="Output" x="608" y="80" name="clk_out1" />
+    <pin polarity="Output" x="608" y="176" name="clk_out2" />
+    <pin polarity="Output" x="608" y="976" name="locked" />
+    <graph>
+        <text style="fontsize:40;fontname:Arial" x="32" y="32">pll</text>
+        <rect width="544" x="32" y="32" height="1056" />
+        <line x2="32" y1="80" y2="80" x1="0" />
+        <attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin clk_in1" />
+        <line x2="576" y1="80" y2="80" x1="608" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="80" type="pin clk_out1" />
+        <line x2="576" y1="176" y2="176" x1="608" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="176" type="pin clk_out2" />
+        <line x2="576" y1="976" y2="976" x1="608" />
+        <attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="572" y="976" type="pin locked" />
+    </graph>
+</symbol>
Index: aeon_lite/pll/pll.xco
===================================================================
--- aeon_lite/pll/pll.xco	(nonexistent)
+++ aeon_lite/pll/pll.xco	(revision 149)
@@ -0,0 +1,269 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.7
+# Date: Wed Jul 23 19:13:47 2014
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:clk_wiz:3.6
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -3
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
+# END Select
+# BEGIN Parameters
+CSET calc_done=DONE
+CSET clk_in_sel_port=CLK_IN_SEL
+CSET clk_out1_port=CLKOUT
+CSET clk_out1_use_fine_ps_gui=false
+CSET clk_out2_port=CLKOUT2
+CSET clk_out2_use_fine_ps_gui=false
+CSET clk_out3_port=CLK_OUT3
+CSET clk_out3_use_fine_ps_gui=false
+CSET clk_out4_port=CLK_OUT4
+CSET clk_out4_use_fine_ps_gui=false
+CSET clk_out5_port=CLK_OUT5
+CSET clk_out5_use_fine_ps_gui=false
+CSET clk_out6_port=CLK_OUT6
+CSET clk_out6_use_fine_ps_gui=false
+CSET clk_out7_port=CLK_OUT7
+CSET clk_out7_use_fine_ps_gui=false
+CSET clk_valid_port=CLK_VALID
+CSET clkfb_in_n_port=CLKFB_IN_N
+CSET clkfb_in_p_port=CLKFB_IN_P
+CSET clkfb_in_port=CLKFB_IN
+CSET clkfb_in_signaling=SINGLE
+CSET clkfb_out_n_port=CLKFB_OUT_N
+CSET clkfb_out_p_port=CLKFB_OUT_P
+CSET clkfb_out_port=CLKFB_OUT
+CSET clkfb_stopped_port=CLKFB_STOPPED
+CSET clkin1_jitter_ps=200.0
+CSET clkin1_ui_jitter=0.010
+CSET clkin2_jitter_ps=100.0
+CSET clkin2_ui_jitter=0.010
+CSET clkout1_drives=BUFG
+CSET clkout1_requested_duty_cycle=50.000
+CSET clkout1_requested_out_freq=28.64
+CSET clkout1_requested_phase=0.000
+CSET clkout2_drives=BUFG
+CSET clkout2_requested_duty_cycle=50.000
+CSET clkout2_requested_out_freq=57.28
+CSET clkout2_requested_phase=0.000
+CSET clkout2_used=true
+CSET clkout3_drives=BUFG
+CSET clkout3_requested_duty_cycle=50.000
+CSET clkout3_requested_out_freq=100.000
+CSET clkout3_requested_phase=0.000
+CSET clkout3_used=false
+CSET clkout4_drives=BUFG
+CSET clkout4_requested_duty_cycle=50.000
+CSET clkout4_requested_out_freq=100.000
+CSET clkout4_requested_phase=0.000
+CSET clkout4_used=false
+CSET clkout5_drives=BUFG
+CSET clkout5_requested_duty_cycle=50.000
+CSET clkout5_requested_out_freq=100.000
+CSET clkout5_requested_phase=0.000
+CSET clkout5_used=false
+CSET clkout6_drives=BUFG
+CSET clkout6_requested_duty_cycle=50.000
+CSET clkout6_requested_out_freq=100.000
+CSET clkout6_requested_phase=0.000
+CSET clkout6_used=false
+CSET clkout7_drives=BUFG
+CSET clkout7_requested_duty_cycle=50.000
+CSET clkout7_requested_out_freq=100.000
+CSET clkout7_requested_phase=0.000
+CSET clkout7_used=false
+CSET clock_mgr_type=AUTO
+CSET component_name=pll
+CSET daddr_port=DADDR
+CSET dclk_port=DCLK
+CSET dcm_clk_feedback=1X
+CSET dcm_clk_out1_port=CLKFX
+CSET dcm_clk_out2_port=CLK0
+CSET dcm_clk_out3_port=CLK0
+CSET dcm_clk_out4_port=CLK0
+CSET dcm_clk_out5_port=CLK0
+CSET dcm_clk_out6_port=CLK0
+CSET dcm_clkdv_divide=2.0
+CSET dcm_clkfx_divide=25
+CSET dcm_clkfx_multiply=14
+CSET dcm_clkgen_clk_out1_port=CLKFX
+CSET dcm_clkgen_clk_out2_port=CLKFX
+CSET dcm_clkgen_clk_out3_port=CLKFX
+CSET dcm_clkgen_clkfx_divide=1
+CSET dcm_clkgen_clkfx_md_max=0.000
+CSET dcm_clkgen_clkfx_multiply=4
+CSET dcm_clkgen_clkfxdv_divide=2
+CSET dcm_clkgen_clkin_period=10.000
+CSET dcm_clkgen_notes=None
+CSET dcm_clkgen_spread_spectrum=NONE
+CSET dcm_clkgen_startup_wait=false
+CSET dcm_clkin_divide_by_2=false
+CSET dcm_clkin_period=20.000
+CSET dcm_clkout_phase_shift=NONE
+CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
+CSET dcm_notes=None
+CSET dcm_phase_shift=0
+CSET dcm_pll_cascade=NONE
+CSET dcm_startup_wait=false
+CSET den_port=DEN
+CSET din_port=DIN
+CSET dout_port=DOUT
+CSET drdy_port=DRDY
+CSET dwe_port=DWE
+CSET feedback_source=FDBK_AUTO
+CSET in_freq_units=Units_MHz
+CSET in_jitter_units=Units_UI
+CSET input_clk_stopped_port=INPUT_CLK_STOPPED
+CSET jitter_options=UI
+CSET jitter_sel=No_Jitter
+CSET locked_port=LOCKED
+CSET mmcm_bandwidth=OPTIMIZED
+CSET mmcm_clkfbout_mult_f=4.000
+CSET mmcm_clkfbout_phase=0.000
+CSET mmcm_clkfbout_use_fine_ps=false
+CSET mmcm_clkin1_period=10.000
+CSET mmcm_clkin2_period=10.000
+CSET mmcm_clkout0_divide_f=4.000
+CSET mmcm_clkout0_duty_cycle=0.500
+CSET mmcm_clkout0_phase=0.000
+CSET mmcm_clkout0_use_fine_ps=false
+CSET mmcm_clkout1_divide=1
+CSET mmcm_clkout1_duty_cycle=0.500
+CSET mmcm_clkout1_phase=0.000
+CSET mmcm_clkout1_use_fine_ps=false
+CSET mmcm_clkout2_divide=1
+CSET mmcm_clkout2_duty_cycle=0.500
+CSET mmcm_clkout2_phase=0.000
+CSET mmcm_clkout2_use_fine_ps=false
+CSET mmcm_clkout3_divide=1
+CSET mmcm_clkout3_duty_cycle=0.500
+CSET mmcm_clkout3_phase=0.000
+CSET mmcm_clkout3_use_fine_ps=false
+CSET mmcm_clkout4_cascade=false
+CSET mmcm_clkout4_divide=1
+CSET mmcm_clkout4_duty_cycle=0.500
+CSET mmcm_clkout4_phase=0.000
+CSET mmcm_clkout4_use_fine_ps=false
+CSET mmcm_clkout5_divide=1
+CSET mmcm_clkout5_duty_cycle=0.500
+CSET mmcm_clkout5_phase=0.000
+CSET mmcm_clkout5_use_fine_ps=false
+CSET mmcm_clkout6_divide=1
+CSET mmcm_clkout6_duty_cycle=0.500
+CSET mmcm_clkout6_phase=0.000
+CSET mmcm_clkout6_use_fine_ps=false
+CSET mmcm_clock_hold=false
+CSET mmcm_compensation=ZHOLD
+CSET mmcm_divclk_divide=1
+CSET mmcm_notes=None
+CSET mmcm_ref_jitter1=0.010
+CSET mmcm_ref_jitter2=0.010
+CSET mmcm_startup_wait=false
+CSET num_out_clks=2
+CSET override_dcm=false
+CSET override_dcm_clkgen=false
+CSET override_mmcm=false
+CSET override_pll=false
+CSET platform=nt64
+CSET pll_bandwidth=OPTIMIZED
+CSET pll_clk_feedback=CLKFBOUT
+CSET pll_clkfbout_mult=39
+CSET pll_clkfbout_phase=0.000
+CSET pll_clkin_period=20.000
+CSET pll_clkout0_divide=34
+CSET pll_clkout0_duty_cycle=0.500
+CSET pll_clkout0_phase=0.000
+CSET pll_clkout1_divide=17
+CSET pll_clkout1_duty_cycle=0.500
+CSET pll_clkout1_phase=0.000
+CSET pll_clkout2_divide=1
+CSET pll_clkout2_duty_cycle=0.500
+CSET pll_clkout2_phase=0.000
+CSET pll_clkout3_divide=1
+CSET pll_clkout3_duty_cycle=0.500
+CSET pll_clkout3_phase=0.000
+CSET pll_clkout4_divide=1
+CSET pll_clkout4_duty_cycle=0.500
+CSET pll_clkout4_phase=0.000
+CSET pll_clkout5_divide=1
+CSET pll_clkout5_duty_cycle=0.500
+CSET pll_clkout5_phase=0.000
+CSET pll_compensation=SYSTEM_SYNCHRONOUS
+CSET pll_divclk_divide=2
+CSET pll_notes=None
+CSET pll_ref_jitter=0.010
+CSET power_down_port=POWER_DOWN
+CSET prim_in_freq=50
+CSET prim_in_jitter=0.010
+CSET prim_source=Single_ended_clock_capable_pin
+CSET primary_port=CLKIN
+CSET primitive=MMCM
+CSET primtype_sel=PLL_BASE
+CSET psclk_port=PSCLK
+CSET psdone_port=PSDONE
+CSET psen_port=PSEN
+CSET psincdec_port=PSINCDEC
+CSET relative_inclk=REL_PRIMARY
+CSET reset_port=RESET
+CSET secondary_in_freq=100.000
+CSET secondary_in_jitter=0.010
+CSET secondary_port=CLK_IN2
+CSET secondary_source=Single_ended_clock_capable_pin
+CSET ss_mod_freq=250
+CSET ss_mode=CENTER_HIGH
+CSET status_port=STATUS
+CSET summary_strings=empty
+CSET use_clk_valid=false
+CSET use_clkfb_stopped=false
+CSET use_dyn_phase_shift=false
+CSET use_dyn_reconfig=false
+CSET use_freeze=false
+CSET use_freq_synth=true
+CSET use_inclk_stopped=false
+CSET use_inclk_switchover=false
+CSET use_locked=true
+CSET use_max_i_jitter=false
+CSET use_min_o_jitter=false
+CSET use_min_power=false
+CSET use_phase_alignment=true
+CSET use_power_down=false
+CSET use_reset=false
+CSET use_spread_spectrum=false
+CSET use_spread_spectrum_1=false
+CSET use_status=false
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-05-10T12:44:55Z
+# END Extra information
+GENERATE
+# CRC: 51445c78
Index: aeon_lite/pll/pll_xmdf.tcl
===================================================================
--- aeon_lite/pll/pll_xmdf.tcl	(nonexistent)
+++ aeon_lite/pll/pll_xmdf.tcl	(revision 149)
@@ -0,0 +1,128 @@
+# The package naming convention is <core_name>_xmdf
+package provide pll_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::pll_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::pll_xmdf::xmdfInit { instance } {
+# Variable containg name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name pll
+}
+# ::pll_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::pll_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be magically
+# available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/clk_wiz_readme.txt
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/doc/clk_wiz_ds709.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/doc/clk_wiz_gsg521.pdf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/implement/implement.bat
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/implement/implement.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/implement/xst.prj
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/implement/xst.scr
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/pll_tb.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/functional/simcmds.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/functional/simulate_isim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/functional/simulate_mti.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/functional/simulate_ncsim.sh
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/functional/wave.do
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll/simulation/functional/wave.sv
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll.asy
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll.ejp
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll.vho
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path pll_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module pll
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams
Index: aeon_lite/pll/pll.vho
===================================================================
--- aeon_lite/pll/pll.vho	(nonexistent)
+++ aeon_lite/pll/pll.vho	(revision 149)
@@ -0,0 +1,93 @@
+-- 
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+-- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+------------------------------------------------------------------------------
+-- CLK_OUT1____28.676______0.000______50.0______292.034____257.452
+-- CLK_OUT2____57.353______0.000______50.0______239.345____257.452
+--
+------------------------------------------------------------------------------
+-- "Input Clock   Freq (MHz)    Input Jitter (UI)"
+------------------------------------------------------------------------------
+-- __primary______________50____________0.010
+
+
+-- The following code must appear in the VHDL architecture header:
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component pll
+port
+ (-- Clock in ports
+  CLKIN           : in     std_logic;
+  -- Clock out ports
+  CLKOUT          : out    std_logic;
+  CLKOUT2          : out    std_logic;
+  -- Status and control signals
+  LOCKED            : out    std_logic
+ );
+end component;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : pll
+  port map
+   (-- Clock in ports
+    CLKIN => CLKIN,
+    -- Clock out ports
+    CLKOUT => CLKOUT,
+    CLKOUT2 => CLKOUT2,
+    -- Status and control signals
+    LOCKED => LOCKED);
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
Index: aeon_lite/pll/pll_flist.txt
===================================================================
--- aeon_lite/pll/pll_flist.txt	(nonexistent)
+++ aeon_lite/pll/pll_flist.txt	(revision 149)
@@ -0,0 +1,53 @@
+# Output products list for <pll>
+_xmsgs\pn_parser.xmsgs
+pll.asy
+pll.gise
+pll.sym
+pll.ucf
+pll.vhd
+pll.vho
+pll.xco
+pll.xdc
+pll.xise
+pll\clk_wiz_v3_6_readme.txt
+pll\doc\clk_wiz_v3_6_readme.txt
+pll\doc\clk_wiz_v3_6_vinfo.html
+pll\doc\pg065_clk_wiz.pdf
+pll\example_design\pll_exdes.ucf
+pll\example_design\pll_exdes.vhd
+pll\example_design\pll_exdes.xdc
+pll\implement\implement.bat
+pll\implement\implement.sh
+pll\implement\planAhead_ise.bat
+pll\implement\planAhead_ise.sh
+pll\implement\planAhead_ise.tcl
+pll\implement\planAhead_rdn.bat
+pll\implement\planAhead_rdn.sh
+pll\implement\planAhead_rdn.tcl
+pll\implement\xst.prj
+pll\implement\xst.scr
+pll\simulation\functional\simcmds.tcl
+pll\simulation\functional\simulate_isim.bat
+pll\simulation\functional\simulate_isim.sh
+pll\simulation\functional\simulate_mti.bat
+pll\simulation\functional\simulate_mti.do
+pll\simulation\functional\simulate_mti.sh
+pll\simulation\functional\simulate_ncsim.sh
+pll\simulation\functional\simulate_vcs.sh
+pll\simulation\functional\wave.do
+pll\simulation\functional\wave.sv
+pll\simulation\pll_tb.vhd
+pll\simulation\timing\pll_tb.vhd
+pll\simulation\timing\sdf_cmd_file
+pll\simulation\timing\simcmds.tcl
+pll\simulation\timing\simulate_isim.sh
+pll\simulation\timing\simulate_mti.bat
+pll\simulation\timing\simulate_mti.do
+pll\simulation\timing\simulate_mti.sh
+pll\simulation\timing\simulate_ncsim.sh
+pll\simulation\timing\simulate_vcs.sh
+pll\simulation\timing\ucli_commands.key
+pll\simulation\timing\vcs_session.tcl
+pll\simulation\timing\wave.do
+pll_flist.txt
+pll_xmdf.tcl
Index: aeon_lite/pll/pll.vhd
===================================================================
--- aeon_lite/pll/pll.vhd	(nonexistent)
+++ aeon_lite/pll/pll.vhd	(revision 149)
@@ -0,0 +1,172 @@
+-- file: pll.vhd
+-- 
+-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- "Output    Output      Phase     Duty      Pk-to-Pk        Phase"
+-- "Clock    Freq (MHz) (degrees) Cycle (%) Jitter (ps)  Error (ps)"
+------------------------------------------------------------------------------
+-- CLK_OUT1____28.676______0.000______50.0______292.034____257.452
+-- CLK_OUT2____57.353______0.000______50.0______239.345____257.452
+--
+------------------------------------------------------------------------------
+-- "Input Clock   Freq (MHz)    Input Jitter (UI)"
+------------------------------------------------------------------------------
+-- __primary______________50____________0.010
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.std_logic_arith.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity pll is
+port
+ (-- Clock in ports
+  CLKIN           : in     std_logic;
+  -- Clock out ports
+  CLKOUT          : out    std_logic;
+  CLKOUT2          : out    std_logic;
+  -- Status and control signals
+  LOCKED            : out    std_logic
+ );
+end pll;
+
+architecture xilinx of pll is
+  attribute CORE_GENERATION_INFO : string;
+  attribute CORE_GENERATION_INFO of xilinx : architecture is "pll,clk_wiz_v3_6,{component_name=pll,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=20.000,clkin2_period=20.000,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
+  -- Input clock buffering / unused connectors
+  signal clkin1      : std_logic;
+  -- Output clock buffering / unused connectors
+  signal clkfbout         : std_logic;
+  signal clkfbout_buf     : std_logic;
+  signal clkout0          : std_logic;
+  signal clkout1          : std_logic;
+  signal clkout2_unused   : std_logic;
+  signal clkout3_unused   : std_logic;
+  signal clkout4_unused   : std_logic;
+  signal clkout5_unused   : std_logic;
+  -- Unused status signals
+
+begin
+
+
+  -- Input buffering
+  --------------------------------------
+  clkin1_buf : IBUFG
+  port map
+   (O => clkin1,
+    I => CLKIN);
+
+
+  -- Clocking primitive
+  --------------------------------------
+  -- Instantiation of the PLL primitive
+  --    * Unused inputs are tied off
+  --    * Unused outputs are labeled unused
+
+  pll_base_inst : PLL_BASE
+  generic map
+   (BANDWIDTH            => "OPTIMIZED",
+    CLK_FEEDBACK         => "CLKFBOUT",
+    COMPENSATION         => "SYSTEM_SYNCHRONOUS",
+    DIVCLK_DIVIDE        => 2,
+    CLKFBOUT_MULT        => 39,
+    CLKFBOUT_PHASE       => 0.000,
+    CLKOUT0_DIVIDE       => 34,
+    CLKOUT0_PHASE        => 0.000,
+    CLKOUT0_DUTY_CYCLE   => 0.500,
+    CLKOUT1_DIVIDE       => 17,
+    CLKOUT1_PHASE        => 0.000,
+    CLKOUT1_DUTY_CYCLE   => 0.500,
+    CLKIN_PERIOD         => 20.000,
+    REF_JITTER           => 0.010)
+  port map
+    -- Output clocks
+   (CLKFBOUT            => clkfbout,
+    CLKOUT0             => clkout0,
+    CLKOUT1             => clkout1,
+    CLKOUT2             => clkout2_unused,
+    CLKOUT3             => clkout3_unused,
+    CLKOUT4             => clkout4_unused,
+    CLKOUT5             => clkout5_unused,
+    -- Status and control signals
+    LOCKED              => LOCKED,
+    RST                 => '0',
+    -- Input clock control
+    CLKFBIN             => clkfbout_buf,
+    CLKIN               => clkin1);
+
+  -- Output buffering
+  -------------------------------------
+  clkf_buf : BUFG
+  port map
+   (O => clkfbout_buf,
+    I => clkfbout);
+
+
+  clkout1_buf : BUFG
+  port map
+   (O   => CLKOUT,
+    I   => clkout0);
+
+
+
+  clkout2_buf : BUFG
+  port map
+   (O   => CLKOUT2,
+    I   => clkout1);
+
+end xilinx;
Index: aeon_lite/pll/pll.xise
===================================================================
--- aeon_lite/pll/pll.xise	(nonexistent)
+++ aeon_lite/pll/pll.xise	(revision 149)
@@ -0,0 +1,74 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="pll.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="pll.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|pll|xilinx" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="pll.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/pll" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="pll" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-07-23T21:14:11" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="81FEB3840ACE4C7C9F4657A3E975FFC2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings>
+    <binding xil_pn:location="/pll" xil_pn:name="pll.ucf"/>
+  </bindings>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>
