Index: atari_chips/pokeyv2/lvds_rx_sim/lvds_rx.vhd
===================================================================
--- atari_chips/pokeyv2/lvds_rx_sim/lvds_rx.vhd	(revision 1425)
+++ atari_chips/pokeyv2/lvds_rx_sim/lvds_rx.vhd	(nonexistent)
@@ -1,35 +0,0 @@
--- lvds_rx.vhd
-
--- Generated using ACDS version 23.1 993
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity lvds_rx is
-	port (
-		data  : in  std_logic_vector(0 downto 0) := (others => '0'); --  data.data
-		clock : in  std_logic                    := '0';             -- clock.clock
-		q     : out std_logic_vector(0 downto 0)                     --     q.q
-	);
-end entity lvds_rx;
-
-architecture rtl of lvds_rx is
-	component altera_soft_lvds_rx_uCmNW05P is
-		port (
-			data  : in  std_logic_vector(0 downto 0) := (others => 'X'); -- data
-			clock : in  std_logic                    := 'X';             -- clock
-			q     : out std_logic_vector(0 downto 0)                     -- q
-		);
-	end component altera_soft_lvds_rx_uCmNW05P;
-
-begin
-
-	lvds_rx_inst : component altera_soft_lvds_rx_uCmNW05P
-		port map (
-			data  => data,  --  data.data
-			clock => clock, -- clock.clock
-			q     => q      --     q.q
-		);
-
-end architecture rtl; -- of lvds_rx
Index: atari_chips/pokeyv2/lvds_rx_sim/cadence/cds_libs/lvds_rx.cds.lib
===================================================================
--- atari_chips/pokeyv2/lvds_rx_sim/cadence/cds_libs/lvds_rx.cds.lib	(revision 1425)
+++ atari_chips/pokeyv2/lvds_rx_sim/cadence/cds_libs/lvds_rx.cds.lib	(nonexistent)
@@ -1,23 +0,0 @@
-
-DEFINE std             $CDS_ROOT/tools/inca/files/STD/           
-DEFINE synopsys        $CDS_ROOT/tools/inca/files/SYNOPSYS/      
-DEFINE ieee            $CDS_ROOT/tools/inca/files/IEEE/          
-DEFINE ambit           $CDS_ROOT/tools/inca/files/AMBIT/         
-DEFINE vital_memory    $CDS_ROOT/tools/inca/files/VITAL_MEMORY/  
-DEFINE ncutils         $CDS_ROOT/tools/inca/files/NCUTILS/       
-DEFINE ncinternal      $CDS_ROOT/tools/inca/files/NCINTERNAL/    
-DEFINE ncmodels        $CDS_ROOT/tools/inca/files/NCMODELS/      
-DEFINE cds_assertions  $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
-DEFINE work            ./../libraries/work/                      
-DEFINE altera_ver      ./../libraries/altera_ver/                
-DEFINE lpm_ver         ./../libraries/lpm_ver/                   
-DEFINE sgate_ver       ./../libraries/sgate_ver/                 
-DEFINE altera_mf_ver   ./../libraries/altera_mf_ver/             
-DEFINE fiftyfivenm_ver ./../libraries/fiftyfivenm_ver/           
-DEFINE altera          ./../libraries/altera/                    
-DEFINE lpm             ./../libraries/lpm/                       
-DEFINE sgate           ./../libraries/sgate/                     
-DEFINE altera_mf       ./../libraries/altera_mf/                 
-DEFINE altera_lnsim    ./../libraries/altera_lnsim/              
-DEFINE fiftyfivenm     ./../libraries/fiftyfivenm/               
-DEFINE lvds_rx         ./../libraries/lvds_rx/                   
Index: atari_chips/pokeyv2/lvds_rx_sim/cadence/ncsim_setup.sh
===================================================================
--- atari_chips/pokeyv2/lvds_rx_sim/cadence/ncsim_setup.sh	(revision 1425)
+++ atari_chips/pokeyv2/lvds_rx_sim/cadence/ncsim_setup.sh	(nonexistent)
@@ -1,210 +0,0 @@
-
-# (C) 2001-2021 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and 
-# other software and tools, and its AMPP partner logic functions, and 
-# any output files any of the foregoing (including device programming 
-# or simulation files), and any associated documentation or information 
-# are expressly subject to the terms and conditions of the Altera 
-# Program License Subscription Agreement, Altera MegaCore Function 
-# License Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by Altera 
-# or its authorized distributors. Please refer to the applicable 
-# agreement for further details.
-
-# ACDS 20.1 720 linux 2021.04.24.15:13:51
-
-# ----------------------------------------
-# ncsim - auto-generated simulation script
-
-# ----------------------------------------
-# This script provides commands to simulate the following IP detected in
-# your Quartus project:
-#     lvds_rx
-# 
-# Altera recommends that you source this Quartus-generated IP simulation
-# script from your own customized top-level script, and avoid editing this
-# generated script.
-# 
-# To write a top-level shell script that compiles Altera simulation libraries
-# and the Quartus-generated IP in your project, along with your design and
-# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
-# into a new file, e.g. named "ncsim.sh", and modify text as directed.
-# 
-# You can also modify the simulation flow to suit your needs. Set the
-# following variables to 1 to disable their corresponding processes:
-# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
-# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
-# - SKIP_COM: skip compiling Quartus-generated IP simulation files
-# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
-# 
-# ----------------------------------------
-# # TOP-LEVEL TEMPLATE - BEGIN
-# #
-# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
-# # construct paths to the files required to simulate the IP in your Quartus
-# # project. By default, the IP script assumes that you are launching the
-# # simulator from the IP script location. If launching from another
-# # location, set QSYS_SIMDIR to the output directory you specified when you
-# # generated the IP script, relative to the directory from which you launch
-# # the simulator. In this case, you must also copy the generated files
-# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated - 
-# # into the location from which you launch the simulator, or incorporate
-# # into any existing library setup.
-# #
-# # Run Quartus-generated IP simulation script once to compile Quartus EDA
-# # simulation libraries and Quartus-generated IP simulation files, and copy
-# # any ROM/RAM initialization files to the simulation directory.
-# # - If necessary, specify any compilation options:
-# #   USER_DEFINED_COMPILE_OPTIONS
-# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
-# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
-# #
-# source <script generation output directory>/cadence/ncsim_setup.sh \
-# SKIP_ELAB=1 \
-# SKIP_SIM=1 \
-# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
-# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
-# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
-# QSYS_SIMDIR=<script generation output directory>
-# #
-# # Compile all design files and testbench files, including the top level.
-# # (These are all the files required for simulation other than the files
-# # compiled by the IP script)
-# #
-# ncvlog <compilation options> <design and testbench files>
-# #
-# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
-# # testbench module/entity name.
-# #
-# # Run the IP script again to elaborate and simulate the top level:
-# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
-# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
-# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
-# #
-# source <script generation output directory>/cadence/ncsim_setup.sh \
-# SKIP_FILE_COPY=1 \
-# SKIP_DEV_COM=1 \
-# SKIP_COM=1 \
-# TOP_LEVEL_NAME=<simulation top> \
-# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
-# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
-# #
-# # TOP-LEVEL TEMPLATE - END
-# ----------------------------------------
-# 
-# IP SIMULATION SCRIPT
-# ----------------------------------------
-# If lvds_rx is one of several IP cores in your
-# Quartus project, you can generate a simulation script
-# suitable for inclusion in your top-level simulation
-# script by running the following command line:
-# 
-# ip-setup-simulation --quartus-project=<quartus project>
-# 
-# ip-setup-simulation will discover the Altera IP
-# within the Quartus project, and generate a unified
-# script which supports all the Altera IP within the design.
-# ----------------------------------------
-# ACDS 20.1 720 linux 2021.04.24.15:13:51
-# ----------------------------------------
-# initialize variables
-TOP_LEVEL_NAME="lvds_rx"
-QSYS_SIMDIR="./../"
-QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/20.1/quartus/"
-SKIP_FILE_COPY=0
-SKIP_DEV_COM=0
-SKIP_COM=0
-SKIP_ELAB=0
-SKIP_SIM=0
-USER_DEFINED_ELAB_OPTIONS=""
-USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
-
-# ----------------------------------------
-# overwrite variables - DO NOT MODIFY!
-# This block evaluates each command line argument, typically used for 
-# overwriting variables. An example usage:
-#   sh <simulator>_setup.sh SKIP_SIM=1
-for expression in "$@"; do
-  eval $expression
-  if [ $? -ne 0 ]; then
-    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
-    exit $?
-  fi
-done
-
-# ----------------------------------------
-# initialize simulation properties - DO NOT MODIFY!
-ELAB_OPTIONS=""
-SIM_OPTIONS=""
-if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
-  :
-else
-  :
-fi
-
-# ----------------------------------------
-# create compilation libraries
-mkdir -p ./libraries/work/
-mkdir -p ./libraries/lvds_rx/
-mkdir -p ./libraries/altera_ver/
-mkdir -p ./libraries/lpm_ver/
-mkdir -p ./libraries/sgate_ver/
-mkdir -p ./libraries/altera_mf_ver/
-mkdir -p ./libraries/fiftyfivenm_ver/
-mkdir -p ./libraries/altera/
-mkdir -p ./libraries/lpm/
-mkdir -p ./libraries/sgate/
-mkdir -p ./libraries/altera_mf/
-mkdir -p ./libraries/altera_lnsim/
-mkdir -p ./libraries/fiftyfivenm/
-
-# ----------------------------------------
-# copy RAM/ROM files to simulation directory
-
-# ----------------------------------------
-# compile device library files
-if [ $SKIP_DEV_COM -eq 0 ]; then
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"                -work altera_ver     
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                         -work lpm_ver        
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                            -work sgate_ver      
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                        -work altera_mf_ver  
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v"                -work fiftyfivenm_ver
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"          -work altera         
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"      -work altera         
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"         -work altera         
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"      -work altera         
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd"   -work altera         
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"              -work altera         
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                        -work lpm            
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                       -work lpm            
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                     -work sgate          
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                          -work sgate          
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"           -work altera_mf      
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                      -work altera_mf      
-  ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                    -work altera_lnsim   
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"        -work altera_lnsim   
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm    
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.vhd"              -work fiftyfivenm    
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_components.vhd"         -work fiftyfivenm    
-fi
-
-# ----------------------------------------
-# compile design files in correct order
-if [ $SKIP_COM -eq 0 ]; then
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_rx_twD2Tqf3.v" -work lvds_rx -cdslib ./cds_libs/lvds_rx.cds.lib
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/lvds_rx.vhd"                                                                                     
-fi
-
-# ----------------------------------------
-# elaborate top level design
-if [ $SKIP_ELAB -eq 0 ]; then
-  export GENERIC_PARAM_COMPAT_CHECK=1
-  ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
-fi
-
-# ----------------------------------------
-# simulate
-if [ $SKIP_SIM -eq 0 ]; then
-  eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
-fi

Property changes on: atari_chips/pokeyv2/lvds_rx_sim/cadence/ncsim_setup.sh
___________________________________________________________________
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: atari_chips/pokeyv2/lvds_rx_sim/cadence/cds.lib
===================================================================
--- atari_chips/pokeyv2/lvds_rx_sim/cadence/cds.lib	(revision 1425)
+++ atari_chips/pokeyv2/lvds_rx_sim/cadence/cds.lib	(nonexistent)
@@ -1,23 +0,0 @@
-
-DEFINE std             $CDS_ROOT/tools/inca/files/STD/           
-DEFINE synopsys        $CDS_ROOT/tools/inca/files/SYNOPSYS/      
-DEFINE ieee            $CDS_ROOT/tools/inca/files/IEEE/          
-DEFINE ambit           $CDS_ROOT/tools/inca/files/AMBIT/         
-DEFINE vital_memory    $CDS_ROOT/tools/inca/files/VITAL_MEMORY/  
-DEFINE ncutils         $CDS_ROOT/tools/inca/files/NCUTILS/       
-DEFINE ncinternal      $CDS_ROOT/tools/inca/files/NCINTERNAL/    
-DEFINE ncmodels        $CDS_ROOT/tools/inca/files/NCMODELS/      
-DEFINE cds_assertions  $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
-DEFINE work            ./libraries/work/                         
-DEFINE lvds_rx         ./libraries/lvds_rx/                      
-DEFINE altera_ver      ./libraries/altera_ver/                   
-DEFINE lpm_ver         ./libraries/lpm_ver/                      
-DEFINE sgate_ver       ./libraries/sgate_ver/                    
-DEFINE altera_mf_ver   ./libraries/altera_mf_ver/                
-DEFINE fiftyfivenm_ver ./libraries/fiftyfivenm_ver/              
-DEFINE altera          ./libraries/altera/                       
-DEFINE lpm             ./libraries/lpm/                          
-DEFINE sgate           ./libraries/sgate/                        
-DEFINE altera_mf       ./libraries/altera_mf/                    
-DEFINE altera_lnsim    ./libraries/altera_lnsim/                 
-DEFINE fiftyfivenm     ./libraries/fiftyfivenm/                  
Index: atari_chips/pokeyv2/lvds_rx_sim/cadence/hdl.var
===================================================================
--- atari_chips/pokeyv2/lvds_rx_sim/cadence/hdl.var	(revision 1425)
+++ atari_chips/pokeyv2/lvds_rx_sim/cadence/hdl.var	(nonexistent)
@@ -1,2 +0,0 @@
-
-DEFINE WORK work
Index: atari_chips/pokeyv2/lvds_rx_sim/mentor/msim_setup.tcl
===================================================================
--- atari_chips/pokeyv2/lvds_rx_sim/mentor/msim_setup.tcl	(revision 1425)
+++ atari_chips/pokeyv2/lvds_rx_sim/mentor/msim_setup.tcl	(nonexistent)
@@ -1,294 +0,0 @@
-
-# (C) 2001-2024 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and 
-# other software and tools, and its AMPP partner logic functions, and 
-# any output files any of the foregoing (including device programming 
-# or simulation files), and any associated documentation or information 
-# are expressly subject to the terms and conditions of the Altera 
-# Program License Subscription Agreement, Altera MegaCore Function 
-# License Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by Altera 
-# or its authorized distributors. Please refer to the applicable 
-# agreement for further details.
-
-# ----------------------------------------
-# Auto-generated simulation script msim_setup.tcl
-# ----------------------------------------
-# This script provides commands to simulate the following IP detected in
-# your Quartus project:
-#     lvds_rx
-# 
-# Altera recommends that you source this Quartus-generated IP simulation
-# script from your own customized top-level script, and avoid editing this
-# generated script.
-# 
-# To write a top-level script that compiles Altera simulation libraries and
-# the Quartus-generated IP in your project, along with your design and
-# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
-# into a new file, e.g. named "mentor.do", and modify the text as directed.
-# 
-# ----------------------------------------
-# # TOP-LEVEL TEMPLATE - BEGIN
-# #
-# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
-# # construct paths to the files required to simulate the IP in your Quartus
-# # project. By default, the IP script assumes that you are launching the
-# # simulator from the IP script location. If launching from another
-# # location, set QSYS_SIMDIR to the output directory you specified when you
-# # generated the IP script, relative to the directory from which you launch
-# # the simulator.
-# #
-# set QSYS_SIMDIR <script generation output directory>
-# #
-# # Source the generated IP simulation script.
-# source $QSYS_SIMDIR/mentor/msim_setup.tcl
-# #
-# # Set any compilation options you require (this is unusual).
-# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
-# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
-# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
-# #
-# # Call command to compile the Quartus EDA simulation library.
-# dev_com
-# #
-# # Call command to compile the Quartus-generated IP simulation files.
-# com
-# #
-# # Add commands to compile all design files and testbench files, including
-# # the top level. (These are all the files required for simulation other
-# # than the files compiled by the Quartus-generated IP simulation script)
-# #
-# vlog <compilation options> <design and testbench files>
-# #
-# # Set the top-level simulation or testbench module/entity name, which is
-# # used by the elab command to elaborate the top level.
-# #
-# set TOP_LEVEL_NAME <simulation top>
-# #
-# # Set any elaboration options you require.
-# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
-# #
-# # Call command to elaborate your design and testbench.
-# elab
-# #
-# # Run the simulation.
-# run -a
-# #
-# # Report success to the shell.
-# exit -code 0
-# #
-# # TOP-LEVEL TEMPLATE - END
-# ----------------------------------------
-# 
-# IP SIMULATION SCRIPT
-# ----------------------------------------
-# If lvds_rx is one of several IP cores in your
-# Quartus project, you can generate a simulation script
-# suitable for inclusion in your top-level simulation
-# script by running the following command line:
-# 
-# ip-setup-simulation --quartus-project=<quartus project>
-# 
-# ip-setup-simulation will discover the Altera IP
-# within the Quartus project, and generate a unified
-# script which supports all the Altera IP within the design.
-# ----------------------------------------
-# ACDS 23.1 993 linux 2024.08.31.14:19:57
-
-# ----------------------------------------
-# Initialize variables
-if ![info exists SYSTEM_INSTANCE_NAME] { 
-  set SYSTEM_INSTANCE_NAME ""
-} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
-  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
-}
-
-if ![info exists TOP_LEVEL_NAME] { 
-  set TOP_LEVEL_NAME "lvds_rx"
-}
-
-if ![info exists QSYS_SIMDIR] { 
-  set QSYS_SIMDIR "./../"
-}
-
-if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/23.1std/quartus/"
-}
-
-if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
-  set USER_DEFINED_COMPILE_OPTIONS ""
-}
-if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
-  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
-}
-if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
-  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
-}
-if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
-  set USER_DEFINED_ELAB_OPTIONS ""
-}
-
-# ----------------------------------------
-# Initialize simulation properties - DO NOT MODIFY!
-set ELAB_OPTIONS ""
-set SIM_OPTIONS ""
-if ![ string match "*-64 vsim*" [ vsim -version ] ] {
-} else {
-}
-
-# ----------------------------------------
-# Copy ROM/RAM files to simulation directory
-alias file_copy {
-  echo "\[exec\] file_copy"
-}
-
-# ----------------------------------------
-# Create compilation libraries
-proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
-ensure_lib          ./libraries/     
-ensure_lib          ./libraries/work/
-vmap       work     ./libraries/work/
-vmap       work_lib ./libraries/work/
-if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
-  ensure_lib                  ./libraries/altera_ver/      
-  vmap       altera_ver       ./libraries/altera_ver/      
-  ensure_lib                  ./libraries/lpm_ver/         
-  vmap       lpm_ver          ./libraries/lpm_ver/         
-  ensure_lib                  ./libraries/sgate_ver/       
-  vmap       sgate_ver        ./libraries/sgate_ver/       
-  ensure_lib                  ./libraries/altera_mf_ver/   
-  vmap       altera_mf_ver    ./libraries/altera_mf_ver/   
-  ensure_lib                  ./libraries/altera_lnsim_ver/
-  vmap       altera_lnsim_ver ./libraries/altera_lnsim_ver/
-  ensure_lib                  ./libraries/fiftyfivenm_ver/ 
-  vmap       fiftyfivenm_ver  ./libraries/fiftyfivenm_ver/ 
-  ensure_lib                  ./libraries/altera/          
-  vmap       altera           ./libraries/altera/          
-  ensure_lib                  ./libraries/lpm/             
-  vmap       lpm              ./libraries/lpm/             
-  ensure_lib                  ./libraries/sgate/           
-  vmap       sgate            ./libraries/sgate/           
-  ensure_lib                  ./libraries/altera_mf/       
-  vmap       altera_mf        ./libraries/altera_mf/       
-  ensure_lib                  ./libraries/altera_lnsim/    
-  vmap       altera_lnsim     ./libraries/altera_lnsim/    
-  ensure_lib                  ./libraries/fiftyfivenm/     
-  vmap       fiftyfivenm      ./libraries/fiftyfivenm/     
-}
-ensure_lib         ./libraries/lvds_rx/
-vmap       lvds_rx ./libraries/lvds_rx/
-
-# ----------------------------------------
-# Compile device library files
-alias dev_com {
-  echo "\[exec\] dev_com"
-  if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"               -work altera_ver      
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                        -work lpm_ver         
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                           -work sgate_ver       
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                       -work altera_mf_ver   
-    eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                   -work altera_lnsim_ver
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v"               -work fiftyfivenm_ver 
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm_ver 
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"         -work altera          
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"     -work altera          
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"        -work altera          
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"     -work altera          
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd"  -work altera          
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"             -work altera          
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                       -work lpm             
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                      -work lpm             
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                    -work sgate           
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                         -work sgate           
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"          -work altera_mf       
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                     -work altera_mf       
-    eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv"   -work altera_lnsim    
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"       -work altera_lnsim    
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm     
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.vhd"             -work fiftyfivenm     
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_components.vhd"        -work fiftyfivenm     
-  }
-}
-
-# ----------------------------------------
-# Compile the design files in correct order
-alias com {
-  echo "\[exec\] com"
-  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_rx_uCmNW05P.v" -work lvds_rx
-  eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS    "$QSYS_SIMDIR/lvds_rx.vhd"                                                  
-}
-
-# ----------------------------------------
-# Elaborate top level design
-alias elab {
-  echo "\[exec\] elab"
-  eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L lvds_rx -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
-}
-
-# ----------------------------------------
-# Elaborate the top level design with -voptargs=+acc option
-alias elab_debug {
-  echo "\[exec\] elab_debug"
-  eval vsim -voptargs=+acc -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L lvds_rx -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
-}
-
-# ----------------------------------------
-# Compile all the design files and elaborate the top level design
-alias ld "
-  dev_com
-  com
-  elab
-"
-
-# ----------------------------------------
-# Compile all the design files and elaborate the top level design with -voptargs=+acc
-alias ld_debug "
-  dev_com
-  com
-  elab_debug
-"
-
-# ----------------------------------------
-# Print out user commmand line aliases
-alias h {
-  echo "List Of Command Line Aliases"
-  echo
-  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
-  echo
-  echo "dev_com                                           -- Compile device library files"
-  echo
-  echo "com                                               -- Compile the design files in correct order"
-  echo
-  echo "elab                                              -- Elaborate top level design"
-  echo
-  echo "elab_debug                                        -- Elaborate the top level design with -voptargs=+acc option"
-  echo
-  echo "ld                                                -- Compile all the design files and elaborate the top level design"
-  echo
-  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -voptargs=+acc"
-  echo
-  echo 
-  echo
-  echo "List Of Variables"
-  echo
-  echo "TOP_LEVEL_NAME                                    -- Top level module name."
-  echo "                                                     For most designs, this should be overridden"
-  echo "                                                     to enable the elab/elab_debug aliases."
-  echo
-  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
-  echo
-  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
-  echo
-  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
-  echo
-  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
-  echo
-  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
-  echo
-  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
-  echo
-  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
-}
-file_copy
-h
Index: atari_chips/pokeyv2/lvds_rx_sim/synopsys/vcsmx/vcsmx_setup.sh
===================================================================
--- atari_chips/pokeyv2/lvds_rx_sim/synopsys/vcsmx/vcsmx_setup.sh	(revision 1425)
+++ atari_chips/pokeyv2/lvds_rx_sim/synopsys/vcsmx/vcsmx_setup.sh	(nonexistent)
@@ -1,213 +0,0 @@
-
-# (C) 2001-2024 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and 
-# other software and tools, and its AMPP partner logic functions, and 
-# any output files any of the foregoing (including device programming 
-# or simulation files), and any associated documentation or information 
-# are expressly subject to the terms and conditions of the Altera 
-# Program License Subscription Agreement, Altera MegaCore Function 
-# License Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by Altera 
-# or its authorized distributors. Please refer to the applicable 
-# agreement for further details.
-
-# ACDS 23.1 993 linux 2024.08.31.14:19:57
-
-# ----------------------------------------
-# vcsmx - auto-generated simulation script
-
-# ----------------------------------------
-# This script provides commands to simulate the following IP detected in
-# your Quartus project:
-#     lvds_rx
-# 
-# Altera recommends that you source this Quartus-generated IP simulation
-# script from your own customized top-level script, and avoid editing this
-# generated script.
-# 
-# To write a top-level shell script that compiles Altera simulation libraries 
-# and the Quartus-generated IP in your project, along with your design and
-# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
-# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
-# 
-# You can also modify the simulation flow to suit your needs. Set the
-# following variables to 1 to disable their corresponding processes:
-# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
-# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
-# - SKIP_COM: skip compiling Quartus-generated IP simulation files
-# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
-# 
-# ----------------------------------------
-# # TOP-LEVEL TEMPLATE - BEGIN
-# #
-# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
-# # construct paths to the files required to simulate the IP in your Quartus
-# # project. By default, the IP script assumes that you are launching the
-# # simulator from the IP script location. If launching from another
-# # location, set QSYS_SIMDIR to the output directory you specified when you
-# # generated the IP script, relative to the directory from which you launch
-# # the simulator. In this case, you must also copy the generated library
-# # setup "synopsys_sim.setup" into the location from which you launch the
-# # simulator, or incorporate into any existing library setup.
-# #
-# # Run Quartus-generated IP simulation script once to compile Quartus EDA
-# # simulation libraries and Quartus-generated IP simulation files, and copy
-# # any ROM/RAM initialization files to the simulation directory.
-# #
-# # - If necessary, specify any compilation options:
-# #   USER_DEFINED_COMPILE_OPTIONS
-# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
-# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
-# #
-# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
-# SKIP_ELAB=1 \
-# SKIP_SIM=1 \
-# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
-# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
-# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
-# QSYS_SIMDIR=<script generation output directory>
-# #
-# # Compile all design files and testbench files, including the top level.
-# # (These are all the files required for simulation other than the files
-# # compiled by the IP script)
-# #
-# vlogan <compilation options> <design and testbench files>
-# #
-# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
-# # testbench module/entity name.
-# #
-# # Run the IP script again to elaborate and simulate the top level:
-# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
-# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
-# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
-# #
-# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
-# SKIP_FILE_COPY=1 \
-# SKIP_DEV_COM=1 \
-# SKIP_COM=1 \
-# TOP_LEVEL_NAME="'-top <simulation top>'" \
-# QSYS_SIMDIR=<script generation output directory> \
-# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
-# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
-# #
-# # TOP-LEVEL TEMPLATE - END
-# ----------------------------------------
-# 
-# IP SIMULATION SCRIPT
-# ----------------------------------------
-# If lvds_rx is one of several IP cores in your
-# Quartus project, you can generate a simulation script
-# suitable for inclusion in your top-level simulation
-# script by running the following command line:
-# 
-# ip-setup-simulation --quartus-project=<quartus project>
-# 
-# ip-setup-simulation will discover the Altera IP
-# within the Quartus project, and generate a unified
-# script which supports all the Altera IP within the design.
-# ----------------------------------------
-# ACDS 23.1 993 linux 2024.08.31.14:19:57
-# ----------------------------------------
-# initialize variables
-TOP_LEVEL_NAME="lvds_rx"
-QSYS_SIMDIR="./../../"
-QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/23.1std/quartus/"
-SKIP_FILE_COPY=0
-SKIP_DEV_COM=0
-SKIP_COM=0
-SKIP_ELAB=0
-SKIP_SIM=0
-USER_DEFINED_ELAB_OPTIONS=""
-USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
-
-# ----------------------------------------
-# overwrite variables - DO NOT MODIFY!
-# This block evaluates each command line argument, typically used for 
-# overwriting variables. An example usage:
-#   sh <simulator>_setup.sh SKIP_SIM=1
-for expression in "$@"; do
-  eval $expression
-  if [ $? -ne 0 ]; then
-    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
-    exit $?
-  fi
-done
-
-# ----------------------------------------
-# initialize simulation properties - DO NOT MODIFY!
-ELAB_OPTIONS=""
-SIM_OPTIONS=""
-if [[ `vcs -platform` != *"amd64"* ]]; then
-  :
-else
-  :
-fi
-
-# ----------------------------------------
-# create compilation libraries
-mkdir -p ./libraries/work/
-mkdir -p ./libraries/lvds_rx/
-mkdir -p ./libraries/altera_ver/
-mkdir -p ./libraries/lpm_ver/
-mkdir -p ./libraries/sgate_ver/
-mkdir -p ./libraries/altera_mf_ver/
-mkdir -p ./libraries/altera_lnsim_ver/
-mkdir -p ./libraries/fiftyfivenm_ver/
-mkdir -p ./libraries/altera/
-mkdir -p ./libraries/lpm/
-mkdir -p ./libraries/sgate/
-mkdir -p ./libraries/altera_mf/
-mkdir -p ./libraries/altera_lnsim/
-mkdir -p ./libraries/fiftyfivenm/
-
-# ----------------------------------------
-# copy RAM/ROM files to simulation directory
-
-# ----------------------------------------
-# compile device library files
-if [ $SKIP_DEV_COM -eq 0 ]; then
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"                 -work altera_ver      
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                          -work lpm_ver         
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                             -work sgate_ver       
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                         -work altera_mf_ver   
-  vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                     -work altera_lnsim_ver
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v"                 -work fiftyfivenm_ver 
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm_ver 
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"           -work altera          
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"       -work altera          
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"          -work altera          
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"       -work altera          
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd"    -work altera          
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"               -work altera          
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                         -work lpm             
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                        -work lpm             
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                      -work sgate           
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                           -work sgate           
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"            -work altera_mf       
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                       -work altera_mf       
-  vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                     -work altera_lnsim    
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"         -work altera_lnsim    
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm     
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.vhd"               -work fiftyfivenm     
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_components.vhd"          -work fiftyfivenm     
-fi
-
-# ----------------------------------------
-# compile design files in correct order
-if [ $SKIP_COM -eq 0 ]; then
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_rx_uCmNW05P.v" -work lvds_rx
-  vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QSYS_SIMDIR/lvds_rx.vhd"                                                  
-fi
-
-# ----------------------------------------
-# elaborate top level design
-if [ $SKIP_ELAB -eq 0 ]; then
-  vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
-fi
-
-# ----------------------------------------
-# simulate
-if [ $SKIP_SIM -eq 0 ]; then
-  ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
-fi

Property changes on: atari_chips/pokeyv2/lvds_rx_sim/synopsys/vcsmx/vcsmx_setup.sh
___________________________________________________________________
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: atari_chips/pokeyv2/lvds_rx_sim/synopsys/vcsmx/synopsys_sim.setup
===================================================================
--- atari_chips/pokeyv2/lvds_rx_sim/synopsys/vcsmx/synopsys_sim.setup	(revision 1425)
+++ atari_chips/pokeyv2/lvds_rx_sim/synopsys/vcsmx/synopsys_sim.setup	(nonexistent)
@@ -1,18 +0,0 @@
-
-WORK > DEFAULT
-DEFAULT:          ./libraries/work/            
-work:             ./libraries/work/            
-lvds_rx:          ./libraries/lvds_rx/         
-altera_ver:       ./libraries/altera_ver/      
-lpm_ver:          ./libraries/lpm_ver/         
-sgate_ver:        ./libraries/sgate_ver/       
-altera_mf_ver:    ./libraries/altera_mf_ver/   
-altera_lnsim_ver: ./libraries/altera_lnsim_ver/
-fiftyfivenm_ver:  ./libraries/fiftyfivenm_ver/ 
-altera:           ./libraries/altera/          
-lpm:              ./libraries/lpm/             
-sgate:            ./libraries/sgate/           
-altera_mf:        ./libraries/altera_mf/       
-altera_lnsim:     ./libraries/altera_lnsim/    
-fiftyfivenm:      ./libraries/fiftyfivenm/     
-LIBRARY_SCAN = TRUE
Index: atari_chips/pokeyv2/lvds_rx_sim/aldec/rivierapro_setup.tcl
===================================================================
--- atari_chips/pokeyv2/lvds_rx_sim/aldec/rivierapro_setup.tcl	(revision 1425)
+++ atari_chips/pokeyv2/lvds_rx_sim/aldec/rivierapro_setup.tcl	(nonexistent)
@@ -1,300 +0,0 @@
-
-# (C) 2001-2024 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and 
-# other software and tools, and its AMPP partner logic functions, and 
-# any output files any of the foregoing (including device programming 
-# or simulation files), and any associated documentation or information 
-# are expressly subject to the terms and conditions of the Altera 
-# Program License Subscription Agreement, Altera MegaCore Function 
-# License Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by Altera 
-# or its authorized distributors. Please refer to the applicable 
-# agreement for further details.
-
-# ACDS 23.1 993 linux 2024.08.31.14:19:57
-# ----------------------------------------
-# Auto-generated simulation script rivierapro_setup.tcl
-# ----------------------------------------
-# This script provides commands to simulate the following IP detected in
-# your Quartus project:
-#     lvds_rx
-# 
-# Altera recommends that you source this Quartus-generated IP simulation
-# script from your own customized top-level script, and avoid editing this
-# generated script.
-# 
-# To write a top-level script that compiles Altera simulation libraries and
-# the Quartus-generated IP in your project, along with your design and
-# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
-# into a new file, e.g. named "aldec.do", and modify the text as directed.
-# 
-# ----------------------------------------
-# # TOP-LEVEL TEMPLATE - BEGIN
-# #
-# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
-# # construct paths to the files required to simulate the IP in your Quartus
-# # project. By default, the IP script assumes that you are launching the
-# # simulator from the IP script location. If launching from another
-# # location, set QSYS_SIMDIR to the output directory you specified when you
-# # generated the IP script, relative to the directory from which you launch
-# # the simulator.
-# #
-# set QSYS_SIMDIR <script generation output directory>
-# #
-# # Source the generated IP simulation script.
-# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
-# #
-# # Set any compilation options you require (this is unusual).
-# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
-# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
-# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
-# #
-# # Call command to compile the Quartus EDA simulation library.
-# dev_com
-# #
-# # Call command to compile the Quartus-generated IP simulation files.
-# com
-# #
-# # Add commands to compile all design files and testbench files, including
-# # the top level. (These are all the files required for simulation other
-# # than the files compiled by the Quartus-generated IP simulation script)
-# #
-# vlog -sv2k5 <your compilation options> <design and testbench files>
-# #
-# # Set the top-level simulation or testbench module/entity name, which is
-# # used by the elab command to elaborate the top level.
-# #
-# set TOP_LEVEL_NAME <simulation top>
-# #
-# # Set any elaboration options you require.
-# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
-# #
-# # Call command to elaborate your design and testbench.
-# elab
-# #
-# # Run the simulation.
-# run
-# #
-# # Report success to the shell.
-# exit -code 0
-# #
-# # TOP-LEVEL TEMPLATE - END
-# ----------------------------------------
-# 
-# IP SIMULATION SCRIPT
-# ----------------------------------------
-# If lvds_rx is one of several IP cores in your
-# Quartus project, you can generate a simulation script
-# suitable for inclusion in your top-level simulation
-# script by running the following command line:
-# 
-# ip-setup-simulation --quartus-project=<quartus project>
-# 
-# ip-setup-simulation will discover the Altera IP
-# within the Quartus project, and generate a unified
-# script which supports all the Altera IP within the design.
-# ----------------------------------------
-
-# ----------------------------------------
-# Initialize variables
-if ![info exists SYSTEM_INSTANCE_NAME] { 
-  set SYSTEM_INSTANCE_NAME ""
-} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
-  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
-}
-
-if ![info exists TOP_LEVEL_NAME] { 
-  set TOP_LEVEL_NAME "lvds_rx"
-}
-
-if ![info exists QSYS_SIMDIR] { 
-  set QSYS_SIMDIR "./../"
-}
-
-if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/23.1std/quartus/"
-}
-
-if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
-  set USER_DEFINED_COMPILE_OPTIONS ""
-}
-if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
-  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
-}
-if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
-  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
-}
-if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
-  set USER_DEFINED_ELAB_OPTIONS ""
-}
-
-# ----------------------------------------
-# Initialize simulation properties - DO NOT MODIFY!
-set ELAB_OPTIONS ""
-set SIM_OPTIONS ""
-if ![ string match "*-64 vsim*" [ vsim -version ] ] {
-} else {
-}
-
-set Aldec "Riviera"
-if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
-  set Aldec "Active"
-}
-
-if { [ string match "Active" $Aldec ] } {
-  scripterconf -tcl
-  createdesign "$TOP_LEVEL_NAME"  "."
-  opendesign "$TOP_LEVEL_NAME"
-}
-
-# ----------------------------------------
-# Copy ROM/RAM files to simulation directory
-alias file_copy {
-  echo "\[exec\] file_copy"
-}
-
-# ----------------------------------------
-# Create compilation libraries
-proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
-ensure_lib      ./libraries     
-ensure_lib      ./libraries/work
-vmap       work ./libraries/work
-ensure_lib                  ./libraries/altera_ver      
-vmap       altera_ver       ./libraries/altera_ver      
-ensure_lib                  ./libraries/lpm_ver         
-vmap       lpm_ver          ./libraries/lpm_ver         
-ensure_lib                  ./libraries/sgate_ver       
-vmap       sgate_ver        ./libraries/sgate_ver       
-ensure_lib                  ./libraries/altera_mf_ver   
-vmap       altera_mf_ver    ./libraries/altera_mf_ver   
-ensure_lib                  ./libraries/altera_lnsim_ver
-vmap       altera_lnsim_ver ./libraries/altera_lnsim_ver
-ensure_lib                  ./libraries/fiftyfivenm_ver 
-vmap       fiftyfivenm_ver  ./libraries/fiftyfivenm_ver 
-ensure_lib                  ./libraries/altera          
-vmap       altera           ./libraries/altera          
-ensure_lib                  ./libraries/lpm             
-vmap       lpm              ./libraries/lpm             
-ensure_lib                  ./libraries/sgate           
-vmap       sgate            ./libraries/sgate           
-ensure_lib                  ./libraries/altera_mf       
-vmap       altera_mf        ./libraries/altera_mf       
-ensure_lib                  ./libraries/altera_lnsim    
-vmap       altera_lnsim     ./libraries/altera_lnsim    
-ensure_lib                  ./libraries/fiftyfivenm     
-vmap       fiftyfivenm      ./libraries/fiftyfivenm     
-ensure_lib         ./libraries/lvds_rx
-vmap       lvds_rx ./libraries/lvds_rx
-
-# ----------------------------------------
-# Compile device library files
-alias dev_com {
-  echo "\[exec\] dev_com"
-  eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"              -work altera_ver      
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                       -work lpm_ver         
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                          -work sgate_ver       
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                      -work altera_mf_ver   
-  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim_ver
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v"              -work fiftyfivenm_ver 
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm_ver 
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera          
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera          
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera          
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera          
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera          
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera          
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm             
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm             
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate           
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate           
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf       
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf       
-  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim    
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim    
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm     
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.vhd"            -work fiftyfivenm     
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_components.vhd"       -work fiftyfivenm     
-}
-
-# ----------------------------------------
-# Compile the design files in correct order
-alias com {
-  echo "\[exec\] com"
-  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_rx_uCmNW05P.v" -work lvds_rx
-  eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QSYS_SIMDIR/lvds_rx.vhd"                                                  
-}
-
-# ----------------------------------------
-# Elaborate top level design
-alias elab {
-  echo "\[exec\] elab"
-  eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L lvds_rx -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
-}
-
-# ----------------------------------------
-# Elaborate the top level design with -dbg -O2 option
-alias elab_debug {
-  echo "\[exec\] elab_debug"
-  eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L lvds_rx -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
-}
-
-# ----------------------------------------
-# Compile all the design files and elaborate the top level design
-alias ld "
-  dev_com
-  com
-  elab
-"
-
-# ----------------------------------------
-# Compile all the design files and elaborate the top level design with -dbg -O2
-alias ld_debug "
-  dev_com
-  com
-  elab_debug
-"
-
-# ----------------------------------------
-# Print out user commmand line aliases
-alias h {
-  echo "List Of Command Line Aliases"
-  echo
-  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
-  echo
-  echo "dev_com                                           -- Compile device library files"
-  echo
-  echo "com                                               -- Compile the design files in correct order"
-  echo
-  echo "elab                                              -- Elaborate top level design"
-  echo
-  echo "elab_debug                                        -- Elaborate the top level design with -dbg -O2 option"
-  echo
-  echo "ld                                                -- Compile all the design files and elaborate the top level design"
-  echo
-  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -dbg -O2"
-  echo
-  echo 
-  echo
-  echo "List Of Variables"
-  echo
-  echo "TOP_LEVEL_NAME                                    -- Top level module name."
-  echo "                                                     For most designs, this should be overridden"
-  echo "                                                     to enable the elab/elab_debug aliases."
-  echo
-  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
-  echo
-  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
-  echo
-  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
-  echo
-  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
-  echo
-  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
-  echo
-  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
-  echo
-  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
-}
-file_copy
-h
Index: atari_chips/pokeyv2/lvds_rx_sim/altera_soft_lvds/altera_soft_lvds_rx_twD2Tqf3.v
===================================================================
--- atari_chips/pokeyv2/lvds_rx_sim/altera_soft_lvds/altera_soft_lvds_rx_twD2Tqf3.v	(revision 1425)
+++ atari_chips/pokeyv2/lvds_rx_sim/altera_soft_lvds/altera_soft_lvds_rx_twD2Tqf3.v	(nonexistent)
@@ -1,58 +0,0 @@
-//lpm_ff CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="ON" LPM_WIDTH=1 clock data q
-//VERSION_BEGIN 20.1 cbx_lpm_ff 2020:11:11:17:03:37:SJ cbx_mgl 2020:11:11:17:50:46:SJ  VERSION_END
-// synthesis VERILOG_INPUT_VERSION VERILOG_2001
-// altera message_off 10463
-
-
-
-// Copyright (C) 2020  Intel Corporation. All rights reserved.
-//  Your use of Intel Corporation's design tools, logic functions 
-//  and other software and tools, and any partner logic 
-//  functions, and any output files from any of the foregoing 
-//  (including device programming or simulation files), and any 
-//  associated documentation or information are expressly subject 
-//  to the terms and conditions of the Intel Program License 
-//  Subscription Agreement, the Intel Quartus Prime License Agreement,
-//  the Intel FPGA IP License Agreement, or other applicable license
-//  agreement, including, without limitation, that your use is for
-//  the sole purpose of programming logic devices manufactured by
-//  Intel and sold by Intel or its authorized distributors.  Please
-//  refer to the applicable agreement for further details, at
-//  https://fpgasoftware.intel.com/eula.
-
-
-
-//synthesis_resources = lut 1 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  altera_soft_lvds_rx_twD2Tqf3
-	( 
-	clock,
-	data,
-	q) /* synthesis synthesis_clearbox=1 */;
-	input   clock;
-	input   [0:0]  data;
-	output   [0:0]  q;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_off
-`endif
-	tri0   [0:0]  data;
-`ifndef ALTERA_RESERVED_QIS
-// synopsys translate_on
-`endif
-
-	reg	[0:0]	ff_dffe;
-	wire enable;
-
-	// synopsys translate_off
-	initial
-		ff_dffe = 0;
-	// synopsys translate_on
-	always @ ( posedge clock)
-		if (enable == 1'b1)   ff_dffe <= data;
-	assign
-		enable = 1'b1,
-		q = ff_dffe;
-endmodule //altera_soft_lvds_rx_twD2Tqf3
-//VALID FILE
Index: atari_chips/pokeyv2/lvds_tx_sim/cadence/cds_libs/lvds_tx.cds.lib
===================================================================
--- atari_chips/pokeyv2/lvds_tx_sim/cadence/cds_libs/lvds_tx.cds.lib	(revision 1425)
+++ atari_chips/pokeyv2/lvds_tx_sim/cadence/cds_libs/lvds_tx.cds.lib	(nonexistent)
@@ -1,23 +0,0 @@
-
-DEFINE std             $CDS_ROOT/tools/inca/files/STD/           
-DEFINE synopsys        $CDS_ROOT/tools/inca/files/SYNOPSYS/      
-DEFINE ieee            $CDS_ROOT/tools/inca/files/IEEE/          
-DEFINE ambit           $CDS_ROOT/tools/inca/files/AMBIT/         
-DEFINE vital_memory    $CDS_ROOT/tools/inca/files/VITAL_MEMORY/  
-DEFINE ncutils         $CDS_ROOT/tools/inca/files/NCUTILS/       
-DEFINE ncinternal      $CDS_ROOT/tools/inca/files/NCINTERNAL/    
-DEFINE ncmodels        $CDS_ROOT/tools/inca/files/NCMODELS/      
-DEFINE cds_assertions  $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
-DEFINE work            ./../libraries/work/                      
-DEFINE altera_ver      ./../libraries/altera_ver/                
-DEFINE lpm_ver         ./../libraries/lpm_ver/                   
-DEFINE sgate_ver       ./../libraries/sgate_ver/                 
-DEFINE altera_mf_ver   ./../libraries/altera_mf_ver/             
-DEFINE fiftyfivenm_ver ./../libraries/fiftyfivenm_ver/           
-DEFINE altera          ./../libraries/altera/                    
-DEFINE lpm             ./../libraries/lpm/                       
-DEFINE sgate           ./../libraries/sgate/                     
-DEFINE altera_mf       ./../libraries/altera_mf/                 
-DEFINE altera_lnsim    ./../libraries/altera_lnsim/              
-DEFINE fiftyfivenm     ./../libraries/fiftyfivenm/               
-DEFINE lvds_tx         ./../libraries/lvds_tx/                   
Index: atari_chips/pokeyv2/lvds_tx_sim/cadence/ncsim_setup.sh
===================================================================
--- atari_chips/pokeyv2/lvds_tx_sim/cadence/ncsim_setup.sh	(revision 1425)
+++ atari_chips/pokeyv2/lvds_tx_sim/cadence/ncsim_setup.sh	(nonexistent)
@@ -1,210 +0,0 @@
-
-# (C) 2001-2021 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and 
-# other software and tools, and its AMPP partner logic functions, and 
-# any output files any of the foregoing (including device programming 
-# or simulation files), and any associated documentation or information 
-# are expressly subject to the terms and conditions of the Altera 
-# Program License Subscription Agreement, Altera MegaCore Function 
-# License Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by Altera 
-# or its authorized distributors. Please refer to the applicable 
-# agreement for further details.
-
-# ACDS 20.1 720 linux 2021.04.24.15:12:23
-
-# ----------------------------------------
-# ncsim - auto-generated simulation script
-
-# ----------------------------------------
-# This script provides commands to simulate the following IP detected in
-# your Quartus project:
-#     lvds_tx
-# 
-# Altera recommends that you source this Quartus-generated IP simulation
-# script from your own customized top-level script, and avoid editing this
-# generated script.
-# 
-# To write a top-level shell script that compiles Altera simulation libraries
-# and the Quartus-generated IP in your project, along with your design and
-# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
-# into a new file, e.g. named "ncsim.sh", and modify text as directed.
-# 
-# You can also modify the simulation flow to suit your needs. Set the
-# following variables to 1 to disable their corresponding processes:
-# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
-# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
-# - SKIP_COM: skip compiling Quartus-generated IP simulation files
-# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
-# 
-# ----------------------------------------
-# # TOP-LEVEL TEMPLATE - BEGIN
-# #
-# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
-# # construct paths to the files required to simulate the IP in your Quartus
-# # project. By default, the IP script assumes that you are launching the
-# # simulator from the IP script location. If launching from another
-# # location, set QSYS_SIMDIR to the output directory you specified when you
-# # generated the IP script, relative to the directory from which you launch
-# # the simulator. In this case, you must also copy the generated files
-# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated - 
-# # into the location from which you launch the simulator, or incorporate
-# # into any existing library setup.
-# #
-# # Run Quartus-generated IP simulation script once to compile Quartus EDA
-# # simulation libraries and Quartus-generated IP simulation files, and copy
-# # any ROM/RAM initialization files to the simulation directory.
-# # - If necessary, specify any compilation options:
-# #   USER_DEFINED_COMPILE_OPTIONS
-# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
-# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
-# #
-# source <script generation output directory>/cadence/ncsim_setup.sh \
-# SKIP_ELAB=1 \
-# SKIP_SIM=1 \
-# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
-# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
-# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
-# QSYS_SIMDIR=<script generation output directory>
-# #
-# # Compile all design files and testbench files, including the top level.
-# # (These are all the files required for simulation other than the files
-# # compiled by the IP script)
-# #
-# ncvlog <compilation options> <design and testbench files>
-# #
-# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
-# # testbench module/entity name.
-# #
-# # Run the IP script again to elaborate and simulate the top level:
-# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
-# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
-# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
-# #
-# source <script generation output directory>/cadence/ncsim_setup.sh \
-# SKIP_FILE_COPY=1 \
-# SKIP_DEV_COM=1 \
-# SKIP_COM=1 \
-# TOP_LEVEL_NAME=<simulation top> \
-# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
-# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
-# #
-# # TOP-LEVEL TEMPLATE - END
-# ----------------------------------------
-# 
-# IP SIMULATION SCRIPT
-# ----------------------------------------
-# If lvds_tx is one of several IP cores in your
-# Quartus project, you can generate a simulation script
-# suitable for inclusion in your top-level simulation
-# script by running the following command line:
-# 
-# ip-setup-simulation --quartus-project=<quartus project>
-# 
-# ip-setup-simulation will discover the Altera IP
-# within the Quartus project, and generate a unified
-# script which supports all the Altera IP within the design.
-# ----------------------------------------
-# ACDS 20.1 720 linux 2021.04.24.15:12:23
-# ----------------------------------------
-# initialize variables
-TOP_LEVEL_NAME="lvds_tx"
-QSYS_SIMDIR="./../"
-QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/20.1/quartus/"
-SKIP_FILE_COPY=0
-SKIP_DEV_COM=0
-SKIP_COM=0
-SKIP_ELAB=0
-SKIP_SIM=0
-USER_DEFINED_ELAB_OPTIONS=""
-USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
-
-# ----------------------------------------
-# overwrite variables - DO NOT MODIFY!
-# This block evaluates each command line argument, typically used for 
-# overwriting variables. An example usage:
-#   sh <simulator>_setup.sh SKIP_SIM=1
-for expression in "$@"; do
-  eval $expression
-  if [ $? -ne 0 ]; then
-    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
-    exit $?
-  fi
-done
-
-# ----------------------------------------
-# initialize simulation properties - DO NOT MODIFY!
-ELAB_OPTIONS=""
-SIM_OPTIONS=""
-if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
-  :
-else
-  :
-fi
-
-# ----------------------------------------
-# create compilation libraries
-mkdir -p ./libraries/work/
-mkdir -p ./libraries/lvds_tx/
-mkdir -p ./libraries/altera_ver/
-mkdir -p ./libraries/lpm_ver/
-mkdir -p ./libraries/sgate_ver/
-mkdir -p ./libraries/altera_mf_ver/
-mkdir -p ./libraries/fiftyfivenm_ver/
-mkdir -p ./libraries/altera/
-mkdir -p ./libraries/lpm/
-mkdir -p ./libraries/sgate/
-mkdir -p ./libraries/altera_mf/
-mkdir -p ./libraries/altera_lnsim/
-mkdir -p ./libraries/fiftyfivenm/
-
-# ----------------------------------------
-# copy RAM/ROM files to simulation directory
-
-# ----------------------------------------
-# compile device library files
-if [ $SKIP_DEV_COM -eq 0 ]; then
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"                -work altera_ver     
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                         -work lpm_ver        
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                            -work sgate_ver      
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                        -work altera_mf_ver  
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v"                -work fiftyfivenm_ver
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"          -work altera         
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"      -work altera         
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"         -work altera         
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"      -work altera         
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd"   -work altera         
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"              -work altera         
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                        -work lpm            
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                       -work lpm            
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                     -work sgate          
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                          -work sgate          
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"           -work altera_mf      
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                      -work altera_mf      
-  ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                    -work altera_lnsim   
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"        -work altera_lnsim   
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm    
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.vhd"              -work fiftyfivenm    
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_components.vhd"         -work fiftyfivenm    
-fi
-
-# ----------------------------------------
-# compile design files in correct order
-if [ $SKIP_COM -eq 0 ]; then
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_tx_twD5CSXW.v" -work lvds_tx -cdslib ./cds_libs/lvds_tx.cds.lib
-  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/lvds_tx.vhd"                                                                                     
-fi
-
-# ----------------------------------------
-# elaborate top level design
-if [ $SKIP_ELAB -eq 0 ]; then
-  export GENERIC_PARAM_COMPAT_CHECK=1
-  ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
-fi
-
-# ----------------------------------------
-# simulate
-if [ $SKIP_SIM -eq 0 ]; then
-  eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
-fi

Property changes on: atari_chips/pokeyv2/lvds_tx_sim/cadence/ncsim_setup.sh
___________________________________________________________________
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: atari_chips/pokeyv2/lvds_tx_sim/cadence/cds.lib
===================================================================
--- atari_chips/pokeyv2/lvds_tx_sim/cadence/cds.lib	(revision 1425)
+++ atari_chips/pokeyv2/lvds_tx_sim/cadence/cds.lib	(nonexistent)
@@ -1,23 +0,0 @@
-
-DEFINE std             $CDS_ROOT/tools/inca/files/STD/           
-DEFINE synopsys        $CDS_ROOT/tools/inca/files/SYNOPSYS/      
-DEFINE ieee            $CDS_ROOT/tools/inca/files/IEEE/          
-DEFINE ambit           $CDS_ROOT/tools/inca/files/AMBIT/         
-DEFINE vital_memory    $CDS_ROOT/tools/inca/files/VITAL_MEMORY/  
-DEFINE ncutils         $CDS_ROOT/tools/inca/files/NCUTILS/       
-DEFINE ncinternal      $CDS_ROOT/tools/inca/files/NCINTERNAL/    
-DEFINE ncmodels        $CDS_ROOT/tools/inca/files/NCMODELS/      
-DEFINE cds_assertions  $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
-DEFINE work            ./libraries/work/                         
-DEFINE lvds_tx         ./libraries/lvds_tx/                      
-DEFINE altera_ver      ./libraries/altera_ver/                   
-DEFINE lpm_ver         ./libraries/lpm_ver/                      
-DEFINE sgate_ver       ./libraries/sgate_ver/                    
-DEFINE altera_mf_ver   ./libraries/altera_mf_ver/                
-DEFINE fiftyfivenm_ver ./libraries/fiftyfivenm_ver/              
-DEFINE altera          ./libraries/altera/                       
-DEFINE lpm             ./libraries/lpm/                          
-DEFINE sgate           ./libraries/sgate/                        
-DEFINE altera_mf       ./libraries/altera_mf/                    
-DEFINE altera_lnsim    ./libraries/altera_lnsim/                 
-DEFINE fiftyfivenm     ./libraries/fiftyfivenm/                  
Index: atari_chips/pokeyv2/lvds_tx_sim/cadence/hdl.var
===================================================================
--- atari_chips/pokeyv2/lvds_tx_sim/cadence/hdl.var	(revision 1425)
+++ atari_chips/pokeyv2/lvds_tx_sim/cadence/hdl.var	(nonexistent)
@@ -1,2 +0,0 @@
-
-DEFINE WORK work
Index: atari_chips/pokeyv2/lvds_tx_sim/lvds_tx.vhd
===================================================================
--- atari_chips/pokeyv2/lvds_tx_sim/lvds_tx.vhd	(revision 1425)
+++ atari_chips/pokeyv2/lvds_tx_sim/lvds_tx.vhd	(nonexistent)
@@ -1,32 +0,0 @@
--- lvds_tx.vhd
-
--- Generated using ACDS version 23.1 993
-
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-entity lvds_tx is
-	port (
-		tx_in  : in  std_logic_vector(0 downto 0) := (others => '0'); --  tx_in.tx_in
-		tx_out : out std_logic_vector(0 downto 0)                     -- tx_out.tx_out
-	);
-end entity lvds_tx;
-
-architecture rtl of lvds_tx is
-	component altera_soft_lvds_tx_uCmMXfGB is
-		port (
-			tx_in  : in  std_logic_vector(0 downto 0) := (others => 'X'); -- tx_in
-			tx_out : out std_logic_vector(0 downto 0)                     -- tx_out
-		);
-	end component altera_soft_lvds_tx_uCmMXfGB;
-
-begin
-
-	lvds_tx_inst : component altera_soft_lvds_tx_uCmMXfGB
-		port map (
-			tx_in  => tx_in,  --  tx_in.tx_in
-			tx_out => tx_out  -- tx_out.tx_out
-		);
-
-end architecture rtl; -- of lvds_tx
Index: atari_chips/pokeyv2/lvds_tx_sim/mentor/msim_setup.tcl
===================================================================
--- atari_chips/pokeyv2/lvds_tx_sim/mentor/msim_setup.tcl	(revision 1425)
+++ atari_chips/pokeyv2/lvds_tx_sim/mentor/msim_setup.tcl	(nonexistent)
@@ -1,294 +0,0 @@
-
-# (C) 2001-2024 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and 
-# other software and tools, and its AMPP partner logic functions, and 
-# any output files any of the foregoing (including device programming 
-# or simulation files), and any associated documentation or information 
-# are expressly subject to the terms and conditions of the Altera 
-# Program License Subscription Agreement, Altera MegaCore Function 
-# License Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by Altera 
-# or its authorized distributors. Please refer to the applicable 
-# agreement for further details.
-
-# ----------------------------------------
-# Auto-generated simulation script msim_setup.tcl
-# ----------------------------------------
-# This script provides commands to simulate the following IP detected in
-# your Quartus project:
-#     lvds_tx
-# 
-# Altera recommends that you source this Quartus-generated IP simulation
-# script from your own customized top-level script, and avoid editing this
-# generated script.
-# 
-# To write a top-level script that compiles Altera simulation libraries and
-# the Quartus-generated IP in your project, along with your design and
-# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
-# into a new file, e.g. named "mentor.do", and modify the text as directed.
-# 
-# ----------------------------------------
-# # TOP-LEVEL TEMPLATE - BEGIN
-# #
-# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
-# # construct paths to the files required to simulate the IP in your Quartus
-# # project. By default, the IP script assumes that you are launching the
-# # simulator from the IP script location. If launching from another
-# # location, set QSYS_SIMDIR to the output directory you specified when you
-# # generated the IP script, relative to the directory from which you launch
-# # the simulator.
-# #
-# set QSYS_SIMDIR <script generation output directory>
-# #
-# # Source the generated IP simulation script.
-# source $QSYS_SIMDIR/mentor/msim_setup.tcl
-# #
-# # Set any compilation options you require (this is unusual).
-# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
-# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
-# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
-# #
-# # Call command to compile the Quartus EDA simulation library.
-# dev_com
-# #
-# # Call command to compile the Quartus-generated IP simulation files.
-# com
-# #
-# # Add commands to compile all design files and testbench files, including
-# # the top level. (These are all the files required for simulation other
-# # than the files compiled by the Quartus-generated IP simulation script)
-# #
-# vlog <compilation options> <design and testbench files>
-# #
-# # Set the top-level simulation or testbench module/entity name, which is
-# # used by the elab command to elaborate the top level.
-# #
-# set TOP_LEVEL_NAME <simulation top>
-# #
-# # Set any elaboration options you require.
-# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
-# #
-# # Call command to elaborate your design and testbench.
-# elab
-# #
-# # Run the simulation.
-# run -a
-# #
-# # Report success to the shell.
-# exit -code 0
-# #
-# # TOP-LEVEL TEMPLATE - END
-# ----------------------------------------
-# 
-# IP SIMULATION SCRIPT
-# ----------------------------------------
-# If lvds_tx is one of several IP cores in your
-# Quartus project, you can generate a simulation script
-# suitable for inclusion in your top-level simulation
-# script by running the following command line:
-# 
-# ip-setup-simulation --quartus-project=<quartus project>
-# 
-# ip-setup-simulation will discover the Altera IP
-# within the Quartus project, and generate a unified
-# script which supports all the Altera IP within the design.
-# ----------------------------------------
-# ACDS 23.1 993 linux 2024.08.31.14:19:17
-
-# ----------------------------------------
-# Initialize variables
-if ![info exists SYSTEM_INSTANCE_NAME] { 
-  set SYSTEM_INSTANCE_NAME ""
-} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
-  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
-}
-
-if ![info exists TOP_LEVEL_NAME] { 
-  set TOP_LEVEL_NAME "lvds_tx"
-}
-
-if ![info exists QSYS_SIMDIR] { 
-  set QSYS_SIMDIR "./../"
-}
-
-if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/23.1std/quartus/"
-}
-
-if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
-  set USER_DEFINED_COMPILE_OPTIONS ""
-}
-if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
-  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
-}
-if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
-  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
-}
-if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
-  set USER_DEFINED_ELAB_OPTIONS ""
-}
-
-# ----------------------------------------
-# Initialize simulation properties - DO NOT MODIFY!
-set ELAB_OPTIONS ""
-set SIM_OPTIONS ""
-if ![ string match "*-64 vsim*" [ vsim -version ] ] {
-} else {
-}
-
-# ----------------------------------------
-# Copy ROM/RAM files to simulation directory
-alias file_copy {
-  echo "\[exec\] file_copy"
-}
-
-# ----------------------------------------
-# Create compilation libraries
-proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
-ensure_lib          ./libraries/     
-ensure_lib          ./libraries/work/
-vmap       work     ./libraries/work/
-vmap       work_lib ./libraries/work/
-if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
-  ensure_lib                  ./libraries/altera_ver/      
-  vmap       altera_ver       ./libraries/altera_ver/      
-  ensure_lib                  ./libraries/lpm_ver/         
-  vmap       lpm_ver          ./libraries/lpm_ver/         
-  ensure_lib                  ./libraries/sgate_ver/       
-  vmap       sgate_ver        ./libraries/sgate_ver/       
-  ensure_lib                  ./libraries/altera_mf_ver/   
-  vmap       altera_mf_ver    ./libraries/altera_mf_ver/   
-  ensure_lib                  ./libraries/altera_lnsim_ver/
-  vmap       altera_lnsim_ver ./libraries/altera_lnsim_ver/
-  ensure_lib                  ./libraries/fiftyfivenm_ver/ 
-  vmap       fiftyfivenm_ver  ./libraries/fiftyfivenm_ver/ 
-  ensure_lib                  ./libraries/altera/          
-  vmap       altera           ./libraries/altera/          
-  ensure_lib                  ./libraries/lpm/             
-  vmap       lpm              ./libraries/lpm/             
-  ensure_lib                  ./libraries/sgate/           
-  vmap       sgate            ./libraries/sgate/           
-  ensure_lib                  ./libraries/altera_mf/       
-  vmap       altera_mf        ./libraries/altera_mf/       
-  ensure_lib                  ./libraries/altera_lnsim/    
-  vmap       altera_lnsim     ./libraries/altera_lnsim/    
-  ensure_lib                  ./libraries/fiftyfivenm/     
-  vmap       fiftyfivenm      ./libraries/fiftyfivenm/     
-}
-ensure_lib         ./libraries/lvds_tx/
-vmap       lvds_tx ./libraries/lvds_tx/
-
-# ----------------------------------------
-# Compile device library files
-alias dev_com {
-  echo "\[exec\] dev_com"
-  if ![ string match "*Intel*FPGA*" [ vsim -version ] ] {
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"               -work altera_ver      
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                        -work lpm_ver         
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                           -work sgate_ver       
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                       -work altera_mf_ver   
-    eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                   -work altera_lnsim_ver
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v"               -work fiftyfivenm_ver 
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm_ver 
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"         -work altera          
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"     -work altera          
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"        -work altera          
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"     -work altera          
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd"  -work altera          
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"             -work altera          
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                       -work lpm             
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                      -work lpm             
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                    -work sgate           
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                         -work sgate           
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"          -work altera_mf       
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                     -work altera_mf       
-    eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv"   -work altera_lnsim    
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"       -work altera_lnsim    
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm     
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.vhd"             -work fiftyfivenm     
-    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_components.vhd"        -work fiftyfivenm     
-  }
-}
-
-# ----------------------------------------
-# Compile the design files in correct order
-alias com {
-  echo "\[exec\] com"
-  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_tx_uCmMXfGB.v" -work lvds_tx
-  eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS    "$QSYS_SIMDIR/lvds_tx.vhd"                                                  
-}
-
-# ----------------------------------------
-# Elaborate top level design
-alias elab {
-  echo "\[exec\] elab"
-  eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L lvds_tx -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
-}
-
-# ----------------------------------------
-# Elaborate the top level design with -voptargs=+acc option
-alias elab_debug {
-  echo "\[exec\] elab_debug"
-  eval vsim -voptargs=+acc -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L lvds_tx -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
-}
-
-# ----------------------------------------
-# Compile all the design files and elaborate the top level design
-alias ld "
-  dev_com
-  com
-  elab
-"
-
-# ----------------------------------------
-# Compile all the design files and elaborate the top level design with -voptargs=+acc
-alias ld_debug "
-  dev_com
-  com
-  elab_debug
-"
-
-# ----------------------------------------
-# Print out user commmand line aliases
-alias h {
-  echo "List Of Command Line Aliases"
-  echo
-  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
-  echo
-  echo "dev_com                                           -- Compile device library files"
-  echo
-  echo "com                                               -- Compile the design files in correct order"
-  echo
-  echo "elab                                              -- Elaborate top level design"
-  echo
-  echo "elab_debug                                        -- Elaborate the top level design with -voptargs=+acc option"
-  echo
-  echo "ld                                                -- Compile all the design files and elaborate the top level design"
-  echo
-  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -voptargs=+acc"
-  echo
-  echo 
-  echo
-  echo "List Of Variables"
-  echo
-  echo "TOP_LEVEL_NAME                                    -- Top level module name."
-  echo "                                                     For most designs, this should be overridden"
-  echo "                                                     to enable the elab/elab_debug aliases."
-  echo
-  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
-  echo
-  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
-  echo
-  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
-  echo
-  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
-  echo
-  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
-  echo
-  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
-  echo
-  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
-}
-file_copy
-h
Index: atari_chips/pokeyv2/lvds_tx_sim/synopsys/vcsmx/synopsys_sim.setup
===================================================================
--- atari_chips/pokeyv2/lvds_tx_sim/synopsys/vcsmx/synopsys_sim.setup	(revision 1425)
+++ atari_chips/pokeyv2/lvds_tx_sim/synopsys/vcsmx/synopsys_sim.setup	(nonexistent)
@@ -1,18 +0,0 @@
-
-WORK > DEFAULT
-DEFAULT:          ./libraries/work/            
-work:             ./libraries/work/            
-lvds_tx:          ./libraries/lvds_tx/         
-altera_ver:       ./libraries/altera_ver/      
-lpm_ver:          ./libraries/lpm_ver/         
-sgate_ver:        ./libraries/sgate_ver/       
-altera_mf_ver:    ./libraries/altera_mf_ver/   
-altera_lnsim_ver: ./libraries/altera_lnsim_ver/
-fiftyfivenm_ver:  ./libraries/fiftyfivenm_ver/ 
-altera:           ./libraries/altera/          
-lpm:              ./libraries/lpm/             
-sgate:            ./libraries/sgate/           
-altera_mf:        ./libraries/altera_mf/       
-altera_lnsim:     ./libraries/altera_lnsim/    
-fiftyfivenm:      ./libraries/fiftyfivenm/     
-LIBRARY_SCAN = TRUE
Index: atari_chips/pokeyv2/lvds_tx_sim/synopsys/vcsmx/vcsmx_setup.sh
===================================================================
--- atari_chips/pokeyv2/lvds_tx_sim/synopsys/vcsmx/vcsmx_setup.sh	(revision 1425)
+++ atari_chips/pokeyv2/lvds_tx_sim/synopsys/vcsmx/vcsmx_setup.sh	(nonexistent)
@@ -1,213 +0,0 @@
-
-# (C) 2001-2024 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and 
-# other software and tools, and its AMPP partner logic functions, and 
-# any output files any of the foregoing (including device programming 
-# or simulation files), and any associated documentation or information 
-# are expressly subject to the terms and conditions of the Altera 
-# Program License Subscription Agreement, Altera MegaCore Function 
-# License Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by Altera 
-# or its authorized distributors. Please refer to the applicable 
-# agreement for further details.
-
-# ACDS 23.1 993 linux 2024.08.31.14:19:17
-
-# ----------------------------------------
-# vcsmx - auto-generated simulation script
-
-# ----------------------------------------
-# This script provides commands to simulate the following IP detected in
-# your Quartus project:
-#     lvds_tx
-# 
-# Altera recommends that you source this Quartus-generated IP simulation
-# script from your own customized top-level script, and avoid editing this
-# generated script.
-# 
-# To write a top-level shell script that compiles Altera simulation libraries 
-# and the Quartus-generated IP in your project, along with your design and
-# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
-# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
-# 
-# You can also modify the simulation flow to suit your needs. Set the
-# following variables to 1 to disable their corresponding processes:
-# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
-# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
-# - SKIP_COM: skip compiling Quartus-generated IP simulation files
-# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
-# 
-# ----------------------------------------
-# # TOP-LEVEL TEMPLATE - BEGIN
-# #
-# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
-# # construct paths to the files required to simulate the IP in your Quartus
-# # project. By default, the IP script assumes that you are launching the
-# # simulator from the IP script location. If launching from another
-# # location, set QSYS_SIMDIR to the output directory you specified when you
-# # generated the IP script, relative to the directory from which you launch
-# # the simulator. In this case, you must also copy the generated library
-# # setup "synopsys_sim.setup" into the location from which you launch the
-# # simulator, or incorporate into any existing library setup.
-# #
-# # Run Quartus-generated IP simulation script once to compile Quartus EDA
-# # simulation libraries and Quartus-generated IP simulation files, and copy
-# # any ROM/RAM initialization files to the simulation directory.
-# #
-# # - If necessary, specify any compilation options:
-# #   USER_DEFINED_COMPILE_OPTIONS
-# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
-# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
-# #
-# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
-# SKIP_ELAB=1 \
-# SKIP_SIM=1 \
-# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
-# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
-# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
-# QSYS_SIMDIR=<script generation output directory>
-# #
-# # Compile all design files and testbench files, including the top level.
-# # (These are all the files required for simulation other than the files
-# # compiled by the IP script)
-# #
-# vlogan <compilation options> <design and testbench files>
-# #
-# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
-# # testbench module/entity name.
-# #
-# # Run the IP script again to elaborate and simulate the top level:
-# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
-# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
-# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
-# #
-# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
-# SKIP_FILE_COPY=1 \
-# SKIP_DEV_COM=1 \
-# SKIP_COM=1 \
-# TOP_LEVEL_NAME="'-top <simulation top>'" \
-# QSYS_SIMDIR=<script generation output directory> \
-# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
-# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
-# #
-# # TOP-LEVEL TEMPLATE - END
-# ----------------------------------------
-# 
-# IP SIMULATION SCRIPT
-# ----------------------------------------
-# If lvds_tx is one of several IP cores in your
-# Quartus project, you can generate a simulation script
-# suitable for inclusion in your top-level simulation
-# script by running the following command line:
-# 
-# ip-setup-simulation --quartus-project=<quartus project>
-# 
-# ip-setup-simulation will discover the Altera IP
-# within the Quartus project, and generate a unified
-# script which supports all the Altera IP within the design.
-# ----------------------------------------
-# ACDS 23.1 993 linux 2024.08.31.14:19:17
-# ----------------------------------------
-# initialize variables
-TOP_LEVEL_NAME="lvds_tx"
-QSYS_SIMDIR="./../../"
-QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/23.1std/quartus/"
-SKIP_FILE_COPY=0
-SKIP_DEV_COM=0
-SKIP_COM=0
-SKIP_ELAB=0
-SKIP_SIM=0
-USER_DEFINED_ELAB_OPTIONS=""
-USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
-
-# ----------------------------------------
-# overwrite variables - DO NOT MODIFY!
-# This block evaluates each command line argument, typically used for 
-# overwriting variables. An example usage:
-#   sh <simulator>_setup.sh SKIP_SIM=1
-for expression in "$@"; do
-  eval $expression
-  if [ $? -ne 0 ]; then
-    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
-    exit $?
-  fi
-done
-
-# ----------------------------------------
-# initialize simulation properties - DO NOT MODIFY!
-ELAB_OPTIONS=""
-SIM_OPTIONS=""
-if [[ `vcs -platform` != *"amd64"* ]]; then
-  :
-else
-  :
-fi
-
-# ----------------------------------------
-# create compilation libraries
-mkdir -p ./libraries/work/
-mkdir -p ./libraries/lvds_tx/
-mkdir -p ./libraries/altera_ver/
-mkdir -p ./libraries/lpm_ver/
-mkdir -p ./libraries/sgate_ver/
-mkdir -p ./libraries/altera_mf_ver/
-mkdir -p ./libraries/altera_lnsim_ver/
-mkdir -p ./libraries/fiftyfivenm_ver/
-mkdir -p ./libraries/altera/
-mkdir -p ./libraries/lpm/
-mkdir -p ./libraries/sgate/
-mkdir -p ./libraries/altera_mf/
-mkdir -p ./libraries/altera_lnsim/
-mkdir -p ./libraries/fiftyfivenm/
-
-# ----------------------------------------
-# copy RAM/ROM files to simulation directory
-
-# ----------------------------------------
-# compile device library files
-if [ $SKIP_DEV_COM -eq 0 ]; then
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"                 -work altera_ver      
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                          -work lpm_ver         
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                             -work sgate_ver       
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                         -work altera_mf_ver   
-  vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                     -work altera_lnsim_ver
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v"                 -work fiftyfivenm_ver 
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm_ver 
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"           -work altera          
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"       -work altera          
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"          -work altera          
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"       -work altera          
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd"    -work altera          
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"               -work altera          
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                         -work lpm             
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                        -work lpm             
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                      -work sgate           
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                           -work sgate           
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"            -work altera_mf       
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                       -work altera_mf       
-  vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                     -work altera_lnsim    
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"         -work altera_lnsim    
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm     
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.vhd"               -work fiftyfivenm     
-  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_components.vhd"          -work fiftyfivenm     
-fi
-
-# ----------------------------------------
-# compile design files in correct order
-if [ $SKIP_COM -eq 0 ]; then
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_tx_uCmMXfGB.v" -work lvds_tx
-  vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QSYS_SIMDIR/lvds_tx.vhd"                                                  
-fi
-
-# ----------------------------------------
-# elaborate top level design
-if [ $SKIP_ELAB -eq 0 ]; then
-  vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
-fi
-
-# ----------------------------------------
-# simulate
-if [ $SKIP_SIM -eq 0 ]; then
-  ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
-fi

Property changes on: atari_chips/pokeyv2/lvds_tx_sim/synopsys/vcsmx/vcsmx_setup.sh
___________________________________________________________________
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: atari_chips/pokeyv2/lvds_tx_sim/aldec/rivierapro_setup.tcl
===================================================================
--- atari_chips/pokeyv2/lvds_tx_sim/aldec/rivierapro_setup.tcl	(revision 1425)
+++ atari_chips/pokeyv2/lvds_tx_sim/aldec/rivierapro_setup.tcl	(nonexistent)
@@ -1,300 +0,0 @@
-
-# (C) 2001-2024 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and 
-# other software and tools, and its AMPP partner logic functions, and 
-# any output files any of the foregoing (including device programming 
-# or simulation files), and any associated documentation or information 
-# are expressly subject to the terms and conditions of the Altera 
-# Program License Subscription Agreement, Altera MegaCore Function 
-# License Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by Altera 
-# or its authorized distributors. Please refer to the applicable 
-# agreement for further details.
-
-# ACDS 23.1 993 linux 2024.08.31.14:19:17
-# ----------------------------------------
-# Auto-generated simulation script rivierapro_setup.tcl
-# ----------------------------------------
-# This script provides commands to simulate the following IP detected in
-# your Quartus project:
-#     lvds_tx
-# 
-# Altera recommends that you source this Quartus-generated IP simulation
-# script from your own customized top-level script, and avoid editing this
-# generated script.
-# 
-# To write a top-level script that compiles Altera simulation libraries and
-# the Quartus-generated IP in your project, along with your design and
-# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
-# into a new file, e.g. named "aldec.do", and modify the text as directed.
-# 
-# ----------------------------------------
-# # TOP-LEVEL TEMPLATE - BEGIN
-# #
-# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
-# # construct paths to the files required to simulate the IP in your Quartus
-# # project. By default, the IP script assumes that you are launching the
-# # simulator from the IP script location. If launching from another
-# # location, set QSYS_SIMDIR to the output directory you specified when you
-# # generated the IP script, relative to the directory from which you launch
-# # the simulator.
-# #
-# set QSYS_SIMDIR <script generation output directory>
-# #
-# # Source the generated IP simulation script.
-# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
-# #
-# # Set any compilation options you require (this is unusual).
-# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
-# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
-# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
-# #
-# # Call command to compile the Quartus EDA simulation library.
-# dev_com
-# #
-# # Call command to compile the Quartus-generated IP simulation files.
-# com
-# #
-# # Add commands to compile all design files and testbench files, including
-# # the top level. (These are all the files required for simulation other
-# # than the files compiled by the Quartus-generated IP simulation script)
-# #
-# vlog -sv2k5 <your compilation options> <design and testbench files>
-# #
-# # Set the top-level simulation or testbench module/entity name, which is
-# # used by the elab command to elaborate the top level.
-# #
-# set TOP_LEVEL_NAME <simulation top>
-# #
-# # Set any elaboration options you require.
-# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
-# #
-# # Call command to elaborate your design and testbench.
-# elab
-# #
-# # Run the simulation.
-# run
-# #
-# # Report success to the shell.
-# exit -code 0
-# #
-# # TOP-LEVEL TEMPLATE - END
-# ----------------------------------------
-# 
-# IP SIMULATION SCRIPT
-# ----------------------------------------
-# If lvds_tx is one of several IP cores in your
-# Quartus project, you can generate a simulation script
-# suitable for inclusion in your top-level simulation
-# script by running the following command line:
-# 
-# ip-setup-simulation --quartus-project=<quartus project>
-# 
-# ip-setup-simulation will discover the Altera IP
-# within the Quartus project, and generate a unified
-# script which supports all the Altera IP within the design.
-# ----------------------------------------
-
-# ----------------------------------------
-# Initialize variables
-if ![info exists SYSTEM_INSTANCE_NAME] { 
-  set SYSTEM_INSTANCE_NAME ""
-} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
-  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
-}
-
-if ![info exists TOP_LEVEL_NAME] { 
-  set TOP_LEVEL_NAME "lvds_tx"
-}
-
-if ![info exists QSYS_SIMDIR] { 
-  set QSYS_SIMDIR "./../"
-}
-
-if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/23.1std/quartus/"
-}
-
-if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
-  set USER_DEFINED_COMPILE_OPTIONS ""
-}
-if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
-  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
-}
-if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
-  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
-}
-if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
-  set USER_DEFINED_ELAB_OPTIONS ""
-}
-
-# ----------------------------------------
-# Initialize simulation properties - DO NOT MODIFY!
-set ELAB_OPTIONS ""
-set SIM_OPTIONS ""
-if ![ string match "*-64 vsim*" [ vsim -version ] ] {
-} else {
-}
-
-set Aldec "Riviera"
-if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
-  set Aldec "Active"
-}
-
-if { [ string match "Active" $Aldec ] } {
-  scripterconf -tcl
-  createdesign "$TOP_LEVEL_NAME"  "."
-  opendesign "$TOP_LEVEL_NAME"
-}
-
-# ----------------------------------------
-# Copy ROM/RAM files to simulation directory
-alias file_copy {
-  echo "\[exec\] file_copy"
-}
-
-# ----------------------------------------
-# Create compilation libraries
-proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
-ensure_lib      ./libraries     
-ensure_lib      ./libraries/work
-vmap       work ./libraries/work
-ensure_lib                  ./libraries/altera_ver      
-vmap       altera_ver       ./libraries/altera_ver      
-ensure_lib                  ./libraries/lpm_ver         
-vmap       lpm_ver          ./libraries/lpm_ver         
-ensure_lib                  ./libraries/sgate_ver       
-vmap       sgate_ver        ./libraries/sgate_ver       
-ensure_lib                  ./libraries/altera_mf_ver   
-vmap       altera_mf_ver    ./libraries/altera_mf_ver   
-ensure_lib                  ./libraries/altera_lnsim_ver
-vmap       altera_lnsim_ver ./libraries/altera_lnsim_ver
-ensure_lib                  ./libraries/fiftyfivenm_ver 
-vmap       fiftyfivenm_ver  ./libraries/fiftyfivenm_ver 
-ensure_lib                  ./libraries/altera          
-vmap       altera           ./libraries/altera          
-ensure_lib                  ./libraries/lpm             
-vmap       lpm              ./libraries/lpm             
-ensure_lib                  ./libraries/sgate           
-vmap       sgate            ./libraries/sgate           
-ensure_lib                  ./libraries/altera_mf       
-vmap       altera_mf        ./libraries/altera_mf       
-ensure_lib                  ./libraries/altera_lnsim    
-vmap       altera_lnsim     ./libraries/altera_lnsim    
-ensure_lib                  ./libraries/fiftyfivenm     
-vmap       fiftyfivenm      ./libraries/fiftyfivenm     
-ensure_lib         ./libraries/lvds_tx
-vmap       lvds_tx ./libraries/lvds_tx
-
-# ----------------------------------------
-# Compile device library files
-alias dev_com {
-  echo "\[exec\] dev_com"
-  eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"              -work altera_ver      
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                       -work lpm_ver         
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                          -work sgate_ver       
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                      -work altera_mf_ver   
-  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim_ver
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v"              -work fiftyfivenm_ver 
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm_ver 
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera          
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera          
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera          
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera          
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera          
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera          
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm             
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm             
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate           
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate           
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf       
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf       
-  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim    
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim    
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm     
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.vhd"            -work fiftyfivenm     
-  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_components.vhd"       -work fiftyfivenm     
-}
-
-# ----------------------------------------
-# Compile the design files in correct order
-alias com {
-  echo "\[exec\] com"
-  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_soft_lvds/altera_soft_lvds_tx_uCmMXfGB.v" -work lvds_tx
-  eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QSYS_SIMDIR/lvds_tx.vhd"                                                  
-}
-
-# ----------------------------------------
-# Elaborate top level design
-alias elab {
-  echo "\[exec\] elab"
-  eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L lvds_tx -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
-}
-
-# ----------------------------------------
-# Elaborate the top level design with -dbg -O2 option
-alias elab_debug {
-  echo "\[exec\] elab_debug"
-  eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L lvds_tx -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
-}
-
-# ----------------------------------------
-# Compile all the design files and elaborate the top level design
-alias ld "
-  dev_com
-  com
-  elab
-"
-
-# ----------------------------------------
-# Compile all the design files and elaborate the top level design with -dbg -O2
-alias ld_debug "
-  dev_com
-  com
-  elab_debug
-"
-
-# ----------------------------------------
-# Print out user commmand line aliases
-alias h {
-  echo "List Of Command Line Aliases"
-  echo
-  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
-  echo
-  echo "dev_com                                           -- Compile device library files"
-  echo
-  echo "com                                               -- Compile the design files in correct order"
-  echo
-  echo "elab                                              -- Elaborate top level design"
-  echo
-  echo "elab_debug                                        -- Elaborate the top level design with -dbg -O2 option"
-  echo
-  echo "ld                                                -- Compile all the design files and elaborate the top level design"
-  echo
-  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -dbg -O2"
-  echo
-  echo 
-  echo
-  echo "List Of Variables"
-  echo
-  echo "TOP_LEVEL_NAME                                    -- Top level module name."
-  echo "                                                     For most designs, this should be overridden"
-  echo "                                                     to enable the elab/elab_debug aliases."
-  echo
-  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
-  echo
-  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
-  echo
-  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
-  echo
-  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
-  echo
-  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
-  echo
-  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
-  echo
-  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
-}
-file_copy
-h
Index: atari_chips/pokeyv2/lvds_tx_sim/altera_soft_lvds/altera_soft_lvds_tx_twD5CSXW.v
===================================================================
--- atari_chips/pokeyv2/lvds_tx_sim/altera_soft_lvds/altera_soft_lvds_tx_twD5CSXW.v	(revision 1425)
+++ atari_chips/pokeyv2/lvds_tx_sim/altera_soft_lvds/altera_soft_lvds_tx_twD5CSXW.v	(nonexistent)
@@ -1,44 +0,0 @@
-//altlvds_tx CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CBX_SINGLE_OUTPUT_FILE="ON" COMMON_RX_TX_PLL="OFF" CORECLOCK_DIVIDE_BY=2 DATA_RATE="720.0 Mbps" DESERIALIZATION_FACTOR=1 DEVICE_FAMILY="MAX 10" DIFFERENTIAL_DRIVE=0 ENABLE_CLK_LATENCY="OFF" IMPLEMENT_IN_LES="ON" INCLOCK_BOOST=0 INCLOCK_DATA_ALIGNMENT="EDGE_ALIGNED" INCLOCK_PERIOD=5000 INCLOCK_PHASE_SHIFT=0 MULTI_CLOCK="OFF" NUMBER_OF_CHANNELS=1 OUTCLOCK_ALIGNMENT="EDGE_ALIGNED" OUTCLOCK_DIVIDE_BY=1 OUTCLOCK_DUTY_CYCLE=50 OUTCLOCK_MULTIPLY_BY=1 OUTCLOCK_PHASE_SHIFT=0 OUTCLOCK_RESOURCE="AUTO" OUTPUT_DATA_RATE=720 PLL_COMPENSATION_MODE="AUTO" PLL_SELF_RESET_ON_LOSS_LOCK="OFF" PREEMPHASIS_SETTING=0 REGISTERED_INPUT="OFF" USE_EXTERNAL_PLL="OFF" USE_NO_PHASE_SHIFT="ON" VOD_SETTING=0 tx_in tx_inclock tx_out CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
-//VERSION_BEGIN 20.1 cbx_altaccumulate 2020:11:11:17:03:37:SJ cbx_altclkbuf 2020:11:11:17:03:37:SJ cbx_altddio_in 2020:11:11:17:03:37:SJ cbx_altddio_out 2020:11:11:17:03:37:SJ cbx_altera_syncram_nd_impl 2020:11:11:17:03:37:SJ cbx_altiobuf_bidir 2020:11:11:17:03:37:SJ cbx_altiobuf_in 2020:11:11:17:03:37:SJ cbx_altiobuf_out 2020:11:11:17:03:37:SJ cbx_altlvds_tx 2020:11:11:17:03:37:SJ cbx_altpll 2020:11:11:17:03:37:SJ cbx_altsyncram 2020:11:11:17:03:37:SJ cbx_arriav 2020:11:11:17:03:36:SJ cbx_cyclone 2020:11:11:17:03:37:SJ cbx_cycloneii 2020:11:11:17:03:37:SJ cbx_lpm_add_sub 2020:11:11:17:03:37:SJ cbx_lpm_compare 2020:11:11:17:03:37:SJ cbx_lpm_counter 2020:11:11:17:03:37:SJ cbx_lpm_decode 2020:11:11:17:03:37:SJ cbx_lpm_mux 2020:11:11:17:03:37:SJ cbx_lpm_shiftreg 2020:11:11:17:03:37:SJ cbx_maxii 2020:11:11:17:03:37:SJ cbx_mgl 2020:11:11:17:50:46:SJ cbx_nadder 2020:11:11:17:03:37:SJ cbx_stratix 2020:11:11:17:03:37:SJ cbx_stratixii 2020:11:11:17:03:37:SJ cbx_stratixiii 2020:11:11:17:03:37:SJ cbx_stratixv 2020:11:11:17:03:37:SJ cbx_util_mgl 2020:11:11:17:03:37:SJ  VERSION_END
-// synthesis VERILOG_INPUT_VERSION VERILOG_2001
-// altera message_off 10463
-
-
-
-// Copyright (C) 2020  Intel Corporation. All rights reserved.
-//  Your use of Intel Corporation's design tools, logic functions 
-//  and other software and tools, and any partner logic 
-//  functions, and any output files from any of the foregoing 
-//  (including device programming or simulation files), and any 
-//  associated documentation or information are expressly subject 
-//  to the terms and conditions of the Intel Program License 
-//  Subscription Agreement, the Intel Quartus Prime License Agreement,
-//  the Intel FPGA IP License Agreement, or other applicable license
-//  agreement, including, without limitation, that your use is for
-//  the sole purpose of programming logic devices manufactured by
-//  Intel and sold by Intel or its authorized distributors.  Please
-//  refer to the applicable agreement for further details, at
-//  https://fpgasoftware.intel.com/eula.
-
-
-
-//synthesis_resources = 
-//synopsys translate_off
-`timescale 1 ps / 1 ps
-//synopsys translate_on
-module  altera_soft_lvds_tx_twD5CSXW
-	( 
-	tx_in,
-	tx_inclock,
-	tx_out) /* synthesis synthesis_clearbox=1 */;
-	input   [0:0]  tx_in;
-	input   tx_inclock;
-	output   [0:0]  tx_out;
-
-	wire  [0:0]  tx_out_wire;
-
-	assign
-		tx_out = tx_out_wire,
-		tx_out_wire = tx_in;
-endmodule //altera_soft_lvds_tx_twD5CSXW
-//VALID FILE
