Index: atari_chips/gtia/osc_out.qip
===================================================================
--- atari_chips/gtia/osc_out.qip	(nonexistent)
+++ atari_chips/gtia/osc_out.qip	(revision 1318)
@@ -0,0 +1,77 @@
+set_global_assignment -entity "osc_out" -library "osc_out" -name IP_TOOL_NAME "altera_gpio_lite"
+set_global_assignment -entity "osc_out" -library "osc_out" -name IP_TOOL_VERSION "18.0"
+set_global_assignment -entity "osc_out" -library "osc_out" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "osc_out" -name MISC_FILE [file join $::quartus(qip_path) "osc_out.cmp"]
+set_global_assignment -entity "osc_out" -library "osc_out" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
+set_global_assignment -entity "osc_out" -library "osc_out" -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -entity "osc_out" -library "osc_out" -name IP_QSYS_MODE "UNKNOWN"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -entity "osc_out" -library "osc_out" -name IP_COMPONENT_NAME "b3NjX291dA=="
+set_global_assignment -entity "osc_out" -library "osc_out" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "osc_out" -library "osc_out" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "osc_out" -library "osc_out" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "osc_out" -library "osc_out" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "osc_out" -library "osc_out" -name IP_COMPONENT_VERSION "MTguMA=="
+set_global_assignment -entity "osc_out" -library "osc_out" -name IP_COMPONENT_DESCRIPTION "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_NAME "YWx0ZXJhX2dwaW9fbGl0ZQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_VERSION "MTguMA=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_DESCRIPTION "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIGZhbWlseQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "UElOX1RZUEU=::b3V0cHV0::RGF0YSBkaXJlY3Rpb24="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "U0laRQ==::MQ==::RGF0YSB3aWR0aA=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX3RydWVfZGlmZl9idWY=::ZmFsc2U=::VXNlIHRydWUgZGlmZmVyZW50aWFsIGJ1ZmZlcg=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX3BzZXVkb19kaWZmX2J1Zg==::ZmFsc2U=::VXNlIHBzZXVkbyBkaWZmZXJlbnRpYWwgYnVmZmVy"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX2J1c19ob2xk::ZmFsc2U=::VXNlIGJ1cy1ob2xkIGNpcmN1aXRyeQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX29wZW5fZHJhaW4=::ZmFsc2U=::VXNlIG9wZW4gZHJhaW4gb3V0cHV0"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9vZV9wb3J0::ZmFsc2U=::RW5hYmxlIG9lIHBvcnQ="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX2lvX3JlZ19tb2Rl::ZGRy::UmVnaXN0ZXIgbW9kZQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9hY2xyX3BvcnQ=::ZmFsc2U=::RW5hYmxlIGFjbHIgcG9ydA=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9hc2V0X3BvcnQ=::ZmFsc2U=::RW5hYmxlIGFzZXQgcG9ydA=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9zY2xyX3BvcnQ=::ZmFsc2U=::RW5hYmxlIHNjbHIgcG9ydA=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX3NldF9yZWdpc3RlcnNfdG9fcG93ZXJfdXBfaGlnaA==::ZmFsc2U=::U2V0IHJlZ2lzdGVycyB0byBwb3dlciB1cCBoaWdoICh3aGVuIGFjbHIsIHNjbHIgYW5kIGFzZXQgcG9ydHMgYXJlIG5vdCB1c2VkKQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX2Nsb2NrX2VuYWJsZQ==::ZmFsc2U=::RW5hYmxlIGluY2xvY2tlbi9vdXRjbG9ja2VuIHBvcnRz"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vdXRwdXQ=::ZmFsc2U=::SW52ZXJ0IGRpbg=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9yZWdpc3Rlcl90b19kcml2ZV9vYnVmX29l::ZmFsc2U=::VXNlIGEgc2luZ2xlIHJlZ2lzdGVyIHRvIGRyaXZlIHRoZSBvdXRwdXQgZW5hYmxlIChvZSkgc2lnbmFsIGF0IHRoZSBJL08gYnVmZmVy"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9kZGlvX3JlZ190b19kcml2ZV9vZQ==::ZmFsc2U=::VXNlIERESU8gcmVnaXN0ZXJzIHRvIGRyaXZlIHRoZSBvdXRwdXQgZW5hYmxlIChvZSkgc2lnbmFsIGF0IHRoZSBJL08gYnVmZmVy"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9hZHZhbmNlZF9kZHJfZmVhdHVyZXM=::ZmFsc2U=::RW5hYmxlIGFkdmFuY2VkIEREUiBmZWF0dXJlcw=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9waGFzZV9kZXRlY3Rvcl9mb3JfY2s=::ZmFsc2U=::RW5hYmxlIFBoYXNlIERldGVjdG9yIGZyb20gQ0sgbG9vcGJhY2sgc2lnbmFs"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9vZV9oYWxmX2N5Y2xlX2RlbGF5::dHJ1ZQ==::QWRkIGhhbGYtY3ljbGUgZGVsYXkgdG8gT0Ugc2lnbmFs"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9ocl9jbG9jaw==::ZmFsc2U=::RW5hYmxlIGhhbGYtcmF0ZSBjbG9jayBwb3J0"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9pbnZlcnRfaHJfY2xvY2tfcG9ydA==::ZmFsc2U=::RW5hYmxlIGludmVydF9ocl9jbG9jayBwb3J0"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9jbGtkaXZfaW5wdXRfY2xvY2s=::ZmFsc2U=::SW52ZXJ0IGNsb2NrIGRpdmlkZXIgaW5wdXQgY2xvY2s="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vdXRwdXRfY2xvY2s=::ZmFsc2U=::SW52ZXJ0IERESU8gb3V0Y2xvY2s="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vZV9pbmNsb2Nr::ZmFsc2U=::SW52ZXJ0IG91dHB1dCBlbmFibGUgKG9lKSByZWdpc3RlciBpbmNsb2Nr"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJfTU9ERQ==::ZGRy::UkVHSVNURVJfTU9ERQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "QlVGRkVSX1RZUEU=::c2luZ2xlLWVuZGVk::QlVGRkVSX1RZUEU="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "QVNZTkNfTU9ERQ==::bm9uZQ==::QVNZTkNfTU9ERQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "U1lOQ19NT0RF::bm9uZQ==::U1lOQ19NT0RF"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "QlVTX0hPTEQ=::ZmFsc2U=::QlVTX0hPTEQ="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "T1BFTl9EUkFJTl9PVVRQVVQ=::ZmFsc2U=::T1BFTl9EUkFJTl9PVVRQVVQ="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "RU5BQkxFX09FX1BPUlQ=::ZmFsc2U=::RU5BQkxFX09FX1BPUlQ="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05TTEVFUF9QT1JU::ZmFsc2U=::RU5BQkxFX05TTEVFUF9QT1JU"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NMT0NLX0VOQV9QT1JU::ZmFsc2U=::RU5BQkxFX0NMT0NLX0VOQV9QT1JU"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "U0VUX1JFR0lTVEVSX09VVFBVVFNfSElHSA==::ZmFsc2U=::U0VUX1JFR0lTVEVSX09VVFBVVFNfSElHSA=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09VVFBVVA==::ZmFsc2U=::SU5WRVJUX09VVFBVVA=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "SU5WRVJUX0lOUFVUX0NMT0NL::ZmFsc2U=::SU5WRVJUX0lOUFVUX0NMT0NL"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "VVNFX09ORV9SRUdfVE9fRFJJVkVfT0U=::ZmFsc2U=::VVNFX09ORV9SRUdfVE9fRFJJVkVfT0U="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "VVNFX0RESU9fUkVHX1RPX0RSSVZFX09F::ZmFsc2U=::VVNFX0RESU9fUkVHX1RPX0RSSVZFX09F"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFUw==::ZmFsc2U=::VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFUw=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFU19GT1JfSU5QVVRfT05MWQ==::ZmFsc2U=::VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFU19GT1JfSU5QVVRfT05MWQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "RU5BQkxFX09FX0hBTEZfQ1lDTEVfREVMQVk=::dHJ1ZQ==::RU5BQkxFX09FX0hBTEZfQ1lDTEVfREVMQVk="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "SU5WRVJUX0NMS0RJVl9JTlBVVF9DTE9DSw==::ZmFsc2U=::SU5WRVJUX0NMS0RJVl9JTlBVVF9DTE9DSw=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1BIQVNFX0lOVkVSVF9DVFJMX1BPUlQ=::ZmFsc2U=::RU5BQkxFX1BIQVNFX0lOVkVSVF9DVFJMX1BPUlQ="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0hSX0NMT0NL::ZmFsc2U=::RU5BQkxFX0hSX0NMT0NL"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09VVFBVVF9DTE9DSw==::ZmFsc2U=::SU5WRVJUX09VVFBVVF9DTE9DSw=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09FX0lOQ0xPQ0s=::ZmFsc2U=::SU5WRVJUX09FX0lOQ0xPQ0s="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1BIQVNFX0RFVEVDVE9SX0ZPUl9DSw==::ZmFsc2U=::RU5BQkxFX1BIQVNFX0RFVEVDVE9SX0ZPUl9DSw=="
+
+set_global_assignment -library "osc_out" -name VHDL_FILE [file join $::quartus(qip_path) "osc_out.vhd"]
+set_global_assignment -library "osc_out" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "osc_out/altera_gpio_lite.sv"]
+
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_TOOL_NAME "altera_gpio_lite"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_TOOL_VERSION "18.0"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_out" -name IP_TOOL_ENV "mwpim"
Index: atari_chips/gtia/osc_out.spd
===================================================================
--- atari_chips/gtia/osc_out.spd	(nonexistent)
+++ atari_chips/gtia/osc_out.spd	(revision 1318)
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<simPackage>
+ <file
+   path="osc_out_sim/altera_gpio_lite/altera_gpio_lite.sv"
+   type="SYSTEM_VERILOG"
+   library="osc_out" />
+ <file
+   path="osc_out_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv"
+   type="SYSTEM_VERILOG_ENCRYPT"
+   library="osc_out"
+   simulator="modelsim" />
+ <file path="osc_out_sim/osc_out.vhd" type="VHDL" />
+ <topLevel name="osc_out" />
+ <deviceFamily name="max10" />
+</simPackage>
Index: atari_chips/gtia/osc_out_sim/cadence/hdl.var
===================================================================
--- atari_chips/gtia/osc_out_sim/cadence/hdl.var	(nonexistent)
+++ atari_chips/gtia/osc_out_sim/cadence/hdl.var	(revision 1318)
@@ -0,0 +1,2 @@
+
+DEFINE WORK work
Index: atari_chips/gtia/gtiamax.qsf
===================================================================
--- atari_chips/gtia/gtiamax.qsf	(revision 1317)
+++ atari_chips/gtia/gtiamax.qsf	(revision 1318)
@@ -42,7 +42,7 @@
 set_global_assignment -name TOP_LEVEL_ENTITY gtiamax
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:35:48  JUNE 01, 2018"
-set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
@@ -64,6 +64,11 @@
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to S[1]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to S[2]
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to S[3]
+
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to T[0]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to T[1]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to T[2]
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to T[3]
 #
 #set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to AUD[1]
 #set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to AUD[2]
@@ -333,5 +338,12 @@
 set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[30] -to auto_signaltap_0|vcc -section_id auto_signaltap_0
 set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT crc[31] -to auto_signaltap_0|gnd -section_id auto_signaltap_0
 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=512" -section_id auto_signaltap_0
+set_global_assignment -name QIP_FILE osc_in.qip
+set_global_assignment -name SIP_FILE osc_in.sip
+set_global_assignment -name QIP_FILE osc_out.qip
+set_global_assignment -name SIP_FILE osc_out.sip
+
+
+
 set_global_assignment -name SLD_FILE db/gtiastp_auto_stripped.stp
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: atari_chips/gtia/gtiamax.vhd
===================================================================
--- atari_chips/gtia/gtiamax.vhd	(revision 1317)
+++ atari_chips/gtia/gtiamax.vhd	(revision 1318)
@@ -37,7 +37,7 @@
 		PAL :  IN STD_LOGIC; -- PAL clock (5/4...)
 
 		GPIO :  INOUT  STD_LOGIC_VECTOR(11 DOWNTO 0);
-		NC :  INOUT  STD_LOGIC_VECTOR(6 DOWNTO 1);
+		NC :  IN  STD_LOGIC_VECTOR(6 DOWNTO 1);
 		CAD3 : IN STD_LOGIC;
 
 		CSYNC : OUT STD_LOGIC;
@@ -62,6 +62,23 @@
 			locked   : out std_logic
 		);
 	end component;
+	
+	component osc_in is
+		port (
+			inclock : in  std_logic                    := '0';
+			dout    : out std_logic_vector(1 downto 0);
+			pad_in  : in  std_logic_vector(0 downto 0) := (others => '0') 
+		);
+	end component osc_in;
+	
+	component osc_out is
+		port (
+			outclock : in  std_logic                    := '0'; 
+			din      : in  std_logic_vector(1 downto 0) := (others => '0'); 
+			pad_out  : out std_logic_vector(0 downto 0)                    
+		);
+	end component osc_out;	
+	
 
 	signal OSC_CLK : std_logic;
 	signal PHI2_6X : std_logic;
@@ -90,8 +107,8 @@
 
 	signal PAL_NTSC_N : std_logic;
 
-	signal COLOUR_OSC : std_logic;
-	signal COLOUR_OSC_PHASED : std_logic;
+	signal COLOUR_OSC : std_logic_vector(1 downto 0);
+	signal COLOUR_OSC_PHASED : std_logic_vector(1 downto 0);
 
 	signal OSC_CLEAN : std_logic;
 	signal OSC_CLEAN_VIDEO : std_logic;
@@ -115,10 +132,30 @@
 	signal AN_DEL_REG : std_logic_vector(2 downto 0);
 	signal AN_DEL2_NEXT : std_logic_vector(2 downto 0);
 	signal AN_DEL2_REG : std_logic_vector(2 downto 0);
+	
+	signal ddr_pal : std_logic_vector(1 downto 0);
 BEGIN
-	NC <= (others=>'Z');
+	--NC <= (others=>'Z');
 	GPIO <= (others=>'Z');
 
+	pal_in : osc_in
+	port map
+	(
+		inclock => fast_clk,
+		dout => colour_osc,
+		pad_in(0)  => pal
+	);
+--colour_osc <= pal_clean when pal_ntsc_n='1' else osc_clean_video;
+
+	col_out : osc_out
+	port map 
+	(
+		outclock => fast_clk, 
+		din => colour_osc_phased,
+		pad_out(0)=> color
+	);		
+--COLOR <= colour_osc_phased;
+	
 	oscillator : int_osc
 	port map 
 	(
@@ -126,7 +163,6 @@
 		oscena => '1'
 	);
 
-
 	--phi_multiplier : entity work.phi_mult
 	--port map 
 	--(
@@ -272,8 +308,6 @@
 
 GTIA_WRITE_ENABLE <= NOT(WRITE_N) and REQUEST;
 
-colour_osc <= pal_clean when pal_ntsc_n='1' else osc_clean_video;
-
 col_phase : entity work.hue
 PORT MAP 
 ( 
@@ -301,7 +335,7 @@
 S(3) <= '0' when S_OUT(3)='1' else 'Z';
 
 CSYNC <= NOT(VIDEO_CSYNC);
-COLOR <= colour_osc_phased;
+--COLOR <= colour_osc_phased;
 LUM(3 downto 0) <= VIDEO_COLOUR(3 downto 0);
 
 FO0 <= OSC_CLEAN;
Index: atari_chips/gtia/hue.vhd
===================================================================
--- atari_chips/gtia/hue.vhd	(revision 1317)
+++ atari_chips/gtia/hue.vhd	(revision 1318)
@@ -24,8 +24,8 @@
 	vpos_lsb : in std_logic;
 	pal : in std_logic;
 
-	colour_osc : in std_logic;
-	colour_osc_phased : out std_logic
+	colour_osc : in std_logic_vector(1 downto 0);
+	colour_osc_phased : out std_logic_vector(1 downto 0)
 );
 END hue;
 
@@ -39,17 +39,17 @@
 	signal colour_shift : std_logic_vector(7 downto 0);
 	signal base_shift : std_logic_vector(7 downto 0);
 
-	signal colour_osc_delay_next : std_logic_vector(255 downto 0);
-	signal colour_osc_delay_reg : std_logic_vector(255 downto 0);
+	signal colour_osc_delay_next : std_logic_vector(511 downto 0);
+	signal colour_osc_delay_reg : std_logic_vector(511 downto 0);
 
-	signal colour_osc_phased_next : std_logic;
-	signal colour_osc_phased_reg : std_logic;
+	signal colour_osc_phased_next : std_logic_vector(1 downto 0);
+	signal colour_osc_phased_reg : std_logic_vector(1 downto 0);
 BEGIN
 	process(clk,reset_n)
 	begin
 		if (reset_n='0') then
 			colour_osc_delay_reg <= (others=>'0');
-			colour_osc_phased_reg <= '0';
+			colour_osc_phased_reg <= "00";
 		elsif (clk'event and clk='1') then
 			colour_osc_delay_reg <= colour_osc_delay_next;
 			colour_osc_phased_reg <= colour_osc_phased_next;
@@ -59,12 +59,14 @@
 	-- next state
 	process(colour_osc_delay_reg,colour_osc)
 	begin
-		colour_osc_delay_next(255 downto 0) <= colour_osc_delay_reg(254 downto 0)&colour_osc;
+		colour_osc_delay_next(511 downto 0) <= colour_osc_delay_reg(509 downto 0)&colour_osc;
 	end process;
 
 	process(colour_osc_delay_reg,sin_phase,sin_on)
+		variable idx : integer;
 	begin
-		colour_osc_phased_next <= colour_osc_delay_reg(to_integer(unsigned(sin_phase))/4);
+		idx := to_integer(unsigned(sin_phase))/2;
+		colour_osc_phased_next <= colour_osc_delay_reg(idx+1 downto idx);
 	end process;
 
 	-- 4.43361875MHz - PAL carrier  - i.e. 12.8 clock cycles per sin wave! so if we have 256 sine entries,+5*16/4 per cycle, +20 per cycle
@@ -134,7 +136,7 @@
 		end if;
 	end process;
 
-	colour_osc_phased <= colour_osc_phased_reg when sin_on='1' else '0';
+	colour_osc_phased <= colour_osc_phased_reg when sin_on='1' else "00";
 
 END vhdl;
 
Index: atari_chips/gtia/osc_in/altera_gpio_lite.sv
===================================================================
--- atari_chips/gtia/osc_in/altera_gpio_lite.sv	(nonexistent)
+++ atari_chips/gtia/osc_in/altera_gpio_lite.sv	(revision 1318)
@@ -0,0 +1,1200 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module altgpio_one_bit(
+	inclock,
+	outclock,
+	phy_mem_clock,
+	inclocken,
+	outclocken,
+	oe,
+	din,
+	dout,
+	pad,
+	pad_b,
+	aset,
+	sclr,
+	hr_clock,
+	fr_clock,
+	mimic_clock,
+	nsleep
+);
+
+	parameter PIN_TYPE = "output"; 
+	parameter BUFFER_TYPE = "single-ended"; 
+	parameter REGISTER_MODE = "bypass"; 
+	parameter ASYNC_MODE = "none"; 
+	parameter SYNC_MODE = "none"; 
+	parameter BUS_HOLD = "false"; 
+	parameter SET_REGISTER_OUTPUTS_HIGH = "false";  
+	parameter USE_ENHANCED_DDR_HIO_REGISTER = "false"; 
+	parameter BYPASS_THREE_QUARTER_REGISTER = "true"; 
+	parameter INVERT_OUTPUT = "false"; 
+	parameter INVERT_INPUT_CLOCK = "false"; 
+	parameter INVERT_OUTPUT_CLOCK = "false"; 
+	parameter INVERT_OE_INCLOCK = "false"; 
+	parameter USE_ONE_REG_TO_DRIVE_OE = "false"; 
+	parameter USE_DDIO_REG_TO_DRIVE_OE = "false"; 
+	parameter OPEN_DRAIN_OUTPUT = "false"; 
+	parameter ENABLE_OE_HALF_CYCLE_DELAY = "true"; 
+	parameter USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY = "false"; 
+	parameter ENABLE_CLOCK_ENA_PORT = "false"; 
+	parameter ENABLE_HR_CLOCK = "false"; 
+	parameter ENABLE_PHASE_DETECTOR_FOR_CK = "false"; 
+	parameter ENABLE_NSLEEP_PORT = "false"; 
+
+	localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? 2:1;
+	localparam DDIO_REG_POWER_UP = (ASYNC_MODE == "preset" || SET_REGISTER_OUTPUTS_HIGH == "true") ? "high" : "low";
+
+	input inclock;
+	input outclock;
+	input inclocken;
+	input outclocken;
+	input oe;
+	input nsleep;
+	input [DATA_SIZE - 1:0] din;
+	output [DATA_SIZE - 1:0] dout;
+	inout pad;
+	inout pad_b;
+	input aset;
+	input sclr;
+	input phy_mem_clock;
+	input hr_clock;
+	(* altera_attribute = "-name GLOBAL_SIGNAL\"OFF\"" *) output fr_clock;
+	output mimic_clock;
+
+	wire din_ddr;
+	wire buf_in;
+
+	wire oe_out;
+	wire nsleep_in;
+
+    generate
+        if (PIN_TYPE == "output" || PIN_TYPE == "bidir")
+        begin
+			wire [1:0] din_fr;
+            if (INVERT_OUTPUT == "false")
+			begin
+				assign din_fr = din;
+			end
+			else
+			begin
+				assign din_fr = ~din;
+			end
+
+			wire outclock_wire;
+			if (REGISTER_MODE != "bypass")
+			begin
+				if (INVERT_OUTPUT_CLOCK == "false")
+				begin: normal_input_clock
+					assign outclock_wire = outclock;
+				end
+				else
+				begin: inverted_output_clock
+					assign outclock_wire = ~outclock;
+				end
+			end
+
+			wire outclocken_wire;
+			assign  outclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? outclocken : 1'b1;
+
+			if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "true")
+			begin
+				if (ASYNC_MODE != "none")
+					begin: async_mode_out_path_enhanced_ddr
+								fiftyfivenm_ddio_out
+								#(
+									.async_mode(ASYNC_MODE),
+									.sync_mode(SYNC_MODE),
+									.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+									.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+									.power_up(DDIO_REG_POWER_UP),
+									.use_new_clocking_model("true")
+								) fr_out_data_ddio (
+									.datainhi(din_fr[0]),
+									.datainlo(din_fr[1]),
+									.dataout(din_ddr),
+									.clkhi(outclock_wire),
+									.clklo(outclock_wire),
+									.muxsel(outclock_wire),
+									.areset(aset),
+									.ena(outclocken_wire),
+									.phymemclock(phy_mem_clock)
+									`ifndef ALTERA_RESERVED_QIS
+									,
+									.clk (outclock_wire),
+									.sreset(1'b0),
+									.dfflo(),
+									.dffhi(),
+									.devpor(1'b1),
+									.devclrn(1'b1)
+									`endif
+								);
+					end
+				else if (SYNC_MODE != "none")
+					begin: sync_mode_out_path_enhanced_ddr
+								fiftyfivenm_ddio_out
+								#(
+									.async_mode(ASYNC_MODE),
+									.sync_mode(SYNC_MODE),
+									.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+									.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+									.power_up(DDIO_REG_POWER_UP),
+									.use_new_clocking_model("true")
+								) fr_out_data_ddio (
+									.datainhi(din_fr[0]),
+									.datainlo(din_fr[1]),
+									.dataout(din_ddr),
+									.clkhi(outclock_wire),
+									.clklo(outclock_wire),
+									.muxsel(outclock_wire),
+									.sreset(sclr),
+									.ena(outclocken_wire),
+									.phymemclock(phy_mem_clock)
+									`ifndef ALTERA_RESERVED_QIS
+									,
+									.clk (outclock_wire),
+									.areset(1'b0),
+									.dfflo(),
+									.dffhi(),
+									.devpor(1'b1),
+									.devclrn(1'b1)
+									`endif
+								);
+					end
+				else
+					begin: out_path_enhanced_ddr
+								fiftyfivenm_ddio_out
+								#(
+									.async_mode(ASYNC_MODE),
+									.sync_mode(SYNC_MODE),
+									.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+									.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+									.power_up(DDIO_REG_POWER_UP),
+									.use_new_clocking_model("true")
+								) fr_out_data_ddio (
+									.datainhi(din_fr[0]),
+									.datainlo(din_fr[1]),
+									.dataout(din_ddr),
+									.clkhi(outclock_wire),
+									.clklo(outclock_wire),
+									.muxsel(outclock_wire),
+									.ena(outclocken_wire),
+									.phymemclock(phy_mem_clock)
+									`ifndef ALTERA_RESERVED_QIS
+									,
+									.areset(1'b0),
+									.clk(1'b0),
+									.sreset(1'b0),
+									.dfflo(),
+									.dffhi(),
+									.devpor(1'b1),
+									.devclrn(1'b1)
+									`endif
+								);
+					end
+			end
+			else if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "false")
+			begin
+				if (ASYNC_MODE != "none")
+						begin: async_mode_out_path_ddr
+							fiftyfivenm_ddio_out
+							#(
+								.async_mode(ASYNC_MODE),
+								.sync_mode(SYNC_MODE),
+								.power_up(DDIO_REG_POWER_UP),
+								.use_new_clocking_model("true"),
+								.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+							) fr_out_data_ddio (
+								.datainhi(din_fr[0]),
+								.datainlo(din_fr[1]),
+								.dataout(din_ddr),
+								.clkhi(outclock_wire),
+								.clklo(outclock_wire),
+								.muxsel(outclock_wire),
+								.areset(aset),
+								.ena(outclocken_wire)
+								`ifndef ALTERA_RESERVED_QIS
+								,
+								.clk(1'b0),
+								.phymemclock(1'b0),
+								.sreset(1'b0),
+								.dfflo(),
+								.dffhi(),
+								.devpor(1'b1),
+								.devclrn(1'b1)
+								`endif
+							);
+						end
+				else if (SYNC_MODE != "none")
+						begin: sync_mode_out_path_ddr
+							fiftyfivenm_ddio_out
+							#(
+								.async_mode(ASYNC_MODE),
+								.sync_mode(SYNC_MODE),
+								.power_up(DDIO_REG_POWER_UP),
+								.use_new_clocking_model("true"),
+								.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+							) fr_out_data_ddio (
+								.datainhi(din_fr[0]),
+								.datainlo(din_fr[1]),
+								.dataout(din_ddr),
+								.clkhi(outclock_wire),
+								.clklo(outclock_wire),
+								.muxsel(outclock_wire),
+								.sreset(sclr),
+								.ena(outclocken_wire)
+								`ifndef ALTERA_RESERVED_QIS
+								,
+								.areset(1'b0),
+								.clk(1'b0),
+								.phymemclock(1'b0),
+								.dfflo(),
+								.dffhi(),
+								.devpor(1'b1),
+								.devclrn(1'b1)
+								`endif
+							);
+						end
+				else
+						begin: out_path_ddr
+							fiftyfivenm_ddio_out
+							#(
+								.async_mode(ASYNC_MODE),
+								.sync_mode(SYNC_MODE),
+								.power_up(DDIO_REG_POWER_UP),
+								.use_new_clocking_model("true"),
+								.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+							) fr_out_data_ddio (
+								.datainhi(din_fr[0]),
+								.datainlo(din_fr[1]),
+								.dataout(din_ddr),
+								.clkhi(outclock_wire),
+								.clklo(outclock_wire),
+								.muxsel(outclock_wire),
+								.ena(outclocken_wire)
+								`ifndef ALTERA_RESERVED_QIS
+								,
+								.areset(1'b0),
+								.clk(1'b0),
+								.phymemclock(1'b0),
+								.sreset(1'b0),
+								.dfflo(),
+								.dffhi(),
+								.devpor(1'b1),
+								.devclrn(1'b1)
+								`endif
+							);
+						end
+			end
+            else if (REGISTER_MODE == "single-register")
+            begin: out_path_sdr
+   			  reg reg_data_out /* synthesis altera_attribute="FAST_OUTPUT_REGISTER=on" */;
+                always @(posedge outclock_wire)
+                    reg_data_out <= din_fr[0];
+
+                assign din_ddr = reg_data_out;
+			end
+            else  
+            begin: out_path_reg_none
+                assign din_ddr = din_fr[0];
+            end
+        end
+    endgenerate
+
+    generate
+
+	    if (PIN_TYPE == "bidir" || PIN_TYPE == "output")
+        begin
+			wire oe_inclk_wire;
+			if (USE_ONE_REG_TO_DRIVE_OE == "true" || USE_DDIO_REG_TO_DRIVE_OE == "true")
+			begin
+				if (INVERT_OE_INCLOCK == "false")
+				begin: normal_oe_inclock
+					assign oe_inclk_wire = outclock;
+				end
+				else
+				begin: inverted_oe_inclock
+					assign oe_inclk_wire = ~outclock;
+				end
+			end
+
+			wire oe_outclocken_wire;
+			assign  oe_outclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? outclocken : 1'b1;
+
+			if (USE_DDIO_REG_TO_DRIVE_OE == "true")
+			begin
+				if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "true")
+				begin
+					if (ASYNC_MODE != "none")
+						begin: async_mode_oe_path_enhanced_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.areset(aset),
+											.ena(oe_outclocken_wire),
+											.phymemclock(phy_mem_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else if (SYNC_MODE != "none")
+						begin: sync_mode_oe_path_enhanced_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.sreset(sclr),
+											.ena(oe_outclocken_wire),
+											.phymemclock(phy_mem_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else
+						begin: oe_path_enhanced_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.ena(oe_outclocken_wire),
+											.phymemclock(phy_mem_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+				end
+				else if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "false")
+				begin
+					if (ASYNC_MODE != "none")
+						begin: async_mode_oe_path_ddr
+								fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.areset(aset),
+											.ena(oe_outclocken_wire)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.phymemclock(1'b0),
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else if (SYNC_MODE != "none")
+						begin: sync_mode_oe_path_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.sreset(sclr),
+											.ena(oe_outclocken_wire)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.phymemclock(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else
+						begin: oe_path_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.ena(oe_outclocken_wire)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.phymemclock(1'b0),
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+				end
+			end
+			else if (USE_ONE_REG_TO_DRIVE_OE == "true")
+			begin: oe_path_sdr
+					fiftyfivenm_ff oe_reg (
+							.clk(oe_inclk_wire),
+							.d(~oe),
+							.clrn(1'b1),
+							.ena(1'b1),
+							.q(oe_out)
+						);
+            end
+            else if (USE_ONE_REG_TO_DRIVE_OE == "false" && USE_DDIO_REG_TO_DRIVE_OE == "false")
+            begin: oe_path_reg_none
+				assign oe_out = ~oe;
+            end
+        end
+	endgenerate
+
+    generate
+        if (PIN_TYPE == "input" || PIN_TYPE == "bidir")
+        begin
+            wire [1:0] ddr_input;
+			wire inclock_wire;
+
+			if (REGISTER_MODE != "bypass")
+			begin
+				if (INVERT_INPUT_CLOCK == "false")
+				begin: normal_input_clock
+					assign inclock_wire = inclock;
+				end
+				else
+				begin: inverted_input_clock
+					assign inclock_wire = ~inclock;
+				end
+			end
+
+			wire inclocken_wire;
+			assign  inclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? inclocken : 1'b1;
+
+         	if (REGISTER_MODE == "ddr")
+         	begin
+		        if (USE_ENHANCED_DDR_HIO_REGISTER == "true" || USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY == "true")
+				begin
+						if (ENABLE_HR_CLOCK == "true")
+						begin
+								if (ASYNC_MODE != "none")
+									begin: async_mode_in_path_enhanced_ddr_with_halfrateresyncclk
+										fiftyfivenm_ddio_in
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.power_up(DDIO_REG_POWER_UP),
+											.invert_input_clock(INVERT_INPUT_CLOCK)
+										) fr_in_ddio (
+											.datain(buf_in),
+											.clk(inclock_wire),
+											.ena(inclocken_wire),
+											.halfrateresyncclk(hr_clock),
+											.regouthi(ddr_input[1]),
+											.regoutlo(ddr_input[0]),
+											.clkout(fr_clock),
+											.areset(aset)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.sreset(1'b0),
+											.dfflo(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+									end
+								else if (SYNC_MODE != "none")
+									begin:sync_mode_in_path_enhanced_ddr_with_halfrateresyncclk
+										fiftyfivenm_ddio_in
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.power_up(DDIO_REG_POWER_UP),
+											.invert_input_clock(INVERT_INPUT_CLOCK)
+										) fr_in_ddio (
+											.datain(buf_in),
+											.clk (inclock_wire),
+											.ena(inclocken_wire),
+											.sreset(sclr),
+											.halfrateresyncclk(hr_clock),
+											.regouthi(ddr_input[1]),
+											.regoutlo(ddr_input[0]),
+											.clkout(fr_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.dfflo(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+									end
+								else
+									begin:in_path_enhanced_ddr_with_halfrateresyncclk
+										fiftyfivenm_ddio_in
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.power_up(DDIO_REG_POWER_UP),
+											.invert_input_clock(INVERT_INPUT_CLOCK)
+										) fr_in_ddio (
+											.datain(buf_in),
+											.clk (inclock_wire),
+											.ena(inclocken_wire),
+											.halfrateresyncclk(hr_clock),
+											.regouthi(ddr_input[1]),
+											.regoutlo(ddr_input[0]),
+											.clkout(fr_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.sreset(1'b0),
+											.areset(1'b0),
+											.dfflo(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+									end
+						end
+						else
+						begin
+							if (ASYNC_MODE != "none")
+								begin: async_mode_in_path_enhanced_ddr
+									fiftyfivenm_ddio_in
+									#(
+										.async_mode(ASYNC_MODE),
+										.sync_mode(SYNC_MODE),
+										.power_up(DDIO_REG_POWER_UP),
+										.invert_input_clock(INVERT_INPUT_CLOCK)
+									) fr_in_ddio (
+										.datain(buf_in),
+										.clk(inclock_wire),
+										.ena(inclocken_wire),
+										.regouthi(ddr_input[1]),
+										.regoutlo(ddr_input[0]),
+										.clkout(fr_clock),
+										.areset(aset)
+										`ifndef ALTERA_RESERVED_QIS
+										,
+										.sreset(1'b0),
+										.dfflo(),
+										.devpor(1'b1),
+										.devclrn(1'b1),
+										.halfrateresyncclk(1'b0)
+										`endif
+									);
+								end
+							else if (SYNC_MODE != "none")
+								begin:sync_mode_in_path_enhanced_ddr
+									fiftyfivenm_ddio_in
+									#(
+										.async_mode(ASYNC_MODE),
+										.sync_mode(SYNC_MODE),
+										.power_up(DDIO_REG_POWER_UP),
+										.invert_input_clock(INVERT_INPUT_CLOCK)
+									) fr_in_ddio (
+										.datain(buf_in),
+										.clk (inclock_wire),
+										.ena(inclocken_wire),
+										.sreset(sclr),
+										.regouthi(ddr_input[1]),
+										.regoutlo(ddr_input[0]),
+										.clkout(fr_clock)
+										`ifndef ALTERA_RESERVED_QIS
+										,
+										.areset(1'b0),
+										.dfflo(),
+										.devpor(1'b1),
+										.devclrn(1'b1),
+										.halfrateresyncclk(1'b0)
+										`endif
+									);
+								end
+							else
+								begin:in_path_enhanced_ddr
+									fiftyfivenm_ddio_in
+									#(
+										.async_mode(ASYNC_MODE),
+										.sync_mode(SYNC_MODE),
+										.power_up(DDIO_REG_POWER_UP),
+										.invert_input_clock(INVERT_INPUT_CLOCK)
+									) fr_in_ddio (
+										.datain(buf_in),
+										.clk (inclock_wire),
+										.ena(inclocken_wire),
+										.regouthi(ddr_input[1]),
+										.regoutlo(ddr_input[0]),
+										.clkout(fr_clock)
+										`ifndef ALTERA_RESERVED_QIS
+										,
+										.sreset(1'b0),
+										.areset(1'b0),
+										.dfflo(),
+										.devpor(1'b1),
+										.devclrn(1'b1),
+										.halfrateresyncclk(1'b0)
+										`endif
+									);
+								end
+						end
+				end
+				else if (ENABLE_PHASE_DETECTOR_FOR_CK == "true")
+					begin
+						assign mimic_clock = buf_in;
+					end
+				else
+				begin: in_path_ddr
+					wire input_cell_l_q;
+					wire input_aset;
+
+					assign input_aset = ( ASYNC_MODE == "clear") ? !aset : aset;
+
+					fiftyfivenm_ff input_cell_l (
+						.clk(inclock_wire),
+						.d(buf_in),
+						.clrn(input_aset),
+						.ena(inclocken_wire),
+						.q(input_cell_l_q)
+					);
+
+					fiftyfivenm_ff input_latch_l (
+						.clk(~inclock_wire),
+						.d(input_cell_l_q),
+						.clrn(input_aset),
+						.ena(inclocken_wire),
+						.q(ddr_input[0])
+					);
+
+					fiftyfivenm_ff input_cell_h (
+						.clk(~inclock_wire),
+						.d(buf_in),
+						.clrn(input_aset),
+						.ena(inclocken_wire),
+						.q(ddr_input[1])
+					);
+
+				end
+			end
+			else if (REGISTER_MODE == "single-register")
+            begin: in_path_sdr
+                reg reg_data_in /* synthesis altera_attribute="FAST_INPUT_REGISTER=on" */;
+                always @(posedge inclock_wire) begin
+                    reg_data_in <= buf_in;
+                end
+                assign ddr_input[0] = reg_data_in;
+            end
+            else
+            begin: in_path_reg_none
+                assign ddr_input[0] = buf_in;
+            end
+
+            assign dout[DATA_SIZE - 1:0] = ddr_input[DATA_SIZE - 1:0];
+
+        end
+    endgenerate
+
+	generate
+		if (PIN_TYPE == "output" || PIN_TYPE == "bidir")
+		begin
+			if(BUFFER_TYPE == "pseudo_differential")
+			begin: pseudo_diff_output_buf
+
+				wire wire_pseudo_diff_o;
+				wire wire_pseudo_diff_o_bar;
+
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf_a (
+					.i(wire_pseudo_diff_o),
+					.oe(~oe_out),
+					.o(pad),
+					.obar()
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf_a_bar (
+					.i(wire_pseudo_diff_o_bar),
+					.oe(~oe_out),
+					.o(pad_b),
+					.obar()
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+
+				fiftyfivenm_pseudo_diff_out pseudo_diff_a
+				(
+					.i(din_ddr),
+					.o(wire_pseudo_diff_o),
+					.obar(wire_pseudo_diff_o_bar)
+				);
+
+
+
+			end
+			else if (BUFFER_TYPE == "true_differential")
+			begin: true_diff_output_buf
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf (
+					.i(din_ddr),
+					.oe(~oe_out),
+					.o(pad),
+					.obar(pad_b)
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+			end
+			else
+			begin: output_buf
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf (
+					.i(din_ddr),
+					.oe(~oe_out),
+					.o(pad),
+					.obar()
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+			end
+		end
+	endgenerate
+
+	assign nsleep_in = (ENABLE_NSLEEP_PORT == "true") ? nsleep : 1'b1;
+
+	generate
+		if (PIN_TYPE == "input" || PIN_TYPE == "bidir")
+		begin
+			if(BUFFER_TYPE == "true_differential" || BUFFER_TYPE == "pseudo_differential")
+			begin: diff_input_buf
+				if (ENABLE_NSLEEP_PORT == "true")
+				begin: diff_input_buf_with_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.ibar(pad_b),
+						.o(buf_in),
+						.nsleep(nsleep_in)
+					);
+				end
+				else
+				begin: diff_input_buf_without_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.ibar(pad_b),
+						.o(buf_in)
+					);
+				end
+			end
+			else
+			begin:input_buf
+				if (ENABLE_NSLEEP_PORT == "true")
+				begin: input_buf_with_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.o(buf_in),
+						.nsleep(nsleep_in)
+						`ifndef ALTERA_RESERVED_QIS
+						,
+						.ibar(1'b0)
+						`endif
+					);
+				end
+				else
+				begin: input_buf_without_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.o(buf_in)
+						`ifndef ALTERA_RESERVED_QIS
+						,
+						.ibar(1'b0)
+						`endif
+					);
+				end
+			end
+		end
+	endgenerate
+
+	generate
+		if (PIN_TYPE == "output")
+		begin
+			assign dout = {DATA_SIZE{1'b0}};
+		end
+
+		if (PIN_TYPE == "output" || REGISTER_MODE != "ddr" || USE_ENHANCED_DDR_HIO_REGISTER == "false")
+		begin
+			assign fr_clock = 1'b0;
+		end
+
+		if (PIN_TYPE == "input" || PIN_TYPE == "output" || REGISTER_MODE != "ddr" || ENABLE_PHASE_DETECTOR_FOR_CK == "false")
+		begin
+			assign mimic_clock = 1'b0;
+		end
+	endgenerate
+
+endmodule
+
+module altera_gpio_lite(
+	inclock,
+	outclock,
+	inclocken,
+	outclocken,
+	oe,
+	din,
+	dout,
+	pad_io,
+	pad_io_b,
+	pad_in,
+	pad_in_b,
+	pad_out,
+	pad_out_b,
+	aset,
+	aclr,
+	phy_mem_clock,
+	sclr,
+	hr_clock,
+	fr_clock,
+	invert_hr_clock,
+	mimic_clock,
+	nsleep
+);
+
+	parameter PIN_TYPE = "output"; 
+	parameter BUFFER_TYPE = "single-ended"; 
+	parameter REGISTER_MODE = "bypass"; 
+	parameter SIZE = 4;
+	parameter ASYNC_MODE = "none"; 
+	parameter SYNC_MODE = "none"; 
+	parameter BUS_HOLD = "false"; 
+	parameter SET_REGISTER_OUTPUTS_HIGH = "false"; 
+	parameter INVERT_OUTPUT = "false"; 
+	parameter INVERT_INPUT_CLOCK = "false"; 
+	parameter INVERT_OUTPUT_CLOCK = "false"; 
+	parameter INVERT_OE_INCLOCK = "false"; 
+	parameter USE_ONE_REG_TO_DRIVE_OE = "false"; 
+	parameter USE_DDIO_REG_TO_DRIVE_OE = "false"; 
+	parameter OPEN_DRAIN_OUTPUT = "false"; 
+	parameter USE_ADVANCED_DDR_FEATURES = "false"; 
+	parameter USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY = "false"; 
+	parameter INVERT_CLKDIV_INPUT_CLOCK = "false"; 
+	parameter ENABLE_HR_CLOCK = "false"; 
+	parameter ENABLE_OE_HALF_CYCLE_DELAY = "true"; 
+	parameter ENABLE_OE_PORT = "false"; 
+	parameter ENABLE_CLOCK_ENA_PORT = "false"; 
+	parameter ENABLE_PHASE_INVERT_CTRL_PORT = "false"; 
+	parameter ENABLE_PHASE_DETECTOR_FOR_CK = "false"; 
+	parameter ENABLE_NSLEEP_PORT = "false"; 
+
+    localparam USE_ENHANCED_DDR_HIO_REGISTER = USE_ADVANCED_DDR_FEATURES;
+	localparam BYPASS_THREE_QUARTER_REGISTER = (USE_ADVANCED_DDR_FEATURES == "true") ? "false" : "true";
+	localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? 2 : 1;
+
+	input inclock;
+	input outclock;
+	input inclocken;
+	input outclocken;
+	input [SIZE - 1:0] oe;
+	input [SIZE - 1:0] nsleep;
+	input [SIZE * DATA_SIZE - 1:0] din;
+	output [SIZE * DATA_SIZE - 1:0] dout;
+	inout [SIZE - 1:0] pad_io;
+	inout [SIZE - 1:0] pad_io_b;
+	input [SIZE - 1:0] pad_in;
+	input [SIZE - 1:0] pad_in_b;
+	output [SIZE - 1:0] pad_out;
+	output [SIZE - 1:0] pad_out_b;
+	input aset;
+	input aclr;
+	input sclr;
+	input phy_mem_clock;
+	input invert_hr_clock;
+	output [SIZE - 1:0] fr_clock;
+	output wire hr_clock;
+	output [SIZE - 1:0] mimic_clock;
+
+	wire [SIZE * DATA_SIZE - 1:0] din_reordered;
+	wire [SIZE * DATA_SIZE - 1:0] dout_reordered;
+	wire aclr_aset_wire;
+	wire sclr_wire;
+	wire [SIZE - 1:0] pad_io;
+	wire [SIZE - 1:0] pad_io_b;
+
+
+	assign aclr_aset_wire = (ASYNC_MODE == "clear") ? aclr : (ASYNC_MODE == "preset") ? aset : 1'b1;
+	assign sclr_wire = (SYNC_MODE == "clear") ? sclr : 1'b0;
+
+	generate
+		if (PIN_TYPE == "input")
+		begin
+			assign pad_io = pad_in;
+			assign pad_io_b = pad_in_b;
+			assign pad_out = {SIZE{1'b0}};
+			assign pad_out_b = {SIZE{1'b0}};
+		end
+		else if (PIN_TYPE == "output")
+		begin
+			assign pad_out = pad_io;
+			assign pad_out_b = pad_io_b;
+		end
+		else begin
+			assign pad_out = {SIZE{1'b0}};
+			assign pad_out_b = {SIZE{1'b0}};
+		end
+	endgenerate
+
+	genvar j, k;
+	generate
+		begin : reorder
+			for(j = 0; j < SIZE ; j = j + 1) begin : j_loop
+				for(k = 0; k < DATA_SIZE; k = k + 1) begin : k_d_loop
+					assign din_reordered[j * DATA_SIZE + k] = din[j + k * SIZE];
+					assign dout[j + k * SIZE] = dout_reordered[j * DATA_SIZE + k];
+				end
+			end
+		end
+	endgenerate
+
+	genvar i;
+	generate
+		begin : gpio_one_bit
+			for(i = 0 ; i < SIZE ; i = i + 1) begin : i_loop
+				wire oe_wire;
+				wire nsleep_wire;
+
+
+				assign oe_wire = (PIN_TYPE == "output" && ENABLE_OE_PORT == "false") ? 1'b1 :
+				                  (PIN_TYPE == "input") ? 1'b0 : oe[i];
+
+
+				assign nsleep_wire = (PIN_TYPE == "input" && ENABLE_NSLEEP_PORT == "false") ? 1'b1 :
+														(PIN_TYPE == "output") ? 1'b0 : nsleep[i];
+
+				altgpio_one_bit #(
+					.PIN_TYPE(PIN_TYPE),
+					.BUFFER_TYPE(BUFFER_TYPE),
+					.REGISTER_MODE(REGISTER_MODE),
+					.ASYNC_MODE(ASYNC_MODE),
+					.SYNC_MODE(SYNC_MODE),
+					.BUS_HOLD(BUS_HOLD),
+					.SET_REGISTER_OUTPUTS_HIGH(SET_REGISTER_OUTPUTS_HIGH),
+					.USE_ENHANCED_DDR_HIO_REGISTER(USE_ENHANCED_DDR_HIO_REGISTER),
+					.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY(USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY),
+					.BYPASS_THREE_QUARTER_REGISTER(BYPASS_THREE_QUARTER_REGISTER),
+					.INVERT_OUTPUT(INVERT_OUTPUT),
+					.INVERT_INPUT_CLOCK(INVERT_INPUT_CLOCK),
+					.INVERT_OUTPUT_CLOCK(INVERT_OUTPUT_CLOCK),
+					.INVERT_OE_INCLOCK(INVERT_OE_INCLOCK),
+					.USE_ONE_REG_TO_DRIVE_OE(USE_ONE_REG_TO_DRIVE_OE),
+					.USE_DDIO_REG_TO_DRIVE_OE(USE_DDIO_REG_TO_DRIVE_OE),
+					.OPEN_DRAIN_OUTPUT(OPEN_DRAIN_OUTPUT),
+					.ENABLE_OE_HALF_CYCLE_DELAY(ENABLE_OE_HALF_CYCLE_DELAY),
+					.ENABLE_CLOCK_ENA_PORT(ENABLE_CLOCK_ENA_PORT),
+					.ENABLE_HR_CLOCK(ENABLE_HR_CLOCK),
+					.ENABLE_PHASE_DETECTOR_FOR_CK(ENABLE_PHASE_DETECTOR_FOR_CK),
+					.ENABLE_NSLEEP_PORT(ENABLE_NSLEEP_PORT)
+				) altgpio_bit_i (
+					.inclock(inclock),
+					.outclock(outclock),
+					.phy_mem_clock(phy_mem_clock),
+					.inclocken(inclocken),
+					.outclocken(outclocken),
+					.oe(oe_wire),
+					.din(din_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]),
+					.dout(dout_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]),
+					.pad(pad_io[i]),
+					.pad_b(pad_io_b[i]),
+					.aset(aclr_aset_wire),
+					.sclr(sclr_wire),
+					.fr_clock(fr_clock[i]),
+					.hr_clock(hr_clock),
+					.mimic_clock(mimic_clock[i]),
+					.nsleep(nsleep_wire)
+				);
+			end
+		end
+	endgenerate
+
+	generate
+		if ((PIN_TYPE == "input" || PIN_TYPE == "bidir") && (ENABLE_HR_CLOCK == "true"))
+		begin
+			if (ENABLE_PHASE_INVERT_CTRL_PORT == "true")
+			begin
+				if (SYNC_MODE == "clear")
+				begin : clock_divider_sync_mode_invert_hr_clock
+					fiftyfivenm_io_clock_divider
+					#(
+						.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+						.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+						.sync_mode(SYNC_MODE)
+					) io_clkdiv (
+						.clk(inclock),
+						.phaseinvertctrl(invert_hr_clock),
+						.sreset(sclr_wire),
+						.clkout(hr_clock)
+					);
+				end
+				else
+				begin : clock_divider_invert_hr_clock
+					fiftyfivenm_io_clock_divider
+						#(
+							.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+							.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+							.sync_mode(SYNC_MODE)
+						) io_clkdiv (
+							.clk(inclock),
+							.phaseinvertctrl(invert_hr_clock),
+							.clkout(hr_clock)
+							`ifndef ALTERA_RESERVED_QIS
+							,
+							.sreset(1'b0)
+							`endif
+						);
+				end
+			end
+			else
+			begin
+				if (SYNC_MODE == "clear")
+				begin : clock_divider_sync_mode
+					fiftyfivenm_io_clock_divider
+					#(
+						.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+						.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+						.sync_mode(SYNC_MODE)
+					) io_clkdiv (
+						.clk(inclock),
+						.sreset(sclr_wire),
+						.clkout(hr_clock)
+						`ifndef ALTERA_RESERVED_QIS
+						,
+						.phaseinvertctrl(1'b0)
+						`endif
+					);
+				end
+				else
+				begin : clock_divider
+					fiftyfivenm_io_clock_divider
+						#(
+							.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+							.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+							.sync_mode(SYNC_MODE)
+						) io_clkdiv (
+							.clk(inclock),
+							.clkout(hr_clock)
+							`ifndef ALTERA_RESERVED_QIS
+							,
+							.sreset(1'b0),
+							.phaseinvertctrl(1'b0)
+							`endif
+						);
+				end
+			end
+		end
+		else begin
+			assign hr_clock = 1'b0;
+		end
+	endgenerate
+
+endmodule
Index: atari_chips/gtia/osc_in.bsf
===================================================================
--- atari_chips/gtia/osc_in.bsf	(nonexistent)
+++ atari_chips/gtia/osc_in.bsf	(revision 1318)
@@ -0,0 +1,70 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2018  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 176 184)
+	(text "osc_in" (rect 69 -1 94 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 168 20 180)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "inclock" (rect 0 0 25 12)(font "Arial" (font_size 8)))
+		(text "inclock" (rect 4 61 46 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 64 72)(line_width 1))
+	)
+	(port
+		(pt 0 152)
+		(input)
+		(text "pad_in" (rect 0 0 25 12)(font "Arial" (font_size 8)))
+		(text "pad_in" (rect 4 141 40 152)(font "Arial" (font_size 8)))
+		(line (pt 0 152)(pt 64 152)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(output)
+		(text "dout[1..0]" (rect 0 0 35 12)(font "Arial" (font_size 8)))
+		(text "dout[1..0]" (rect 4 101 64 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 64 112)(line_width 3))
+	)
+	(drawing
+		(text "inclock" (rect 26 43 94 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 69 67 174 144)(font "Arial" (color 0 0 0)))
+		(text "dout" (rect 40 83 104 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 69 107 174 224)(font "Arial" (color 0 0 0)))
+		(text "pad_in" (rect 26 123 88 259)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 69 147 174 304)(font "Arial" (color 0 0 0)))
+		(text " altera_gpio_lite " (rect 108 168 324 346)(font "Arial" ))
+		(line (pt 64 32)(pt 112 32)(line_width 1))
+		(line (pt 112 32)(pt 112 168)(line_width 1))
+		(line (pt 64 168)(pt 112 168)(line_width 1))
+		(line (pt 64 32)(pt 64 168)(line_width 1))
+		(line (pt 65 52)(pt 65 76)(line_width 1))
+		(line (pt 66 52)(pt 66 76)(line_width 1))
+		(line (pt 65 92)(pt 65 116)(line_width 1))
+		(line (pt 66 92)(pt 66 116)(line_width 1))
+		(line (pt 65 132)(pt 65 156)(line_width 1))
+		(line (pt 66 132)(pt 66 156)(line_width 1))
+		(line (pt 0 0)(pt 176 0)(line_width 1))
+		(line (pt 176 0)(pt 176 184)(line_width 1))
+		(line (pt 0 184)(pt 176 184)(line_width 1))
+		(line (pt 0 0)(pt 0 184)(line_width 1))
+	)
+)
Index: atari_chips/gtia/osc_in.cmp
===================================================================
--- atari_chips/gtia/osc_in.cmp	(nonexistent)
+++ atari_chips/gtia/osc_in.cmp	(revision 1318)
@@ -0,0 +1,8 @@
+	component osc_in is
+		port (
+			inclock : in  std_logic                    := 'X';             -- export
+			dout    : out std_logic_vector(1 downto 0);                    -- export
+			pad_in  : in  std_logic_vector(0 downto 0) := (others => 'X')  -- export
+		);
+	end component osc_in;
+
Index: atari_chips/gtia/osc_out_sim/osc_out.vhd
===================================================================
--- atari_chips/gtia/osc_out_sim/osc_out.vhd	(nonexistent)
+++ atari_chips/gtia/osc_out_sim/osc_out.vhd	(revision 1318)
@@ -0,0 +1,127 @@
+-- osc_out.vhd
+
+-- Generated using ACDS version 18.0 614
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity osc_out is
+	port (
+		outclock : in  std_logic                    := '0';             -- outclock.export
+		din      : in  std_logic_vector(1 downto 0) := (others => '0'); --      din.export
+		pad_out  : out std_logic_vector(0 downto 0)                     --  pad_out.export
+	);
+end entity osc_out;
+
+architecture rtl of osc_out is
+	component altera_gpio_lite is
+		generic (
+			PIN_TYPE                                 : string  := "output";
+			SIZE                                     : integer := 4;
+			REGISTER_MODE                            : string  := "bypass";
+			BUFFER_TYPE                              : string  := "single-ended";
+			ASYNC_MODE                               : string  := "none";
+			SYNC_MODE                                : string  := "none";
+			BUS_HOLD                                 : string  := "false";
+			OPEN_DRAIN_OUTPUT                        : string  := "false";
+			ENABLE_OE_PORT                           : string  := "false";
+			ENABLE_NSLEEP_PORT                       : string  := "false";
+			ENABLE_CLOCK_ENA_PORT                    : string  := "false";
+			SET_REGISTER_OUTPUTS_HIGH                : string  := "false";
+			INVERT_OUTPUT                            : string  := "false";
+			INVERT_INPUT_CLOCK                       : string  := "false";
+			USE_ONE_REG_TO_DRIVE_OE                  : string  := "false";
+			USE_DDIO_REG_TO_DRIVE_OE                 : string  := "false";
+			USE_ADVANCED_DDR_FEATURES                : string  := "false";
+			USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY : string  := "false";
+			ENABLE_OE_HALF_CYCLE_DELAY               : string  := "true";
+			INVERT_CLKDIV_INPUT_CLOCK                : string  := "false";
+			ENABLE_PHASE_INVERT_CTRL_PORT            : string  := "false";
+			ENABLE_HR_CLOCK                          : string  := "false";
+			INVERT_OUTPUT_CLOCK                      : string  := "false";
+			INVERT_OE_INCLOCK                        : string  := "false";
+			ENABLE_PHASE_DETECTOR_FOR_CK             : string  := "false"
+		);
+		port (
+			outclock        : in    std_logic                    := 'X';             -- export
+			din             : in    std_logic_vector(1 downto 0) := (others => 'X'); -- export
+			pad_out         : out   std_logic_vector(0 downto 0);                    -- export
+			outclocken      : in    std_logic                    := 'X';             -- export
+			inclock         : in    std_logic                    := 'X';             -- export
+			inclocken       : in    std_logic                    := 'X';             -- export
+			fr_clock        : out   std_logic_vector(0 downto 0);                    -- export
+			hr_clock        : out   std_logic;                                       -- export
+			invert_hr_clock : in    std_logic                    := 'X';             -- export
+			phy_mem_clock   : in    std_logic                    := 'X';             -- export
+			mimic_clock     : out   std_logic_vector(0 downto 0);                    -- export
+			dout            : out   std_logic_vector(1 downto 0);                    -- export
+			pad_io          : inout std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			pad_io_b        : inout std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			pad_in          : in    std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			pad_in_b        : in    std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			pad_out_b       : out   std_logic_vector(0 downto 0);                    -- export
+			aset            : in    std_logic                    := 'X';             -- export
+			aclr            : in    std_logic                    := 'X';             -- export
+			sclr            : in    std_logic                    := 'X';             -- export
+			nsleep          : in    std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			oe              : in    std_logic_vector(0 downto 0) := (others => 'X')  -- export
+		);
+	end component altera_gpio_lite;
+
+begin
+
+	osc_out_inst : component altera_gpio_lite
+		generic map (
+			PIN_TYPE                                 => "output",
+			SIZE                                     => 1,
+			REGISTER_MODE                            => "ddr",
+			BUFFER_TYPE                              => "single-ended",
+			ASYNC_MODE                               => "none",
+			SYNC_MODE                                => "none",
+			BUS_HOLD                                 => "false",
+			OPEN_DRAIN_OUTPUT                        => "false",
+			ENABLE_OE_PORT                           => "false",
+			ENABLE_NSLEEP_PORT                       => "false",
+			ENABLE_CLOCK_ENA_PORT                    => "false",
+			SET_REGISTER_OUTPUTS_HIGH                => "false",
+			INVERT_OUTPUT                            => "false",
+			INVERT_INPUT_CLOCK                       => "false",
+			USE_ONE_REG_TO_DRIVE_OE                  => "false",
+			USE_DDIO_REG_TO_DRIVE_OE                 => "false",
+			USE_ADVANCED_DDR_FEATURES                => "false",
+			USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY => "false",
+			ENABLE_OE_HALF_CYCLE_DELAY               => "true",
+			INVERT_CLKDIV_INPUT_CLOCK                => "false",
+			ENABLE_PHASE_INVERT_CTRL_PORT            => "false",
+			ENABLE_HR_CLOCK                          => "false",
+			INVERT_OUTPUT_CLOCK                      => "false",
+			INVERT_OE_INCLOCK                        => "false",
+			ENABLE_PHASE_DETECTOR_FOR_CK             => "false"
+		)
+		port map (
+			outclock        => outclock, -- outclock.export
+			din             => din,      --      din.export
+			pad_out         => pad_out,  --  pad_out.export
+			outclocken      => '1',      -- (terminated)
+			inclock         => '0',      -- (terminated)
+			inclocken       => '0',      -- (terminated)
+			fr_clock        => open,     -- (terminated)
+			hr_clock        => open,     -- (terminated)
+			invert_hr_clock => '0',      -- (terminated)
+			phy_mem_clock   => '0',      -- (terminated)
+			mimic_clock     => open,     -- (terminated)
+			dout            => open,     -- (terminated)
+			pad_io          => open,     -- (terminated)
+			pad_io_b        => open,     -- (terminated)
+			pad_in          => "0",      -- (terminated)
+			pad_in_b        => "0",      -- (terminated)
+			pad_out_b       => open,     -- (terminated)
+			aset            => '0',      -- (terminated)
+			aclr            => '0',      -- (terminated)
+			sclr            => '0',      -- (terminated)
+			nsleep          => "0",      -- (terminated)
+			oe              => "0"       -- (terminated)
+		);
+
+end architecture rtl; -- of osc_out
Index: atari_chips/gtia/osc_out_sim.f
===================================================================
--- atari_chips/gtia/osc_out_sim.f	(nonexistent)
+++ atari_chips/gtia/osc_out_sim.f	(revision 1318)
@@ -0,0 +1,3 @@
+osc_out_sim/osc_out.vhd
+osc_out_sim/altera_gpio_lite/altera_gpio_lite.sv
+osc_out_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv
Index: atari_chips/gtia/osc_out_sim/aldec/rivierapro_setup.tcl
===================================================================
--- atari_chips/gtia/osc_out_sim/aldec/rivierapro_setup.tcl	(nonexistent)
+++ atari_chips/gtia/osc_out_sim/aldec/rivierapro_setup.tcl	(revision 1318)
@@ -0,0 +1,300 @@
+
+# (C) 2001-2018 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 18.0 614 linux 2018.10.28.22:04:02
+# ----------------------------------------
+# Auto-generated simulation script rivierapro_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     osc_out
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "aldec.do", and modify the text as directed.
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog -sv2k5 <your compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If osc_out is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] { 
+  set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
+  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] { 
+  set TOP_LEVEL_NAME "osc_out"
+}
+
+if ![info exists QSYS_SIMDIR] { 
+  set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] { 
+  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/18.0/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
+  set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
+  set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+set Aldec "Riviera"
+if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
+  set Aldec "Active"
+}
+
+if { [ string match "Active" $Aldec ] } {
+  scripterconf -tcl
+  createdesign "$TOP_LEVEL_NAME"  "."
+  opendesign "$TOP_LEVEL_NAME"
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+  echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib      ./libraries     
+ensure_lib      ./libraries/work
+vmap       work ./libraries/work
+ensure_lib                  ./libraries/altera_ver      
+vmap       altera_ver       ./libraries/altera_ver      
+ensure_lib                  ./libraries/lpm_ver         
+vmap       lpm_ver          ./libraries/lpm_ver         
+ensure_lib                  ./libraries/sgate_ver       
+vmap       sgate_ver        ./libraries/sgate_ver       
+ensure_lib                  ./libraries/altera_mf_ver   
+vmap       altera_mf_ver    ./libraries/altera_mf_ver   
+ensure_lib                  ./libraries/altera_lnsim_ver
+vmap       altera_lnsim_ver ./libraries/altera_lnsim_ver
+ensure_lib                  ./libraries/fiftyfivenm_ver 
+vmap       fiftyfivenm_ver  ./libraries/fiftyfivenm_ver 
+ensure_lib                  ./libraries/altera          
+vmap       altera           ./libraries/altera          
+ensure_lib                  ./libraries/lpm             
+vmap       lpm              ./libraries/lpm             
+ensure_lib                  ./libraries/sgate           
+vmap       sgate            ./libraries/sgate           
+ensure_lib                  ./libraries/altera_mf       
+vmap       altera_mf        ./libraries/altera_mf       
+ensure_lib                  ./libraries/altera_lnsim    
+vmap       altera_lnsim     ./libraries/altera_lnsim    
+ensure_lib                  ./libraries/fiftyfivenm     
+vmap       fiftyfivenm      ./libraries/fiftyfivenm     
+ensure_lib         ./libraries/osc_out
+vmap       osc_out ./libraries/osc_out
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+  echo "\[exec\] dev_com"
+  eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"              -work altera_ver      
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                       -work lpm_ver         
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                          -work sgate_ver       
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                      -work altera_mf_ver   
+  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim_ver
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v"              -work fiftyfivenm_ver 
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm_ver 
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera          
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera          
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera          
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera          
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera          
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera          
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm             
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm             
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate           
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate           
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf       
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf       
+  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim    
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim    
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm     
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.vhd"            -work fiftyfivenm     
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_components.vhd"       -work fiftyfivenm     
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+  echo "\[exec\] com"
+  eval  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_gpio_lite/altera_gpio_lite.sv" -work osc_out
+  eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/osc_out.vhd"                                       
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+  echo "\[exec\] elab"
+  eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L osc_out -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -dbg -O2 option
+alias elab_debug {
+  echo "\[exec\] elab_debug"
+  eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L osc_out -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+  dev_com
+  com
+  elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -dbg -O2
+alias ld_debug "
+  dev_com
+  com
+  elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+  echo "List Of Command Line Aliases"
+  echo
+  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
+  echo
+  echo "dev_com                                           -- Compile device library files"
+  echo
+  echo "com                                               -- Compile the design files in correct order"
+  echo
+  echo "elab                                              -- Elaborate top level design"
+  echo
+  echo "elab_debug                                        -- Elaborate the top level design with -dbg -O2 option"
+  echo
+  echo "ld                                                -- Compile all the design files and elaborate the top level design"
+  echo
+  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -dbg -O2"
+  echo
+  echo 
+  echo
+  echo "List Of Variables"
+  echo
+  echo "TOP_LEVEL_NAME                                    -- Top level module name."
+  echo "                                                     For most designs, this should be overridden"
+  echo "                                                     to enable the elab/elab_debug aliases."
+  echo
+  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
+  echo
+  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
+  echo
+  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
+  echo
+  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo
+  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h
Index: atari_chips/gtia/osc_out_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv
===================================================================
--- atari_chips/gtia/osc_out_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv	(nonexistent)
+++ atari_chips/gtia/osc_out_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv	(revision 1318)
@@ -0,0 +1,713 @@
+// Copyright (C) 2018 Intel Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Intel and is being provided
+// in accordance with and subject to the protections of the
+// applicable Intel Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Intel
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Intel Program License Subscription
+// Agreement, the Intel Quartus Prime License Agreement, the
+// Intel FPGA IP License Agreement, or other applicable license
+// agreement, including, without limitation, that your use is 
+// for the sole purpose of simulating designs for use exclusively
+// in logic devices manufactured by Intel and sold by Intel or 
+// its authorized distributors. Please refer to the applicable
+// agreement for further details. Intel products and services
+// are protected under numerous U.S. and foreign patents, 
+// maskwork rights, copyrights and other intellectual property laws.
+// Intel assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 18.0std
+// ALTERA_TIMESTAMP:Wed Apr 25 07:09:40 PDT 2018
+// encrypted_file_type : local_encrypted
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6e"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+fmmgwONj8YLVFvc9fzLQt7vQ6qNjohAyiwgrgqxvvIA/p2m2OK6Azwxg4RpSfucB
+t8igxEqwdy5LEhpwhZkkLsrurOpDLiHsF34i1lhbKgwB9v8c9mHbkGd6X741IBJr
+WsCDuEfFTKBDX0bX8wvL+NF4dYh8nobVYKXUGff6rpo=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 32384)
++RsIbtnldMRALbzsiW80qZ2rfTbzXsyC9jdHu+gf6XnD3AsZhYK5zCEPnRv4pySJ
+bZKhJtpelHssEQbQj1gm2sidjk72T2b+em+fDYP/zSWAo2HbSpQ7suMGBwIQx6d4
+wCLXdsbPpg0183l0WXdB9EKQFm0Vk5DjX6LqvfZK+3VSdWzZOAse9J3YFaH3W59l
+3pQlelSTVMVISjqVBozQV41Bwi0ECbUU5P94I9PH8Uh+3FwqFJOXcdPSqnkprVYI
+t0L0scxgXG83cRdfyXvZlSWYdepmulrUXNFmXa4Jm0+g1Ygj98+m6EMh29PCRdyh
+YKzR0OXVGEGYEhVb3EUcbBogrg7PnnHK7vz4/LzsYM7xTds/NsNKuk871jlTZDB5
+w+n4d9XuLzSiW/a1lAeQNHhojwPy0oxm+qPk1XlotTicrs4KhcXS78jwF0EEdkCg
+Oi7XtFgBhaimK/i2q54jR144UdulgognqeN9tDCm7VC/Xbr/W4J6ZAVH0ka5yBwT
+JuxdgbbXHhnKImQH+alJxkNGGF0GgC5/u5UnA041gg2aI3TE9W3OuPBqUkOcBVwo
+rRJzwavki+k2vTU2G9HcutRGFeKkVmZABl7nPrwR9qSgdfwTZbik8gSle+iZQC+w
+hTiJBk7X9tmqrDrtIIr4dJ3suJj/Hny9J4gd2pLlJEM+VlNubmhU+AuFdBoMUeS9
+9FeTIf1rAluK62bELVqirXef7COzc/KCQGnpooQO2VsY6IfPB2eHM5ebnE78R7ul
+JyGUk4uxWSw+d0OoYAnRwP52tskbJesUMBx1VcJf7T8jpzAzihCusLd5AvNGRNj1
+PKIrKR82dKUXQ9PGhsJauYqZV/MLRKU3AXIqQpgMosw3rMxhcneZWLEzAxgo/T9y
+u0HP1S0BJedOOiFLcFg+QANuvc+qZtnwmBVHFXZgGJzaKbnJlefxSJL36HsDRkL/
+SGCNUZpodf07c+cr6sJXFO3Fi1y3ebu7lIy1X5eb1R1ff/F4ACATdeAL5InF+ukd
+dJWtHrrSfwYr13MX4JU0ctNkOC23teI46uc3tL4hUElvcR+C/rmj0FSibWMq9QlS
+c+cVWd6XVsmgoxuSvb0hjuMTTD5/Sp8cD1gU5eRxBeX+WDRn3vdIxxJIpgVVY4EE
+789cPYmzEe1oCN2xhzgPD6weZY4FBc8QOP0Nzl2lPHcZmODH3+qllQgwtJkutsFF
+uVcZM1W+win+TGqb1GGlBpaEHo7+W39tMe9BS+MBJxNjdGJ8Q5VIfrkUoNhROvL9
+mziCl/ogTy7wFO8ghTgkGSgkwJ49Ce0cBZFC/pfjTwNVAHnxUnVLwKZ016Zs+xx4
+I317UD3z/A9oYeEuKxOoCVQklpNCI/WqBfp9pxXSogy/ZRwn6rN0HUD+a9VU28Zc
+JrAxf9jaiET6t9KdvPSOckOT09siOO30PAeFnU/CYnFWx+JqQG5ZLFfqf7z4ty0R
+ER3D4T+4vR76Za8VcM4egzsM4iAmhNngOkWV1bGY5aUk/r7nGtVz+w4yqRoGDrwp
+5SsU0o/+M7PRsdNBmW4j0AMtGj8aClJ2u2mcaJfgEQ1lvN0gCsxJ07nhyFw5mMcj
+k6fzIEU0hQdBaW4T/nRy7ORGiGCNUoGbkrCIX7IRD7K9rzYxdkrH/f5Yp8R4MvKD
+tTAhQswnt4v9pe+Rjg72e/hRPgYX+soIilNaH30TBrNMHrc+f563vXCcA1/GZnSm
+TIYMVOTSXv7mjuuHc/cRJb7VYH9HR/haSQO97ZPazaAYZj86dFAozctoJdgt3X8g
+SWG9yAvWiZQLx5V+bVyXAtDjJP649cAnD23mIzX7HkGeXa4aFrJkOCTrqwvyMqPQ
+mmmcElafr1cfrOWL9jqk+byJ/aG7pFpj5fxS80rc+zos2Y0rBEAyfWSu29ODnylh
+uXXc94JK5HOym0JopTk0cuT2YOpZgHShawgQxISfv0v1RB17ZUbAL2/yIYwBaK+Z
+orgQ7z5ki0pJd8Vycdr/6u40qJntB2HhqvYj1J0bcQ4ayBhrIfEppAZjUIbD8fmT
+CeHR49qrlgY20O0or5X+1rr4YUqHhOHnH303BzvQTAeec4WM1v3B6kFDbymTH0Qp
+cquKfDCc1gTDIBHOqO/tFz3+uf7BX6JFZvXDpaXlBg8obaNx7SkQWwOb512RcbLi
+whd0/XXsiVkOaP7j+GV5R3RBeEHuq70e7BC4CYoriAvmNfjhepE6AaYfcPlkkje0
+E7BkSWA+sdBFYw+lViSJurJI4V/2dg1s3Xw6vBp2BiXGAzyM9wgyJzggDu7Jk00Z
+HURXlglXxVufFJL3vYRhveyaMHLigoN9UmucF/9TMoJzeEY+5uPmHuxXLpdtmfaB
+xFAifnatl23HuAVlLGzZ0wqnjPX1WaSx+XG+mvw39BW1ZCCO33iE6h/yBYU8ZCbs
+qsePlE9woL4KZvg+vWswb391qA//xP6Th3w5z5y2+RZj+X9TMxBQqtLCyoUoDCtz
+LcMAf/hJ+2CBAL3qZOTFHpxxXWk/3M4d2FwCCqiybrSAUmXBJbRBl91ndclmnpB0
+7v9rqnKaoVXd+3eMudLxU3TlzFBGNfGPWfeetpkbJQ+dMRXAj6y4Dk88Azj1lV7U
+MDJjdFUD9NSzL+t2mNIbdGsuzbcErASacbB7F4KOKuidfzD7ecfpOjPpE9744Aux
+c8uOUCz4L3wYnSEAi8B0/eslOUFFm7u91fnTqjclYO0TyN13nFi/OtkHezimGItp
+DJ9p4iPheCMq8+ruSaOOkQOEUT+3dbSCUeP/v23O6D+Acbr8E5b3Akvhojd2dPt8
+u1BHFavtfaP+bLZXH2X7XC+8auw5/sKkjSX8JGnrNQl9qgv/RDOUNEJrmOWOigfr
+1jdknV2OGlKI6UfHxak9FH6UMNvk1aHxIcUEc/+aJId3jJd8x/zjOAFDHSVa8K3h
+eQYYBsDD9vU206MknbcL77i7s7JfBHEpDXRNZgMX1m2g4Q6OaFs0aZn9S2RbeVE/
+tpe49w44Wt3Punzp6D5yoRJBeHxTjrCYqfc+se/84wrQ4k+tRg3DcIrQ7qGxNhfg
+F4SVRNN0Qeh0YXyrJrYXPWDUYcZFgtk+2ffLTSBEEM13tvuzB7pWJKy6/SgBPpYX
+WFzffIO9ce4KRkjJ0U7KH8vn/D2tD3JhPXXfhCMAmLZSPUvxYh49ZeYpXkaLr9Aj
+xyWJzpsqZuES32EArfSu/BMuLEM0kgwgg2vDPQoLZVMu58rTQi/hnvfu9Xvz7UeB
++YtR7cDeZy+D42SgBvNInjeRciKkctZtgG7PElgl8fpZwQ3faLj/Z75P7ppUGo+A
+oj3T//ioGtUF77VDpVD9Q+2Yy/cKiwZ4HTJB2Kl9RtIlF75XMxlYVTvjICsF5KUB
+H6RQfDzNxO0DMzvBd3B5j+F8j36U38bzAnkGtD4HP5SHJp5R0i97KEaQADDoFqd3
+i75yMT524qg6htjbPIuZ1zvZ+8n5Itwpf5rEqF81YCTirdVjK73kIigkJFihOfKP
+sCYO0B6o81BT/HA1WIJqYpAG9Fqz4aoLwiZzpBnahJ1x2oA/xCQbfkb5bK/eHrQ7
+7qtwe+lWjWio2e6wmiZ3FTGHua5pVfrDLHZvICY989X88jAnfOhpnbV1eyWu7zvH
+NjAzDNv6A5FsbcK0JhegIIYStRBGigQr3ed005vXWKRIQtd3sc68OXfJr68xOMgh
+rRXpOpjzS/M26xC7hVbGqf1/qc7ggkqJJfSXVp+6G9S1WSuzuO1vu5d4lW9pL34f
+FRkVhGQ8vxtmzvR/D5dB0GK3lR5JIBNxGwQyGlp2P7PQehRRDu0asAZ5ZvlvDhZS
+hzwPlRgdTET3N3fEqmM9oZ1VWXDZbV1FhFZdzKLBnxDCN00qrhJoy545nRiJT4ve
+/vn2LfnnQWpe3egrREv+kYKJ5fXeWu6svXci0YrXMNOiE/3wTMgjCO0heptyanPS
+nhwbX/GxFb681JS8GrNEs6C+T5bbEEsCgvSCs7aANE/a4KwOy0Hoi0IgbP/FMjLP
+uWzWKHYvZ0kZqo7Vl2U47OmxcOtKWKVAR26bETUhBm9IloU0nJhaW/uD3KIOQlI3
+67zA0Td8afb0Cy6R2fU3TZvwnqGEBmdnDX75qPY23LlMYpc+UL3HZpoUhRumtKVg
+Nn2Layqa///p7A8i4MnycA+HjB4xNVqKZcEMfupGFh0m2d5+6leVTwcB4HK/aBah
+yenZclsLwAPWdSWqJ2loCby8P/PAQsLM239PrbDkLAiHuChrtaIF4WD7GCmjhGRm
+SY8RneCQ51E7tT567bsc++vDkPgQmgW69dFSz3gr42rRRoeXEYIft14EQ80Q+bdh
+tkfN/BBLVjldYVBdJSo/bwVJJ8+lhIhnYbJqf3GIqOq1QWTNG9RnAZPoH2+BPwTL
+BfYMWufy+1WV9DimGkqAzxfuC56iYWLSh+sMacouWd9fqQ58LmeU7TJcvmNi1xp0
+Ia6ib2eXMoAQ1ylrN4mLg6oNmu4uZUSBAwWid20Nhm6G4Y4wjP+l7b3zFCQbnwBY
+QJMVHjzZx/IyaV0qXs3AyGKmsi6CWbeTm9+JMEesLrj1ar5jjR8CMXPvvnl5JVcn
+2dxqj5I3Eh8ZVF809p9r96m4XhjW9tW9OvgPLhv3F89gYRbQNihDCKAU0t/Zqji1
+uT3VkCw+bibj4NLEalZs+YBfmx6iPHYblxGym8ufcm6fZilhLQuOmpVgxZ3KSKLs
+YAGSRrj/dVZQQFA/yhvEtDNOBNG+HttjcFoduA3feSAi/iMuo0WSnxD5pH0SEomZ
+AfA4g5BUBWX4lGqq1ZUTqxzbnGXCBS+B3c8dXBkDYDnkxfJ21Cpm2HbaxeqedVy2
+eR7LfemnSrhwWiwf3fSWEJlAhy967SxhpGUgnSKwYiI6CmpxF8K4YtbeVy+9M5fI
+AMJDiVhkdtYzD8pnsiECLIHa8nCE2xuLPd25cE0avA3S0sGHKQXQ2wbtTMXxEShH
+2Y1YWIkEWO1rsu2Rmn51aV+xwxHg/cNPepc53JxxBXTh4amJ2O+NhjYhrkzlylnW
+GN+/RhERRE/O1eIwos5Lo7JfKwVEWzGkjSxcwIH4zZf5tWFL3YkqMcx+YjiPmP2J
+x2xB37hVhCShkZjz8kgRrw0GKhxs/pQz4jY7CvRxD4y5/f0Cc92SWlUeQGnWASCb
+sUdQWWhENdfyORr5jaFjTajmg1rLSlHDh+Hf1fzl79TMKzgtzb/Fq4x+kjgBaD+c
+3Dm+cxIfz2Njq0JEoZ2iFupyPcSxNiO33u/KaU2uI26JdTMWTqlzCtn5z8I3ruQf
+Vp7Y75nH21N4V6LZT55eozfoc8XtruwwAb6CXJglHQSKvuwZ9zZfIpCsudnS0Hgr
+5NiQEF+htB6KSLDZ7RI1b8UCuOsAz0JmPrvpoyi7HQlnZHf9OrC1XFzxz3saRpcX
+lmXvkQjlOFrs+mlanBtUrxdEh0Bawb1dnrW1uGNGC7avlgO/T+9+mc07yh4rQVbK
+csLzMGBTNbbPBLalUQZHRvtDQYVMLMBEb+8j54uKtOcDWhNuZ3aT6Ms/NJUE2+Fr
+K56UbDo2Yi0OafK4p1xIO7ZRBaD1xjWS98vDeEJNK6c0wFTgKdn3ii1jT0PUlgSR
+Qn3c8q+9tTEq2S/DxMcLWq9DoVXaLZaV5K0rUQozNCsBFQr/lI5GeTgrpq8UaK74
+z27FhKYr8CO7Z7eCgOBQXowZONFMCv7ygfq+6vi8VEe16soFHRsAcDq4L3/VISN6
+Gr4REZaRtokNoS/XNwuRNmD8DK4kN6FS4ey17oreguFU0cRbPiQHGmTAbQIxAp2v
+ndmKmCQta5ab0jwjX7rzGINATfG8IZc81ZTb8IqjAzZBBCCuj1cNsSesdesjrk/K
+aYS4sKsFa56klpjNGbFd6y4p16r+Quee3Q8UiZc3HRgX9Idd9sfzghsJ6Vrj8qD2
+APbTGloBxuyrTF3dMdLu/awKc1o9+8ryKVvJx3/3O7zLjYWBcEFoN9Yk2/eKdMc1
+zzmKWrlIG25qhjNAtAlOY5Iil1BwMZgPGxdusmLud+uOYSknVf99Amn3t5A57NBJ
+/TExj4UGwFJKMoldqVhGrGDfb0Y/aU0tjQ6+MWTnPnkUG3SohUpA0x9H3oJGCqtY
+Dn9iNOO68RQjWBk74/z4kjgD6nvctWROH7bkkj0nhyOQLF0aA3M9GG4Lom2uJ+9D
+Ta1DF7Svsop7ifcC745tEXa6sYYzJTYLAUvfUxgz8F+ofVSYurVt2jHLnBUgG3CT
+PeVY0WPch/rSP+GKOTuy2DqXQgrPU85sVQYTz6pX+dWEoOb+ssHEqq4g3wXuLBmc
+I6UEI+dZJx3tco+PY7HXsiOYznk+c3DqENYTkskywDeHkVEE8R/ZxKTpgstoEHwe
+l79Ty6ONhUiZ9rw8PaQoZ3gR4jTDJrW1B+ARF4i7OE4TrO4m7QkBKwJgS5Iqky0h
+e8VulUoAdjqtVez7E6San3KPDUyGg5GmpzbI5bta/fBYXlIMe9ct9NQSIZqeWgiC
+Sz65J9pfPnlk4JfThLR4dL0JdC6DUJ6+ESgMQvS6NMG8uyZdXKlX8vOpnjc/8xss
+UOAWX9p5bLxNtUAFU8nn/oHuN/HyuKgHzeMcu7CXj+D2gcxJ4Mlbucr7lVs6pAft
+LPDKsqyxX2xu5kLbzgCCaN4nyB79sQw3WfCEU/y7Z7xNWVZoolfBVi8OdgEGZYBI
+P4pB8g7jVg+QQUv2rsplfTzLI1HA/q5hzjo0CecK+hpEB+iU/TnuVzaSUmJUKhas
+u0tZPqkZbcNVuH1IAIjbbgBxQqQsW/V58k1rxtV3ohUgIYaBeclgsvXne0MJbOaL
+kbp/dPyZMANYSIevIYdWi+PQecoJdH1UVs2FO3YZKXRclK5s3J/N4g02Ddch0csj
+GMyEkwIKzxdSe/+HjIK0TAjJfFpk8am6yCBwS3Nu0nrkvYXJyTBEUVRvar34HCSy
+OE3+epv0w28ujaB8YOUR+MvdLDbdQRf36+5e7x3LwTPs1z0kRi+l4IBHpt/uutTf
+zq36XI7ins1roLyGk3tmMopEq/ZgSeV6niuxh41+jZ7oChCX9Pb8VFT5sHU5VFfM
+SOVYDnqt7d4HmwGc1mthgjzbxhvlyO01+d64HoEDFKayKkCwElcWp/HiaUPP/TdX
+CTqms0SFC/dckL6yO0QQ3/zn408Rj+KmsOBdsNBcgZl5etHXRPisgWApJ/z6JR95
+2+Ogb/+Pprs7hr8MbeJoZSPuby7mPTjnGBdX8mJl/rQA58SMbhxVTkKp8aXCMWrh
+PDNvi89ELx2xdre4bNjRCcRD1wbgklnMAWkl6vVHrpxb6dFsXrHSiokBQSVCyDdQ
+pgLB8f7AO3tQq/1Ax6xwKIDU8VxxprXXy9eOb7NTsjspzwCh5F35BLE0l/v25yyh
+Xt3Ud/mvOfXNa67q2K10k/2ZNAf7B5nSr5XTc5+9HmzVlyH7pq2Tc6+E1gC7ixbL
+qE58D3Lv8PXulwOfO7JEnS7/NKmRS/1KBuszqMDGUjrf7PxucKMwxH7h57GY+s66
+PFXyNccmsJVa8GQHZH7iHK+TvdUkIdQ+GjWQgfGyLghIirLw+QdPNUz4qmodHei8
+/ZzmGeMuhXj0SRvAvpiB7Nk8i3CuWrmJ4C89p5VhDxnaIYul9DCgFIQjKjS3Tksz
+2yEbg8NQyanzhKiJMjLexZ8UlXyntfqOg/Gn7JzoRd2SAs+1pulIUKihfaeFCHvt
+Wfun/hw/mXREEMSj/gl16x+W7s8CBwxxfVjbOVl1Vw+TzjICLGGzQnlVP1Ik8g7n
+xI4IL7200Jv3Jjaw6TjmtgQ2reMcQYIZnJB4hwN+WZrEzTGz0KxMiXT/9dMSfADx
+S0K1CO5yIzgGLhF3GEZvcu8/O6QSPiWLD1BeInypReJaKF3sLb9GtDw0vb0XDyn9
+HN9soqa8y4ezvIFcMNTQ5lhq+bZkwPiqpJkQ1dLV4O52ye3SrTWvaInEjVL35rJJ
+cJvsan7SRo8BaofkV4aVa4VbYO85a4UgwUZ1nlUxOH1SQA+lkLeN+NtiRccP1iw5
+QUxnymdI/3AEzgq6vUF0tPHCTFQp7nq65UGIqBJ0mSf19M1/to1ffnceflwtTRaW
+oVVh/7n+GGEbCs55mhOzjTj4eFTEEAAOZ0lmaQTpmfvvYmIzgn7GIlv28++zKVsf
+G83p1HuPLyhqma8ct1ti0QD2EUgWXr3x2zROdl0b5ZNAgw3DY/rW/FvxcLuPBd0m
+HxR3UwD3RSbAUjdHzsks8tP2D4UxDB1HBizX5eJiuLCRW13mu7/EJwviGYAVJ5xH
+8xryASO6bYt1rBGH7Xsz4cYwhSPYkoGSqaPipPcFZVt0GargN/AiTsr43is6YfVx
+37dcCUr9aFM6vRH1IEEeEf2SbVtNQZrsw7mdRf6CZevUYaucjXHuVGpY0a8npi93
+eycv2cf3pZlgKFg1U/2w8j9KYkdHwc24G3urOKqYgdUsWMZyNutzCJ/BhkPfE7Nv
+Lq95IeeMUkJbpMxTxnmPOFc2D0S0TAZUKQ3BdlzCuo9PdtFe2kK+qASObGfoKbtw
+AE9BWiNuxueOjq9rGBKJVD9+MMlG4z7IJlDBb5Smgbr3MD0imF802qo4g+yF0yDT
+6hr/GUOnsO5veT8CXX6t++6G9l6DjY0+y/kUlwosmlgCtm8XBpQFe/w/C15YA4nx
+lr0SE+3NkTSSSvoVNI2xq6ijCeDWM0NrlsC7Kuf4bL4pHxb2SQUL2UsYNBxBMqkF
+OkzHSw4Q/5YwpLNC+qMQPDCrDEXW74oLsyutBtpH+DPK2YhCdQkrwlORO/rozul+
+lFmrITMxwUoqel79myFvSr/u/cjp/7057DZW+7PVG4u+T7bfnUAMWo05THmsC3oD
+X1KTZHhMAxtYaHqqYRerS8YVua4J664WplnG1fO3LiC16HA4s/dlXIsah1SSfv3l
+APScYcuu6WjhUAfyKRuP8u0F+kdMdHhi8CYtjSakpwS94rxfSsb/jNy9ZgtkB/2m
+yrWxEluT44L3QnuIoCecx52BGY9RiNXWai9nktCu0XfWU9TMzFmWN2j7PvAWkJ6l
+KYQgbdwxqOePaB6rRMku5zy46y0D7Y0wHoQFbxrX3CWhqVOsOocq6nC8DMvAQJgo
+ViF/sZ+0Ij+31wiJD2Jr4qL0qEdoHBakXL2pWsC2tU65/ZLUQgkwWV4sNobpq7k2
+fA/xbbfMZFIjBN884P3hviWHhMkNZRvRUve+vfa/pw0B9nUwOOgKnNE9zllzB/Nx
+gjDTAxQHIEyQrXEH0dliVAGlHTJrLUr3HYb8r0fafae1SC16egETGolFNfWdvdqn
+R057+Lj7xOUQ8TOyrqYDGW3I+ulOblBvZd1dVnvGBTmMQLDTYaVbxDL67muyeJse
+ohEbhnubpmcgXGhsUGxWxrvtlUmcrPhfTQz4+jpOxIIJkBCOQ+YLIOmRsyZid7gT
+70DiLuPmWaFwD4EAXfNCfiPUD1egSvAhoAhJjFgSW6+nRijS1ZpmVfI2rqSEjiD/
+rNUu78vQy6Dd10Vx0i09M4a+nquPGrK5WNyFpOeiv679esMk6A2aXJIOtvWbOvJA
+axaGG67kZIIG2F4Dd6ORGbRRqGpUCy17zW2czchJ3pEPBmtrV6zTacA+HSJvXOXx
+6zbolB6J2cEoIsDNrqy3rIL1uQk0r/SyLpDCn7LH0iOWOoaW/4As5Lz5qECVkD5S
+aur2a2xL+mEU+q/03SM34ZKhnf1U9wjzIgsduXFLDCGsh0nuthxzggs9bkqNzIRU
+V5YG6O3xsLtwdXhZ7BOj55irJ3TmmBw+ycAvlv6ix8waCPZ2wyOQunvXUHdybUq5
+cuSGzlvXO9Umnx9krlc8fmfu9Eifz0HiF1Q9ZSGroMIlBKyXKODUcLO2BoUeqE/X
+3GXAKcVI3fcq5SjpT7NRZkMY93jY5SAFpf90vZ6LV7mpkg4EsNp6/aHkDaOiJNs9
+J2vuXSTDIkOidA4ka6PUONTF2uWoZ0HVCnzGiegvp/3EvDvCwbDXetPfUjgcBKvM
+RuCFXeypRhkjBO5CHBTEfVN4NwjSiOnMXdwceynab2Z23G9NQ6MPwURnzX5kqp9f
+9vTNTL5WyP4PAjzZLhTT7Iuffl9f4bjpwwoZhbq2T903PNacQiooVD6/zD8BGck8
+tebqQ7sxfJux+NWAmD3Wy9KdEsqGvD+o11RBcr4ZaSylVPR4WrLCsFhAUBcCDcu5
+is8UufvQtNJAql7sdFmsOOtjPii0DIm/dKwZ9uwnWlZat4x0X/oZpjdKvCgK3qFC
+GpuKOQxZ6HEHyeh1Js7urEoQ8ku6d97k7/15VVX5IfVXUg/xwF8SiZ/F1EmtlYlL
+Dp5fQNfafBIRzvhKuNyKKQpvF8mZjL38ZYFlfVNJJT8jbE3QEEMkMEQHGr4ze/Ct
+OZnKH3JWDSERV3wKVgqro7p2RgChQBYjeobjRT2gNCR+TkbSoiS5+n0V9zHgaD1g
+0kosuEa1p8HiZ+tAyL/ccVZiL1E/S8PErxUIba9iFP5/bnLRBQStNU6Xbtg9kJM0
+EVKQAGhz7f1rmXRDROcshnZM/Hl2UziRG8MpHo3sKlbNskzW3NaMAK5mgYGC1eAE
+ZStsX/CsVZLErODW/+HlUn1Rza3sqG6P21Rx6j20eFo6qleoTNFiI7uWplUVKpvX
+64OEK9JP6iwGPssrMlm87Z3HjUHKkji2Svrn4chxnpMEfB+a9d2dw6qQ1HL72qjI
+1Sh0e9/z6+ly9DlDQKWNrGV2trKKK0piWcSECfITLG/gDyLmZcoPgLDoca5e+4uk
+/CCAQ8SabqNF29ldQkXuBB0rIRYqKeb3Z0KQQ97EqAqDqKzrDGAg4J9s8H3j/z3s
+Sg2WuUIl/OBzrh4T8i2arjVI+Oveto3aGiaBPW9JgO2n9ODTXoujb1bd/JwZIhYl
+wNaRhfSxUd6yDkQDc+RJy9X1tJMpTDiZkixXE6ySXV85PW/HY01b9bz21MIVvoGk
+ItyDuj5ve7O2nw3Q9Px4h6T7ZPZKaBfOdclOQBu8Z4UWbpJXFrThQR5aAPzPARYQ
+Uj55DEdgFJBwA0ASdeg8psjJQuaSiQAsH+9O+V/9Hcp2ZdlC+LVivsdy+05HB4Mr
+c+CMVfcwqevOR7y17Lv8QcHDpPQtJMECNeH+wMAgvlX4sAh3dy6ZVbqG0kI7PvaO
+WN57V++/TpTRby5vsJkcRkz1p0kv6NcgWGNbqihtx15563AqhTOsu0+6HtbEEDNr
+6LW9rO+cdyfn/AgZhXuRnB5kmEMkl7bKfNFTBNRz9XkHoAW64vE/LHPj5nj41FQL
+FqT/tYvhZ8pnbTpIRVtWNcemuH3NK13vjMxbNZIj4Dnb8j+rcIVYkCye7oUHSTZz
+ztlEuBDl13kptwYYFYNXQeIvsartAR2XbNkXD1ax39g8sVsbwEjYW1N+5QoFbL+l
+6g2q1NWJlum5SWqs//zNikuB7yuJKmCOReT3xID+UGwxg/MNBDznVOUpFYa9+tb+
+i3OSF2LWtxnqtiDxR3HT1caeSmrAWJgfFrPHzeAutSyQU7PL+Kld8FI5gKaMQQsQ
+h8cWFM5BS2lH8f0Bpwiy6Wwj9xhatRLWF2vVj9rLo44j1AxYNuB1pHx5/h0RbY0l
+SeHGj4ahceEkYncJBaZzn/7epuvoXYeYu3KniY90ZB8A0tFV0xIyuL1Z9gYxNAO8
+KOIOzR7uB/Ncq9uIyHZvwd3ehlvH6s+0DX71AjiaJGZFXCnoR+rrHC3CzdrURsT0
+bY3qjzQ1godaudvm1tBBoMLTTyWRslHLARXzCbLhMme0u2RUUddz5XS9rGSbMvLM
+KWIubKtIyKQjWdlaBUPiuEnIdi3Ix1VsYkrHgqVHJpmsZUYDucPRQ0bxzMvAFJ16
+ZmxNnLv0L+mXMhXhFNGdGX4ytFqB8lnAvVGuSAqYBdRRBUzqwVH1V8KK7URlzySt
+L6g8gH3BaEqR4FQsdZdJdtcR/xnL35vlfqxhbr+0T7l2IGK65kP7zM7yPtNte+RM
+v/Lyldmouxwq9gFouT2jtiH4gm9jzXhfItdVlEOJxuLVtN/j/fc6+MJ4epQa/+QD
+2GWQfOzwoP3UD2m+3vuWDnvQzTQB+PoCtmswwVdY5rayKUazh7MdOpKLpjlPwGv1
+0DxSZOUVCQVNJf4ffGi84tJ5NTwTv3s2zW5kS6vV9G68Trn3PGSBhSuCYUby0OX1
+R4Owtj4y+0J+IBjm8W35OI1wQRfGCZdcWPuKIBy2LjoA33ADxvUbclHF42LfzJHq
+35z0iS0vJIi7m7dSZ6nVidkHXUtqZLFYuXScbHIDID0+C+9yhTx0+I3WyIDUXWWH
+hMQjl0XLh0BiMexRcO+vXHBVbO1bESekLVOS9ArZZz+LpigkQVPoXZcKocK++6lw
+pv0TH5MRkcalqdMu/eZtc0nGt93VKHIlVR9zLP4d9bO2kvcLdpYRntOhf6Kx+z5J
+pr1rsPNVLsXxng+njBdgPj3Houke1AJLEfxXo1chc4tBP8o7r8tCb+jsv5Z8/Jiy
+VYhM5VIgKMMhIm2ANVrH9VwhNm4ZuosIPkTQdMnWRWcwJKkhV7eiWI9Mv3wI+tSC
+pn+87GNnmuVexF+XYK0hcQfIislssWOEdcS3NsehtuauPw7ZxN3ff0BP85U1ICqq
+rc0hOihSseI1AySZ0TILp33kdOwqm64zX0gSFKfA0Z28znoBf1K/aRgl2LoMfs4b
+c+ZmtSUUVlEw4O222Wn3CT2P8fi4oIg8PBn1X7r9qvvj3BABPwT5c0fVjSUKmMIQ
+/kQjIMUc1j4+PWUIa6/iC8BjBWDraB4okIYUyte3f8uSuNOdjgNZjL4tj5XKDW5t
+whVlYnYDQ7J3I74fsI7Iwzzr9brznpKtUAPKChYMBeLEaHDQ9izec5SAZcg8Xz2z
+JSI5axK+ljYFzBc0DIYtv5XxHjslPH1W6Neg3r5K8ALito6OUusYLhPDB214pkeE
+WJcNI7abtmu0DCkmnXqIjxDnA3a6UZi+YiWTzu5kRF/+Ahtvq3+chFqW8AgD1X0o
+GSznfOxEEFjAJi/huzf1eQNq/Airl7jdFwyJODGOPsKVc/RBd4VjWGuUbPM0tkNM
+2lta1CGgvwfRDPnaWXXzqirS3W6F/FiICconH4lfwXvxM/s24JQTBbIOkSu8jk9F
+IP/PiZLZxVNiHq4mRW3UW1HDe690vGkH3FZQLs2dIOaBE9810/o66/eFJWsIKH+N
+5CHs8EhtIH4Gv7KyJRP2p0qQkwGLajDGmr4iLVaXevYOYjHi4YHDJwLi67Gqdn6W
+ufdyK1aNnyF754THZ5sa1hzdvD6YabV5EBEXim5AVujbH93FWJlpAWQKPX7t3Fkr
+ub7Dmd21L64tlng+WTmm98oVHth+kB0JMuxwY+b2PVAOSiQukJCBcyLB64YTa3Ug
+j6UlCCa3FTah7xPY8lyZzxNUFOXTGIbUU9uRhGvyTW466fYw0JPenJ9QKxjqbns8
+KvXgwOuA1MixwLPVcsQ8SLzmQFftKYD/t8OtZoSjwEDMEi+yyGGw0XKL/99Qjpaw
+ZNvG8JULUwGKlNLVroWk0Co0h8xf7NUMiIN8SZF4QorvBkWgw12peeQvR4ftI3TH
+/rVHbqbsFDrEfTcwjtmdFLlnsi4zaQpkhBV1x81/RjQX94xLt2Gmtr+wSGskM0Dj
+WAdHNsgkGhN1CmKHkylPOBFlSN33LiZ5m1IFdii1j9yTzbqgc04XWyi7q6UybKU5
+/3KTRgW5agVz0PIQEc3ebTPgPbF1zFYtn8+AjO5xQr9YpYiAogzUOD0fbZH7odKz
+J5fz4aoZqB8DZc1mPlrJkaLbtjG0+dkA1yDPuyrwHs3TDoTSP6STntt3UZuaWllA
+O497eRb9FmoBFJuCwcsyBjSzi1ig1WGm3l2NGcy9Ql30RsS8hP784GvuDwh6Dd6s
+//cCMLeSlIFqIgJh0Cc9Cc//fn1zAw+NnQzsQTE/fRDglkSmSFZigi6L3MO+8A5T
+VZx68DJjoqhi2rNVF4M0AFCUOCdfs9pDGb9wcpEsR4CFUV9f1ox8P9RUrCBxqGaC
+X4p+t1Zn/gufyMRd+govtIcq9juLSHMpcRsGGiVRN7drmBDfs/i/0iOMZIo/jPd6
+BEGPIW6+V12x1ceRJyJ5B6BlGqjBq7Z1wl77nsYVNyBJxNB/wGiMx+5ePM9D93Ai
++J1pFdV6JOXLnzR/Qylvd/Rzwl+LNdsClldcpO0/r/cuzRYRXyZOdrreLPz6TG5f
+IgcuH9dbgW1uCD2WEFcny2so3MlliAhlt8ag9O8m72YndZI6oO8mGA0cNeuWYe7N
+cGVXdU+O01f8mjIjIWFXXn0WcNsHnfyW/JTnFmivYz3i+PMGWoh8NrVE6u9LTgJ4
+MQx/mBPSfgPnCVd6gc7e+k+7er6ElFtuWLjyFfO/4LeNBSVVDKPsSq3v5mkVwy35
+sXor9oI4F/Z+nfycaOQgYKQwXPRapeTCUM/Sdcx3SuG29fPvlgq00Z9QWe2ryI+p
+600PTlh8SZGWaspFmNG8VV8gF5pdE0ndklODE8XkfEqa6ygt7YBgqK8I/BUPSPNV
+nKeJQYTUWIJRJbzcr5tfaI8tIXhcY2bI66tKvjASkS1uDVWLwB/N7NMWQ21XHokJ
+ywj0l+mC/wG+J2RnJ3/eaTuUPbcf9ocohqhSH6juGnFWTMK7QjWMw4WW+j4iId91
+Nd/8Lv2xGqUCbrc3skH4z7IBjjdCVItsR+YshtQjyzAkvG3TXsCnNYAR4KgvE2dC
+MRUEbf2iq24fYXlyfwwqr5Lrgw5cB1kFOc3H3qVK0vMAn+iaIsVI2x7oLQlkYJl/
+5OIgDxWmTiK+1CerP3nCjKqvvvBQ8ENEsrDK6Z8SXu/A49CcKMLKQRiSvAsdb6bP
+WOsAtquXr+57lZarbMAP0DQMvvWKjRuPuFtELUfCIyAkxF/NQwZujN4T5N8L76cl
+1WADSwGZ6zNlqb6BmvnTRm+Io8DwO8ihO7FTac6zziAh73Z+BMmtTEWL91biapCi
+gNXq0qteWJ25++JkUJ9aK4k+1/tAkdd3ZIDN9k/09+5ZgDj3EI4P2lMFkpRneXr6
+EnYBcsJxzVPaaH4o0Iq0n4bJGZoMp1LUdDstE5FHrgEQABAXtdRQtxRrC42C46GL
+XU+wpxDKvnfqgx9fE21z0thUCSWT9u9PCmtS6cJt37OAuZWcg7URuKzON9InlG+b
+92pMs1fb/OAzFB+LCnDJn/VAUlxoED0+uVAeE5ywbD9qkwogeN7rTGJ7ew0okw8H
++cGR+kwPVQXXnTIn4AZRafRXrKNsA2tFqPNafyUzYY1Thj+PmdtOk8M3avy+G7Gp
+nDXwx8w5aE78qSnrdi8PFr16nbq/p6mPVU/crlZ9Efr4CFxNZO6E71tuKVKlRA+S
+/TPzlVqjSyTOtyd4WrWsQsApZ1sQPmaAQD64d8YQ4oUsuJuguk5uWeSqtJn5GNAV
+SZtlDmODoKGquZDKKIQISLLaCXO5D0v23xm6yg95/HJNdt4EV/xm9adz9XViUtCV
+b53nqvMIdqFDlD6auoXJsoqlI9iLdV6Y3vBjCEuK7BPmcPRzJelWmIY+l6Lz4jJD
+mkoqea1mgYopWxCRSiqIZ6mQR70YbTXclL8QrVncaYl3msBAlUK0iNkx/FcwsEh2
+mxjA/YrISCkaYs4EleykIXCSWqPqSyAk3vGKveAdlA5P8KFcOxERcHP1X4Rayh6J
+RdCbceR5XDp+GT9zBHPZWA3XOISAc16BNqSWGRHBN8y57dBEQZVWmjcJ/DII+LRc
+VKTiyMzJitqvPOR7sNl0nPUeDEczNoXkqCTmmAt7b3jv1w76CTQNoitDdKFyUoWy
+Bg481cw0WsM/S7TgRDFCbbe1gAVP6yrpPOnRkMFEo3mbkBz/n5PcqIvob/ERbb8E
+RzZisrXR7sVJFetncL8Ucl6pYs8OVYKZMmr8U9EBBFTnIeQ58qadOcIjX0eP9Tnq
+XNOoqh7DzTx7Dd+FDbe+jZcA91EC0I3YidQN1tpqifJ+eIejYW/TZsSc3jzjprj2
+M3C/z/a/C4ed/0eAUt1dEQuVzJv7gNble0a1Rj/+AEDOZGftvjmvVvW9ojxQf6Rz
+BBEcgVtK5hOIHuiPcpbpZZWQLOK0PGASYM0PH1jJ6poEzNrK0y/ougQS+9g5EAnG
+67TTt76PC98GLDgwfZ3DwYDuKzCqtvlMtQFNvXZDJKjyjA+oLo6+Pb5vtNfgkmXF
+oYsiNIxGgcYr7fsGVFjvppln+EHxKvUxy7smS5+eWCKjXdNzQYL3XZqt0zS0H2ZX
+4jEfY0/Qk/I5hVg6btFhqhGD3aMTfykXM/lO3pbRgDkgA3/sz57BhS5SqIemQvgu
+RDOANG7vq5ywCJgz5uK1pLcrbY+nXtV4JpNnayaPfyLFj2nj6CPnp9ur/T2/P/9S
+wwYln50rZUJHk8Cb5ojpMcuUZkklSvdc9h5HGM59Js7CUtijNn6VuLbICRj8yw6C
+8+qGeFD32IbNXpIg0uvNKT9Q1OHr7JKNL2Dc4f7I5rPTp1cMP95O7HySnqWPeMsX
+kBGly2xnPLZFpPAwIl2wARScuaJhVGqnvwQ/+1uk3wHP8QDP9qQV3tgRxA7o14J8
+N2yB0YToWeMPhp5Cz7v1fzlxhTi44QE4k6qcx85Nq0Uc1PDn24lOZv5iXxKHwsxL
+z0E8o4iZtT1kt3SnwXXbUJKiBqMumsuviOu45Jx9KvJK4WtX1yRbabgb4dp5At41
+futX9F4cANi0Xhj//ERc8yJ9OKtPqQvyWq3orO6bY3c7dhaVmI2MruxsKkmbUOC8
+jiCsgvilKMz8PaWNtMPL1gygST30ROkpIqu3ZzGb8mGXWEy0rGuTpxBK72Wi5bZq
+74qX+fAx4WC8CIdCxXbdaoqXFCMvv77Mojtg44aosuKtZrLhNyGEeNSu089CtdGo
+LPEezbfxOzKYHOEsgr6MKAZNDSE9hWWs9mQvVJUeqRWa/IOXVvUXivj7nqF2156g
+b5AEZ3LyhgkRvGrz86JutzfrsTiU36GA2/BMfP5RHY3qhsvnvCu6FSRFfyMWf14F
+vQfz1OiI/uao2jdtGySo267FOyz8QxAlkYSw8twgT1SDdr7hEPXSXve75SZ15Ern
+FAWdNNd5FRscRraXAEZDEl3nOZ/GX5VyqKE+FyCIKh/CyBTtvbB4//BScdCgslCK
+Zo7fHuIaIV0dVuW5MxuUQIi1Y+3NFe1R9Cg5gWUr4ahhqSgxEwvaea1hinN0nvon
+dcyicVXzz8UpcM9IPZndtI5w5/HbjHq1lRnBja7I8ficX0dFEcvUdToagC5SAO28
+zQ7paOHWdoIFHvwP+/67HBHUDz9btzJh1jxcB4V1ZrWbYsTg3LFT1CLddiIw5FoU
+3Fl82ihGZRRQtF71j1bywRWgrZJbgjmi08aKz+RGCuHruZkPlZZMJDmtdnH7xi0A
+xb8rkJAlEwUcIYWv1efqKGEfGCWpm1CfHXvI9+Y/Qja2ZtirrYR7vQIAxVsGYBzO
+qNP9gGxA+jTxNly+cOTRYVV20onX+rCSol241TCJRK+zhVIuwr1RWzwNiSZV3wEW
+K69ik8CTEVmiLcDSOAgl26E18hveQJ9JRAQ059SJNn0SZms4lfY2DLm8O/eFBS67
+DTBA3D4gy1bF2G4NS6H8bUrUAd5UvNpo9qczGq2+XC54CcqorL+AONWyBaICs/T5
+XZYehsP5qwlxJCTl3RwYImJRnthsBBW4wTrd9kIPdr5odc2Re+qnoYSBtJOVlc5u
+2TXSV1rr/VaBLTGDkkkkpS5CBr4+Hi5PC2XRK9CYBtt6F586LMz8xSnWqU7Fa4jk
+Cz0DsBvKpUM6rwUUL3SHrDkUuibY72C7un602/0mMLyc8PKLa5XXgHdsh4MZbMSX
+pcLJR+1qcM1csTJrJtCbSX5Hyu3wI+9TfpH6jhzCi4ef0QiesiyDoeJgjFa8FzrK
+Iwcoq+ZqOcS2bw4nqULvzrKlEdZP/lwFc15Ns+S+JLeMZt6Oor5QjKLA9p7fWw8c
+TQE6Wyd80qsT/lwBowKIqiK6dR8QnCYi907Cuqe20Ps7qiORoESMYtp8rA+0DKNX
+RoeYK80WluejcYWx7dvKGkUrG5rdFEPV79WGpMdU+E/k+fz678SHwlEQZEgoqfip
+0UeOJgBbedekeIq62p7vZInSnKF1WBhF6gsNxWz7GmTokNNDPup4QlI++L4Z/cCE
+H5ncdGXNfYqMcNUrvnGKwvIdw6sxqdTIaWkCLB9SWgUPD1D7SC30B/lInkyL0SH+
+L1dwwOa/h+tqzO0PwEOUGxxfu4am4MGzUUXosRXcZBsUCzowmqVF7AtoJAcwUpDP
+H9BTVwDcU8yuPyAMCGZxts2Mm0icT82eDuiJjzL43UFphErn/qK5cy9bkMVUFcb5
+L7p1JIURvSDMwifNg2gSV8ldldLGtViKn284wtg6nMxADp+umI6IUJTluwJb2mX0
+6Hfa6TspEyL5DKFv4u/XRRmfDrxYJ6sJGw/PNoW75DQf8vnS2BBrsuAIEgr+pz4l
+2UqxdUXoa4chaysvo4OHUi2ZZz7hq2+1rXJCPGD875eeMIvOcIByQaQaRlLZFCsW
+ODLN/mmMhttsbBlkQs2vPU11XzKELmA7Igcm2E5qVXdPlH/BjJN1xl10j7hEZSoZ
+whdJYURHnXx0/cXEr97R6WuFnmlGArrDsr9wzfhD7ZTt/zv9GLzoxLshX93nZp3J
+lp3Q6ME0YRwm/Zjz4JB0jxxxe1pADhvk6DYThDX2esv4C2J9CoSbmDrwWcR8c1Fk
+aQbpuRpCsV3Gja+GDP43+yMBp2EScUdy7vY1A+RQgFYrfY/AFFjXzFf6Kcl82Yf9
+eGtn0ASZCcSHRqUcm5KqGBrsssAiESGT51jbZsTvly0Dfgo402qfEWmMe6P5ZLUp
+ekFacm1eR9r5NV9pdO+BaGw55nKVfigfNPBROFo0HwqAGtGozWnOJoNUUjtiUdAh
+7KQK1K+JzBjoO1RTDI/UA2ALVF2xILkXEABmsO6g2oGmklERkKBs0NkPsJoToC9P
+kliq/TSC/oggK8HzVIA6R1cGoaM05ThbHwd0E2SY8w8AQGAbqLSC8iJ97mG3QhC1
+Rqi1XDvQkHWRxjynEr8CDeekse5O6NnFU9B7vciXYe0BQS3VSFBXtTFlT71+nIaF
+fxRxzUw8spFYHeXIO5j3h5VqvPNBiWYDwmYgTjqallMD/oa3Vr8Do6hflTyw9kKt
+lTS1Im5pVfT4ryY150uPKbVYXyk8Lw0HZLRIynQJ11iyopEAsBeiFF/RSNIC4h20
+K0HSlEwdcC4u10YaR4W8A2wBa2POH+F5Gj/foOCoa19YlO4VDAKBBc5ANkeljbla
+kC97jw4tlTcdaSSRTqGG59tnKSkVy74LXFGpoy9MHc76ZH/5FeL+Zy1+8BG+hwBw
+zrMszmt+1NJcWa9kqADWNKluxxUB/lKkdMPbnGZx4Qv6rAMOfJwntSToJeUt0Y/3
+ZjOW7vjD0Ra3f50yWJcKJbAJDde/mkC7H+MyOKztf8XMYWh+eGL7eyJmEOVueAsz
+iOcVkZrlZU1jw8IVnaZz5U7PbTCrlUcGtbPFKrF64smIEgk5OkM7SRkQPUP1uVN2
+n0wFfYy8+KqktMqQhkaYeUbAodN3c3ILIWD5I1vwDWrcNAmjsQJ7c+LZrLAHMqia
+hEsI92IsCN4qBOiLI+1HUqOplluUhf36fRchOhU6StR0I68EbIlT3VI00hGbUDgY
+S8rdrtC6qIWdXoPFHJziIwUz+LAgQ0KkrK+ezCBwkCS+u79lU/BLHlhoZW2GqCY6
+5jMx1W+jqVcpFjgMr3QYIp8jeVMM7YccjlQnMwtVNCTII5Z2nsITgHomuvkJ98H2
+UPZ3+otwfc9oLibefECLfceUUB7PS5lK9KV7qlBuqeSHujkGw17bh2rMq89pPk/D
+46jotoqv0Ahh2rjM6zadnL3DkzefbND6PBuw6QpxiNAh1xbqMoM8LYPSEX5D0r+e
+iYZOrcoCmGQ2M19EDpEqdRvLQ63216fU2aBfYoTt6YgIE3AufUzggTAu659nAJ+9
+YS9Kzr0J9lQ3mdK5nZiVrHlYd8YeoUS5BPYBMVU5ARK/EGKfhO0KnwoIEjdjGsOm
+LKictHM6ffssTPWmdL1yDNLhn9pn94+RRpxn+ArrghHwukxy50iLkzQe2vgL7r0o
+U2V1zFa1BCWNo8NeJCPGLtTCgPflrXOmmvaepAQ14ZUnUuH+gpga0s3i4zRlg/13
+mvqA1C/qH6VRgbAe8etdyym+2wvrH704x+2q109K1u8GAcWlZ8RsnPTzD+iI3qzm
+OxePzP2A/oQiKvwuGjSov6DK0My3IlO3MumK0vTnLmOHZxw1AbrbFHoC3051cRaT
+FbF6et7Iai4QNl6yLC0/oLqjAfjksWZTdKufKDuewVDQEEuGRWHyc6sNYNXNqaHO
+QfS4Ii5Cir+cHr/2vJsi68MmQi8Unzx1TN3RSdBkejG+ky2GN6+kX4HJji4lWT9M
+vN7U1kbG/xwm+3gbjNdul++QSHwfJS93L8UWXc3irNztM5WPcKPsvnWHf2LC9ppg
+k0Jc5yVv7+mB2JLVBmoTHzXia4Vz5EJK3g7pq6gkYzjuvdSmi0JG8vSxMwjaQcQx
+r13Igap9vQR4sMTT8G4rxWh7Q6oNw5djm5X3m8eyieEgqiiS7vbs+ZAJGJJqxzjC
+HjxEv6L9Zah/CFqGpOuiCpeTkB0S1Kgx+ex2YNv4Zdsar0WKqwuERfP7o2J16qXB
+4QxI8/LLSIsp0OhFxZkRvUMHxlpfAhxwQC4qthaDqsvunR/gDyPPeJu1bxsEYHwU
+uRQ5RPsLRx5FQbu/OPctDxR0YdZ2CM0RiGWx6FTOoHdAwJlto8gwer6CDNhzMuMO
+QS2UhIbBHG7+Rmid4r7AyMNKoiinxvLcpxBYiubV1ERxQ1wWHjNE0bCff2gUZ3o/
+gYrL4RmndVV1i/BSetu6cPx4kohA+ddcsKAUDpe+pg8AlZ0w3WSveYvxY/RBCEHa
+hrf9YQmgLAPdW1PhtUtQ23MUXYA96hUfEdOsfkmw8StV2ylBZViJ861yCj5m6vam
+jdT/DWMwaTSj/lQJAs8xVELW5k8a4z0mcqYI9HG+5hu44pvekvmFskVplRdwZm9p
+DjOgISSq1rmoH4RaSpkMY0cN9VHDSZkyVKuPdVrZLWzsX9D1RVXUD6q3mmNcdCu1
+tcYqAeyJrO7IPhqezH3F5Xr7zqtby+/2Ndgj6CwbHlR/h36/N2gQ0K9Q9Lq8QF5h
+ajxHmwV9jztL2K+ZCJNeNP8nakqRn16IFzcsBxjQ4Ll1MJ/U4/YhN0rGYLvwJTTG
+b8lRakYHG9C69d3Jat22hdV/3vxC5wQV2iICdaSlhlDBxYAOPDvztnxj5s5hPBq3
+4mlXJSAjK6cpClh5icul1gd3xcnDgztfOHIhbLhszgffCbBcFeSi7e8Qg4VOuDK3
+YqrejNTikIUAo5zd2iETNtjoUVliG90dl9qKC3q4NOQEFR/FfXBKUMXnC1b2Qy7l
+kutEOWyvrWfl6AL+Nb8Q8Ni71OdvmzKhyxFeD2ICNUrxDIsDvZsvN8pFHTUgfVxc
+vqbj0IL7BboFVI3skJGJzqLGOAqc82pzRsEwrxOrtXMe9rGwN3aenTDlwGv7cyxF
+l11itZ/Jc5lUV2879epkjbUXiP8aQlkJuEHLIoLT8vnmXv1L0X1aweJfmcArC9js
+55vdr+1zkoVmjKptRPAm+t4FsNK0jU+NiaDHwAOlIjbJckc4eCc0cSX0R11qmwir
+O7FpgnksSaVYMc1Awr1ezJa2ksrvGAW+O2x2OfwqsQ/2dxiUt6OHzD57oAp5RtEw
+4kSh/lrAhCm0EKS3N6meKOXKqkCZV+dU0GV28GM47QfQ60+SkuyQXM5JRVMVEDN0
+qlDh1B/g0oC6D+3YMIydi8nfjQ3+1Pw8iBT9aPjVMBIvnJEUkMRw4lSF670Q4BHZ
+b5sLHQC51QZYfNUrvdgT5v2SGUq0ERbrm4clCT7fKfErPB4npJqGqafuNO5vI95l
+1QfQF20jdL1M0YAi68X/sJCVBEtpQzzD8KrcJrSPjAIpczAF9UGLjYv8GiYoOSyp
+zu0FMyNqshVe+76QszK1BG1r7UyWAUh1xyiX3wC91NRrTlDy+G4pKKyEIOl93mrG
+6e4kw7V/WUqjS+IsKTOVXHwttEpTu7w8dlXxn0Mk1yiWllxQjeJoCEKHXdA+dFzF
+OG/x7RREHTEFkJLNskQz6oKf7Zjv6r6Z3sQ6RYs72VK13Af9VZOKedEevouqgPdG
+E8uZu8ftB86jgLCeTCXrcRWrqeWaFyybD3vd19aCoxlgjZS3uL+GysD/Qt7IsEGX
+TMX8Fa0zQXWOX2dl2x1q8tTpxmlKP21rdfVJ0sr6F++QVr872eA7EItsWWdDStvy
+hq+ySYedj3ZWB65YD0fwOocq4yTVEtQAfIucIazXo/4KN/3jQw/Ui5BmHkw1cfre
++Vxw81CnQT2vBaNgOws6wGev/YkcHrbwoKJzoyJTasiylIHNPKFAK1VJ17/NZWZ5
+sEdod576quT59WNg8RczGF1KVZN0uP2KgE2B07tGv5FoFXB4LfiaQNhJKbDDGzwM
+Jf9Ma40dwXP0QmtlKBCCj4Qb/I7RjNl2FSa5jTFP17Qp3wuS66h+MjpIgh/H7sAs
+p2672d2rnqhMtWdvM8ItzrWfTi3O3dUgV0JZyD2geA29TW/Dwqo8WwpYsuifr6yv
+8g2Vtbq/asA64CP0cVgIV/UZOfaNLuLx6gRH4DqxcSTZ118mG0/lazIu98zyYDWD
+NZPxW8O4oJCAZcVk8DR39gddq/YYlS5ys7cdKZG0eM87DdEmmvvPfB7dZJzNJHVs
+KxOIfFLyD3o3BNyRdJqO/+b2796Qy8fqUvJjq4nchf6AjPwDxY0sizDnvBQLrTLm
+MDNB41n+MfnA4HvchsIJ9EibyzOe5Jwyp/zXD98QbxrpOrIaStph+T2XKvXGmmFQ
+U4IL5j6oz/eoc+OcTnyLwek8SRSpy5rd3J/txR5z3Fo9yw+UTlPKT/IXQAOfzi4g
+iDjLQGEzn3AX6vlgZ1rbU1RnDiy8BRq/TSP9ZBsNFfkfxFznUzNjAA6AXpD2Xvwa
+QPxXRM0DTMCKZzBk3JvwBi20pS+xuHfHdBz2rUieU9BgXQZxHjxQp+DFtBMGhN6T
+EwD/RwlYsWBpQslAUL9NBhoYDQ9pGyvhZGeD76cKae52c/dZI3ucCTqYOKdVzipq
+7XNZVxfVCzcR3S8JmQr+qSXX/6sWCzkITWi1+8fekCK5HcZISPzh7dkUCdwu/r6F
+rYDkU2LHoDIagm0yMBUmzEqs0bQZVDyX00K+BZ+HJJxFl9rXLt4kz4Xl3jDKXBll
+NINYX1Yrj9Zzk6PdBF2qumdX3hqUYstuAfYwdaudmdMGqdutoXwC2rpONSk0WdsK
+yEWLxfcQprfBsN9kYdF2QhwaGd2BhiP9sV4cAkcHNMb8SpBCYaDo6j/lbaBvUqhn
+RdKhhaBtH6XpnePTLJTBATVQZsvVnY8PTa+ckP6vmsovK6NZLHdeOCR7Zs8LHLCF
+xSqOa3Q7M/Z/zbrmjoFVPJ1LQdLWXKID0erR/BTIw4TEbAWA9Dqqc9XmXS54uxwW
+fDC167rH7SNK9JUKkHFZKgZxUk2mgBp3krma3wSvGUmxCa3w0TghZ//30G3L/bAR
+fn8EpzjP3Do4bt9oDjmYnLTW+/TEOSxjLSHzB93fnI0EKWtiZg0GiOGTB2Iw0RvF
+bAu1rPMlq6WTmrlg+Fuw2uKuCk8Y6OyGyaRO04QVb8TZ0JBGp/b4jX+T4Zi4U/wC
+lc14eJiR1+i8DZizMz7qJV5kJCwLOONWzBxds7yjVfY7ey6wnhtblFFznnUjpuhs
+qwpudohMbbtsicLcLxjrkQLoG8MEpgQtJAS5rCxiKVTZe+JwSI9kTYv1ssAAjgJs
+VodpQDHKt+DND0eeBG14net4pRSI4ZQahuJ95Utrq/QWlvptvV0R2/i4uanNdNTz
+dYaE2uffs9Kzs5kiT7JpBqVMX4uQznPhU4ZweJnZtcW5TBv1tX1bGAJ3b4aSpOC1
+el+Z0/qk5Z+S+bNtMMa8I2Lg5xcIcAovOHY6dl1azyFsAaw+qmvKsKWwFv10k1ls
+nyVDsH8zvdA7ts3nLRsYwiXmK5eA9n21WRB253oHh3Ft2WfP4H/HM8xo8te3lnTD
+TaSVn0qg4tvFbiescWIG/e/qR+De18vm41J+WFdO0bTuqmsuSVaCyu4hnrHgO5LM
+IOTr2H4n6sAAmO9L4dG3sA0QoU+1k69yUrH9ReP2c/M3GV2MlA0g3zwYzi1H/uAQ
+oR+o1yG+U2Dq16qEM2gXN1NIcgjeYRtlG81qGWXUHkDHWXaG6GYF4UOr4EboL1UP
+noLX2R3xVji3Vkc2u+vo3DOdkmAq+NgsuaRI8VkxgYr8oVeBEi2BlrpucGCtt8IB
+vcW6eyFwL8QlzLCHbL80VsJ5LwYaAEEM96IEHsQn7RiW6H9bVzhKI/UnvhItMETP
+zixueiKUxSctJeQnuacgGFRXHh2qxymwjkayLv+efsEK42J3DtQsEXIvqY5ri4dn
+cU+RaQOdx9fLo9xy2Nv7p5x0MOP1Ntib17hXg3mrpc7cgTjXT6G3xTk6FTCA8ns8
+84wNdesXx2luk827ghkXYz4QuEo9sdocFvouV6+WEPHkgycKcadlIdHyglA1h/nC
+JbGvsuZHmvpQMipqSUQB+eVtQ1stWSwZdwL7DubLZjhyh4jCtXmoA/Dhybuci4gP
+RJY0Ef41f1Vir+yrLoXAp0tfHSqtex8VxAn3ZH6qpXJLpMnQghLp9LEhVtECywPz
+7/W2znRM8JgiysapSCDATvzu93YFswah7z7ZtnXY4ssdUNtt7LuGcHw6JqvFeFd4
+T9s2YMH+QBlIT3Q4BlxMuBLV0V2h2CQLODS9Afw+TuFbdY1gT7hIcH/S4X+D8xgM
+DMV26hbKCdHCFB83FNyvTtmFN709pd7ieIZvXqptMEAUehqdRBYyqHeavGGyhfG6
+mSYfHO8IikFaiAPRKRRP4podFYn/kfWM/5eNOHzGKp80ovUaP6VVz0Zgie25GJry
+KaJ5xvSBn+sPPdRaYt1XmTYqvk68hX+MQKG/Vk+xCGs1jZ8vGEYgsooijl3z0Dpo
+0LfZhioG3ov+WihjTR26zXPQ3ZVlrjKzy62kenD+S87NFYBlLSwfFTvmC633os9L
+Nw47z0mut2PW313cBEFGWY4r44zZNheBSyQK3kFuVXXOXw7tDVOujlboVs4AwHd7
+fgiWThCIRpwE1vOX5VaKodw0aQuRdykDZhzGuEKbi+02ZSTMgYug+0EBcZxakJqp
+QA6YE6VuvSvjNcN66luLO6JJuS43KoxS/IBb5XcQKxwjumxc6UEbxH8+dvB9N9CW
+mGQ16kVzzF0W626sPRwD5O2R9GWmacoIHVx2n38BJD8j7pFt5Rek6dFciHb+wa6f
+g5tDf0aqGejvwxBWqhmR3Ci5gsTVnOFlZh4kY8LjSttqGdNSxy/A0kNe2Nv55k8m
+OyuS7RStIGUV8/DIhduOFg7vVmdWvB/7WQK6ZSeF1as0DxO6A3HflKMWl+0ETLyS
+w2pKbizGpzqI9IPzZ/WuDy7SHtAToeR6XmrFrNtROuzkCcCppELSxqQCEEpNDOwc
+fgfcIwXWT+nlDqAkZycVkjxGk/4Zn/CyObqs7Sh6RetQCR1gfTlex8SePD1wNTrc
+gdRx/aoRn2JKEMGkus2HEuIB3Yveaf5cfSCYKxakjvRDZ0ijYu62tMGDx197soJM
++99kKjvRkXo5ZMURyDmun3mO2LWLtkhgJS2qlY8m6zRY8cotROICB06xx+dVlGhS
+B2gH8Sq1EuVdtaEGhWkXSDCB6zIAvfsR5OGWMi5TJZnQT6J8Q5YfXH2kgu5wp55n
+TBBNyJeHGuoPQe0tmPMcnxgrDZTdfabKhuICwwansEltFiwjWkxDrQUSuD8Yp1le
+5B18ZIH8H2ic4zQcIkAUFWUGkaJnLRQfN4nNr/ZYLJMVjL6lW3mPZZCuVKhv5eAK
+Wvh9iLYHGxIXNf1SM3KVdGRwbEHP2du8pkAE44pLuDrza5NGRhsdwHVHrcqqMtnx
+666jYeOlppSIxrc0x4SDiEHwD6vpsT3RdmZ4AGqXYIV1NTFzIb/yTmZy7Q8yAv5q
+O7EBagDx9dmoCZjs4rEsAVcbqDvvt24lLLFzb+yYxHng0qe6ebVBW3f+o9IVzGF8
+tWCXNeALPJENlah6rrZHS3qZjZ1V+CaXA+ima3NL5uNJ3yzBeiJ19xAMYBc4TNsZ
+yvYYOyjxkkqeoM8JaPL/MpUO0XFsWK+/bXRhj4zBSvXDZdgnV0sKan2rtqtOS2EJ
+eXkOay2xLpkeMvggpQlggSy4v/S3DU6a+mX9/BskrxUob1ViKPId3h195ZkWSnH3
+rqAK1NO694XOlsEfeVQsS0sKkZC54EZ4qnXe59YJ7CAmyb5HlRCSjSda/wumG21f
+s72kd0q/irdOGY4NYoV7nhostbehphq3cqr8GbW1PWKlOogYTbLsrosGh6z5GdwN
+WITkd04B4V+Kb+TIrxzkUxC69taI4EIpZ4ms8lMikqwyiuRfZTa3s6q4c+paAMKx
+MeWeEq9m2NFtPNpsLcreE9odicUrn8kkJQgEhvdewkoCvBcwHykYRbFEmP99rTSq
+6mueYMwTskenK5yvT4oZEn94gSkeC8iNaGCURZ7/0Tu/GgIVk2HYB6j9O5HAkL/h
+OrA29HISNAGN5vcF9mQ9egu6W9JyW21cynJZviiY+xQENK+fiGqcWUuEArY6L88T
+TDhNVZzRs3KU8HEa3CUVCXRyriNU+Exg4CzmGjrYf1cXo8I3o/RcPhFLice/nFyc
+yZgNksgZM2zR9sFx9Cj02luaaaShi/VUtvKwx5vulyQwHUaZAHaxYO9t7/WEgehY
+z5raRbh92bpWzNqeKVbosCicqWFPHM9Xbbj2vJdkfFn7xlZdxzEjbeHJUAepkhSL
+gtgNpxuZJKzw/Eoy3h7XoCj69lVNJnRZjAlnllQOcn66ZmiO4b4ZxDfaQD/VyTmW
+/8nx7PiSVm/sCReYUYt9I2rhefnlTZgJ1Q3c0umR8iR/Ec77zB3USHocvzRWEiEN
+nLGxmHkb5Gvwo23vPCEmTH3p6mrGlVrsRlXDZK8saj2AG5AnDn3VFIz/uROGgUt9
+3Xj3cxL599UjnXTkB/heKjKksWDXNBdVZiopvBsNN/Q9tJBaEJcKq22nEB/R7sQY
+YoV+UNQJaZFlTPla1c3PPqLxegyhRLcm15oiZU+W9NN5SR1ghqcHGsoWvcwqMLkf
+KtxyA6SNhgddQsQD4yVlOCZOPRHp9FohnuV63KQZC1vRHhvd20zjDlW7cOfl9t8F
+JHAJbsFTvpYzHnKa/xAQhVTAlBMMq4ZeJveHEbAa4fnwo44nVY7I/9Zn5TL0fHmZ
+X6V6kd7t9Tnj8ZBODqGTGVCK1TxLQi3S4t+egjf7tuV4duOPU3tzGggPskfPt5Ih
+CQ+zxi93ZR9OSaXQEOe+IBvoaqunpx51y0oux5Z9iBefnDHJgksmgUTT2YUln0kb
+yjbJpeJZAmBAB1zT4/J4+20Mhocqtd8Cbr0h6DcdZqWGIsJAk2HMqpnmjjzmgyQq
+pXuJ5Kyql8CgCz+w2YufGbPyViObx8z8UcYB7Xadkx7Hd9C1pbDZH/ilm7DpQU9t
+AsCK+2t+vRfnnGsCWikNjBkIDi2mgvJrv2bUCQOn1yEiPdmUbxly9k6HZ942R9aI
+5336E/QtBRh32Vw+nWGAGOMvxh0AWnq2dUi+KIMjXE7M0sh+pJp1zHWDJbFj6mh9
+bGuTgXpgmAci6cijKKmbIsMHA1R6w/z4hgmvtlwuZSABK1mtnLRCz+Jacoh+BRn5
+CSbJkEybT2AkmDfp5cXxKkouk3W0rIHQ9pdLWYzm50CTnIbNl/c0sofujVoGZDaw
+TEt3tAAOCIfzAVvP8Hs7uJDqXe3WfY7MBhDIYsvIEK7pSmRbNNHG5/FESElU8Zyj
+NMRoDJa2HiUv9gbVcU+sVPKo4LJY5s7Kqi1qTXy+wJIe2hNngNkwJlmhHJ86huWi
+432B/iVXHxwXgT7E7yWCRzOMkdwO4kEYuIdo/M/cqjNc+B80sONHZZR/9LC6sUS1
+PceVfAmiu7vH8reJDPyDmoH7MG1mFjUUNdFwUIp9GU786X/2utLOQ0naPKhHsuPj
+h8Bj5zcnSLtUaqEXhQErGyV9AqtsFNgqm4NB8pQRfDdPzQBKRizqkDCwqguqxSLB
+z6UlJCixgb/hsbhdcZ7kw5baIc7Q/vqgPU2v2QIp+pfE6hkTFObwIu2KH5xHSVlm
+qd302e39M8NGQY3DdWj/HXr3KHAepbX8N/mHchsipmjeTjSMvAZN3sMFCSX671V5
+cbLQSEt8NKd8MexySAeLAGGwlKC7IbIuS3YaxANrcLrCDCRu+B/8WAD96U26A4Jx
+EiGF1XhD1oMdR6duB4NZvM4XMdfuR3SC2RnlMeQKKQx+CPWg0bNwxwHxmZxJD5gM
++iuy5QfAY6y+ZZDyPD9apTiiewWslRuKFFthcBcyrhCv6ltNfbFb9n/zg7JqLNQT
+oJz6XuN002XEdt0GKJ1qHO8WSwnd7iTnrbjP6HbgkLqJ3dE6CJtZjhAezcGAi6eB
+1ba3w9iOuUMCX/mPM5hj/7DGnWqTMVTIl1okxJsgI+aAdYAKybSS7fP+fqV4GGoy
+yXt1p1mGxijnHGh6d/7MyAdg2DSnVW8pbxXklioc+wrFxjQOpvhyMKbcowykrSPZ
+1WYRtIoKdoryOjqQ4OaXHzaNyy3KK26M01fD6uJtMOQAkWRhsky4jKEQyiDmg++W
+jLV8F6Wi8oI1BvPpKWf0OBWfmZOsZVfW/sMN9LhI7s9NUUK9d6XzSdCZYHZZGtk1
+YRBbdEPrSS0oaHpTcfhMim8oskzqYqiSGNmRYHAMbY4GtxbW6Wyh3qb2rhc/EXhw
+YZ6uTSYi9Z6bkS4tRVbn6I6CMJNJa4dmSjWEWoX1OZUyHPy3rN4Cm4E1KuaqkFbE
+gCnkl4NNgV0XX7FAxT4RZ7avh/ny1RClgm5rVUhrNTzOo11LBP6ZAgK3u05upbB9
+JPvpa+3gE6FJEaDYEIDQfNIy5qRJgECVFoRvPslyrXgVVqJg0e9gAkv0SJ65VCnH
+rTp2mgBL97v73tyHzyT5zTMyv6kggnMrRj9xX+cOdawSpD9nuZtTulIqVAQcL97N
+FBtDHAK5yVgESj7wOevJUdxpjc8Sx2n9P+U0FAPokZayBhbzy1yzcW3pChAPn/gV
+57jfQ/DHoSeiQkaZkS59NjYHe9kwzgVIKGmFeYD/Tgv+XEMEvpxBSmKS3Wp5+M9B
+PEl4JSXxP6Sv4pLa6gWNLvRhdjaUD8AgMVEoKNwDq71XzOZ5A8xsrrQXQny1bSys
+ZvJRxFnihE2dVFmSJWhC4+zdfG0PkpdF12YzntP8w/zIrKPAOfD+8rAK6PMnycuH
+Z4FnA3B748h7qRDqXY0qSljhZ6OpiEbAC9hP1CngTY2Vrig5zG48dhCXVeZ+PH34
+JH5PpQ1BRbhoTguIBy50qrhapNUQDr2CTeJ3SuTn5ciBe4g6s3VSLBS1hkIDB0lq
+T70LBUnIHB2xk8u1oHKChEKQ6nh7F3ovB9t/Gwa3eF6mhjsiv3vkE39PKK4Pnqzw
+MeFrWgyhM4MN17K2TRxvPpdyXkvt8vBcc2WCuFNWeafat8KJQBe/Z0FpzceLq9bg
+b01dpmZSbsT301AC8hwCOS+ANempFeMLQ/Vc5zkTVdumFFtGa03jGEDoASmXxyAu
+G61bkfil5YPzAgWpn/EfJY9aX+HBwTaIKUBFIQEVlLsZph2O3qN1aT7ZO895kBwL
+MxWsISH1wdFFd9mUV57YJjE8jcXprksiur+2Wq9DWv4mlRSlBnAQ2wxm1u5pRKKe
+GE8R99SSTHF5r+8BSJ/IsC13twRdgcTtuqNUeBaOMjenOPN7ZXx5UhSKPppWeTuU
+nFKnIOmJgZOvHQo8USGMYW1/xtzrsk5hpdLAcmitczO0AaycueaqBDwKs0NrerEg
+w/Hzt9mHwLGv6S16PLuwsbaSvNEn9qcqMPPutP6U84dNjoF51DQyZ0nXfByzcSId
+acS/WYAZRueSMInaLqELbi0wdYYJxuTBjyyYWwlA+uI9TOor/p1l53GbcZZ4k160
++WO55CEhPtvwD7KNn3YVj6PT6IN6aXuHC4c1Clgk6Dj63KKXPn32w1wUsZjccgJG
+3OFIScU3s3EIV4vUtaZoTRmXSAYijyTNUk6sO57B2WHiv8s/AJDcRb3lwaQl08e+
+FgepJ8dNsXeEDxUly+Cq8/EiVk748bncwhsOU/cu6BZwzsbgKHKTdV4e6o4+P/e2
+wedAlC0+pll1LxptPcYTPDcZZC7pRko39V6qT5McYNnijiyDw9g2oaQ9V+2lUXhn
+68j12y4EA1B1bstshzE/5pKPZ5TQcEx8xEkxeKVaUqe0b0yG3HBWZAfNC9/08iZb
+64lZFnKNIjzR/4S3O0KuioUadbQbsTWa1LJgLrcTUFK5C5JxbdSnTMSIvgh3TVsb
+4kY71VBMs1xFkJbVva1eDt8GlLcszPHkzRltGCMyQWNXk2slvwZKJLJUWnoMI97G
+sc0bgkNl/XsKJn1dswbfErYRkRUzqwk6rjNxqjS48LI22BPrB93u6Kx+13+RGNb2
+dJ21wGguMjF05hd6Or3lpxGJFKAJb0+oUoUr4SmmM61DsoJTj+FJCxfPrWmDpenj
+1MNsBPojz+DmeoSKsIbDPNQr0LYqWYrbdHOYQYmJx0dwL2beTddrBtfH8I5+YZC5
+ZSA41ur0f1Km6DlsiikBvkHcz1i6cFXVpn2OIrO9tLS3Jp+mwDyLULfldOfjcAea
+/XoNXNfAHlNgyQDWh47o8uFp4BuEFtALspIj7gnG44x0E1bG7VQ4h2t6ul7RQdUy
+3lrktvmKN4rbIjv/0/vNjiSq4CwGMiezOT3JfE4H+2+HrhemKyqg+bYe7UPJvSdn
+OQ9SdNJszct28WQb2Larh6Cz5LZ5z/hKUmU1D5+K5FGcmr20YOibnZnPbDFCJRu8
+6JALCsqrQVBVU5V+/yoTw/d2awPZLgpNbZR7XImmghJeUAXKCBCYP/C862j5eT0x
+fVDOWiQKKRmiaPU48FfswO5fw6rKvLFc0JSwJ3DUdeDCnR7u4ig1LP69zRcfmpgg
+hZ0VZQH164UBDYvwBRIJN2ZIO6Tga1nOXpVDpUm3T/n1PieP7SoAEZGRGa/X/coD
+ppGRs1qFWjsWIb18tfYQu0zJgq+1+3llKq707gbSW9FZ0TVsMQTVaqCRZEuObzL/
+KE24GB3FsAUVsMjmuBoIrz1SsYWo/SshWgqixaR0PHwRMGzPJHeT0t09VFBkkYHN
+nCilIjhgoZwv80GSB5quQ62RP1fRdspQ8H4SulTBlBql8EvCxZBvG0kHmkCArLlX
+puuxt8d7A2LVImZ4Vx00a2tgm0FIvXCgnqIacNgy1BDvKekOMIWBETgWF5pEV9BU
+hdlEjObq3FZAnuhFDj/IMtlq1NpsH3qa8eYAF+M5i+KBRfp4pwwb8s5lzoOXoXel
+FkGzQJ9tFUiNwz15ztNltChWcgpGztFVz8sX+Tm+wLIJ6JTvW7DTZeXiEllh0uub
+X3qG27J4ROVTYZA+aWkwh0HpDEtITFe727Q+bXSDaQOhxTQ60NCAD7pErFp4l4nv
+e/+c4C3Y8Wj9kG15rtnz+XsER14C4kqD2WF2YsNeUzcrEP7jUX8/vT7tub56Ax7w
+yyM9QJKNdNsBS8mzy/qoVoK57WOoTw0vZEV7G+jqvogvwxdo51cj4NzWUy4CF6Yc
+KEsFC5WzR8vB2TrET9sbU+4yh+3zP4op7axyRPXNyNsYa5KWEK2STYy5vxK31+qi
+nIX0CMLQUK7Ku12GUfPr3rWDVhYsaXECQSNMQdpvo0gJZTW+6VspBmNBSUoeqRe6
+WzFZYxsiIZrI8PizrnUEkDXksJhdsbfo2JAG6q2fmzRN6JbZj2xgFDe+qwu2laW2
+fAatLpoX1wAZPmD7G1I4tm0ukjFap8xRWgs5n+o+6n+bsKGJ1X7Mvs/eD0i8eRax
+st+Yli8aFWdaisMeG6GBvVxkvWIDhPegJ6J1kNl7sEO3ceYK5zJvt5DSF5hJ6Awu
+jUGuV6v06nWQjfV2bMG8avDms15O5E1CxlKAuC43Ig3HJ/3vJBM0uVdJzWlIJh22
+zoPrCsHeAQpZENUwVfGjKeHTVo3aJU3bMZMrL56zQvaXPzWZsX+dIvJgEdjsJJJV
+mk7M3Xl7HtYWRY1m6v5syxrL5uoC5QXdVYtYqCbiXUyJGDih3TVTTPDh6LWzqn3W
+zxw/3P7/ZBJTkmlOqTQAzUwfnSFKQeZmRt8l1PFHAC1F1Qem8fF+oJGucVf6a3/Z
+D3PH52t4g/s1bHrzHYIFAmTghtK+vIo5XawcMY72bu+WlH0yMZE7a+FRta3lK9wa
+0qjppwv1gfg6DwGYzg/IzjFYLi3wMBvK8uap90seKtsYpK7C5VzVT8ctXyHhKxIo
+OsLEcfhGHtAEawB19nd5pe99QRXztUNbju/ZrZ8H0j++EYv2+f/eirbSfoiUQcDO
+oTzTlEdUZyAq3eu68uLaSniIT48Uepi8BPwkIH009Rq6ZqeenwB6FerLJ5Di/OP/
+QKlDFiXa4h4momwDwN2U2NSs0RJoMN97FGU4hK/vhX0V+Y6sRIjOntY/11Pc6mTw
+eMnRTWu0VidUKKf97BCmeg4P2GuytqMhDucUj+NBd1RUGnMN6C4ZSG+/T30C46uc
+IhjSK04VFM0skzhGRbZyoIH0nU+S+53By22NcWolWBciLR5VXq90MWtevbFIasmH
+idMfdmbW32koHDH2vctLgCUX0b/5Wgt4V2UCf7x7TK2s5j7eF4aZHhRSvk+ly91a
+q/XroRV8zyUVF+w9amRooAFkIYzQs3vxYMD2BhnWwU0sCcS7WYopWgnoEHkenRmo
+Wx05Rn3Aihie+FPgSW+CQHAexBuc1hI9UZyy+OIJSiUPFhT4BnQ1gTX5WmhLjqWX
+S4KsRFDXQLHw7uFEjOk5zgveUywLEymZQzPEdOFLkHuMvKJK/WDWdG0PPP81fIzA
+Ax/lB4lyDb8a+gu+cXtqLrOLEUfGvYnhDQALVyK0uEqtchiyZStqwYNjM2D2Epel
+cKp7y+GbGaZC1tF6SMuzyOsupHSk6UWxXfJ3cCDU+MT2OZaLYffMPVxpPC5Bo/bG
+8/p3hc4aEiWCRUG3pxLcEsK9XrZ+FKo8qqOHtBM1A4PIwbCLR463ZWezRnpQHF6n
+VZqddZwMItJ+yf1zuewBfejkI1QLFt+1A+kW8rL9h8m6KNhpP9lK2RWXRf+SNPvY
+z7YioYLhVfGnA7Gnv6QRC5v2B0MP5CgAXqRwAN89MI4F/Wb5CBZETrb0MSCDgCMe
+lv0dMdlih6xDQiqlrC6dHRMgr2FHgBEpQbM9Kz7lWwrfi1Yxic7E7xaXaCVJ9d6j
+E7AskHIRBwu8owABNx2W4+HtgLYw6z6rv8jdZlPGsv/yMdxPIyUL5az5vhdSaRKp
+IJ05NxbBaM0zM9yx+aw8sMXyTdy6HkWfo2DjEBItrTg7sWHj9hXzh491tq6cEWze
+Lu17Eu02OE+6CmJ0IfRe1oRbAW/HSw+GKoybHLRTCyAzKo5QEjwE1W59RIMtxOMs
+g7biTbIrcFuEJuAV36m+DEbGTuuXwmv/wWdJPypL6v7q4jr1QPS0r0l/ZZYZMGI/
+uHrDGkv03BFU0tJ/rjCakn9hSrfA7qYbNAbp30IT4rhPyFifuqgtbYNAFTO9Db3s
+08W8/h5W0TwRtcqK92sGveSZzRj3CE5B1bDgA1oqRdRu991JwAG8HvRN4Q4vc/aB
+OcxzZfunj5Jo8farEdcFqcE6/vVA6itJ2FO0/Uu+5oW0VCvhGj/0I539r1sWyvl5
+iQQkVj2BxxJdtkAMeaOxaxrpU4TWW1wW+uvZi1KABcyItUMYaPfkzUxvm2D4FV46
+zc9KZXEbqJ0GjeJdp6XvgNHFGkW4TQffkEnW0V2aq7RG8PiH8e3q6PkCn30c+SB9
+5SlJr/N+Ff3qnpcJEtqzyyjjZDhIXzUf4HC0q0IHT8Mk0Bix9Hlwe8p2GZP0rhqE
+54HJyimY0py36zyzBMNnAIoSSFASUY+ll7el4cu3RoYjgo9NZK43Z22UJneLPube
+oqK46c1MbEOUbf4+sEjTAsnLgZu26ENAmBtbflkLfab86HjEsKDH2cS6P9hMcE54
++OCbQVSAMX+n/ZWcJZFaO4luobouiWRG8VjAhrX3eM+VsHSWBLAfeAROlNtGPJ8L
+gcL7hWPhsIhHKvgNO/5wrC9Y04cx0oXm59dI5IGHoIYfZ2o7YnYYglThIMJJbjdC
+c+inOfgQjDBOSlWICuNEWhK7GQpop/bKMc+IjA5VgFafFuFZT/Rd0zuBEPRaVWuZ
+BumZyGkxSZOtohtG41JUBt2E6V4Ar4jU86sDlhqrc40vZD2XBjWIMR555yJG8uXG
+p69+qy/Xnmx+Kw7NSfQfldrdE/b4DFqx3+XfReHuBGKKLmNbOVtFuY297Pqv1W1k
+R1FWOglIyx/hvm/Jxo6IsClDY0itKmWyk2BAZP9Rpxs1RdrK5KlgYGpLrhQi1PTj
+Xyy2xZsxledRLOidlxTNZdoaxOJDPhd001rtSWgTmC4ENU2omgZTn5li1E7d9qVo
+Rh5iT0h1Gsnqda7ETrTgm2iOoTr6eADkmrlXayogkyjUHUzr7nMRjb8Nn8vyc6Co
+H7fKtSC3yUVaVC0oUjpU4Yxoi6N/oQbPCQR7cDjmS9nq/M9Wx7/Fs7/oXKkKuRsm
+eD5GMSqTYBHC9MH2v18kNyw9Y8Jdqp9mdD1GNyP7GU7SFgKMFGyJcsAOp2X8RcPv
+aUbb46zhkTYt2niSUyNiwP6288xcQ+7GkQvU8PKVKwJGZj6Xv+T6OyIOMRToPfVG
+V658vFMq1TFenf40fUsZP/Q+225dGHdPlbn186L9+E5MOXNLk+KFxsj11yxrtZ02
+9zdBeAwJ9OBBliA5yV8x3rTEuXhTBOzGHK7Jz7EkE28lj2NJEjaFo5r6n9RFSTDl
+EUFVxdab+wRge/KIyUTcs0iLLQD8XPRmpFjZ0sHXqzLKKzUa/HfYReh0oWZnH394
+9/Ue6UXeeATyjpsEudecaie/ura/8jlKe/ctR19wh8IBP+FG8LE1MBvQewqsAEX3
+B1VIpdMej/WtvjvI8KW2ooYBklhcJyc0vw+X7GNwNLZJ2rw/vO2EFKiHHHuIEvju
+HhTJE8DWAV2lfWzeeS0J3kqhem13VXhbxkdNayPKstFD/Ac6vMffMNZEG28XI/Lk
+Z7+qRn97sAdD7MhHySZFB7kPnHjUTWf5QjLs4g2vVwQZbFgwIySNo9wZHElirZ+6
+bAjMGP8Q4POKK9gwgpRi77D4FatF0nIUXDHMBC9X/pmP/GjDVC43RycwhOUnqfgb
+Y6ytBCQ8Xbbn6JUXzJI7edGSH3avi9LbFZ7nI75kp/p7MOqFeVOFra3LINNlvumz
+Y6IlG214AkKFBiyKqcekH0oMk+0vYQN/4PEkRZru5NB6gfxSum4ypp2vw5hqrT6e
+CpQr+7TNJ1XR8Iv0Ny4QS1UDpcNq8yW6jTfCfZctFT6LdoHTk18XZz4Oyr0WALxa
+d6+5UB38gHakuGhC7xyiAEADBFy96cHqtE3N2K3DWyt5p92AgNnkEmlHJLp5MO5Q
+7s749maf5RwdMV7ur7GZHWyl9wijgpGPbHizRb6yTvOFzzW24+9EQ3I6gqfFtPJJ
+wU/Ua2i3Dxcx9ni89jGQYH7wLipCMHpeTtjjbCeIyGdToA4no4Db96T6rtIWfv7N
+zsjSv8X+PSPMrwUeF9e791qNDKdp+Eds39ZMvJdsbUbXoMz0aaMofPpa+uko0hwX
+zVd2PqqfVHbwLxMZt/bF+NJ0SRlN+jQZ76RBRkGBHT5aqJRVC+AmtOL6tRD9GT0r
+IqiCw9Y3A2SvWp+QeXyx91EoJ+1huVZuQTFlujULMoahEdsK+bemtFtWYT5oVIWQ
+B/svABWqK+Q3OccSnD3H63eDAsmLag2K54b6C4JyjdKK12SDkWobCqrgK1UvdXLl
+vxlkmr+7sJhwaKzl9qW8usgJeLK1M+0jlJb9qn7bn2jU6oZWdPeErf+csvR5c+Cl
+3Lsss8XJSHlXiNrh8T/MXSm3GdHdrXDIHJpqmF2Jihr9AlYdnNG898w3ZCmGDQJ4
+61WRv2IdoeFKo3uUKHuqB4fqnSl1xAqNyJxfUmZZG0OpX/TyGWhCkuRsKEzAuivo
+qka39zgoA0dcHoh9vGMRcN/bDMOY/K+gxREWqbTFYyv5mCFpCzWi3hVDgtk5lcyA
++auOMf2wE27liEdMjsez8OszzdhR158IcenRhtpRGI7mNXkRWOr55SvQfVaZBn7+
+8WrZ1ZMjIgHtBxtCYowV8exQ67jPG1+nwnhete+RpUD4rqKYNsItPFWAvCPDTGr0
+U87CZYzt76dCM+vGlC7wFYXctBzJQMjaZypG3zjShq6o7vV6VQ3+uuNtK69FdM/u
+edJkaSNL8Ewu2jGQ5p7br3rPufiJzYk4I+PD2/s/ixi6e+uIo4a5WtoDYYDEBJET
+ICKP4b3ED07/ry4dI0k597DghHIHDWZ7+/eVOQHNqhbTZmOrnq67uOXmeS/pVv9q
+nEf4+vokTkTuwohe61E02xPsIHIe1BtZQ0GTx/hkyueJhlIGYomeznN6j+qWQvHp
+92yuSbWx7SIjQQBXwSw+947PoLdG+OXqb2vAQJurOXVu70DG1JJFDJsmwRok5Vwd
+M2icyqbjHCepXtHGjnnZklOX6hoDnlBnRgVlEFl9zSmTI55GPtwpTUkDDYEmGFCA
+gzhkaN8Y80+qyhB13Gp5yjhcPjH7RWVzIyd7Y5rF+1zNJ70g+TonPCf1jxZYvaRA
+2A8DwvITnPqNoOACCYkBSuKsVMPNsSbhmp+Ij4QPWmjoFkTuTX/usCgQHwPYPmj2
+NIZgF+4vc43zQ5mIGjXONym5y/QXDBDFo0a5dQRuHe08WTOxzCfgS4KMHZiFILFA
+YTpOlULzgZ867BoT/Gr0NMnd2G62R9J47g97ZIe0D5TiY0ryWRsDVyRy3KXZdli7
+OcuHNbDfYjkwWwrgSE7Hba6u5iBmNt6lckimyq/7uSZ0h9Infw4DqdGDBHUnWVSI
+sJgY8r4VUG3DPSxkLfBJltHuVs0ee24CSNvWe+rUTP47cLX/Q485G0NmgUXc7jxd
+JuYYPOfY/ZoMV6RIZNjSIFR2vuw1hxK00m/8f9z+w3IBHa5Zk32NfsW4HPgEO9zE
+nDBWyRQakMp4C09LX6ukEmV/wHVuS9pOnCgNt2McTxLnZV/SgW2gEG6uCKddiD/2
+LBBbawxfH+rlqgQGtkZQA20xAFRVX7yoapxaAWH6OLmEoLKb9k40K882LrDw7UpU
+7v21Exi+nFxOuJDM13PL6jXvAf+OKOEL9W6wKZC1D1VlGBR2AIdfhh8QJ+anjQxy
+sfLTC0gmU7xXSahWn7rqscHgOIVRjXJ+wrJniUIcf4q/Lbn1Kxvnh9Y4MMPUjhJV
+KRAfQ0nb+7+IdJBUFK/ydc5fQXQ08jZRgmbkwL/xwgaXQ3cm/lKERwTTKamBhtE3
+sdfHcpbLw0cwLC8PZeoMZpfBgxckbYokK6XUP2NdlsYBYjqB1TY/jpzzNI4U0gea
+0Ueg7hIwVMR+UqXFjGKD5tZrQ9NdsLo40ImE1GmIF+k5vr6udWOsl+RIHVKC9mv7
+X7IW8IHUGQ8B2mtZKqjE6qXINaprLpfluFj/TFu3mTtb5o5eVOIx6AYIId4BoIY0
+DxWNTXlTIG6LbpGCM/tIskZGabpiiBFqNYfZBf+yJWsS3lRsp7kOCzeTyENScAyu
+mWzXCuXY7c1CUvHygdycAOZ7SYsgR048hJFSbJb86jzmHttXTnEHkMD/CvlZ06gx
+yQNGAXDwz9VoX+/NOWSlwtxWZPb4DMeHxFFYXGFTcSwEDd2/2ErISuRjyPiDVCwc
+7pGO839e5ou+a+YadsBdRIYAJBaM2Hrj2leHXvHdlC7zgrgyHNPujnH9af6qgfO3
+sfazDN20J+YPvSkQI3WuJYwqN4y0f9ET+oYOs8mls2q9/NQYKTslg1qCfaFxz5sD
++JmhzwS5KwSA/nLIi0PGji/1kFNXGvUJQasMsk5LWAnA328uupalqs+H3MZlixyj
+cIKI7KdmX66WwMjvCMDLH/c2S/J0rhn1Wo5bhqUKqSKUTLRwB2hEByXHgxh6KWjU
+10+2eIP6GGhRpU1iCmbtcf9hoZryJxEGpkqIqwISiKyvYKs5XMegWI9TedZZja0D
+9Onc1w0RSMtXZM8w0MVl7mZaSKo97Y6R9RCpPpNjnlm0XjfSS/D6DuPt6xlP5egj
+Oro/yC2VShmGom9mxUEfC4en4euZyCajcncc0rkIWw28IbNcb3iKlpdeKVzYn3uD
+XEoNKEIEGuq+y+w/86Xje6SLzc6litUQeo7IMMt8Ud2LSEYJtJDucCkZ2Xy8HtQQ
+iHn2zB8Y3K9d13n6/baceDwn7oIyNAKefAjjnQfxMP23Wt4iukFKgzpc2blwABVN
+uyKIeD9n5yGKGRntCLgqX9w29m8iDA6tbJfhkIkeO90Jhw4T179BqX8UDO1ATJXS
+Z0RAX9gU+z7EH4aEVqDJOTh47O9QCSFZWInUnoLKuDcaMK0aj7+8JS7U8G9qFxW9
+MTmoIHd+kBYn9Jjsg/DlQfA4CCI2ciJN5dVCVCthf3YJgaTKQYSi47DUgXh/37y5
+A1StllDhJqqcsd0darcIsU5tBrWGTBXljSBSOmCkMSFgf0vtASDouxeS2vV9RvWt
+s3YzogN0qXotFDTJoh8jXVikGyESU/of4JaFfKau/aHbS98ZEAWR/f3x7ry7M7Eh
+/04MTzXJJVYU9TWTHymq6tEUUfC+OkObUD3VUHsTaVWKACUaY2ts+vV/JFMC/vsF
+OdSCMtEOauEuSTlcIXrHZvfM2VtOf4r+jAAuPdcw8QDyskIgr+U/+n24TApOxQSd
+E8kniEh43xiQYkxj+WuuxN++o7qJHS2fCqVubDJZYnvNP5Iq4HB9yziKuO4NMwNe
+LLZtvbM8aqcVLw+hKi0SGvEycTnbcbIIibAjngWkNWZp5aXoneUQs6yWEtz464d1
+/ggR+qEiZLkOrDEp1X9ToDoukq/SlTgbKvsrZIdC7dXW6L6hd5v100eFdH1H+pNh
+OP+tadP/sGywvv96sLbs15UNk5vj75IQdjSIjqoGTsemIXvR9qHBjdop2fQnQE53
+ieBGN1CRK44TYXpS6QG2TFnUSHaBS139dmJ0dYviMJOYr9oP8qhuR7qZlfFeNJHm
+YDHdN7HnsZOmZp9Nle6CRB4XkqkYGRUjs7i2GA+TKXRmQOCO1qhZMnHmlyatYSz4
+kI9CNOR9p6H1Gq0399A9rcCZQNDPOQYAx9MtMtfRwBJsV3JaYriasxTyjYS2tL1K
+jY4ze788+DIZTZNPjXas2dpv+lbk6/qCUiz/CNTbZElG3as5rfzwUVKpulFNy1sS
+NJEiBdRAAEFxDVZtRFyvp/bjvYFyah4hYM3S3Bkoc8OFjwyALu8BaAAL+I1iqM3F
+H3BuCgW/grgls79ZHBA6BSn/MpuJvhxKuTWOrYBv3Q0SyvBJEp/uxvL/o/zDDnfM
+c/Y4B3R2sHE6eiQQx5H4FIRDfq0eDIE/CF29lYezBblhe+Gnqk/BrPkj+AoweM1g
+AXg5i990DD/mD5dQpaCY6nLpuqeisiIGNiU9zn5Qi9AgAOFHg9UT13Y61k/SPwla
+D+WbHZ6GB1cPOdO2B29lgZPxHyJLl0FiQB9i6O3sHkLCcHOiBjHqeYmliGWIAeUv
+i/46hSc21cOsB9jBjVyXHMN3pP8jVGZaJyip9aD4s7pH6srTo3gap2hl3A08AJX6
+LCk4+JWnoDIzeCvJQolHsMHmc/p5aFPWcXPFR14Y7K81GHwS0u+Pg2nJ94tGAXSl
+x/DE8L7Xqp+6LH8jorkzYhqoFt4OeSZTRz2pZ/x+u5lagx/v53q3pA+qWG8BFcUg
+fOzWu+7O3JOgLRFS4KZsj3YZVxCa4sPOJshDMHUdW4EYEiDNvj5oZDX9X4NtriSp
+1H0VAiWkNZPFGe5ZpFIY0fv+e4w0zX6CXE3Dw0laN835ieH7qxqGMz5FN293WnVR
+AuilL1bah5uWLfsR54iPCFGc8TnkSHnihGnJWd9Rka7MmYir+piF1X/+I5DbJWZd
+G9Y5rm5bhdrjFmOs7viUxP3JyHdEstAy5nim/5r7aDO4y71GDE81toiZMcLQSfFZ
+3PyWl0zEKXoSt+2YgUSoZ9ahl8j0OQx7y8yDOwlgif4Au3LjB5V2nGmBgAt9UP4Z
+mgCsbdRJIei9+7VhRTENBQlqZLvJMndR024buuNDgnc7JVfA0+jlKyDeBspSd15M
+DwXkTmuT6xwbU82v2okOkelJCzvmD4dRP8KhQMa2t6oszBKajDIFy5PS9t65sOl7
+URNLX53AWSNM0TWn9981HHBJVPgYtFRCWUdopTFWnT9qdUW+eTURm20xliK4ifKp
+NmEZviFEv86mAOHKtHse16b6RYlS8SE28W9nr9D4qELYrw5D53nGaRwRkGTlqYki
+YwxDX584Eni0Ht9RvwrQ67ahMtnE2nWtq5A3EPDqw2J4n+EEZvv+wHDwbzejeqv9
+VejdY5F+VIIKQdqPz7SAZYu6NEw8HKF3OCzzvC9vZacrPquioga4NPGyiV23G9fL
+xqz8RgR48gbpVyA0/hMgb6IDiSKgD5/mTCVbvgpnsWkDQi9ppAajqJmZSVf0fIkJ
+Hz3m1U8dWYvhdOC1NxM7GgCZcGoE7N15PXauUlo/45M+anSs677/cV6JaphE8kCR
+U9gcmfV6PfHXstHqKK1N5p/t3tVWODYVKQ43Afvs3Of8QZ8UdmPyNYCgy/yxUo+K
+6/wW6lp9BWFDBdP7o1UKTDIpXJcBQdfKWfjk2cGNWfXkI6LqQBqLQXDc8JsHSk4m
+bVmQjJgFDRR/NcXFT88NQH2rbAja0aYGPjgjUprkJOMRr33pr92RlacrPCSBST7z
+LnWJJytfxgwBpzjjGeJazsI/RV8eigjNPqAl4JKOcr2xY5Pbkspj0+kU+7cgpidz
+w4dLtXQsWwWuwkcgFrn9WMXrL6hTHOF5Ta5XRZ/yW9zlNV/zMO50AnHRNRHXCNY4
+vdmag7GEGA2+XzBfXZ5IjGkcYJ72SxHABCER0WP2QzXHAu6G4v7Ezloy7Y3Htz4w
+qAI+QnQpULdLMpnuFWKUepPFL9hkeFdIb2F4mHst1Vv31co8SxUEJsGbDNqHrTmK
+RFXh4ogltqxIIPBGrnYhJDEK9Iev28trSXhpELdQuArDSUb42i9s0AHj0Oh47hJh
+OON0n4EFldqs8sAI/NZhGXfZzpFwomaD1KPyl+Unlm8ioRmlm9G7uH7a1MIq4/3l
+s9RAAW6hOPkhu4OIXIe7Oep/Nc1FhRuXxdXeBuZbWSKS62f38szjIQS6hrgYkWLk
+cAoUrj3t2wOh1ZtvkiW8zA6UJlrP4MJ62kARCeR8CIkkScejREz8O2qHLrmOsqsK
+hDjDEoX67QigBtnmfpNGQgb2mwJcIiYr5LkjHsvB7r/atxYndiGZ071f2CX9ghag
+jpRpq0zjNOCjonzMmaY7yi2Ova9seFOEKowr+mII/fE3ZB3TADpAlnAXUv/0waD9
+DB3ExmMK1I/jcLYbOt7kR/Rbs1l4u+QHXocqgSVCtritQUE8DsHa3diJXSM+HSTz
+ZRV7PNBIHMc+g6k44GC1eIGDmgOhp/xuouwyEhjrEXWDgpq8FuzhWtj8VHE17Upj
+16+KQlC4Z9yJ6AUmKjYnbdLtOU9RdYAvXroohLRH5HhMzBgNpYDFSVSGoR6dCtrO
+V71dh/6JWZuGS8g4g/rFDcWCovzFaVkvayKks7aDWK+ZSGIsq1dLsQ3QP7+/eCw/
+aDlgxJx9Bx3bSWo49OTHyTTLwldFaO72INTl6rXNFigulyEM+zQonQgwOD5HZyE4
+L7+f6ULxmIOuYQLAxPcunGLsXAz0sMxayhlm01VM5qLYRp2Z5H+2uR5S05UrqPSC
+2k615o9ZTFG+/rdI4jkUUZrX22n3bkXZo2Nir25bCTIej7L1UYHys0Qvs0mFroeQ
+/nrVDZHcyys2dNFBzxW2YWRRLdO7wMz3RdK3S1nMoBTSA09WyQD3M8tZvutxjpUP
+CiI+1OrJpKs7kPCQ4VdWT85dvLVc21HQEprgWjyPN3GODwmwRPM9zXXQgg7x5WYl
+MQ4yQr4wwSF1RmkDPV7WMD/+4rwXO8F6Ax/3rFvJLBoO2Ez2UTaMyHC+HFa7L0tu
+Ei5J+GouQiw5jg82DvqgdwMpIuU2IjAS6Wen0q1MYTg/HTS6Xe2oaEyd3OT3LqMe
+81N6AeXddL1JMHZECrdovl8QlZH/Uww+2Yk/aYa01sRx4a01UD/whPxEMDtXGE1T
+qXPSre4H4tJ52RnKWXbTlczC01J5JLLrW/8L8q6s9ULDXchExA8BAxCOJ4eTJjdU
+YuzSC0gps2qkIK9NCoTv4Pmzjk48WewWOM768c7GajxUKfzZIVnRCzezyIXTHVi+
+Vf6xvsCrk0yoOdtbW0rdIn22jzbzQT9q/dJvNw/PXcDD5LuU6UwLGPM1akvRmzUG
+2VnT0Qd+GpeFw5/NARFs0dN2pfB04Vt2ZR0ytsRA1JDpFtI3QNJtf/GczebhiMQP
++81uuG80sljhz2t4sQ9SWkLglFGRsUJw6OVNWLq4u3ewLqtbA8DXRcS8hixX1Kd8
+l60xZDi2DzgUpTwsTRrPCqqHhYBZ78z6GCtrZ2BIjNlZ3/mzNMh7V7LHKjIENMHi
+FgtSitvA1U+EXQyTI/i43Ix4oVdTdS6JAYMWaTqX7jrXgmoJK2DdrFtYob1sQdMl
+eWcwK8oXWQ1IUyM77hpnvpQu9WJ6k9p8LB4p8wl2jlmOVJh2kbZTG4dVYK9LvUNh
+rixIIH9duDFRAmp6rDDGl509JVpgaHGo33Tx7ji8H/4=
+`pragma protect end_protected
Index: atari_chips/gtia/osc_out_sim/cadence/cds_libs/osc_out.cds.lib
===================================================================
--- atari_chips/gtia/osc_out_sim/cadence/cds_libs/osc_out.cds.lib	(nonexistent)
+++ atari_chips/gtia/osc_out_sim/cadence/cds_libs/osc_out.cds.lib	(revision 1318)
@@ -0,0 +1,23 @@
+
+DEFINE std             $CDS_ROOT/tools/inca/files/STD/           
+DEFINE synopsys        $CDS_ROOT/tools/inca/files/SYNOPSYS/      
+DEFINE ieee            $CDS_ROOT/tools/inca/files/IEEE/          
+DEFINE ambit           $CDS_ROOT/tools/inca/files/AMBIT/         
+DEFINE vital_memory    $CDS_ROOT/tools/inca/files/VITAL_MEMORY/  
+DEFINE ncutils         $CDS_ROOT/tools/inca/files/NCUTILS/       
+DEFINE ncinternal      $CDS_ROOT/tools/inca/files/NCINTERNAL/    
+DEFINE ncmodels        $CDS_ROOT/tools/inca/files/NCMODELS/      
+DEFINE cds_assertions  $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work            ./../libraries/work/                      
+DEFINE altera_ver      ./../libraries/altera_ver/                
+DEFINE lpm_ver         ./../libraries/lpm_ver/                   
+DEFINE sgate_ver       ./../libraries/sgate_ver/                 
+DEFINE altera_mf_ver   ./../libraries/altera_mf_ver/             
+DEFINE fiftyfivenm_ver ./../libraries/fiftyfivenm_ver/           
+DEFINE altera          ./../libraries/altera/                    
+DEFINE lpm             ./../libraries/lpm/                       
+DEFINE sgate           ./../libraries/sgate/                     
+DEFINE altera_mf       ./../libraries/altera_mf/                 
+DEFINE altera_lnsim    ./../libraries/altera_lnsim/              
+DEFINE fiftyfivenm     ./../libraries/fiftyfivenm/               
+DEFINE osc_out         ./../libraries/osc_out/                   
Index: atari_chips/gtia/osc_out_sim/mentor/msim_setup.tcl
===================================================================
--- atari_chips/gtia/osc_out_sim/mentor/msim_setup.tcl	(nonexistent)
+++ atari_chips/gtia/osc_out_sim/mentor/msim_setup.tcl	(revision 1318)
@@ -0,0 +1,295 @@
+
+# (C) 2001-2018 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ----------------------------------------
+# Auto-generated simulation script msim_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     osc_out
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "mentor.do", and modify the text as directed.
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/mentor/msim_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog <compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run -a
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If osc_out is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 18.0 614 linux 2018.10.28.22:04:02
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] { 
+  set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
+  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] { 
+  set TOP_LEVEL_NAME "osc_out"
+}
+
+if ![info exists QSYS_SIMDIR] { 
+  set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] { 
+  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/18.0/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
+  set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
+  set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+  echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib          ./libraries/     
+ensure_lib          ./libraries/work/
+vmap       work     ./libraries/work/
+vmap       work_lib ./libraries/work/
+if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+  ensure_lib                  ./libraries/altera_ver/      
+  vmap       altera_ver       ./libraries/altera_ver/      
+  ensure_lib                  ./libraries/lpm_ver/         
+  vmap       lpm_ver          ./libraries/lpm_ver/         
+  ensure_lib                  ./libraries/sgate_ver/       
+  vmap       sgate_ver        ./libraries/sgate_ver/       
+  ensure_lib                  ./libraries/altera_mf_ver/   
+  vmap       altera_mf_ver    ./libraries/altera_mf_ver/   
+  ensure_lib                  ./libraries/altera_lnsim_ver/
+  vmap       altera_lnsim_ver ./libraries/altera_lnsim_ver/
+  ensure_lib                  ./libraries/fiftyfivenm_ver/ 
+  vmap       fiftyfivenm_ver  ./libraries/fiftyfivenm_ver/ 
+  ensure_lib                  ./libraries/altera/          
+  vmap       altera           ./libraries/altera/          
+  ensure_lib                  ./libraries/lpm/             
+  vmap       lpm              ./libraries/lpm/             
+  ensure_lib                  ./libraries/sgate/           
+  vmap       sgate            ./libraries/sgate/           
+  ensure_lib                  ./libraries/altera_mf/       
+  vmap       altera_mf        ./libraries/altera_mf/       
+  ensure_lib                  ./libraries/altera_lnsim/    
+  vmap       altera_lnsim     ./libraries/altera_lnsim/    
+  ensure_lib                  ./libraries/fiftyfivenm/     
+  vmap       fiftyfivenm      ./libraries/fiftyfivenm/     
+}
+ensure_lib         ./libraries/osc_out/
+vmap       osc_out ./libraries/osc_out/
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+  echo "\[exec\] dev_com"
+  if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"               -work altera_ver      
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                        -work lpm_ver         
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                           -work sgate_ver       
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                       -work altera_mf_ver   
+    eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                   -work altera_lnsim_ver
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v"               -work fiftyfivenm_ver 
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm_ver 
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"         -work altera          
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"     -work altera          
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"        -work altera          
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"     -work altera          
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd"  -work altera          
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"             -work altera          
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                       -work lpm             
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                      -work lpm             
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                    -work sgate           
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                         -work sgate           
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"          -work altera_mf       
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                     -work altera_mf       
+    eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv"   -work altera_lnsim    
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"       -work altera_lnsim    
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm     
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.vhd"             -work fiftyfivenm     
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_components.vhd"        -work fiftyfivenm     
+  }
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+  echo "\[exec\] com"
+  eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_gpio_lite/altera_gpio_lite.sv"        -work osc_out
+  eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_gpio_lite/mentor/altera_gpio_lite.sv" -work osc_out
+  eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QSYS_SIMDIR/osc_out.vhd"                                              
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+  echo "\[exec\] elab"
+  eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L osc_out -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with novopt option
+alias elab_debug {
+  echo "\[exec\] elab_debug"
+  eval vsim -novopt -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L osc_out -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+  dev_com
+  com
+  elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -novopt
+alias ld_debug "
+  dev_com
+  com
+  elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+  echo "List Of Command Line Aliases"
+  echo
+  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
+  echo
+  echo "dev_com                                           -- Compile device library files"
+  echo
+  echo "com                                               -- Compile the design files in correct order"
+  echo
+  echo "elab                                              -- Elaborate top level design"
+  echo
+  echo "elab_debug                                        -- Elaborate the top level design with novopt option"
+  echo
+  echo "ld                                                -- Compile all the design files and elaborate the top level design"
+  echo
+  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -novopt"
+  echo
+  echo 
+  echo
+  echo "List Of Variables"
+  echo
+  echo "TOP_LEVEL_NAME                                    -- Top level module name."
+  echo "                                                     For most designs, this should be overridden"
+  echo "                                                     to enable the elab/elab_debug aliases."
+  echo
+  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
+  echo
+  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
+  echo
+  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
+  echo
+  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo
+  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h
Index: atari_chips/gtia/osc_out_sim/synopsys/vcsmx/vcsmx_setup.sh
===================================================================
--- atari_chips/gtia/osc_out_sim/synopsys/vcsmx/vcsmx_setup.sh	(nonexistent)
+++ atari_chips/gtia/osc_out_sim/synopsys/vcsmx/vcsmx_setup.sh	(revision 1318)
@@ -0,0 +1,213 @@
+
+# (C) 2001-2018 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 18.0 614 linux 2018.10.28.22:04:02
+
+# ----------------------------------------
+# vcsmx - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     osc_out
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level shell script that compiles Altera simulation libraries 
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
+# 
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated library
+# # setup "synopsys_sim.setup" into the location from which you launch the
+# # simulator, or incorporate into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# #
+# # - If necessary, specify any compilation options:
+# #   USER_DEFINED_COMPILE_OPTIONS
+# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# vlogan <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME="'-top <simulation top>'" \
+# QSYS_SIMDIR=<script generation output directory> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If osc_out is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 18.0 614 linux 2018.10.28.22:04:02
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="osc_out"
+QSYS_SIMDIR="./../../"
+QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/18.0/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for 
+# overwriting variables. An example usage:
+#   sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+  eval $expression
+  if [ $? -ne 0 ]; then
+    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+    exit $?
+  fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `vcs -platform` != *"amd64"* ]]; then
+  :
+else
+  :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/osc_out/
+mkdir -p ./libraries/altera_ver/
+mkdir -p ./libraries/lpm_ver/
+mkdir -p ./libraries/sgate_ver/
+mkdir -p ./libraries/altera_mf_ver/
+mkdir -p ./libraries/altera_lnsim_ver/
+mkdir -p ./libraries/fiftyfivenm_ver/
+mkdir -p ./libraries/altera/
+mkdir -p ./libraries/lpm/
+mkdir -p ./libraries/sgate/
+mkdir -p ./libraries/altera_mf/
+mkdir -p ./libraries/altera_lnsim/
+mkdir -p ./libraries/fiftyfivenm/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"                 -work altera_ver      
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                          -work lpm_ver         
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                             -work sgate_ver       
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                         -work altera_mf_ver   
+  vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                     -work altera_lnsim_ver
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v"                 -work fiftyfivenm_ver 
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm_ver 
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"           -work altera          
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"       -work altera          
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"          -work altera          
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"       -work altera          
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd"    -work altera          
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"               -work altera          
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                         -work lpm             
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                        -work lpm             
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                      -work sgate           
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                           -work sgate           
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"            -work altera_mf       
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                       -work altera_mf       
+  vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                     -work altera_lnsim    
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"         -work altera_lnsim    
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm     
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.vhd"               -work fiftyfivenm     
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_components.vhd"          -work fiftyfivenm     
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+  vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_gpio_lite/altera_gpio_lite.sv" -work osc_out
+  vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS             "$QSYS_SIMDIR/osc_out.vhd"                                       
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+  vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+  ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
+fi

Property changes on: atari_chips/gtia/osc_out_sim/synopsys/vcsmx/vcsmx_setup.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: atari_chips/gtia/osc_in.qip
===================================================================
--- atari_chips/gtia/osc_in.qip	(nonexistent)
+++ atari_chips/gtia/osc_in.qip	(revision 1318)
@@ -0,0 +1,76 @@
+set_global_assignment -entity "osc_in" -library "osc_in" -name IP_TOOL_NAME "altera_gpio_lite"
+set_global_assignment -entity "osc_in" -library "osc_in" -name IP_TOOL_VERSION "18.0"
+set_global_assignment -entity "osc_in" -library "osc_in" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "osc_in" -name MISC_FILE [file join $::quartus(qip_path) "osc_in.cmp"]
+set_global_assignment -entity "osc_in" -library "osc_in" -name IP_TARGETED_DEVICE_FAMILY "MAX 10"
+set_global_assignment -entity "osc_in" -library "osc_in" -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}"
+set_global_assignment -entity "osc_in" -library "osc_in" -name IP_QSYS_MODE "UNKNOWN"
+set_global_assignment -name SYNTHESIS_ONLY_QIP ON
+set_global_assignment -entity "osc_in" -library "osc_in" -name IP_COMPONENT_NAME "b3NjX2lu"
+set_global_assignment -entity "osc_in" -library "osc_in" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "osc_in" -library "osc_in" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "osc_in" -library "osc_in" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "osc_in" -library "osc_in" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "osc_in" -library "osc_in" -name IP_COMPONENT_VERSION "MTguMA=="
+set_global_assignment -entity "osc_in" -library "osc_in" -name IP_COMPONENT_DESCRIPTION "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_NAME "YWx0ZXJhX2dwaW9fbGl0ZQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_DISPLAY_NAME "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_REPORT_HIERARCHY "Off"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_INTERNAL "Off"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_VERSION "MTguMA=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_DESCRIPTION "R1BJTyBMaXRlIEludGVsIEZQR0EgSVA="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "REVWSUNFX0ZBTUlMWQ==::TUFYIDEw::RGV2aWNlIGZhbWlseQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "UElOX1RZUEU=::aW5wdXQ=::RGF0YSBkaXJlY3Rpb24="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "U0laRQ==::MQ==::RGF0YSB3aWR0aA=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX3RydWVfZGlmZl9idWY=::ZmFsc2U=::VXNlIHRydWUgZGlmZmVyZW50aWFsIGJ1ZmZlcg=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX2J1c19ob2xk::ZmFsc2U=::VXNlIGJ1cy1ob2xkIGNpcmN1aXRyeQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9vZV9wb3J0::ZmFsc2U=::RW5hYmxlIG9lIHBvcnQ="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9uc2xlZXBfcG9ydA==::ZmFsc2U=::RW5hYmxlIG5zbGVlcCBwb3J0IChvbmx5IGF2YWlsYWJsZSBpbiBzZWxlY3RlZCBkZXZpY2VzKQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX2lvX3JlZ19tb2Rl::ZGRy::UmVnaXN0ZXIgbW9kZQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9hY2xyX3BvcnQ=::ZmFsc2U=::RW5hYmxlIGFjbHIgcG9ydA=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9zY2xyX3BvcnQ=::ZmFsc2U=::RW5hYmxlIHNjbHIgcG9ydA=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX3NldF9yZWdpc3RlcnNfdG9fcG93ZXJfdXBfaGlnaA==::ZmFsc2U=::U2V0IHJlZ2lzdGVycyB0byBwb3dlciB1cCBoaWdoICh3aGVuIGFjbHIsIHNjbHIgYW5kIGFzZXQgcG9ydHMgYXJlIG5vdCB1c2VkKQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX2Nsb2NrX2VuYWJsZQ==::ZmFsc2U=::RW5hYmxlIGluY2xvY2tlbi9vdXRjbG9ja2VuIHBvcnRz"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9pbnB1dF9jbG9jaw==::ZmFsc2U=::SW52ZXJ0IERESU8gaW5jbG9jaw=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9yZWdpc3Rlcl90b19kcml2ZV9vYnVmX29l::ZmFsc2U=::VXNlIGEgc2luZ2xlIHJlZ2lzdGVyIHRvIGRyaXZlIHRoZSBvdXRwdXQgZW5hYmxlIChvZSkgc2lnbmFsIGF0IHRoZSBJL08gYnVmZmVy"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9kZGlvX3JlZ190b19kcml2ZV9vZQ==::ZmFsc2U=::VXNlIERESU8gcmVnaXN0ZXJzIHRvIGRyaXZlIHRoZSBvdXRwdXQgZW5hYmxlIChvZSkgc2lnbmFsIGF0IHRoZSBJL08gYnVmZmVy"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9hZHZhbmNlZF9kZHJfZmVhdHVyZXM=::ZmFsc2U=::RW5hYmxlIGFkdmFuY2VkIEREUiBmZWF0dXJlcw=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9waGFzZV9kZXRlY3Rvcl9mb3JfY2s=::ZmFsc2U=::RW5hYmxlIFBoYXNlIERldGVjdG9yIGZyb20gQ0sgbG9vcGJhY2sgc2lnbmFs"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9vZV9oYWxmX2N5Y2xlX2RlbGF5::dHJ1ZQ==::QWRkIGhhbGYtY3ljbGUgZGVsYXkgdG8gT0Ugc2lnbmFs"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9ocl9jbG9jaw==::ZmFsc2U=::RW5hYmxlIGhhbGYtcmF0ZSBjbG9jayBwb3J0"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9pbnZlcnRfaHJfY2xvY2tfcG9ydA==::ZmFsc2U=::RW5hYmxlIGludmVydF9ocl9jbG9jayBwb3J0"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9jbGtkaXZfaW5wdXRfY2xvY2s=::ZmFsc2U=::SW52ZXJ0IGNsb2NrIGRpdmlkZXIgaW5wdXQgY2xvY2s="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vdXRwdXRfY2xvY2s=::ZmFsc2U=::SW52ZXJ0IERESU8gb3V0Y2xvY2s="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX2ludmVydF9vZV9pbmNsb2Nr::ZmFsc2U=::SW52ZXJ0IG91dHB1dCBlbmFibGUgKG9lKSByZWdpc3RlciBpbmNsb2Nr"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9oYXJkZW5lZF9kZGlvX2lucHV0X3JlZ2lzdGVycw==::ZmFsc2U=::SW1wbGVtZW50IERESU8gaW5wdXQgcmVnaXN0ZXJzIGluIGhhcmQgaW1wbGVtZW50YXRpb24gKE9ubHkgYXZhaWxhYmxlIGluIGNlcnRhaW4gZGV2aWNlcyk="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "UkVHSVNURVJfTU9ERQ==::ZGRy::UkVHSVNURVJfTU9ERQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "QlVGRkVSX1RZUEU=::c2luZ2xlLWVuZGVk::QlVGRkVSX1RZUEU="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "QVNZTkNfTU9ERQ==::bm9uZQ==::QVNZTkNfTU9ERQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "U1lOQ19NT0RF::bm9uZQ==::U1lOQ19NT0RF"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "QlVTX0hPTEQ=::ZmFsc2U=::QlVTX0hPTEQ="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "T1BFTl9EUkFJTl9PVVRQVVQ=::ZmFsc2U=::T1BFTl9EUkFJTl9PVVRQVVQ="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "RU5BQkxFX09FX1BPUlQ=::ZmFsc2U=::RU5BQkxFX09FX1BPUlQ="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "RU5BQkxFX05TTEVFUF9QT1JU::ZmFsc2U=::RU5BQkxFX05TTEVFUF9QT1JU"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0NMT0NLX0VOQV9QT1JU::ZmFsc2U=::RU5BQkxFX0NMT0NLX0VOQV9QT1JU"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "U0VUX1JFR0lTVEVSX09VVFBVVFNfSElHSA==::ZmFsc2U=::U0VUX1JFR0lTVEVSX09VVFBVVFNfSElHSA=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09VVFBVVA==::ZmFsc2U=::SU5WRVJUX09VVFBVVA=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "SU5WRVJUX0lOUFVUX0NMT0NL::ZmFsc2U=::SU5WRVJUX0lOUFVUX0NMT0NL"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "VVNFX09ORV9SRUdfVE9fRFJJVkVfT0U=::ZmFsc2U=::VVNFX09ORV9SRUdfVE9fRFJJVkVfT0U="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "VVNFX0RESU9fUkVHX1RPX0RSSVZFX09F::ZmFsc2U=::VVNFX0RESU9fUkVHX1RPX0RSSVZFX09F"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFUw==::ZmFsc2U=::VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFUw=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFU19GT1JfSU5QVVRfT05MWQ==::ZmFsc2U=::VVNFX0FEVkFOQ0VEX0REUl9GRUFUVVJFU19GT1JfSU5QVVRfT05MWQ=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "RU5BQkxFX09FX0hBTEZfQ1lDTEVfREVMQVk=::dHJ1ZQ==::RU5BQkxFX09FX0hBTEZfQ1lDTEVfREVMQVk="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "SU5WRVJUX0NMS0RJVl9JTlBVVF9DTE9DSw==::ZmFsc2U=::SU5WRVJUX0NMS0RJVl9JTlBVVF9DTE9DSw=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1BIQVNFX0lOVkVSVF9DVFJMX1BPUlQ=::ZmFsc2U=::RU5BQkxFX1BIQVNFX0lOVkVSVF9DVFJMX1BPUlQ="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "RU5BQkxFX0hSX0NMT0NL::ZmFsc2U=::RU5BQkxFX0hSX0NMT0NL"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09VVFBVVF9DTE9DSw==::ZmFsc2U=::SU5WRVJUX09VVFBVVF9DTE9DSw=="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "SU5WRVJUX09FX0lOQ0xPQ0s=::ZmFsc2U=::SU5WRVJUX09FX0lOQ0xPQ0s="
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_COMPONENT_PARAMETER "RU5BQkxFX1BIQVNFX0RFVEVDVE9SX0ZPUl9DSw==::ZmFsc2U=::RU5BQkxFX1BIQVNFX0RFVEVDVE9SX0ZPUl9DSw=="
+
+set_global_assignment -library "osc_in" -name VHDL_FILE [file join $::quartus(qip_path) "osc_in.vhd"]
+set_global_assignment -library "osc_in" -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) "osc_in/altera_gpio_lite.sv"]
+
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_TOOL_NAME "altera_gpio_lite"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_TOOL_VERSION "18.0"
+set_global_assignment -entity "altera_gpio_lite" -library "osc_in" -name IP_TOOL_ENV "mwpim"
Index: atari_chips/gtia/osc_in.sip
===================================================================
--- atari_chips/gtia/osc_in.sip	(nonexistent)
+++ atari_chips/gtia/osc_in.sip	(revision 1318)
@@ -0,0 +1,8 @@
+set_global_assignment -entity "osc_in" -library "lib_osc_in" -name IP_TOOL_NAME "altera_gpio_lite"
+set_global_assignment -entity "osc_in" -library "lib_osc_in" -name IP_TOOL_VERSION "18.0"
+set_global_assignment -entity "osc_in" -library "lib_osc_in" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "lib_osc_in" -name SPD_FILE [file join $::quartus(sip_path) "osc_in.spd"]
+
+set_global_assignment -library "lib_osc_in" -name MISC_FILE [file join $::quartus(sip_path) "osc_in_sim/osc_in.vhd"]
+set_global_assignment -library "lib_osc_in" -name MISC_FILE [file join $::quartus(sip_path) "osc_in_sim/altera_gpio_lite/altera_gpio_lite.sv"]
+set_global_assignment -library "lib_osc_in" -name MISC_FILE [file join $::quartus(sip_path) "osc_in_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv"]
Index: atari_chips/gtia/osc_in.spd
===================================================================
--- atari_chips/gtia/osc_in.spd	(nonexistent)
+++ atari_chips/gtia/osc_in.spd	(revision 1318)
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<simPackage>
+ <file
+   path="osc_in_sim/altera_gpio_lite/altera_gpio_lite.sv"
+   type="SYSTEM_VERILOG"
+   library="osc_in" />
+ <file
+   path="osc_in_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv"
+   type="SYSTEM_VERILOG_ENCRYPT"
+   library="osc_in"
+   simulator="modelsim" />
+ <file path="osc_in_sim/osc_in.vhd" type="VHDL" />
+ <topLevel name="osc_in" />
+ <deviceFamily name="max10" />
+</simPackage>
Index: atari_chips/gtia/osc_in.vhd
===================================================================
--- atari_chips/gtia/osc_in.vhd	(nonexistent)
+++ atari_chips/gtia/osc_in.vhd	(revision 1318)
@@ -0,0 +1,187 @@
+-- megafunction wizard: %GPIO Lite Intel FPGA IP v18.0%
+-- GENERATION: XML
+-- osc_in.vhd
+
+-- Generated using ACDS version 18.0 614
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity osc_in is
+	port (
+		inclock : in  std_logic                    := '0';             -- inclock.export
+		dout    : out std_logic_vector(1 downto 0);                    --    dout.export
+		pad_in  : in  std_logic_vector(0 downto 0) := (others => '0')  --  pad_in.export
+	);
+end entity osc_in;
+
+architecture rtl of osc_in is
+	component altera_gpio_lite is
+		generic (
+			PIN_TYPE                                 : string  := "output";
+			SIZE                                     : integer := 4;
+			REGISTER_MODE                            : string  := "bypass";
+			BUFFER_TYPE                              : string  := "single-ended";
+			ASYNC_MODE                               : string  := "none";
+			SYNC_MODE                                : string  := "none";
+			BUS_HOLD                                 : string  := "false";
+			OPEN_DRAIN_OUTPUT                        : string  := "false";
+			ENABLE_OE_PORT                           : string  := "false";
+			ENABLE_NSLEEP_PORT                       : string  := "false";
+			ENABLE_CLOCK_ENA_PORT                    : string  := "false";
+			SET_REGISTER_OUTPUTS_HIGH                : string  := "false";
+			INVERT_OUTPUT                            : string  := "false";
+			INVERT_INPUT_CLOCK                       : string  := "false";
+			USE_ONE_REG_TO_DRIVE_OE                  : string  := "false";
+			USE_DDIO_REG_TO_DRIVE_OE                 : string  := "false";
+			USE_ADVANCED_DDR_FEATURES                : string  := "false";
+			USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY : string  := "false";
+			ENABLE_OE_HALF_CYCLE_DELAY               : string  := "true";
+			INVERT_CLKDIV_INPUT_CLOCK                : string  := "false";
+			ENABLE_PHASE_INVERT_CTRL_PORT            : string  := "false";
+			ENABLE_HR_CLOCK                          : string  := "false";
+			INVERT_OUTPUT_CLOCK                      : string  := "false";
+			INVERT_OE_INCLOCK                        : string  := "false";
+			ENABLE_PHASE_DETECTOR_FOR_CK             : string  := "false"
+		);
+		port (
+			inclock         : in    std_logic                    := 'X';             -- export
+			dout            : out   std_logic_vector(1 downto 0);                    -- export
+			pad_in          : in    std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			inclocken       : in    std_logic                    := 'X';             -- export
+			fr_clock        : out   std_logic_vector(0 downto 0);                    -- export
+			hr_clock        : out   std_logic;                                       -- export
+			invert_hr_clock : in    std_logic                    := 'X';             -- export
+			outclock        : in    std_logic                    := 'X';             -- export
+			outclocken      : in    std_logic                    := 'X';             -- export
+			phy_mem_clock   : in    std_logic                    := 'X';             -- export
+			mimic_clock     : out   std_logic_vector(0 downto 0);                    -- export
+			din             : in    std_logic_vector(1 downto 0) := (others => 'X'); -- export
+			pad_io          : inout std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			pad_io_b        : inout std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			pad_in_b        : in    std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			pad_out         : out   std_logic_vector(0 downto 0);                    -- export
+			pad_out_b       : out   std_logic_vector(0 downto 0);                    -- export
+			aset            : in    std_logic                    := 'X';             -- export
+			aclr            : in    std_logic                    := 'X';             -- export
+			sclr            : in    std_logic                    := 'X';             -- export
+			nsleep          : in    std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			oe              : in    std_logic_vector(0 downto 0) := (others => 'X')  -- export
+		);
+	end component altera_gpio_lite;
+
+begin
+
+	osc_in_inst : component altera_gpio_lite
+		generic map (
+			PIN_TYPE                                 => "input",
+			SIZE                                     => 1,
+			REGISTER_MODE                            => "ddr",
+			BUFFER_TYPE                              => "single-ended",
+			ASYNC_MODE                               => "none",
+			SYNC_MODE                                => "none",
+			BUS_HOLD                                 => "false",
+			OPEN_DRAIN_OUTPUT                        => "false",
+			ENABLE_OE_PORT                           => "false",
+			ENABLE_NSLEEP_PORT                       => "false",
+			ENABLE_CLOCK_ENA_PORT                    => "false",
+			SET_REGISTER_OUTPUTS_HIGH                => "false",
+			INVERT_OUTPUT                            => "false",
+			INVERT_INPUT_CLOCK                       => "false",
+			USE_ONE_REG_TO_DRIVE_OE                  => "false",
+			USE_DDIO_REG_TO_DRIVE_OE                 => "false",
+			USE_ADVANCED_DDR_FEATURES                => "false",
+			USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY => "false",
+			ENABLE_OE_HALF_CYCLE_DELAY               => "true",
+			INVERT_CLKDIV_INPUT_CLOCK                => "false",
+			ENABLE_PHASE_INVERT_CTRL_PORT            => "false",
+			ENABLE_HR_CLOCK                          => "false",
+			INVERT_OUTPUT_CLOCK                      => "false",
+			INVERT_OE_INCLOCK                        => "false",
+			ENABLE_PHASE_DETECTOR_FOR_CK             => "false"
+		)
+		port map (
+			inclock         => inclock, -- inclock.export
+			dout            => dout,    --    dout.export
+			pad_in          => pad_in,  --  pad_in.export
+			inclocken       => '1',     -- (terminated)
+			fr_clock        => open,    -- (terminated)
+			hr_clock        => open,    -- (terminated)
+			invert_hr_clock => '0',     -- (terminated)
+			outclock        => '0',     -- (terminated)
+			outclocken      => '0',     -- (terminated)
+			phy_mem_clock   => '0',     -- (terminated)
+			mimic_clock     => open,    -- (terminated)
+			din             => "00",    -- (terminated)
+			pad_io          => open,    -- (terminated)
+			pad_io_b        => open,    -- (terminated)
+			pad_in_b        => "0",     -- (terminated)
+			pad_out         => open,    -- (terminated)
+			pad_out_b       => open,    -- (terminated)
+			aset            => '0',     -- (terminated)
+			aclr            => '0',     -- (terminated)
+			sclr            => '0',     -- (terminated)
+			nsleep          => "0",     -- (terminated)
+			oe              => "0"      -- (terminated)
+		);
+
+end architecture rtl; -- of osc_in
+-- Retrieval info: <?xml version="1.0"?>
+--<!--
+--	Generated by Altera MegaWizard Launcher Utility version 1.0
+--	************************************************************
+--	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--	************************************************************
+--	Copyright (C) 1991-2018 Altera Corporation
+--	Any megafunction design, and related net list (encrypted or decrypted),
+--	support information, device programming or simulation file, and any other
+--	associated documentation or information provided by Altera or a partner
+--	under Altera's Megafunction Partnership Program may be used only to
+--	program PLD devices (but not masked PLD devices) from Altera.  Any other
+--	use of such megafunction design, net list, support information, device
+--	programming or simulation file, or any other related documentation or
+--	information is prohibited for any other purpose, including, but not
+--	limited to modification, reverse engineering, de-compiling, or use with
+--	any other silicon devices, unless such use is explicitly licensed under
+--	a separate agreement with Altera or a megafunction partner.  Title to
+--	the intellectual property, including patents, copyrights, trademarks,
+--	trade secrets, or maskworks, embodied in any such megafunction design,
+--	net list, support information, device programming or simulation file, or
+--	any other related documentation or information provided by Altera or a
+--	megafunction partner, remains with Altera, the megafunction partner, or
+--	their respective licensors.  No other licenses, including any licenses
+--	needed under any third party's intellectual property, are provided herein.
+---->
+-- Retrieval info: <instance entity-name="altera_gpio_lite" version="18.0" >
+-- Retrieval info: 	<generic name="DEVICE_FAMILY" value="MAX 10" />
+-- Retrieval info: 	<generic name="PIN_TYPE" value="input" />
+-- Retrieval info: 	<generic name="SIZE" value="1" />
+-- Retrieval info: 	<generic name="gui_true_diff_buf" value="false" />
+-- Retrieval info: 	<generic name="gui_pseudo_diff_buf" value="false" />
+-- Retrieval info: 	<generic name="gui_bus_hold" value="false" />
+-- Retrieval info: 	<generic name="gui_open_drain" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_oe_port" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_nsleep_port" value="false" />
+-- Retrieval info: 	<generic name="gui_io_reg_mode" value="ddr" />
+-- Retrieval info: 	<generic name="gui_enable_aclr_port" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_aset_port" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_sclr_port" value="false" />
+-- Retrieval info: 	<generic name="gui_set_registers_to_power_up_high" value="false" />
+-- Retrieval info: 	<generic name="gui_clock_enable" value="false" />
+-- Retrieval info: 	<generic name="gui_invert_output" value="false" />
+-- Retrieval info: 	<generic name="gui_invert_input_clock" value="false" />
+-- Retrieval info: 	<generic name="gui_use_register_to_drive_obuf_oe" value="false" />
+-- Retrieval info: 	<generic name="gui_use_ddio_reg_to_drive_oe" value="false" />
+-- Retrieval info: 	<generic name="gui_use_advanced_ddr_features" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_phase_detector_for_ck" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_oe_half_cycle_delay" value="true" />
+-- Retrieval info: 	<generic name="gui_enable_hr_clock" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_invert_hr_clock_port" value="false" />
+-- Retrieval info: 	<generic name="gui_invert_clkdiv_input_clock" value="false" />
+-- Retrieval info: 	<generic name="gui_invert_output_clock" value="false" />
+-- Retrieval info: 	<generic name="gui_invert_oe_inclock" value="false" />
+-- Retrieval info: 	<generic name="gui_use_hardened_ddio_input_registers" value="false" />
+-- Retrieval info: </instance>
+-- IPFS_FILES : osc_in.vho
+-- RELATED_FILES: osc_in.vhd, altera_gpio_lite.sv
Index: atari_chips/gtia/osc_in_sim/aldec/rivierapro_setup.tcl
===================================================================
--- atari_chips/gtia/osc_in_sim/aldec/rivierapro_setup.tcl	(nonexistent)
+++ atari_chips/gtia/osc_in_sim/aldec/rivierapro_setup.tcl	(revision 1318)
@@ -0,0 +1,300 @@
+
+# (C) 2001-2018 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 18.0 614 linux 2018.10.28.22:11:01
+# ----------------------------------------
+# Auto-generated simulation script rivierapro_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     osc_in
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "aldec.do", and modify the text as directed.
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog -sv2k5 <your compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If osc_in is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] { 
+  set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
+  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] { 
+  set TOP_LEVEL_NAME "osc_in"
+}
+
+if ![info exists QSYS_SIMDIR] { 
+  set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] { 
+  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/18.0/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
+  set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
+  set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+set Aldec "Riviera"
+if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
+  set Aldec "Active"
+}
+
+if { [ string match "Active" $Aldec ] } {
+  scripterconf -tcl
+  createdesign "$TOP_LEVEL_NAME"  "."
+  opendesign "$TOP_LEVEL_NAME"
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+  echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib      ./libraries     
+ensure_lib      ./libraries/work
+vmap       work ./libraries/work
+ensure_lib                  ./libraries/altera_ver      
+vmap       altera_ver       ./libraries/altera_ver      
+ensure_lib                  ./libraries/lpm_ver         
+vmap       lpm_ver          ./libraries/lpm_ver         
+ensure_lib                  ./libraries/sgate_ver       
+vmap       sgate_ver        ./libraries/sgate_ver       
+ensure_lib                  ./libraries/altera_mf_ver   
+vmap       altera_mf_ver    ./libraries/altera_mf_ver   
+ensure_lib                  ./libraries/altera_lnsim_ver
+vmap       altera_lnsim_ver ./libraries/altera_lnsim_ver
+ensure_lib                  ./libraries/fiftyfivenm_ver 
+vmap       fiftyfivenm_ver  ./libraries/fiftyfivenm_ver 
+ensure_lib                  ./libraries/altera          
+vmap       altera           ./libraries/altera          
+ensure_lib                  ./libraries/lpm             
+vmap       lpm              ./libraries/lpm             
+ensure_lib                  ./libraries/sgate           
+vmap       sgate            ./libraries/sgate           
+ensure_lib                  ./libraries/altera_mf       
+vmap       altera_mf        ./libraries/altera_mf       
+ensure_lib                  ./libraries/altera_lnsim    
+vmap       altera_lnsim     ./libraries/altera_lnsim    
+ensure_lib                  ./libraries/fiftyfivenm     
+vmap       fiftyfivenm      ./libraries/fiftyfivenm     
+ensure_lib        ./libraries/osc_in
+vmap       osc_in ./libraries/osc_in
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+  echo "\[exec\] dev_com"
+  eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"              -work altera_ver      
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                       -work lpm_ver         
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                          -work sgate_ver       
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                      -work altera_mf_ver   
+  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim_ver
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v"              -work fiftyfivenm_ver 
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm_ver 
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"        -work altera          
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"    -work altera          
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"       -work altera          
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"    -work altera          
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd" -work altera          
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"            -work altera          
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                      -work lpm             
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                     -work lpm             
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                   -work sgate           
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                        -work sgate           
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"         -work altera_mf       
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                    -work altera_mf       
+  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                  -work altera_lnsim    
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"      -work altera_lnsim    
+  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm     
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.vhd"            -work fiftyfivenm     
+  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS          "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_components.vhd"       -work fiftyfivenm     
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+  echo "\[exec\] com"
+  eval  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_gpio_lite/altera_gpio_lite.sv" -work osc_in
+  eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QSYS_SIMDIR/osc_in.vhd"                                       
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+  echo "\[exec\] elab"
+  eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L osc_in -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with -dbg -O2 option
+alias elab_debug {
+  echo "\[exec\] elab_debug"
+  eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L osc_in -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+  dev_com
+  com
+  elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -dbg -O2
+alias ld_debug "
+  dev_com
+  com
+  elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+  echo "List Of Command Line Aliases"
+  echo
+  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
+  echo
+  echo "dev_com                                           -- Compile device library files"
+  echo
+  echo "com                                               -- Compile the design files in correct order"
+  echo
+  echo "elab                                              -- Elaborate top level design"
+  echo
+  echo "elab_debug                                        -- Elaborate the top level design with -dbg -O2 option"
+  echo
+  echo "ld                                                -- Compile all the design files and elaborate the top level design"
+  echo
+  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -dbg -O2"
+  echo
+  echo 
+  echo
+  echo "List Of Variables"
+  echo
+  echo "TOP_LEVEL_NAME                                    -- Top level module name."
+  echo "                                                     For most designs, this should be overridden"
+  echo "                                                     to enable the elab/elab_debug aliases."
+  echo
+  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
+  echo
+  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
+  echo
+  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
+  echo
+  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo
+  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h
Index: atari_chips/gtia/osc_in_sim/altera_gpio_lite/altera_gpio_lite.sv
===================================================================
--- atari_chips/gtia/osc_in_sim/altera_gpio_lite/altera_gpio_lite.sv	(nonexistent)
+++ atari_chips/gtia/osc_in_sim/altera_gpio_lite/altera_gpio_lite.sv	(revision 1318)
@@ -0,0 +1,1200 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module altgpio_one_bit(
+	inclock,
+	outclock,
+	phy_mem_clock,
+	inclocken,
+	outclocken,
+	oe,
+	din,
+	dout,
+	pad,
+	pad_b,
+	aset,
+	sclr,
+	hr_clock,
+	fr_clock,
+	mimic_clock,
+	nsleep
+);
+
+	parameter PIN_TYPE = "output"; 
+	parameter BUFFER_TYPE = "single-ended"; 
+	parameter REGISTER_MODE = "bypass"; 
+	parameter ASYNC_MODE = "none"; 
+	parameter SYNC_MODE = "none"; 
+	parameter BUS_HOLD = "false"; 
+	parameter SET_REGISTER_OUTPUTS_HIGH = "false";  
+	parameter USE_ENHANCED_DDR_HIO_REGISTER = "false"; 
+	parameter BYPASS_THREE_QUARTER_REGISTER = "true"; 
+	parameter INVERT_OUTPUT = "false"; 
+	parameter INVERT_INPUT_CLOCK = "false"; 
+	parameter INVERT_OUTPUT_CLOCK = "false"; 
+	parameter INVERT_OE_INCLOCK = "false"; 
+	parameter USE_ONE_REG_TO_DRIVE_OE = "false"; 
+	parameter USE_DDIO_REG_TO_DRIVE_OE = "false"; 
+	parameter OPEN_DRAIN_OUTPUT = "false"; 
+	parameter ENABLE_OE_HALF_CYCLE_DELAY = "true"; 
+	parameter USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY = "false"; 
+	parameter ENABLE_CLOCK_ENA_PORT = "false"; 
+	parameter ENABLE_HR_CLOCK = "false"; 
+	parameter ENABLE_PHASE_DETECTOR_FOR_CK = "false"; 
+	parameter ENABLE_NSLEEP_PORT = "false"; 
+
+	localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? 2:1;
+	localparam DDIO_REG_POWER_UP = (ASYNC_MODE == "preset" || SET_REGISTER_OUTPUTS_HIGH == "true") ? "high" : "low";
+
+	input inclock;
+	input outclock;
+	input inclocken;
+	input outclocken;
+	input oe;
+	input nsleep;
+	input [DATA_SIZE - 1:0] din;
+	output [DATA_SIZE - 1:0] dout;
+	inout pad;
+	inout pad_b;
+	input aset;
+	input sclr;
+	input phy_mem_clock;
+	input hr_clock;
+	(* altera_attribute = "-name GLOBAL_SIGNAL\"OFF\"" *) output fr_clock;
+	output mimic_clock;
+
+	wire din_ddr;
+	wire buf_in;
+
+	wire oe_out;
+	wire nsleep_in;
+
+    generate
+        if (PIN_TYPE == "output" || PIN_TYPE == "bidir")
+        begin
+			wire [1:0] din_fr;
+            if (INVERT_OUTPUT == "false")
+			begin
+				assign din_fr = din;
+			end
+			else
+			begin
+				assign din_fr = ~din;
+			end
+
+			wire outclock_wire;
+			if (REGISTER_MODE != "bypass")
+			begin
+				if (INVERT_OUTPUT_CLOCK == "false")
+				begin: normal_input_clock
+					assign outclock_wire = outclock;
+				end
+				else
+				begin: inverted_output_clock
+					assign outclock_wire = ~outclock;
+				end
+			end
+
+			wire outclocken_wire;
+			assign  outclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? outclocken : 1'b1;
+
+			if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "true")
+			begin
+				if (ASYNC_MODE != "none")
+					begin: async_mode_out_path_enhanced_ddr
+								fiftyfivenm_ddio_out
+								#(
+									.async_mode(ASYNC_MODE),
+									.sync_mode(SYNC_MODE),
+									.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+									.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+									.power_up(DDIO_REG_POWER_UP),
+									.use_new_clocking_model("true")
+								) fr_out_data_ddio (
+									.datainhi(din_fr[0]),
+									.datainlo(din_fr[1]),
+									.dataout(din_ddr),
+									.clkhi(outclock_wire),
+									.clklo(outclock_wire),
+									.muxsel(outclock_wire),
+									.areset(aset),
+									.ena(outclocken_wire),
+									.phymemclock(phy_mem_clock)
+									`ifndef ALTERA_RESERVED_QIS
+									,
+									.clk (outclock_wire),
+									.sreset(1'b0),
+									.dfflo(),
+									.dffhi(),
+									.devpor(1'b1),
+									.devclrn(1'b1)
+									`endif
+								);
+					end
+				else if (SYNC_MODE != "none")
+					begin: sync_mode_out_path_enhanced_ddr
+								fiftyfivenm_ddio_out
+								#(
+									.async_mode(ASYNC_MODE),
+									.sync_mode(SYNC_MODE),
+									.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+									.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+									.power_up(DDIO_REG_POWER_UP),
+									.use_new_clocking_model("true")
+								) fr_out_data_ddio (
+									.datainhi(din_fr[0]),
+									.datainlo(din_fr[1]),
+									.dataout(din_ddr),
+									.clkhi(outclock_wire),
+									.clklo(outclock_wire),
+									.muxsel(outclock_wire),
+									.sreset(sclr),
+									.ena(outclocken_wire),
+									.phymemclock(phy_mem_clock)
+									`ifndef ALTERA_RESERVED_QIS
+									,
+									.clk (outclock_wire),
+									.areset(1'b0),
+									.dfflo(),
+									.dffhi(),
+									.devpor(1'b1),
+									.devclrn(1'b1)
+									`endif
+								);
+					end
+				else
+					begin: out_path_enhanced_ddr
+								fiftyfivenm_ddio_out
+								#(
+									.async_mode(ASYNC_MODE),
+									.sync_mode(SYNC_MODE),
+									.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+									.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+									.power_up(DDIO_REG_POWER_UP),
+									.use_new_clocking_model("true")
+								) fr_out_data_ddio (
+									.datainhi(din_fr[0]),
+									.datainlo(din_fr[1]),
+									.dataout(din_ddr),
+									.clkhi(outclock_wire),
+									.clklo(outclock_wire),
+									.muxsel(outclock_wire),
+									.ena(outclocken_wire),
+									.phymemclock(phy_mem_clock)
+									`ifndef ALTERA_RESERVED_QIS
+									,
+									.areset(1'b0),
+									.clk(1'b0),
+									.sreset(1'b0),
+									.dfflo(),
+									.dffhi(),
+									.devpor(1'b1),
+									.devclrn(1'b1)
+									`endif
+								);
+					end
+			end
+			else if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "false")
+			begin
+				if (ASYNC_MODE != "none")
+						begin: async_mode_out_path_ddr
+							fiftyfivenm_ddio_out
+							#(
+								.async_mode(ASYNC_MODE),
+								.sync_mode(SYNC_MODE),
+								.power_up(DDIO_REG_POWER_UP),
+								.use_new_clocking_model("true"),
+								.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+							) fr_out_data_ddio (
+								.datainhi(din_fr[0]),
+								.datainlo(din_fr[1]),
+								.dataout(din_ddr),
+								.clkhi(outclock_wire),
+								.clklo(outclock_wire),
+								.muxsel(outclock_wire),
+								.areset(aset),
+								.ena(outclocken_wire)
+								`ifndef ALTERA_RESERVED_QIS
+								,
+								.clk(1'b0),
+								.phymemclock(1'b0),
+								.sreset(1'b0),
+								.dfflo(),
+								.dffhi(),
+								.devpor(1'b1),
+								.devclrn(1'b1)
+								`endif
+							);
+						end
+				else if (SYNC_MODE != "none")
+						begin: sync_mode_out_path_ddr
+							fiftyfivenm_ddio_out
+							#(
+								.async_mode(ASYNC_MODE),
+								.sync_mode(SYNC_MODE),
+								.power_up(DDIO_REG_POWER_UP),
+								.use_new_clocking_model("true"),
+								.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+							) fr_out_data_ddio (
+								.datainhi(din_fr[0]),
+								.datainlo(din_fr[1]),
+								.dataout(din_ddr),
+								.clkhi(outclock_wire),
+								.clklo(outclock_wire),
+								.muxsel(outclock_wire),
+								.sreset(sclr),
+								.ena(outclocken_wire)
+								`ifndef ALTERA_RESERVED_QIS
+								,
+								.areset(1'b0),
+								.clk(1'b0),
+								.phymemclock(1'b0),
+								.dfflo(),
+								.dffhi(),
+								.devpor(1'b1),
+								.devclrn(1'b1)
+								`endif
+							);
+						end
+				else
+						begin: out_path_ddr
+							fiftyfivenm_ddio_out
+							#(
+								.async_mode(ASYNC_MODE),
+								.sync_mode(SYNC_MODE),
+								.power_up(DDIO_REG_POWER_UP),
+								.use_new_clocking_model("true"),
+								.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+							) fr_out_data_ddio (
+								.datainhi(din_fr[0]),
+								.datainlo(din_fr[1]),
+								.dataout(din_ddr),
+								.clkhi(outclock_wire),
+								.clklo(outclock_wire),
+								.muxsel(outclock_wire),
+								.ena(outclocken_wire)
+								`ifndef ALTERA_RESERVED_QIS
+								,
+								.areset(1'b0),
+								.clk(1'b0),
+								.phymemclock(1'b0),
+								.sreset(1'b0),
+								.dfflo(),
+								.dffhi(),
+								.devpor(1'b1),
+								.devclrn(1'b1)
+								`endif
+							);
+						end
+			end
+            else if (REGISTER_MODE == "single-register")
+            begin: out_path_sdr
+   			  reg reg_data_out /* synthesis altera_attribute="FAST_OUTPUT_REGISTER=on" */;
+                always @(posedge outclock_wire)
+                    reg_data_out <= din_fr[0];
+
+                assign din_ddr = reg_data_out;
+			end
+            else  
+            begin: out_path_reg_none
+                assign din_ddr = din_fr[0];
+            end
+        end
+    endgenerate
+
+    generate
+
+	    if (PIN_TYPE == "bidir" || PIN_TYPE == "output")
+        begin
+			wire oe_inclk_wire;
+			if (USE_ONE_REG_TO_DRIVE_OE == "true" || USE_DDIO_REG_TO_DRIVE_OE == "true")
+			begin
+				if (INVERT_OE_INCLOCK == "false")
+				begin: normal_oe_inclock
+					assign oe_inclk_wire = outclock;
+				end
+				else
+				begin: inverted_oe_inclock
+					assign oe_inclk_wire = ~outclock;
+				end
+			end
+
+			wire oe_outclocken_wire;
+			assign  oe_outclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? outclocken : 1'b1;
+
+			if (USE_DDIO_REG_TO_DRIVE_OE == "true")
+			begin
+				if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "true")
+				begin
+					if (ASYNC_MODE != "none")
+						begin: async_mode_oe_path_enhanced_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.areset(aset),
+											.ena(oe_outclocken_wire),
+											.phymemclock(phy_mem_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else if (SYNC_MODE != "none")
+						begin: sync_mode_oe_path_enhanced_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.sreset(sclr),
+											.ena(oe_outclocken_wire),
+											.phymemclock(phy_mem_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else
+						begin: oe_path_enhanced_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.ena(oe_outclocken_wire),
+											.phymemclock(phy_mem_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+				end
+				else if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "false")
+				begin
+					if (ASYNC_MODE != "none")
+						begin: async_mode_oe_path_ddr
+								fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.areset(aset),
+											.ena(oe_outclocken_wire)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.phymemclock(1'b0),
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else if (SYNC_MODE != "none")
+						begin: sync_mode_oe_path_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.sreset(sclr),
+											.ena(oe_outclocken_wire)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.phymemclock(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else
+						begin: oe_path_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.ena(oe_outclocken_wire)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.phymemclock(1'b0),
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+				end
+			end
+			else if (USE_ONE_REG_TO_DRIVE_OE == "true")
+			begin: oe_path_sdr
+					fiftyfivenm_ff oe_reg (
+							.clk(oe_inclk_wire),
+							.d(~oe),
+							.clrn(1'b1),
+							.ena(1'b1),
+							.q(oe_out)
+						);
+            end
+            else if (USE_ONE_REG_TO_DRIVE_OE == "false" && USE_DDIO_REG_TO_DRIVE_OE == "false")
+            begin: oe_path_reg_none
+				assign oe_out = ~oe;
+            end
+        end
+	endgenerate
+
+    generate
+        if (PIN_TYPE == "input" || PIN_TYPE == "bidir")
+        begin
+            wire [1:0] ddr_input;
+			wire inclock_wire;
+
+			if (REGISTER_MODE != "bypass")
+			begin
+				if (INVERT_INPUT_CLOCK == "false")
+				begin: normal_input_clock
+					assign inclock_wire = inclock;
+				end
+				else
+				begin: inverted_input_clock
+					assign inclock_wire = ~inclock;
+				end
+			end
+
+			wire inclocken_wire;
+			assign  inclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? inclocken : 1'b1;
+
+         	if (REGISTER_MODE == "ddr")
+         	begin
+		        if (USE_ENHANCED_DDR_HIO_REGISTER == "true" || USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY == "true")
+				begin
+						if (ENABLE_HR_CLOCK == "true")
+						begin
+								if (ASYNC_MODE != "none")
+									begin: async_mode_in_path_enhanced_ddr_with_halfrateresyncclk
+										fiftyfivenm_ddio_in
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.power_up(DDIO_REG_POWER_UP),
+											.invert_input_clock(INVERT_INPUT_CLOCK)
+										) fr_in_ddio (
+											.datain(buf_in),
+											.clk(inclock_wire),
+											.ena(inclocken_wire),
+											.halfrateresyncclk(hr_clock),
+											.regouthi(ddr_input[1]),
+											.regoutlo(ddr_input[0]),
+											.clkout(fr_clock),
+											.areset(aset)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.sreset(1'b0),
+											.dfflo(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+									end
+								else if (SYNC_MODE != "none")
+									begin:sync_mode_in_path_enhanced_ddr_with_halfrateresyncclk
+										fiftyfivenm_ddio_in
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.power_up(DDIO_REG_POWER_UP),
+											.invert_input_clock(INVERT_INPUT_CLOCK)
+										) fr_in_ddio (
+											.datain(buf_in),
+											.clk (inclock_wire),
+											.ena(inclocken_wire),
+											.sreset(sclr),
+											.halfrateresyncclk(hr_clock),
+											.regouthi(ddr_input[1]),
+											.regoutlo(ddr_input[0]),
+											.clkout(fr_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.dfflo(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+									end
+								else
+									begin:in_path_enhanced_ddr_with_halfrateresyncclk
+										fiftyfivenm_ddio_in
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.power_up(DDIO_REG_POWER_UP),
+											.invert_input_clock(INVERT_INPUT_CLOCK)
+										) fr_in_ddio (
+											.datain(buf_in),
+											.clk (inclock_wire),
+											.ena(inclocken_wire),
+											.halfrateresyncclk(hr_clock),
+											.regouthi(ddr_input[1]),
+											.regoutlo(ddr_input[0]),
+											.clkout(fr_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.sreset(1'b0),
+											.areset(1'b0),
+											.dfflo(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+									end
+						end
+						else
+						begin
+							if (ASYNC_MODE != "none")
+								begin: async_mode_in_path_enhanced_ddr
+									fiftyfivenm_ddio_in
+									#(
+										.async_mode(ASYNC_MODE),
+										.sync_mode(SYNC_MODE),
+										.power_up(DDIO_REG_POWER_UP),
+										.invert_input_clock(INVERT_INPUT_CLOCK)
+									) fr_in_ddio (
+										.datain(buf_in),
+										.clk(inclock_wire),
+										.ena(inclocken_wire),
+										.regouthi(ddr_input[1]),
+										.regoutlo(ddr_input[0]),
+										.clkout(fr_clock),
+										.areset(aset)
+										`ifndef ALTERA_RESERVED_QIS
+										,
+										.sreset(1'b0),
+										.dfflo(),
+										.devpor(1'b1),
+										.devclrn(1'b1),
+										.halfrateresyncclk(1'b0)
+										`endif
+									);
+								end
+							else if (SYNC_MODE != "none")
+								begin:sync_mode_in_path_enhanced_ddr
+									fiftyfivenm_ddio_in
+									#(
+										.async_mode(ASYNC_MODE),
+										.sync_mode(SYNC_MODE),
+										.power_up(DDIO_REG_POWER_UP),
+										.invert_input_clock(INVERT_INPUT_CLOCK)
+									) fr_in_ddio (
+										.datain(buf_in),
+										.clk (inclock_wire),
+										.ena(inclocken_wire),
+										.sreset(sclr),
+										.regouthi(ddr_input[1]),
+										.regoutlo(ddr_input[0]),
+										.clkout(fr_clock)
+										`ifndef ALTERA_RESERVED_QIS
+										,
+										.areset(1'b0),
+										.dfflo(),
+										.devpor(1'b1),
+										.devclrn(1'b1),
+										.halfrateresyncclk(1'b0)
+										`endif
+									);
+								end
+							else
+								begin:in_path_enhanced_ddr
+									fiftyfivenm_ddio_in
+									#(
+										.async_mode(ASYNC_MODE),
+										.sync_mode(SYNC_MODE),
+										.power_up(DDIO_REG_POWER_UP),
+										.invert_input_clock(INVERT_INPUT_CLOCK)
+									) fr_in_ddio (
+										.datain(buf_in),
+										.clk (inclock_wire),
+										.ena(inclocken_wire),
+										.regouthi(ddr_input[1]),
+										.regoutlo(ddr_input[0]),
+										.clkout(fr_clock)
+										`ifndef ALTERA_RESERVED_QIS
+										,
+										.sreset(1'b0),
+										.areset(1'b0),
+										.dfflo(),
+										.devpor(1'b1),
+										.devclrn(1'b1),
+										.halfrateresyncclk(1'b0)
+										`endif
+									);
+								end
+						end
+				end
+				else if (ENABLE_PHASE_DETECTOR_FOR_CK == "true")
+					begin
+						assign mimic_clock = buf_in;
+					end
+				else
+				begin: in_path_ddr
+					wire input_cell_l_q;
+					wire input_aset;
+
+					assign input_aset = ( ASYNC_MODE == "clear") ? !aset : aset;
+
+					fiftyfivenm_ff input_cell_l (
+						.clk(inclock_wire),
+						.d(buf_in),
+						.clrn(input_aset),
+						.ena(inclocken_wire),
+						.q(input_cell_l_q)
+					);
+
+					fiftyfivenm_ff input_latch_l (
+						.clk(~inclock_wire),
+						.d(input_cell_l_q),
+						.clrn(input_aset),
+						.ena(inclocken_wire),
+						.q(ddr_input[0])
+					);
+
+					fiftyfivenm_ff input_cell_h (
+						.clk(~inclock_wire),
+						.d(buf_in),
+						.clrn(input_aset),
+						.ena(inclocken_wire),
+						.q(ddr_input[1])
+					);
+
+				end
+			end
+			else if (REGISTER_MODE == "single-register")
+            begin: in_path_sdr
+                reg reg_data_in /* synthesis altera_attribute="FAST_INPUT_REGISTER=on" */;
+                always @(posedge inclock_wire) begin
+                    reg_data_in <= buf_in;
+                end
+                assign ddr_input[0] = reg_data_in;
+            end
+            else
+            begin: in_path_reg_none
+                assign ddr_input[0] = buf_in;
+            end
+
+            assign dout[DATA_SIZE - 1:0] = ddr_input[DATA_SIZE - 1:0];
+
+        end
+    endgenerate
+
+	generate
+		if (PIN_TYPE == "output" || PIN_TYPE == "bidir")
+		begin
+			if(BUFFER_TYPE == "pseudo_differential")
+			begin: pseudo_diff_output_buf
+
+				wire wire_pseudo_diff_o;
+				wire wire_pseudo_diff_o_bar;
+
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf_a (
+					.i(wire_pseudo_diff_o),
+					.oe(~oe_out),
+					.o(pad),
+					.obar()
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf_a_bar (
+					.i(wire_pseudo_diff_o_bar),
+					.oe(~oe_out),
+					.o(pad_b),
+					.obar()
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+
+				fiftyfivenm_pseudo_diff_out pseudo_diff_a
+				(
+					.i(din_ddr),
+					.o(wire_pseudo_diff_o),
+					.obar(wire_pseudo_diff_o_bar)
+				);
+
+
+
+			end
+			else if (BUFFER_TYPE == "true_differential")
+			begin: true_diff_output_buf
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf (
+					.i(din_ddr),
+					.oe(~oe_out),
+					.o(pad),
+					.obar(pad_b)
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+			end
+			else
+			begin: output_buf
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf (
+					.i(din_ddr),
+					.oe(~oe_out),
+					.o(pad),
+					.obar()
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+			end
+		end
+	endgenerate
+
+	assign nsleep_in = (ENABLE_NSLEEP_PORT == "true") ? nsleep : 1'b1;
+
+	generate
+		if (PIN_TYPE == "input" || PIN_TYPE == "bidir")
+		begin
+			if(BUFFER_TYPE == "true_differential" || BUFFER_TYPE == "pseudo_differential")
+			begin: diff_input_buf
+				if (ENABLE_NSLEEP_PORT == "true")
+				begin: diff_input_buf_with_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.ibar(pad_b),
+						.o(buf_in),
+						.nsleep(nsleep_in)
+					);
+				end
+				else
+				begin: diff_input_buf_without_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.ibar(pad_b),
+						.o(buf_in)
+					);
+				end
+			end
+			else
+			begin:input_buf
+				if (ENABLE_NSLEEP_PORT == "true")
+				begin: input_buf_with_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.o(buf_in),
+						.nsleep(nsleep_in)
+						`ifndef ALTERA_RESERVED_QIS
+						,
+						.ibar(1'b0)
+						`endif
+					);
+				end
+				else
+				begin: input_buf_without_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.o(buf_in)
+						`ifndef ALTERA_RESERVED_QIS
+						,
+						.ibar(1'b0)
+						`endif
+					);
+				end
+			end
+		end
+	endgenerate
+
+	generate
+		if (PIN_TYPE == "output")
+		begin
+			assign dout = {DATA_SIZE{1'b0}};
+		end
+
+		if (PIN_TYPE == "output" || REGISTER_MODE != "ddr" || USE_ENHANCED_DDR_HIO_REGISTER == "false")
+		begin
+			assign fr_clock = 1'b0;
+		end
+
+		if (PIN_TYPE == "input" || PIN_TYPE == "output" || REGISTER_MODE != "ddr" || ENABLE_PHASE_DETECTOR_FOR_CK == "false")
+		begin
+			assign mimic_clock = 1'b0;
+		end
+	endgenerate
+
+endmodule
+
+module altera_gpio_lite(
+	inclock,
+	outclock,
+	inclocken,
+	outclocken,
+	oe,
+	din,
+	dout,
+	pad_io,
+	pad_io_b,
+	pad_in,
+	pad_in_b,
+	pad_out,
+	pad_out_b,
+	aset,
+	aclr,
+	phy_mem_clock,
+	sclr,
+	hr_clock,
+	fr_clock,
+	invert_hr_clock,
+	mimic_clock,
+	nsleep
+);
+
+	parameter PIN_TYPE = "output"; 
+	parameter BUFFER_TYPE = "single-ended"; 
+	parameter REGISTER_MODE = "bypass"; 
+	parameter SIZE = 4;
+	parameter ASYNC_MODE = "none"; 
+	parameter SYNC_MODE = "none"; 
+	parameter BUS_HOLD = "false"; 
+	parameter SET_REGISTER_OUTPUTS_HIGH = "false"; 
+	parameter INVERT_OUTPUT = "false"; 
+	parameter INVERT_INPUT_CLOCK = "false"; 
+	parameter INVERT_OUTPUT_CLOCK = "false"; 
+	parameter INVERT_OE_INCLOCK = "false"; 
+	parameter USE_ONE_REG_TO_DRIVE_OE = "false"; 
+	parameter USE_DDIO_REG_TO_DRIVE_OE = "false"; 
+	parameter OPEN_DRAIN_OUTPUT = "false"; 
+	parameter USE_ADVANCED_DDR_FEATURES = "false"; 
+	parameter USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY = "false"; 
+	parameter INVERT_CLKDIV_INPUT_CLOCK = "false"; 
+	parameter ENABLE_HR_CLOCK = "false"; 
+	parameter ENABLE_OE_HALF_CYCLE_DELAY = "true"; 
+	parameter ENABLE_OE_PORT = "false"; 
+	parameter ENABLE_CLOCK_ENA_PORT = "false"; 
+	parameter ENABLE_PHASE_INVERT_CTRL_PORT = "false"; 
+	parameter ENABLE_PHASE_DETECTOR_FOR_CK = "false"; 
+	parameter ENABLE_NSLEEP_PORT = "false"; 
+
+    localparam USE_ENHANCED_DDR_HIO_REGISTER = USE_ADVANCED_DDR_FEATURES;
+	localparam BYPASS_THREE_QUARTER_REGISTER = (USE_ADVANCED_DDR_FEATURES == "true") ? "false" : "true";
+	localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? 2 : 1;
+
+	input inclock;
+	input outclock;
+	input inclocken;
+	input outclocken;
+	input [SIZE - 1:0] oe;
+	input [SIZE - 1:0] nsleep;
+	input [SIZE * DATA_SIZE - 1:0] din;
+	output [SIZE * DATA_SIZE - 1:0] dout;
+	inout [SIZE - 1:0] pad_io;
+	inout [SIZE - 1:0] pad_io_b;
+	input [SIZE - 1:0] pad_in;
+	input [SIZE - 1:0] pad_in_b;
+	output [SIZE - 1:0] pad_out;
+	output [SIZE - 1:0] pad_out_b;
+	input aset;
+	input aclr;
+	input sclr;
+	input phy_mem_clock;
+	input invert_hr_clock;
+	output [SIZE - 1:0] fr_clock;
+	output wire hr_clock;
+	output [SIZE - 1:0] mimic_clock;
+
+	wire [SIZE * DATA_SIZE - 1:0] din_reordered;
+	wire [SIZE * DATA_SIZE - 1:0] dout_reordered;
+	wire aclr_aset_wire;
+	wire sclr_wire;
+	wire [SIZE - 1:0] pad_io;
+	wire [SIZE - 1:0] pad_io_b;
+
+
+	assign aclr_aset_wire = (ASYNC_MODE == "clear") ? aclr : (ASYNC_MODE == "preset") ? aset : 1'b1;
+	assign sclr_wire = (SYNC_MODE == "clear") ? sclr : 1'b0;
+
+	generate
+		if (PIN_TYPE == "input")
+		begin
+			assign pad_io = pad_in;
+			assign pad_io_b = pad_in_b;
+			assign pad_out = {SIZE{1'b0}};
+			assign pad_out_b = {SIZE{1'b0}};
+		end
+		else if (PIN_TYPE == "output")
+		begin
+			assign pad_out = pad_io;
+			assign pad_out_b = pad_io_b;
+		end
+		else begin
+			assign pad_out = {SIZE{1'b0}};
+			assign pad_out_b = {SIZE{1'b0}};
+		end
+	endgenerate
+
+	genvar j, k;
+	generate
+		begin : reorder
+			for(j = 0; j < SIZE ; j = j + 1) begin : j_loop
+				for(k = 0; k < DATA_SIZE; k = k + 1) begin : k_d_loop
+					assign din_reordered[j * DATA_SIZE + k] = din[j + k * SIZE];
+					assign dout[j + k * SIZE] = dout_reordered[j * DATA_SIZE + k];
+				end
+			end
+		end
+	endgenerate
+
+	genvar i;
+	generate
+		begin : gpio_one_bit
+			for(i = 0 ; i < SIZE ; i = i + 1) begin : i_loop
+				wire oe_wire;
+				wire nsleep_wire;
+
+
+				assign oe_wire = (PIN_TYPE == "output" && ENABLE_OE_PORT == "false") ? 1'b1 :
+				                  (PIN_TYPE == "input") ? 1'b0 : oe[i];
+
+
+				assign nsleep_wire = (PIN_TYPE == "input" && ENABLE_NSLEEP_PORT == "false") ? 1'b1 :
+														(PIN_TYPE == "output") ? 1'b0 : nsleep[i];
+
+				altgpio_one_bit #(
+					.PIN_TYPE(PIN_TYPE),
+					.BUFFER_TYPE(BUFFER_TYPE),
+					.REGISTER_MODE(REGISTER_MODE),
+					.ASYNC_MODE(ASYNC_MODE),
+					.SYNC_MODE(SYNC_MODE),
+					.BUS_HOLD(BUS_HOLD),
+					.SET_REGISTER_OUTPUTS_HIGH(SET_REGISTER_OUTPUTS_HIGH),
+					.USE_ENHANCED_DDR_HIO_REGISTER(USE_ENHANCED_DDR_HIO_REGISTER),
+					.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY(USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY),
+					.BYPASS_THREE_QUARTER_REGISTER(BYPASS_THREE_QUARTER_REGISTER),
+					.INVERT_OUTPUT(INVERT_OUTPUT),
+					.INVERT_INPUT_CLOCK(INVERT_INPUT_CLOCK),
+					.INVERT_OUTPUT_CLOCK(INVERT_OUTPUT_CLOCK),
+					.INVERT_OE_INCLOCK(INVERT_OE_INCLOCK),
+					.USE_ONE_REG_TO_DRIVE_OE(USE_ONE_REG_TO_DRIVE_OE),
+					.USE_DDIO_REG_TO_DRIVE_OE(USE_DDIO_REG_TO_DRIVE_OE),
+					.OPEN_DRAIN_OUTPUT(OPEN_DRAIN_OUTPUT),
+					.ENABLE_OE_HALF_CYCLE_DELAY(ENABLE_OE_HALF_CYCLE_DELAY),
+					.ENABLE_CLOCK_ENA_PORT(ENABLE_CLOCK_ENA_PORT),
+					.ENABLE_HR_CLOCK(ENABLE_HR_CLOCK),
+					.ENABLE_PHASE_DETECTOR_FOR_CK(ENABLE_PHASE_DETECTOR_FOR_CK),
+					.ENABLE_NSLEEP_PORT(ENABLE_NSLEEP_PORT)
+				) altgpio_bit_i (
+					.inclock(inclock),
+					.outclock(outclock),
+					.phy_mem_clock(phy_mem_clock),
+					.inclocken(inclocken),
+					.outclocken(outclocken),
+					.oe(oe_wire),
+					.din(din_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]),
+					.dout(dout_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]),
+					.pad(pad_io[i]),
+					.pad_b(pad_io_b[i]),
+					.aset(aclr_aset_wire),
+					.sclr(sclr_wire),
+					.fr_clock(fr_clock[i]),
+					.hr_clock(hr_clock),
+					.mimic_clock(mimic_clock[i]),
+					.nsleep(nsleep_wire)
+				);
+			end
+		end
+	endgenerate
+
+	generate
+		if ((PIN_TYPE == "input" || PIN_TYPE == "bidir") && (ENABLE_HR_CLOCK == "true"))
+		begin
+			if (ENABLE_PHASE_INVERT_CTRL_PORT == "true")
+			begin
+				if (SYNC_MODE == "clear")
+				begin : clock_divider_sync_mode_invert_hr_clock
+					fiftyfivenm_io_clock_divider
+					#(
+						.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+						.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+						.sync_mode(SYNC_MODE)
+					) io_clkdiv (
+						.clk(inclock),
+						.phaseinvertctrl(invert_hr_clock),
+						.sreset(sclr_wire),
+						.clkout(hr_clock)
+					);
+				end
+				else
+				begin : clock_divider_invert_hr_clock
+					fiftyfivenm_io_clock_divider
+						#(
+							.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+							.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+							.sync_mode(SYNC_MODE)
+						) io_clkdiv (
+							.clk(inclock),
+							.phaseinvertctrl(invert_hr_clock),
+							.clkout(hr_clock)
+							`ifndef ALTERA_RESERVED_QIS
+							,
+							.sreset(1'b0)
+							`endif
+						);
+				end
+			end
+			else
+			begin
+				if (SYNC_MODE == "clear")
+				begin : clock_divider_sync_mode
+					fiftyfivenm_io_clock_divider
+					#(
+						.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+						.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+						.sync_mode(SYNC_MODE)
+					) io_clkdiv (
+						.clk(inclock),
+						.sreset(sclr_wire),
+						.clkout(hr_clock)
+						`ifndef ALTERA_RESERVED_QIS
+						,
+						.phaseinvertctrl(1'b0)
+						`endif
+					);
+				end
+				else
+				begin : clock_divider
+					fiftyfivenm_io_clock_divider
+						#(
+							.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+							.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+							.sync_mode(SYNC_MODE)
+						) io_clkdiv (
+							.clk(inclock),
+							.clkout(hr_clock)
+							`ifndef ALTERA_RESERVED_QIS
+							,
+							.sreset(1'b0),
+							.phaseinvertctrl(1'b0)
+							`endif
+						);
+				end
+			end
+		end
+		else begin
+			assign hr_clock = 1'b0;
+		end
+	endgenerate
+
+endmodule
Index: atari_chips/gtia/osc_in_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv
===================================================================
--- atari_chips/gtia/osc_in_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv	(nonexistent)
+++ atari_chips/gtia/osc_in_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv	(revision 1318)
@@ -0,0 +1,713 @@
+// Copyright (C) 2018 Intel Corporation. All rights reserved.
+// This simulation model contains highly confidential and
+// proprietary information of Intel and is being provided
+// in accordance with and subject to the protections of the
+// applicable Intel Program License Subscription Agreement
+// which governs its use and disclosure. Your use of Intel
+// Corporation's design tools, logic functions and other
+// software and tools, and its AMPP partner logic functions,
+// and any output files any of the foregoing (including device
+// programming or simulation files), and any associated
+// documentation or information are expressly subject to the
+// terms and conditions of the Intel Program License Subscription
+// Agreement, the Intel Quartus Prime License Agreement, the
+// Intel FPGA IP License Agreement, or other applicable license
+// agreement, including, without limitation, that your use is 
+// for the sole purpose of simulating designs for use exclusively
+// in logic devices manufactured by Intel and sold by Intel or 
+// its authorized distributors. Please refer to the applicable
+// agreement for further details. Intel products and services
+// are protected under numerous U.S. and foreign patents, 
+// maskwork rights, copyrights and other intellectual property laws.
+// Intel assumes no responsibility or liability arising out of the
+// application or use of this simulation model.
+// ACDS 18.0std
+// ALTERA_TIMESTAMP:Wed Apr 25 07:09:40 PDT 2018
+// encrypted_file_type : local_encrypted
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "Model Technology", encrypt_agent_info = "6.6e"
+`pragma protect author = "Altera"
+`pragma protect data_method = "aes128-cbc"
+`pragma protect key_keyowner = "MTI" , key_keyname = "MGC-DVT-MTI" , key_method = "rsa"
+`pragma protect key_block encoding = (enctype = "base64", line_length = 64, bytes = 128)
+fmmgwONj8YLVFvc9fzLQt7vQ6qNjohAyiwgrgqxvvIA/p2m2OK6Azwxg4RpSfucB
+t8igxEqwdy5LEhpwhZkkLsrurOpDLiHsF34i1lhbKgwB9v8c9mHbkGd6X741IBJr
+WsCDuEfFTKBDX0bX8wvL+NF4dYh8nobVYKXUGff6rpo=
+`pragma protect data_block encoding = (enctype = "base64", line_length = 64, bytes = 32384)
++RsIbtnldMRALbzsiW80qZ2rfTbzXsyC9jdHu+gf6XnD3AsZhYK5zCEPnRv4pySJ
+bZKhJtpelHssEQbQj1gm2sidjk72T2b+em+fDYP/zSWAo2HbSpQ7suMGBwIQx6d4
+wCLXdsbPpg0183l0WXdB9EKQFm0Vk5DjX6LqvfZK+3VSdWzZOAse9J3YFaH3W59l
+3pQlelSTVMVISjqVBozQV41Bwi0ECbUU5P94I9PH8Uh+3FwqFJOXcdPSqnkprVYI
+t0L0scxgXG83cRdfyXvZlSWYdepmulrUXNFmXa4Jm0+g1Ygj98+m6EMh29PCRdyh
+YKzR0OXVGEGYEhVb3EUcbBogrg7PnnHK7vz4/LzsYM7xTds/NsNKuk871jlTZDB5
+w+n4d9XuLzSiW/a1lAeQNHhojwPy0oxm+qPk1XlotTicrs4KhcXS78jwF0EEdkCg
+Oi7XtFgBhaimK/i2q54jR144UdulgognqeN9tDCm7VC/Xbr/W4J6ZAVH0ka5yBwT
+JuxdgbbXHhnKImQH+alJxkNGGF0GgC5/u5UnA041gg2aI3TE9W3OuPBqUkOcBVwo
+rRJzwavki+k2vTU2G9HcutRGFeKkVmZABl7nPrwR9qSgdfwTZbik8gSle+iZQC+w
+hTiJBk7X9tmqrDrtIIr4dJ3suJj/Hny9J4gd2pLlJEM+VlNubmhU+AuFdBoMUeS9
+9FeTIf1rAluK62bELVqirXef7COzc/KCQGnpooQO2VsY6IfPB2eHM5ebnE78R7ul
+JyGUk4uxWSw+d0OoYAnRwP52tskbJesUMBx1VcJf7T8jpzAzihCusLd5AvNGRNj1
+PKIrKR82dKUXQ9PGhsJauYqZV/MLRKU3AXIqQpgMosw3rMxhcneZWLEzAxgo/T9y
+u0HP1S0BJedOOiFLcFg+QANuvc+qZtnwmBVHFXZgGJzaKbnJlefxSJL36HsDRkL/
+SGCNUZpodf07c+cr6sJXFO3Fi1y3ebu7lIy1X5eb1R1ff/F4ACATdeAL5InF+ukd
+dJWtHrrSfwYr13MX4JU0ctNkOC23teI46uc3tL4hUElvcR+C/rmj0FSibWMq9QlS
+c+cVWd6XVsmgoxuSvb0hjuMTTD5/Sp8cD1gU5eRxBeX+WDRn3vdIxxJIpgVVY4EE
+789cPYmzEe1oCN2xhzgPD6weZY4FBc8QOP0Nzl2lPHcZmODH3+qllQgwtJkutsFF
+uVcZM1W+win+TGqb1GGlBpaEHo7+W39tMe9BS+MBJxNjdGJ8Q5VIfrkUoNhROvL9
+mziCl/ogTy7wFO8ghTgkGSgkwJ49Ce0cBZFC/pfjTwNVAHnxUnVLwKZ016Zs+xx4
+I317UD3z/A9oYeEuKxOoCVQklpNCI/WqBfp9pxXSogy/ZRwn6rN0HUD+a9VU28Zc
+JrAxf9jaiET6t9KdvPSOckOT09siOO30PAeFnU/CYnFWx+JqQG5ZLFfqf7z4ty0R
+ER3D4T+4vR76Za8VcM4egzsM4iAmhNngOkWV1bGY5aUk/r7nGtVz+w4yqRoGDrwp
+5SsU0o/+M7PRsdNBmW4j0AMtGj8aClJ2u2mcaJfgEQ1lvN0gCsxJ07nhyFw5mMcj
+k6fzIEU0hQdBaW4T/nRy7ORGiGCNUoGbkrCIX7IRD7K9rzYxdkrH/f5Yp8R4MvKD
+tTAhQswnt4v9pe+Rjg72e/hRPgYX+soIilNaH30TBrNMHrc+f563vXCcA1/GZnSm
+TIYMVOTSXv7mjuuHc/cRJb7VYH9HR/haSQO97ZPazaAYZj86dFAozctoJdgt3X8g
+SWG9yAvWiZQLx5V+bVyXAtDjJP649cAnD23mIzX7HkGeXa4aFrJkOCTrqwvyMqPQ
+mmmcElafr1cfrOWL9jqk+byJ/aG7pFpj5fxS80rc+zos2Y0rBEAyfWSu29ODnylh
+uXXc94JK5HOym0JopTk0cuT2YOpZgHShawgQxISfv0v1RB17ZUbAL2/yIYwBaK+Z
+orgQ7z5ki0pJd8Vycdr/6u40qJntB2HhqvYj1J0bcQ4ayBhrIfEppAZjUIbD8fmT
+CeHR49qrlgY20O0or5X+1rr4YUqHhOHnH303BzvQTAeec4WM1v3B6kFDbymTH0Qp
+cquKfDCc1gTDIBHOqO/tFz3+uf7BX6JFZvXDpaXlBg8obaNx7SkQWwOb512RcbLi
+whd0/XXsiVkOaP7j+GV5R3RBeEHuq70e7BC4CYoriAvmNfjhepE6AaYfcPlkkje0
+E7BkSWA+sdBFYw+lViSJurJI4V/2dg1s3Xw6vBp2BiXGAzyM9wgyJzggDu7Jk00Z
+HURXlglXxVufFJL3vYRhveyaMHLigoN9UmucF/9TMoJzeEY+5uPmHuxXLpdtmfaB
+xFAifnatl23HuAVlLGzZ0wqnjPX1WaSx+XG+mvw39BW1ZCCO33iE6h/yBYU8ZCbs
+qsePlE9woL4KZvg+vWswb391qA//xP6Th3w5z5y2+RZj+X9TMxBQqtLCyoUoDCtz
+LcMAf/hJ+2CBAL3qZOTFHpxxXWk/3M4d2FwCCqiybrSAUmXBJbRBl91ndclmnpB0
+7v9rqnKaoVXd+3eMudLxU3TlzFBGNfGPWfeetpkbJQ+dMRXAj6y4Dk88Azj1lV7U
+MDJjdFUD9NSzL+t2mNIbdGsuzbcErASacbB7F4KOKuidfzD7ecfpOjPpE9744Aux
+c8uOUCz4L3wYnSEAi8B0/eslOUFFm7u91fnTqjclYO0TyN13nFi/OtkHezimGItp
+DJ9p4iPheCMq8+ruSaOOkQOEUT+3dbSCUeP/v23O6D+Acbr8E5b3Akvhojd2dPt8
+u1BHFavtfaP+bLZXH2X7XC+8auw5/sKkjSX8JGnrNQl9qgv/RDOUNEJrmOWOigfr
+1jdknV2OGlKI6UfHxak9FH6UMNvk1aHxIcUEc/+aJId3jJd8x/zjOAFDHSVa8K3h
+eQYYBsDD9vU206MknbcL77i7s7JfBHEpDXRNZgMX1m2g4Q6OaFs0aZn9S2RbeVE/
+tpe49w44Wt3Punzp6D5yoRJBeHxTjrCYqfc+se/84wrQ4k+tRg3DcIrQ7qGxNhfg
+F4SVRNN0Qeh0YXyrJrYXPWDUYcZFgtk+2ffLTSBEEM13tvuzB7pWJKy6/SgBPpYX
+WFzffIO9ce4KRkjJ0U7KH8vn/D2tD3JhPXXfhCMAmLZSPUvxYh49ZeYpXkaLr9Aj
+xyWJzpsqZuES32EArfSu/BMuLEM0kgwgg2vDPQoLZVMu58rTQi/hnvfu9Xvz7UeB
++YtR7cDeZy+D42SgBvNInjeRciKkctZtgG7PElgl8fpZwQ3faLj/Z75P7ppUGo+A
+oj3T//ioGtUF77VDpVD9Q+2Yy/cKiwZ4HTJB2Kl9RtIlF75XMxlYVTvjICsF5KUB
+H6RQfDzNxO0DMzvBd3B5j+F8j36U38bzAnkGtD4HP5SHJp5R0i97KEaQADDoFqd3
+i75yMT524qg6htjbPIuZ1zvZ+8n5Itwpf5rEqF81YCTirdVjK73kIigkJFihOfKP
+sCYO0B6o81BT/HA1WIJqYpAG9Fqz4aoLwiZzpBnahJ1x2oA/xCQbfkb5bK/eHrQ7
+7qtwe+lWjWio2e6wmiZ3FTGHua5pVfrDLHZvICY989X88jAnfOhpnbV1eyWu7zvH
+NjAzDNv6A5FsbcK0JhegIIYStRBGigQr3ed005vXWKRIQtd3sc68OXfJr68xOMgh
+rRXpOpjzS/M26xC7hVbGqf1/qc7ggkqJJfSXVp+6G9S1WSuzuO1vu5d4lW9pL34f
+FRkVhGQ8vxtmzvR/D5dB0GK3lR5JIBNxGwQyGlp2P7PQehRRDu0asAZ5ZvlvDhZS
+hzwPlRgdTET3N3fEqmM9oZ1VWXDZbV1FhFZdzKLBnxDCN00qrhJoy545nRiJT4ve
+/vn2LfnnQWpe3egrREv+kYKJ5fXeWu6svXci0YrXMNOiE/3wTMgjCO0heptyanPS
+nhwbX/GxFb681JS8GrNEs6C+T5bbEEsCgvSCs7aANE/a4KwOy0Hoi0IgbP/FMjLP
+uWzWKHYvZ0kZqo7Vl2U47OmxcOtKWKVAR26bETUhBm9IloU0nJhaW/uD3KIOQlI3
+67zA0Td8afb0Cy6R2fU3TZvwnqGEBmdnDX75qPY23LlMYpc+UL3HZpoUhRumtKVg
+Nn2Layqa///p7A8i4MnycA+HjB4xNVqKZcEMfupGFh0m2d5+6leVTwcB4HK/aBah
+yenZclsLwAPWdSWqJ2loCby8P/PAQsLM239PrbDkLAiHuChrtaIF4WD7GCmjhGRm
+SY8RneCQ51E7tT567bsc++vDkPgQmgW69dFSz3gr42rRRoeXEYIft14EQ80Q+bdh
+tkfN/BBLVjldYVBdJSo/bwVJJ8+lhIhnYbJqf3GIqOq1QWTNG9RnAZPoH2+BPwTL
+BfYMWufy+1WV9DimGkqAzxfuC56iYWLSh+sMacouWd9fqQ58LmeU7TJcvmNi1xp0
+Ia6ib2eXMoAQ1ylrN4mLg6oNmu4uZUSBAwWid20Nhm6G4Y4wjP+l7b3zFCQbnwBY
+QJMVHjzZx/IyaV0qXs3AyGKmsi6CWbeTm9+JMEesLrj1ar5jjR8CMXPvvnl5JVcn
+2dxqj5I3Eh8ZVF809p9r96m4XhjW9tW9OvgPLhv3F89gYRbQNihDCKAU0t/Zqji1
+uT3VkCw+bibj4NLEalZs+YBfmx6iPHYblxGym8ufcm6fZilhLQuOmpVgxZ3KSKLs
+YAGSRrj/dVZQQFA/yhvEtDNOBNG+HttjcFoduA3feSAi/iMuo0WSnxD5pH0SEomZ
+AfA4g5BUBWX4lGqq1ZUTqxzbnGXCBS+B3c8dXBkDYDnkxfJ21Cpm2HbaxeqedVy2
+eR7LfemnSrhwWiwf3fSWEJlAhy967SxhpGUgnSKwYiI6CmpxF8K4YtbeVy+9M5fI
+AMJDiVhkdtYzD8pnsiECLIHa8nCE2xuLPd25cE0avA3S0sGHKQXQ2wbtTMXxEShH
+2Y1YWIkEWO1rsu2Rmn51aV+xwxHg/cNPepc53JxxBXTh4amJ2O+NhjYhrkzlylnW
+GN+/RhERRE/O1eIwos5Lo7JfKwVEWzGkjSxcwIH4zZf5tWFL3YkqMcx+YjiPmP2J
+x2xB37hVhCShkZjz8kgRrw0GKhxs/pQz4jY7CvRxD4y5/f0Cc92SWlUeQGnWASCb
+sUdQWWhENdfyORr5jaFjTajmg1rLSlHDh+Hf1fzl79TMKzgtzb/Fq4x+kjgBaD+c
+3Dm+cxIfz2Njq0JEoZ2iFupyPcSxNiO33u/KaU2uI26JdTMWTqlzCtn5z8I3ruQf
+Vp7Y75nH21N4V6LZT55eozfoc8XtruwwAb6CXJglHQSKvuwZ9zZfIpCsudnS0Hgr
+5NiQEF+htB6KSLDZ7RI1b8UCuOsAz0JmPrvpoyi7HQlnZHf9OrC1XFzxz3saRpcX
+lmXvkQjlOFrs+mlanBtUrxdEh0Bawb1dnrW1uGNGC7avlgO/T+9+mc07yh4rQVbK
+csLzMGBTNbbPBLalUQZHRvtDQYVMLMBEb+8j54uKtOcDWhNuZ3aT6Ms/NJUE2+Fr
+K56UbDo2Yi0OafK4p1xIO7ZRBaD1xjWS98vDeEJNK6c0wFTgKdn3ii1jT0PUlgSR
+Qn3c8q+9tTEq2S/DxMcLWq9DoVXaLZaV5K0rUQozNCsBFQr/lI5GeTgrpq8UaK74
+z27FhKYr8CO7Z7eCgOBQXowZONFMCv7ygfq+6vi8VEe16soFHRsAcDq4L3/VISN6
+Gr4REZaRtokNoS/XNwuRNmD8DK4kN6FS4ey17oreguFU0cRbPiQHGmTAbQIxAp2v
+ndmKmCQta5ab0jwjX7rzGINATfG8IZc81ZTb8IqjAzZBBCCuj1cNsSesdesjrk/K
+aYS4sKsFa56klpjNGbFd6y4p16r+Quee3Q8UiZc3HRgX9Idd9sfzghsJ6Vrj8qD2
+APbTGloBxuyrTF3dMdLu/awKc1o9+8ryKVvJx3/3O7zLjYWBcEFoN9Yk2/eKdMc1
+zzmKWrlIG25qhjNAtAlOY5Iil1BwMZgPGxdusmLud+uOYSknVf99Amn3t5A57NBJ
+/TExj4UGwFJKMoldqVhGrGDfb0Y/aU0tjQ6+MWTnPnkUG3SohUpA0x9H3oJGCqtY
+Dn9iNOO68RQjWBk74/z4kjgD6nvctWROH7bkkj0nhyOQLF0aA3M9GG4Lom2uJ+9D
+Ta1DF7Svsop7ifcC745tEXa6sYYzJTYLAUvfUxgz8F+ofVSYurVt2jHLnBUgG3CT
+PeVY0WPch/rSP+GKOTuy2DqXQgrPU85sVQYTz6pX+dWEoOb+ssHEqq4g3wXuLBmc
+I6UEI+dZJx3tco+PY7HXsiOYznk+c3DqENYTkskywDeHkVEE8R/ZxKTpgstoEHwe
+l79Ty6ONhUiZ9rw8PaQoZ3gR4jTDJrW1B+ARF4i7OE4TrO4m7QkBKwJgS5Iqky0h
+e8VulUoAdjqtVez7E6San3KPDUyGg5GmpzbI5bta/fBYXlIMe9ct9NQSIZqeWgiC
+Sz65J9pfPnlk4JfThLR4dL0JdC6DUJ6+ESgMQvS6NMG8uyZdXKlX8vOpnjc/8xss
+UOAWX9p5bLxNtUAFU8nn/oHuN/HyuKgHzeMcu7CXj+D2gcxJ4Mlbucr7lVs6pAft
+LPDKsqyxX2xu5kLbzgCCaN4nyB79sQw3WfCEU/y7Z7xNWVZoolfBVi8OdgEGZYBI
+P4pB8g7jVg+QQUv2rsplfTzLI1HA/q5hzjo0CecK+hpEB+iU/TnuVzaSUmJUKhas
+u0tZPqkZbcNVuH1IAIjbbgBxQqQsW/V58k1rxtV3ohUgIYaBeclgsvXne0MJbOaL
+kbp/dPyZMANYSIevIYdWi+PQecoJdH1UVs2FO3YZKXRclK5s3J/N4g02Ddch0csj
+GMyEkwIKzxdSe/+HjIK0TAjJfFpk8am6yCBwS3Nu0nrkvYXJyTBEUVRvar34HCSy
+OE3+epv0w28ujaB8YOUR+MvdLDbdQRf36+5e7x3LwTPs1z0kRi+l4IBHpt/uutTf
+zq36XI7ins1roLyGk3tmMopEq/ZgSeV6niuxh41+jZ7oChCX9Pb8VFT5sHU5VFfM
+SOVYDnqt7d4HmwGc1mthgjzbxhvlyO01+d64HoEDFKayKkCwElcWp/HiaUPP/TdX
+CTqms0SFC/dckL6yO0QQ3/zn408Rj+KmsOBdsNBcgZl5etHXRPisgWApJ/z6JR95
+2+Ogb/+Pprs7hr8MbeJoZSPuby7mPTjnGBdX8mJl/rQA58SMbhxVTkKp8aXCMWrh
+PDNvi89ELx2xdre4bNjRCcRD1wbgklnMAWkl6vVHrpxb6dFsXrHSiokBQSVCyDdQ
+pgLB8f7AO3tQq/1Ax6xwKIDU8VxxprXXy9eOb7NTsjspzwCh5F35BLE0l/v25yyh
+Xt3Ud/mvOfXNa67q2K10k/2ZNAf7B5nSr5XTc5+9HmzVlyH7pq2Tc6+E1gC7ixbL
+qE58D3Lv8PXulwOfO7JEnS7/NKmRS/1KBuszqMDGUjrf7PxucKMwxH7h57GY+s66
+PFXyNccmsJVa8GQHZH7iHK+TvdUkIdQ+GjWQgfGyLghIirLw+QdPNUz4qmodHei8
+/ZzmGeMuhXj0SRvAvpiB7Nk8i3CuWrmJ4C89p5VhDxnaIYul9DCgFIQjKjS3Tksz
+2yEbg8NQyanzhKiJMjLexZ8UlXyntfqOg/Gn7JzoRd2SAs+1pulIUKihfaeFCHvt
+Wfun/hw/mXREEMSj/gl16x+W7s8CBwxxfVjbOVl1Vw+TzjICLGGzQnlVP1Ik8g7n
+xI4IL7200Jv3Jjaw6TjmtgQ2reMcQYIZnJB4hwN+WZrEzTGz0KxMiXT/9dMSfADx
+S0K1CO5yIzgGLhF3GEZvcu8/O6QSPiWLD1BeInypReJaKF3sLb9GtDw0vb0XDyn9
+HN9soqa8y4ezvIFcMNTQ5lhq+bZkwPiqpJkQ1dLV4O52ye3SrTWvaInEjVL35rJJ
+cJvsan7SRo8BaofkV4aVa4VbYO85a4UgwUZ1nlUxOH1SQA+lkLeN+NtiRccP1iw5
+QUxnymdI/3AEzgq6vUF0tPHCTFQp7nq65UGIqBJ0mSf19M1/to1ffnceflwtTRaW
+oVVh/7n+GGEbCs55mhOzjTj4eFTEEAAOZ0lmaQTpmfvvYmIzgn7GIlv28++zKVsf
+G83p1HuPLyhqma8ct1ti0QD2EUgWXr3x2zROdl0b5ZNAgw3DY/rW/FvxcLuPBd0m
+HxR3UwD3RSbAUjdHzsks8tP2D4UxDB1HBizX5eJiuLCRW13mu7/EJwviGYAVJ5xH
+8xryASO6bYt1rBGH7Xsz4cYwhSPYkoGSqaPipPcFZVt0GargN/AiTsr43is6YfVx
+37dcCUr9aFM6vRH1IEEeEf2SbVtNQZrsw7mdRf6CZevUYaucjXHuVGpY0a8npi93
+eycv2cf3pZlgKFg1U/2w8j9KYkdHwc24G3urOKqYgdUsWMZyNutzCJ/BhkPfE7Nv
+Lq95IeeMUkJbpMxTxnmPOFc2D0S0TAZUKQ3BdlzCuo9PdtFe2kK+qASObGfoKbtw
+AE9BWiNuxueOjq9rGBKJVD9+MMlG4z7IJlDBb5Smgbr3MD0imF802qo4g+yF0yDT
+6hr/GUOnsO5veT8CXX6t++6G9l6DjY0+y/kUlwosmlgCtm8XBpQFe/w/C15YA4nx
+lr0SE+3NkTSSSvoVNI2xq6ijCeDWM0NrlsC7Kuf4bL4pHxb2SQUL2UsYNBxBMqkF
+OkzHSw4Q/5YwpLNC+qMQPDCrDEXW74oLsyutBtpH+DPK2YhCdQkrwlORO/rozul+
+lFmrITMxwUoqel79myFvSr/u/cjp/7057DZW+7PVG4u+T7bfnUAMWo05THmsC3oD
+X1KTZHhMAxtYaHqqYRerS8YVua4J664WplnG1fO3LiC16HA4s/dlXIsah1SSfv3l
+APScYcuu6WjhUAfyKRuP8u0F+kdMdHhi8CYtjSakpwS94rxfSsb/jNy9ZgtkB/2m
+yrWxEluT44L3QnuIoCecx52BGY9RiNXWai9nktCu0XfWU9TMzFmWN2j7PvAWkJ6l
+KYQgbdwxqOePaB6rRMku5zy46y0D7Y0wHoQFbxrX3CWhqVOsOocq6nC8DMvAQJgo
+ViF/sZ+0Ij+31wiJD2Jr4qL0qEdoHBakXL2pWsC2tU65/ZLUQgkwWV4sNobpq7k2
+fA/xbbfMZFIjBN884P3hviWHhMkNZRvRUve+vfa/pw0B9nUwOOgKnNE9zllzB/Nx
+gjDTAxQHIEyQrXEH0dliVAGlHTJrLUr3HYb8r0fafae1SC16egETGolFNfWdvdqn
+R057+Lj7xOUQ8TOyrqYDGW3I+ulOblBvZd1dVnvGBTmMQLDTYaVbxDL67muyeJse
+ohEbhnubpmcgXGhsUGxWxrvtlUmcrPhfTQz4+jpOxIIJkBCOQ+YLIOmRsyZid7gT
+70DiLuPmWaFwD4EAXfNCfiPUD1egSvAhoAhJjFgSW6+nRijS1ZpmVfI2rqSEjiD/
+rNUu78vQy6Dd10Vx0i09M4a+nquPGrK5WNyFpOeiv679esMk6A2aXJIOtvWbOvJA
+axaGG67kZIIG2F4Dd6ORGbRRqGpUCy17zW2czchJ3pEPBmtrV6zTacA+HSJvXOXx
+6zbolB6J2cEoIsDNrqy3rIL1uQk0r/SyLpDCn7LH0iOWOoaW/4As5Lz5qECVkD5S
+aur2a2xL+mEU+q/03SM34ZKhnf1U9wjzIgsduXFLDCGsh0nuthxzggs9bkqNzIRU
+V5YG6O3xsLtwdXhZ7BOj55irJ3TmmBw+ycAvlv6ix8waCPZ2wyOQunvXUHdybUq5
+cuSGzlvXO9Umnx9krlc8fmfu9Eifz0HiF1Q9ZSGroMIlBKyXKODUcLO2BoUeqE/X
+3GXAKcVI3fcq5SjpT7NRZkMY93jY5SAFpf90vZ6LV7mpkg4EsNp6/aHkDaOiJNs9
+J2vuXSTDIkOidA4ka6PUONTF2uWoZ0HVCnzGiegvp/3EvDvCwbDXetPfUjgcBKvM
+RuCFXeypRhkjBO5CHBTEfVN4NwjSiOnMXdwceynab2Z23G9NQ6MPwURnzX5kqp9f
+9vTNTL5WyP4PAjzZLhTT7Iuffl9f4bjpwwoZhbq2T903PNacQiooVD6/zD8BGck8
+tebqQ7sxfJux+NWAmD3Wy9KdEsqGvD+o11RBcr4ZaSylVPR4WrLCsFhAUBcCDcu5
+is8UufvQtNJAql7sdFmsOOtjPii0DIm/dKwZ9uwnWlZat4x0X/oZpjdKvCgK3qFC
+GpuKOQxZ6HEHyeh1Js7urEoQ8ku6d97k7/15VVX5IfVXUg/xwF8SiZ/F1EmtlYlL
+Dp5fQNfafBIRzvhKuNyKKQpvF8mZjL38ZYFlfVNJJT8jbE3QEEMkMEQHGr4ze/Ct
+OZnKH3JWDSERV3wKVgqro7p2RgChQBYjeobjRT2gNCR+TkbSoiS5+n0V9zHgaD1g
+0kosuEa1p8HiZ+tAyL/ccVZiL1E/S8PErxUIba9iFP5/bnLRBQStNU6Xbtg9kJM0
+EVKQAGhz7f1rmXRDROcshnZM/Hl2UziRG8MpHo3sKlbNskzW3NaMAK5mgYGC1eAE
+ZStsX/CsVZLErODW/+HlUn1Rza3sqG6P21Rx6j20eFo6qleoTNFiI7uWplUVKpvX
+64OEK9JP6iwGPssrMlm87Z3HjUHKkji2Svrn4chxnpMEfB+a9d2dw6qQ1HL72qjI
+1Sh0e9/z6+ly9DlDQKWNrGV2trKKK0piWcSECfITLG/gDyLmZcoPgLDoca5e+4uk
+/CCAQ8SabqNF29ldQkXuBB0rIRYqKeb3Z0KQQ97EqAqDqKzrDGAg4J9s8H3j/z3s
+Sg2WuUIl/OBzrh4T8i2arjVI+Oveto3aGiaBPW9JgO2n9ODTXoujb1bd/JwZIhYl
+wNaRhfSxUd6yDkQDc+RJy9X1tJMpTDiZkixXE6ySXV85PW/HY01b9bz21MIVvoGk
+ItyDuj5ve7O2nw3Q9Px4h6T7ZPZKaBfOdclOQBu8Z4UWbpJXFrThQR5aAPzPARYQ
+Uj55DEdgFJBwA0ASdeg8psjJQuaSiQAsH+9O+V/9Hcp2ZdlC+LVivsdy+05HB4Mr
+c+CMVfcwqevOR7y17Lv8QcHDpPQtJMECNeH+wMAgvlX4sAh3dy6ZVbqG0kI7PvaO
+WN57V++/TpTRby5vsJkcRkz1p0kv6NcgWGNbqihtx15563AqhTOsu0+6HtbEEDNr
+6LW9rO+cdyfn/AgZhXuRnB5kmEMkl7bKfNFTBNRz9XkHoAW64vE/LHPj5nj41FQL
+FqT/tYvhZ8pnbTpIRVtWNcemuH3NK13vjMxbNZIj4Dnb8j+rcIVYkCye7oUHSTZz
+ztlEuBDl13kptwYYFYNXQeIvsartAR2XbNkXD1ax39g8sVsbwEjYW1N+5QoFbL+l
+6g2q1NWJlum5SWqs//zNikuB7yuJKmCOReT3xID+UGwxg/MNBDznVOUpFYa9+tb+
+i3OSF2LWtxnqtiDxR3HT1caeSmrAWJgfFrPHzeAutSyQU7PL+Kld8FI5gKaMQQsQ
+h8cWFM5BS2lH8f0Bpwiy6Wwj9xhatRLWF2vVj9rLo44j1AxYNuB1pHx5/h0RbY0l
+SeHGj4ahceEkYncJBaZzn/7epuvoXYeYu3KniY90ZB8A0tFV0xIyuL1Z9gYxNAO8
+KOIOzR7uB/Ncq9uIyHZvwd3ehlvH6s+0DX71AjiaJGZFXCnoR+rrHC3CzdrURsT0
+bY3qjzQ1godaudvm1tBBoMLTTyWRslHLARXzCbLhMme0u2RUUddz5XS9rGSbMvLM
+KWIubKtIyKQjWdlaBUPiuEnIdi3Ix1VsYkrHgqVHJpmsZUYDucPRQ0bxzMvAFJ16
+ZmxNnLv0L+mXMhXhFNGdGX4ytFqB8lnAvVGuSAqYBdRRBUzqwVH1V8KK7URlzySt
+L6g8gH3BaEqR4FQsdZdJdtcR/xnL35vlfqxhbr+0T7l2IGK65kP7zM7yPtNte+RM
+v/Lyldmouxwq9gFouT2jtiH4gm9jzXhfItdVlEOJxuLVtN/j/fc6+MJ4epQa/+QD
+2GWQfOzwoP3UD2m+3vuWDnvQzTQB+PoCtmswwVdY5rayKUazh7MdOpKLpjlPwGv1
+0DxSZOUVCQVNJf4ffGi84tJ5NTwTv3s2zW5kS6vV9G68Trn3PGSBhSuCYUby0OX1
+R4Owtj4y+0J+IBjm8W35OI1wQRfGCZdcWPuKIBy2LjoA33ADxvUbclHF42LfzJHq
+35z0iS0vJIi7m7dSZ6nVidkHXUtqZLFYuXScbHIDID0+C+9yhTx0+I3WyIDUXWWH
+hMQjl0XLh0BiMexRcO+vXHBVbO1bESekLVOS9ArZZz+LpigkQVPoXZcKocK++6lw
+pv0TH5MRkcalqdMu/eZtc0nGt93VKHIlVR9zLP4d9bO2kvcLdpYRntOhf6Kx+z5J
+pr1rsPNVLsXxng+njBdgPj3Houke1AJLEfxXo1chc4tBP8o7r8tCb+jsv5Z8/Jiy
+VYhM5VIgKMMhIm2ANVrH9VwhNm4ZuosIPkTQdMnWRWcwJKkhV7eiWI9Mv3wI+tSC
+pn+87GNnmuVexF+XYK0hcQfIislssWOEdcS3NsehtuauPw7ZxN3ff0BP85U1ICqq
+rc0hOihSseI1AySZ0TILp33kdOwqm64zX0gSFKfA0Z28znoBf1K/aRgl2LoMfs4b
+c+ZmtSUUVlEw4O222Wn3CT2P8fi4oIg8PBn1X7r9qvvj3BABPwT5c0fVjSUKmMIQ
+/kQjIMUc1j4+PWUIa6/iC8BjBWDraB4okIYUyte3f8uSuNOdjgNZjL4tj5XKDW5t
+whVlYnYDQ7J3I74fsI7Iwzzr9brznpKtUAPKChYMBeLEaHDQ9izec5SAZcg8Xz2z
+JSI5axK+ljYFzBc0DIYtv5XxHjslPH1W6Neg3r5K8ALito6OUusYLhPDB214pkeE
+WJcNI7abtmu0DCkmnXqIjxDnA3a6UZi+YiWTzu5kRF/+Ahtvq3+chFqW8AgD1X0o
+GSznfOxEEFjAJi/huzf1eQNq/Airl7jdFwyJODGOPsKVc/RBd4VjWGuUbPM0tkNM
+2lta1CGgvwfRDPnaWXXzqirS3W6F/FiICconH4lfwXvxM/s24JQTBbIOkSu8jk9F
+IP/PiZLZxVNiHq4mRW3UW1HDe690vGkH3FZQLs2dIOaBE9810/o66/eFJWsIKH+N
+5CHs8EhtIH4Gv7KyJRP2p0qQkwGLajDGmr4iLVaXevYOYjHi4YHDJwLi67Gqdn6W
+ufdyK1aNnyF754THZ5sa1hzdvD6YabV5EBEXim5AVujbH93FWJlpAWQKPX7t3Fkr
+ub7Dmd21L64tlng+WTmm98oVHth+kB0JMuxwY+b2PVAOSiQukJCBcyLB64YTa3Ug
+j6UlCCa3FTah7xPY8lyZzxNUFOXTGIbUU9uRhGvyTW466fYw0JPenJ9QKxjqbns8
+KvXgwOuA1MixwLPVcsQ8SLzmQFftKYD/t8OtZoSjwEDMEi+yyGGw0XKL/99Qjpaw
+ZNvG8JULUwGKlNLVroWk0Co0h8xf7NUMiIN8SZF4QorvBkWgw12peeQvR4ftI3TH
+/rVHbqbsFDrEfTcwjtmdFLlnsi4zaQpkhBV1x81/RjQX94xLt2Gmtr+wSGskM0Dj
+WAdHNsgkGhN1CmKHkylPOBFlSN33LiZ5m1IFdii1j9yTzbqgc04XWyi7q6UybKU5
+/3KTRgW5agVz0PIQEc3ebTPgPbF1zFYtn8+AjO5xQr9YpYiAogzUOD0fbZH7odKz
+J5fz4aoZqB8DZc1mPlrJkaLbtjG0+dkA1yDPuyrwHs3TDoTSP6STntt3UZuaWllA
+O497eRb9FmoBFJuCwcsyBjSzi1ig1WGm3l2NGcy9Ql30RsS8hP784GvuDwh6Dd6s
+//cCMLeSlIFqIgJh0Cc9Cc//fn1zAw+NnQzsQTE/fRDglkSmSFZigi6L3MO+8A5T
+VZx68DJjoqhi2rNVF4M0AFCUOCdfs9pDGb9wcpEsR4CFUV9f1ox8P9RUrCBxqGaC
+X4p+t1Zn/gufyMRd+govtIcq9juLSHMpcRsGGiVRN7drmBDfs/i/0iOMZIo/jPd6
+BEGPIW6+V12x1ceRJyJ5B6BlGqjBq7Z1wl77nsYVNyBJxNB/wGiMx+5ePM9D93Ai
++J1pFdV6JOXLnzR/Qylvd/Rzwl+LNdsClldcpO0/r/cuzRYRXyZOdrreLPz6TG5f
+IgcuH9dbgW1uCD2WEFcny2so3MlliAhlt8ag9O8m72YndZI6oO8mGA0cNeuWYe7N
+cGVXdU+O01f8mjIjIWFXXn0WcNsHnfyW/JTnFmivYz3i+PMGWoh8NrVE6u9LTgJ4
+MQx/mBPSfgPnCVd6gc7e+k+7er6ElFtuWLjyFfO/4LeNBSVVDKPsSq3v5mkVwy35
+sXor9oI4F/Z+nfycaOQgYKQwXPRapeTCUM/Sdcx3SuG29fPvlgq00Z9QWe2ryI+p
+600PTlh8SZGWaspFmNG8VV8gF5pdE0ndklODE8XkfEqa6ygt7YBgqK8I/BUPSPNV
+nKeJQYTUWIJRJbzcr5tfaI8tIXhcY2bI66tKvjASkS1uDVWLwB/N7NMWQ21XHokJ
+ywj0l+mC/wG+J2RnJ3/eaTuUPbcf9ocohqhSH6juGnFWTMK7QjWMw4WW+j4iId91
+Nd/8Lv2xGqUCbrc3skH4z7IBjjdCVItsR+YshtQjyzAkvG3TXsCnNYAR4KgvE2dC
+MRUEbf2iq24fYXlyfwwqr5Lrgw5cB1kFOc3H3qVK0vMAn+iaIsVI2x7oLQlkYJl/
+5OIgDxWmTiK+1CerP3nCjKqvvvBQ8ENEsrDK6Z8SXu/A49CcKMLKQRiSvAsdb6bP
+WOsAtquXr+57lZarbMAP0DQMvvWKjRuPuFtELUfCIyAkxF/NQwZujN4T5N8L76cl
+1WADSwGZ6zNlqb6BmvnTRm+Io8DwO8ihO7FTac6zziAh73Z+BMmtTEWL91biapCi
+gNXq0qteWJ25++JkUJ9aK4k+1/tAkdd3ZIDN9k/09+5ZgDj3EI4P2lMFkpRneXr6
+EnYBcsJxzVPaaH4o0Iq0n4bJGZoMp1LUdDstE5FHrgEQABAXtdRQtxRrC42C46GL
+XU+wpxDKvnfqgx9fE21z0thUCSWT9u9PCmtS6cJt37OAuZWcg7URuKzON9InlG+b
+92pMs1fb/OAzFB+LCnDJn/VAUlxoED0+uVAeE5ywbD9qkwogeN7rTGJ7ew0okw8H
++cGR+kwPVQXXnTIn4AZRafRXrKNsA2tFqPNafyUzYY1Thj+PmdtOk8M3avy+G7Gp
+nDXwx8w5aE78qSnrdi8PFr16nbq/p6mPVU/crlZ9Efr4CFxNZO6E71tuKVKlRA+S
+/TPzlVqjSyTOtyd4WrWsQsApZ1sQPmaAQD64d8YQ4oUsuJuguk5uWeSqtJn5GNAV
+SZtlDmODoKGquZDKKIQISLLaCXO5D0v23xm6yg95/HJNdt4EV/xm9adz9XViUtCV
+b53nqvMIdqFDlD6auoXJsoqlI9iLdV6Y3vBjCEuK7BPmcPRzJelWmIY+l6Lz4jJD
+mkoqea1mgYopWxCRSiqIZ6mQR70YbTXclL8QrVncaYl3msBAlUK0iNkx/FcwsEh2
+mxjA/YrISCkaYs4EleykIXCSWqPqSyAk3vGKveAdlA5P8KFcOxERcHP1X4Rayh6J
+RdCbceR5XDp+GT9zBHPZWA3XOISAc16BNqSWGRHBN8y57dBEQZVWmjcJ/DII+LRc
+VKTiyMzJitqvPOR7sNl0nPUeDEczNoXkqCTmmAt7b3jv1w76CTQNoitDdKFyUoWy
+Bg481cw0WsM/S7TgRDFCbbe1gAVP6yrpPOnRkMFEo3mbkBz/n5PcqIvob/ERbb8E
+RzZisrXR7sVJFetncL8Ucl6pYs8OVYKZMmr8U9EBBFTnIeQ58qadOcIjX0eP9Tnq
+XNOoqh7DzTx7Dd+FDbe+jZcA91EC0I3YidQN1tpqifJ+eIejYW/TZsSc3jzjprj2
+M3C/z/a/C4ed/0eAUt1dEQuVzJv7gNble0a1Rj/+AEDOZGftvjmvVvW9ojxQf6Rz
+BBEcgVtK5hOIHuiPcpbpZZWQLOK0PGASYM0PH1jJ6poEzNrK0y/ougQS+9g5EAnG
+67TTt76PC98GLDgwfZ3DwYDuKzCqtvlMtQFNvXZDJKjyjA+oLo6+Pb5vtNfgkmXF
+oYsiNIxGgcYr7fsGVFjvppln+EHxKvUxy7smS5+eWCKjXdNzQYL3XZqt0zS0H2ZX
+4jEfY0/Qk/I5hVg6btFhqhGD3aMTfykXM/lO3pbRgDkgA3/sz57BhS5SqIemQvgu
+RDOANG7vq5ywCJgz5uK1pLcrbY+nXtV4JpNnayaPfyLFj2nj6CPnp9ur/T2/P/9S
+wwYln50rZUJHk8Cb5ojpMcuUZkklSvdc9h5HGM59Js7CUtijNn6VuLbICRj8yw6C
+8+qGeFD32IbNXpIg0uvNKT9Q1OHr7JKNL2Dc4f7I5rPTp1cMP95O7HySnqWPeMsX
+kBGly2xnPLZFpPAwIl2wARScuaJhVGqnvwQ/+1uk3wHP8QDP9qQV3tgRxA7o14J8
+N2yB0YToWeMPhp5Cz7v1fzlxhTi44QE4k6qcx85Nq0Uc1PDn24lOZv5iXxKHwsxL
+z0E8o4iZtT1kt3SnwXXbUJKiBqMumsuviOu45Jx9KvJK4WtX1yRbabgb4dp5At41
+futX9F4cANi0Xhj//ERc8yJ9OKtPqQvyWq3orO6bY3c7dhaVmI2MruxsKkmbUOC8
+jiCsgvilKMz8PaWNtMPL1gygST30ROkpIqu3ZzGb8mGXWEy0rGuTpxBK72Wi5bZq
+74qX+fAx4WC8CIdCxXbdaoqXFCMvv77Mojtg44aosuKtZrLhNyGEeNSu089CtdGo
+LPEezbfxOzKYHOEsgr6MKAZNDSE9hWWs9mQvVJUeqRWa/IOXVvUXivj7nqF2156g
+b5AEZ3LyhgkRvGrz86JutzfrsTiU36GA2/BMfP5RHY3qhsvnvCu6FSRFfyMWf14F
+vQfz1OiI/uao2jdtGySo267FOyz8QxAlkYSw8twgT1SDdr7hEPXSXve75SZ15Ern
+FAWdNNd5FRscRraXAEZDEl3nOZ/GX5VyqKE+FyCIKh/CyBTtvbB4//BScdCgslCK
+Zo7fHuIaIV0dVuW5MxuUQIi1Y+3NFe1R9Cg5gWUr4ahhqSgxEwvaea1hinN0nvon
+dcyicVXzz8UpcM9IPZndtI5w5/HbjHq1lRnBja7I8ficX0dFEcvUdToagC5SAO28
+zQ7paOHWdoIFHvwP+/67HBHUDz9btzJh1jxcB4V1ZrWbYsTg3LFT1CLddiIw5FoU
+3Fl82ihGZRRQtF71j1bywRWgrZJbgjmi08aKz+RGCuHruZkPlZZMJDmtdnH7xi0A
+xb8rkJAlEwUcIYWv1efqKGEfGCWpm1CfHXvI9+Y/Qja2ZtirrYR7vQIAxVsGYBzO
+qNP9gGxA+jTxNly+cOTRYVV20onX+rCSol241TCJRK+zhVIuwr1RWzwNiSZV3wEW
+K69ik8CTEVmiLcDSOAgl26E18hveQJ9JRAQ059SJNn0SZms4lfY2DLm8O/eFBS67
+DTBA3D4gy1bF2G4NS6H8bUrUAd5UvNpo9qczGq2+XC54CcqorL+AONWyBaICs/T5
+XZYehsP5qwlxJCTl3RwYImJRnthsBBW4wTrd9kIPdr5odc2Re+qnoYSBtJOVlc5u
+2TXSV1rr/VaBLTGDkkkkpS5CBr4+Hi5PC2XRK9CYBtt6F586LMz8xSnWqU7Fa4jk
+Cz0DsBvKpUM6rwUUL3SHrDkUuibY72C7un602/0mMLyc8PKLa5XXgHdsh4MZbMSX
+pcLJR+1qcM1csTJrJtCbSX5Hyu3wI+9TfpH6jhzCi4ef0QiesiyDoeJgjFa8FzrK
+Iwcoq+ZqOcS2bw4nqULvzrKlEdZP/lwFc15Ns+S+JLeMZt6Oor5QjKLA9p7fWw8c
+TQE6Wyd80qsT/lwBowKIqiK6dR8QnCYi907Cuqe20Ps7qiORoESMYtp8rA+0DKNX
+RoeYK80WluejcYWx7dvKGkUrG5rdFEPV79WGpMdU+E/k+fz678SHwlEQZEgoqfip
+0UeOJgBbedekeIq62p7vZInSnKF1WBhF6gsNxWz7GmTokNNDPup4QlI++L4Z/cCE
+H5ncdGXNfYqMcNUrvnGKwvIdw6sxqdTIaWkCLB9SWgUPD1D7SC30B/lInkyL0SH+
+L1dwwOa/h+tqzO0PwEOUGxxfu4am4MGzUUXosRXcZBsUCzowmqVF7AtoJAcwUpDP
+H9BTVwDcU8yuPyAMCGZxts2Mm0icT82eDuiJjzL43UFphErn/qK5cy9bkMVUFcb5
+L7p1JIURvSDMwifNg2gSV8ldldLGtViKn284wtg6nMxADp+umI6IUJTluwJb2mX0
+6Hfa6TspEyL5DKFv4u/XRRmfDrxYJ6sJGw/PNoW75DQf8vnS2BBrsuAIEgr+pz4l
+2UqxdUXoa4chaysvo4OHUi2ZZz7hq2+1rXJCPGD875eeMIvOcIByQaQaRlLZFCsW
+ODLN/mmMhttsbBlkQs2vPU11XzKELmA7Igcm2E5qVXdPlH/BjJN1xl10j7hEZSoZ
+whdJYURHnXx0/cXEr97R6WuFnmlGArrDsr9wzfhD7ZTt/zv9GLzoxLshX93nZp3J
+lp3Q6ME0YRwm/Zjz4JB0jxxxe1pADhvk6DYThDX2esv4C2J9CoSbmDrwWcR8c1Fk
+aQbpuRpCsV3Gja+GDP43+yMBp2EScUdy7vY1A+RQgFYrfY/AFFjXzFf6Kcl82Yf9
+eGtn0ASZCcSHRqUcm5KqGBrsssAiESGT51jbZsTvly0Dfgo402qfEWmMe6P5ZLUp
+ekFacm1eR9r5NV9pdO+BaGw55nKVfigfNPBROFo0HwqAGtGozWnOJoNUUjtiUdAh
+7KQK1K+JzBjoO1RTDI/UA2ALVF2xILkXEABmsO6g2oGmklERkKBs0NkPsJoToC9P
+kliq/TSC/oggK8HzVIA6R1cGoaM05ThbHwd0E2SY8w8AQGAbqLSC8iJ97mG3QhC1
+Rqi1XDvQkHWRxjynEr8CDeekse5O6NnFU9B7vciXYe0BQS3VSFBXtTFlT71+nIaF
+fxRxzUw8spFYHeXIO5j3h5VqvPNBiWYDwmYgTjqallMD/oa3Vr8Do6hflTyw9kKt
+lTS1Im5pVfT4ryY150uPKbVYXyk8Lw0HZLRIynQJ11iyopEAsBeiFF/RSNIC4h20
+K0HSlEwdcC4u10YaR4W8A2wBa2POH+F5Gj/foOCoa19YlO4VDAKBBc5ANkeljbla
+kC97jw4tlTcdaSSRTqGG59tnKSkVy74LXFGpoy9MHc76ZH/5FeL+Zy1+8BG+hwBw
+zrMszmt+1NJcWa9kqADWNKluxxUB/lKkdMPbnGZx4Qv6rAMOfJwntSToJeUt0Y/3
+ZjOW7vjD0Ra3f50yWJcKJbAJDde/mkC7H+MyOKztf8XMYWh+eGL7eyJmEOVueAsz
+iOcVkZrlZU1jw8IVnaZz5U7PbTCrlUcGtbPFKrF64smIEgk5OkM7SRkQPUP1uVN2
+n0wFfYy8+KqktMqQhkaYeUbAodN3c3ILIWD5I1vwDWrcNAmjsQJ7c+LZrLAHMqia
+hEsI92IsCN4qBOiLI+1HUqOplluUhf36fRchOhU6StR0I68EbIlT3VI00hGbUDgY
+S8rdrtC6qIWdXoPFHJziIwUz+LAgQ0KkrK+ezCBwkCS+u79lU/BLHlhoZW2GqCY6
+5jMx1W+jqVcpFjgMr3QYIp8jeVMM7YccjlQnMwtVNCTII5Z2nsITgHomuvkJ98H2
+UPZ3+otwfc9oLibefECLfceUUB7PS5lK9KV7qlBuqeSHujkGw17bh2rMq89pPk/D
+46jotoqv0Ahh2rjM6zadnL3DkzefbND6PBuw6QpxiNAh1xbqMoM8LYPSEX5D0r+e
+iYZOrcoCmGQ2M19EDpEqdRvLQ63216fU2aBfYoTt6YgIE3AufUzggTAu659nAJ+9
+YS9Kzr0J9lQ3mdK5nZiVrHlYd8YeoUS5BPYBMVU5ARK/EGKfhO0KnwoIEjdjGsOm
+LKictHM6ffssTPWmdL1yDNLhn9pn94+RRpxn+ArrghHwukxy50iLkzQe2vgL7r0o
+U2V1zFa1BCWNo8NeJCPGLtTCgPflrXOmmvaepAQ14ZUnUuH+gpga0s3i4zRlg/13
+mvqA1C/qH6VRgbAe8etdyym+2wvrH704x+2q109K1u8GAcWlZ8RsnPTzD+iI3qzm
+OxePzP2A/oQiKvwuGjSov6DK0My3IlO3MumK0vTnLmOHZxw1AbrbFHoC3051cRaT
+FbF6et7Iai4QNl6yLC0/oLqjAfjksWZTdKufKDuewVDQEEuGRWHyc6sNYNXNqaHO
+QfS4Ii5Cir+cHr/2vJsi68MmQi8Unzx1TN3RSdBkejG+ky2GN6+kX4HJji4lWT9M
+vN7U1kbG/xwm+3gbjNdul++QSHwfJS93L8UWXc3irNztM5WPcKPsvnWHf2LC9ppg
+k0Jc5yVv7+mB2JLVBmoTHzXia4Vz5EJK3g7pq6gkYzjuvdSmi0JG8vSxMwjaQcQx
+r13Igap9vQR4sMTT8G4rxWh7Q6oNw5djm5X3m8eyieEgqiiS7vbs+ZAJGJJqxzjC
+HjxEv6L9Zah/CFqGpOuiCpeTkB0S1Kgx+ex2YNv4Zdsar0WKqwuERfP7o2J16qXB
+4QxI8/LLSIsp0OhFxZkRvUMHxlpfAhxwQC4qthaDqsvunR/gDyPPeJu1bxsEYHwU
+uRQ5RPsLRx5FQbu/OPctDxR0YdZ2CM0RiGWx6FTOoHdAwJlto8gwer6CDNhzMuMO
+QS2UhIbBHG7+Rmid4r7AyMNKoiinxvLcpxBYiubV1ERxQ1wWHjNE0bCff2gUZ3o/
+gYrL4RmndVV1i/BSetu6cPx4kohA+ddcsKAUDpe+pg8AlZ0w3WSveYvxY/RBCEHa
+hrf9YQmgLAPdW1PhtUtQ23MUXYA96hUfEdOsfkmw8StV2ylBZViJ861yCj5m6vam
+jdT/DWMwaTSj/lQJAs8xVELW5k8a4z0mcqYI9HG+5hu44pvekvmFskVplRdwZm9p
+DjOgISSq1rmoH4RaSpkMY0cN9VHDSZkyVKuPdVrZLWzsX9D1RVXUD6q3mmNcdCu1
+tcYqAeyJrO7IPhqezH3F5Xr7zqtby+/2Ndgj6CwbHlR/h36/N2gQ0K9Q9Lq8QF5h
+ajxHmwV9jztL2K+ZCJNeNP8nakqRn16IFzcsBxjQ4Ll1MJ/U4/YhN0rGYLvwJTTG
+b8lRakYHG9C69d3Jat22hdV/3vxC5wQV2iICdaSlhlDBxYAOPDvztnxj5s5hPBq3
+4mlXJSAjK6cpClh5icul1gd3xcnDgztfOHIhbLhszgffCbBcFeSi7e8Qg4VOuDK3
+YqrejNTikIUAo5zd2iETNtjoUVliG90dl9qKC3q4NOQEFR/FfXBKUMXnC1b2Qy7l
+kutEOWyvrWfl6AL+Nb8Q8Ni71OdvmzKhyxFeD2ICNUrxDIsDvZsvN8pFHTUgfVxc
+vqbj0IL7BboFVI3skJGJzqLGOAqc82pzRsEwrxOrtXMe9rGwN3aenTDlwGv7cyxF
+l11itZ/Jc5lUV2879epkjbUXiP8aQlkJuEHLIoLT8vnmXv1L0X1aweJfmcArC9js
+55vdr+1zkoVmjKptRPAm+t4FsNK0jU+NiaDHwAOlIjbJckc4eCc0cSX0R11qmwir
+O7FpgnksSaVYMc1Awr1ezJa2ksrvGAW+O2x2OfwqsQ/2dxiUt6OHzD57oAp5RtEw
+4kSh/lrAhCm0EKS3N6meKOXKqkCZV+dU0GV28GM47QfQ60+SkuyQXM5JRVMVEDN0
+qlDh1B/g0oC6D+3YMIydi8nfjQ3+1Pw8iBT9aPjVMBIvnJEUkMRw4lSF670Q4BHZ
+b5sLHQC51QZYfNUrvdgT5v2SGUq0ERbrm4clCT7fKfErPB4npJqGqafuNO5vI95l
+1QfQF20jdL1M0YAi68X/sJCVBEtpQzzD8KrcJrSPjAIpczAF9UGLjYv8GiYoOSyp
+zu0FMyNqshVe+76QszK1BG1r7UyWAUh1xyiX3wC91NRrTlDy+G4pKKyEIOl93mrG
+6e4kw7V/WUqjS+IsKTOVXHwttEpTu7w8dlXxn0Mk1yiWllxQjeJoCEKHXdA+dFzF
+OG/x7RREHTEFkJLNskQz6oKf7Zjv6r6Z3sQ6RYs72VK13Af9VZOKedEevouqgPdG
+E8uZu8ftB86jgLCeTCXrcRWrqeWaFyybD3vd19aCoxlgjZS3uL+GysD/Qt7IsEGX
+TMX8Fa0zQXWOX2dl2x1q8tTpxmlKP21rdfVJ0sr6F++QVr872eA7EItsWWdDStvy
+hq+ySYedj3ZWB65YD0fwOocq4yTVEtQAfIucIazXo/4KN/3jQw/Ui5BmHkw1cfre
++Vxw81CnQT2vBaNgOws6wGev/YkcHrbwoKJzoyJTasiylIHNPKFAK1VJ17/NZWZ5
+sEdod576quT59WNg8RczGF1KVZN0uP2KgE2B07tGv5FoFXB4LfiaQNhJKbDDGzwM
+Jf9Ma40dwXP0QmtlKBCCj4Qb/I7RjNl2FSa5jTFP17Qp3wuS66h+MjpIgh/H7sAs
+p2672d2rnqhMtWdvM8ItzrWfTi3O3dUgV0JZyD2geA29TW/Dwqo8WwpYsuifr6yv
+8g2Vtbq/asA64CP0cVgIV/UZOfaNLuLx6gRH4DqxcSTZ118mG0/lazIu98zyYDWD
+NZPxW8O4oJCAZcVk8DR39gddq/YYlS5ys7cdKZG0eM87DdEmmvvPfB7dZJzNJHVs
+KxOIfFLyD3o3BNyRdJqO/+b2796Qy8fqUvJjq4nchf6AjPwDxY0sizDnvBQLrTLm
+MDNB41n+MfnA4HvchsIJ9EibyzOe5Jwyp/zXD98QbxrpOrIaStph+T2XKvXGmmFQ
+U4IL5j6oz/eoc+OcTnyLwek8SRSpy5rd3J/txR5z3Fo9yw+UTlPKT/IXQAOfzi4g
+iDjLQGEzn3AX6vlgZ1rbU1RnDiy8BRq/TSP9ZBsNFfkfxFznUzNjAA6AXpD2Xvwa
+QPxXRM0DTMCKZzBk3JvwBi20pS+xuHfHdBz2rUieU9BgXQZxHjxQp+DFtBMGhN6T
+EwD/RwlYsWBpQslAUL9NBhoYDQ9pGyvhZGeD76cKae52c/dZI3ucCTqYOKdVzipq
+7XNZVxfVCzcR3S8JmQr+qSXX/6sWCzkITWi1+8fekCK5HcZISPzh7dkUCdwu/r6F
+rYDkU2LHoDIagm0yMBUmzEqs0bQZVDyX00K+BZ+HJJxFl9rXLt4kz4Xl3jDKXBll
+NINYX1Yrj9Zzk6PdBF2qumdX3hqUYstuAfYwdaudmdMGqdutoXwC2rpONSk0WdsK
+yEWLxfcQprfBsN9kYdF2QhwaGd2BhiP9sV4cAkcHNMb8SpBCYaDo6j/lbaBvUqhn
+RdKhhaBtH6XpnePTLJTBATVQZsvVnY8PTa+ckP6vmsovK6NZLHdeOCR7Zs8LHLCF
+xSqOa3Q7M/Z/zbrmjoFVPJ1LQdLWXKID0erR/BTIw4TEbAWA9Dqqc9XmXS54uxwW
+fDC167rH7SNK9JUKkHFZKgZxUk2mgBp3krma3wSvGUmxCa3w0TghZ//30G3L/bAR
+fn8EpzjP3Do4bt9oDjmYnLTW+/TEOSxjLSHzB93fnI0EKWtiZg0GiOGTB2Iw0RvF
+bAu1rPMlq6WTmrlg+Fuw2uKuCk8Y6OyGyaRO04QVb8TZ0JBGp/b4jX+T4Zi4U/wC
+lc14eJiR1+i8DZizMz7qJV5kJCwLOONWzBxds7yjVfY7ey6wnhtblFFznnUjpuhs
+qwpudohMbbtsicLcLxjrkQLoG8MEpgQtJAS5rCxiKVTZe+JwSI9kTYv1ssAAjgJs
+VodpQDHKt+DND0eeBG14net4pRSI4ZQahuJ95Utrq/QWlvptvV0R2/i4uanNdNTz
+dYaE2uffs9Kzs5kiT7JpBqVMX4uQznPhU4ZweJnZtcW5TBv1tX1bGAJ3b4aSpOC1
+el+Z0/qk5Z+S+bNtMMa8I2Lg5xcIcAovOHY6dl1azyFsAaw+qmvKsKWwFv10k1ls
+nyVDsH8zvdA7ts3nLRsYwiXmK5eA9n21WRB253oHh3Ft2WfP4H/HM8xo8te3lnTD
+TaSVn0qg4tvFbiescWIG/e/qR+De18vm41J+WFdO0bTuqmsuSVaCyu4hnrHgO5LM
+IOTr2H4n6sAAmO9L4dG3sA0QoU+1k69yUrH9ReP2c/M3GV2MlA0g3zwYzi1H/uAQ
+oR+o1yG+U2Dq16qEM2gXN1NIcgjeYRtlG81qGWXUHkDHWXaG6GYF4UOr4EboL1UP
+noLX2R3xVji3Vkc2u+vo3DOdkmAq+NgsuaRI8VkxgYr8oVeBEi2BlrpucGCtt8IB
+vcW6eyFwL8QlzLCHbL80VsJ5LwYaAEEM96IEHsQn7RiW6H9bVzhKI/UnvhItMETP
+zixueiKUxSctJeQnuacgGFRXHh2qxymwjkayLv+efsEK42J3DtQsEXIvqY5ri4dn
+cU+RaQOdx9fLo9xy2Nv7p5x0MOP1Ntib17hXg3mrpc7cgTjXT6G3xTk6FTCA8ns8
+84wNdesXx2luk827ghkXYz4QuEo9sdocFvouV6+WEPHkgycKcadlIdHyglA1h/nC
+JbGvsuZHmvpQMipqSUQB+eVtQ1stWSwZdwL7DubLZjhyh4jCtXmoA/Dhybuci4gP
+RJY0Ef41f1Vir+yrLoXAp0tfHSqtex8VxAn3ZH6qpXJLpMnQghLp9LEhVtECywPz
+7/W2znRM8JgiysapSCDATvzu93YFswah7z7ZtnXY4ssdUNtt7LuGcHw6JqvFeFd4
+T9s2YMH+QBlIT3Q4BlxMuBLV0V2h2CQLODS9Afw+TuFbdY1gT7hIcH/S4X+D8xgM
+DMV26hbKCdHCFB83FNyvTtmFN709pd7ieIZvXqptMEAUehqdRBYyqHeavGGyhfG6
+mSYfHO8IikFaiAPRKRRP4podFYn/kfWM/5eNOHzGKp80ovUaP6VVz0Zgie25GJry
+KaJ5xvSBn+sPPdRaYt1XmTYqvk68hX+MQKG/Vk+xCGs1jZ8vGEYgsooijl3z0Dpo
+0LfZhioG3ov+WihjTR26zXPQ3ZVlrjKzy62kenD+S87NFYBlLSwfFTvmC633os9L
+Nw47z0mut2PW313cBEFGWY4r44zZNheBSyQK3kFuVXXOXw7tDVOujlboVs4AwHd7
+fgiWThCIRpwE1vOX5VaKodw0aQuRdykDZhzGuEKbi+02ZSTMgYug+0EBcZxakJqp
+QA6YE6VuvSvjNcN66luLO6JJuS43KoxS/IBb5XcQKxwjumxc6UEbxH8+dvB9N9CW
+mGQ16kVzzF0W626sPRwD5O2R9GWmacoIHVx2n38BJD8j7pFt5Rek6dFciHb+wa6f
+g5tDf0aqGejvwxBWqhmR3Ci5gsTVnOFlZh4kY8LjSttqGdNSxy/A0kNe2Nv55k8m
+OyuS7RStIGUV8/DIhduOFg7vVmdWvB/7WQK6ZSeF1as0DxO6A3HflKMWl+0ETLyS
+w2pKbizGpzqI9IPzZ/WuDy7SHtAToeR6XmrFrNtROuzkCcCppELSxqQCEEpNDOwc
+fgfcIwXWT+nlDqAkZycVkjxGk/4Zn/CyObqs7Sh6RetQCR1gfTlex8SePD1wNTrc
+gdRx/aoRn2JKEMGkus2HEuIB3Yveaf5cfSCYKxakjvRDZ0ijYu62tMGDx197soJM
++99kKjvRkXo5ZMURyDmun3mO2LWLtkhgJS2qlY8m6zRY8cotROICB06xx+dVlGhS
+B2gH8Sq1EuVdtaEGhWkXSDCB6zIAvfsR5OGWMi5TJZnQT6J8Q5YfXH2kgu5wp55n
+TBBNyJeHGuoPQe0tmPMcnxgrDZTdfabKhuICwwansEltFiwjWkxDrQUSuD8Yp1le
+5B18ZIH8H2ic4zQcIkAUFWUGkaJnLRQfN4nNr/ZYLJMVjL6lW3mPZZCuVKhv5eAK
+Wvh9iLYHGxIXNf1SM3KVdGRwbEHP2du8pkAE44pLuDrza5NGRhsdwHVHrcqqMtnx
+666jYeOlppSIxrc0x4SDiEHwD6vpsT3RdmZ4AGqXYIV1NTFzIb/yTmZy7Q8yAv5q
+O7EBagDx9dmoCZjs4rEsAVcbqDvvt24lLLFzb+yYxHng0qe6ebVBW3f+o9IVzGF8
+tWCXNeALPJENlah6rrZHS3qZjZ1V+CaXA+ima3NL5uNJ3yzBeiJ19xAMYBc4TNsZ
+yvYYOyjxkkqeoM8JaPL/MpUO0XFsWK+/bXRhj4zBSvXDZdgnV0sKan2rtqtOS2EJ
+eXkOay2xLpkeMvggpQlggSy4v/S3DU6a+mX9/BskrxUob1ViKPId3h195ZkWSnH3
+rqAK1NO694XOlsEfeVQsS0sKkZC54EZ4qnXe59YJ7CAmyb5HlRCSjSda/wumG21f
+s72kd0q/irdOGY4NYoV7nhostbehphq3cqr8GbW1PWKlOogYTbLsrosGh6z5GdwN
+WITkd04B4V+Kb+TIrxzkUxC69taI4EIpZ4ms8lMikqwyiuRfZTa3s6q4c+paAMKx
+MeWeEq9m2NFtPNpsLcreE9odicUrn8kkJQgEhvdewkoCvBcwHykYRbFEmP99rTSq
+6mueYMwTskenK5yvT4oZEn94gSkeC8iNaGCURZ7/0Tu/GgIVk2HYB6j9O5HAkL/h
+OrA29HISNAGN5vcF9mQ9egu6W9JyW21cynJZviiY+xQENK+fiGqcWUuEArY6L88T
+TDhNVZzRs3KU8HEa3CUVCXRyriNU+Exg4CzmGjrYf1cXo8I3o/RcPhFLice/nFyc
+yZgNksgZM2zR9sFx9Cj02luaaaShi/VUtvKwx5vulyQwHUaZAHaxYO9t7/WEgehY
+z5raRbh92bpWzNqeKVbosCicqWFPHM9Xbbj2vJdkfFn7xlZdxzEjbeHJUAepkhSL
+gtgNpxuZJKzw/Eoy3h7XoCj69lVNJnRZjAlnllQOcn66ZmiO4b4ZxDfaQD/VyTmW
+/8nx7PiSVm/sCReYUYt9I2rhefnlTZgJ1Q3c0umR8iR/Ec77zB3USHocvzRWEiEN
+nLGxmHkb5Gvwo23vPCEmTH3p6mrGlVrsRlXDZK8saj2AG5AnDn3VFIz/uROGgUt9
+3Xj3cxL599UjnXTkB/heKjKksWDXNBdVZiopvBsNN/Q9tJBaEJcKq22nEB/R7sQY
+YoV+UNQJaZFlTPla1c3PPqLxegyhRLcm15oiZU+W9NN5SR1ghqcHGsoWvcwqMLkf
+KtxyA6SNhgddQsQD4yVlOCZOPRHp9FohnuV63KQZC1vRHhvd20zjDlW7cOfl9t8F
+JHAJbsFTvpYzHnKa/xAQhVTAlBMMq4ZeJveHEbAa4fnwo44nVY7I/9Zn5TL0fHmZ
+X6V6kd7t9Tnj8ZBODqGTGVCK1TxLQi3S4t+egjf7tuV4duOPU3tzGggPskfPt5Ih
+CQ+zxi93ZR9OSaXQEOe+IBvoaqunpx51y0oux5Z9iBefnDHJgksmgUTT2YUln0kb
+yjbJpeJZAmBAB1zT4/J4+20Mhocqtd8Cbr0h6DcdZqWGIsJAk2HMqpnmjjzmgyQq
+pXuJ5Kyql8CgCz+w2YufGbPyViObx8z8UcYB7Xadkx7Hd9C1pbDZH/ilm7DpQU9t
+AsCK+2t+vRfnnGsCWikNjBkIDi2mgvJrv2bUCQOn1yEiPdmUbxly9k6HZ942R9aI
+5336E/QtBRh32Vw+nWGAGOMvxh0AWnq2dUi+KIMjXE7M0sh+pJp1zHWDJbFj6mh9
+bGuTgXpgmAci6cijKKmbIsMHA1R6w/z4hgmvtlwuZSABK1mtnLRCz+Jacoh+BRn5
+CSbJkEybT2AkmDfp5cXxKkouk3W0rIHQ9pdLWYzm50CTnIbNl/c0sofujVoGZDaw
+TEt3tAAOCIfzAVvP8Hs7uJDqXe3WfY7MBhDIYsvIEK7pSmRbNNHG5/FESElU8Zyj
+NMRoDJa2HiUv9gbVcU+sVPKo4LJY5s7Kqi1qTXy+wJIe2hNngNkwJlmhHJ86huWi
+432B/iVXHxwXgT7E7yWCRzOMkdwO4kEYuIdo/M/cqjNc+B80sONHZZR/9LC6sUS1
+PceVfAmiu7vH8reJDPyDmoH7MG1mFjUUNdFwUIp9GU786X/2utLOQ0naPKhHsuPj
+h8Bj5zcnSLtUaqEXhQErGyV9AqtsFNgqm4NB8pQRfDdPzQBKRizqkDCwqguqxSLB
+z6UlJCixgb/hsbhdcZ7kw5baIc7Q/vqgPU2v2QIp+pfE6hkTFObwIu2KH5xHSVlm
+qd302e39M8NGQY3DdWj/HXr3KHAepbX8N/mHchsipmjeTjSMvAZN3sMFCSX671V5
+cbLQSEt8NKd8MexySAeLAGGwlKC7IbIuS3YaxANrcLrCDCRu+B/8WAD96U26A4Jx
+EiGF1XhD1oMdR6duB4NZvM4XMdfuR3SC2RnlMeQKKQx+CPWg0bNwxwHxmZxJD5gM
++iuy5QfAY6y+ZZDyPD9apTiiewWslRuKFFthcBcyrhCv6ltNfbFb9n/zg7JqLNQT
+oJz6XuN002XEdt0GKJ1qHO8WSwnd7iTnrbjP6HbgkLqJ3dE6CJtZjhAezcGAi6eB
+1ba3w9iOuUMCX/mPM5hj/7DGnWqTMVTIl1okxJsgI+aAdYAKybSS7fP+fqV4GGoy
+yXt1p1mGxijnHGh6d/7MyAdg2DSnVW8pbxXklioc+wrFxjQOpvhyMKbcowykrSPZ
+1WYRtIoKdoryOjqQ4OaXHzaNyy3KK26M01fD6uJtMOQAkWRhsky4jKEQyiDmg++W
+jLV8F6Wi8oI1BvPpKWf0OBWfmZOsZVfW/sMN9LhI7s9NUUK9d6XzSdCZYHZZGtk1
+YRBbdEPrSS0oaHpTcfhMim8oskzqYqiSGNmRYHAMbY4GtxbW6Wyh3qb2rhc/EXhw
+YZ6uTSYi9Z6bkS4tRVbn6I6CMJNJa4dmSjWEWoX1OZUyHPy3rN4Cm4E1KuaqkFbE
+gCnkl4NNgV0XX7FAxT4RZ7avh/ny1RClgm5rVUhrNTzOo11LBP6ZAgK3u05upbB9
+JPvpa+3gE6FJEaDYEIDQfNIy5qRJgECVFoRvPslyrXgVVqJg0e9gAkv0SJ65VCnH
+rTp2mgBL97v73tyHzyT5zTMyv6kggnMrRj9xX+cOdawSpD9nuZtTulIqVAQcL97N
+FBtDHAK5yVgESj7wOevJUdxpjc8Sx2n9P+U0FAPokZayBhbzy1yzcW3pChAPn/gV
+57jfQ/DHoSeiQkaZkS59NjYHe9kwzgVIKGmFeYD/Tgv+XEMEvpxBSmKS3Wp5+M9B
+PEl4JSXxP6Sv4pLa6gWNLvRhdjaUD8AgMVEoKNwDq71XzOZ5A8xsrrQXQny1bSys
+ZvJRxFnihE2dVFmSJWhC4+zdfG0PkpdF12YzntP8w/zIrKPAOfD+8rAK6PMnycuH
+Z4FnA3B748h7qRDqXY0qSljhZ6OpiEbAC9hP1CngTY2Vrig5zG48dhCXVeZ+PH34
+JH5PpQ1BRbhoTguIBy50qrhapNUQDr2CTeJ3SuTn5ciBe4g6s3VSLBS1hkIDB0lq
+T70LBUnIHB2xk8u1oHKChEKQ6nh7F3ovB9t/Gwa3eF6mhjsiv3vkE39PKK4Pnqzw
+MeFrWgyhM4MN17K2TRxvPpdyXkvt8vBcc2WCuFNWeafat8KJQBe/Z0FpzceLq9bg
+b01dpmZSbsT301AC8hwCOS+ANempFeMLQ/Vc5zkTVdumFFtGa03jGEDoASmXxyAu
+G61bkfil5YPzAgWpn/EfJY9aX+HBwTaIKUBFIQEVlLsZph2O3qN1aT7ZO895kBwL
+MxWsISH1wdFFd9mUV57YJjE8jcXprksiur+2Wq9DWv4mlRSlBnAQ2wxm1u5pRKKe
+GE8R99SSTHF5r+8BSJ/IsC13twRdgcTtuqNUeBaOMjenOPN7ZXx5UhSKPppWeTuU
+nFKnIOmJgZOvHQo8USGMYW1/xtzrsk5hpdLAcmitczO0AaycueaqBDwKs0NrerEg
+w/Hzt9mHwLGv6S16PLuwsbaSvNEn9qcqMPPutP6U84dNjoF51DQyZ0nXfByzcSId
+acS/WYAZRueSMInaLqELbi0wdYYJxuTBjyyYWwlA+uI9TOor/p1l53GbcZZ4k160
++WO55CEhPtvwD7KNn3YVj6PT6IN6aXuHC4c1Clgk6Dj63KKXPn32w1wUsZjccgJG
+3OFIScU3s3EIV4vUtaZoTRmXSAYijyTNUk6sO57B2WHiv8s/AJDcRb3lwaQl08e+
+FgepJ8dNsXeEDxUly+Cq8/EiVk748bncwhsOU/cu6BZwzsbgKHKTdV4e6o4+P/e2
+wedAlC0+pll1LxptPcYTPDcZZC7pRko39V6qT5McYNnijiyDw9g2oaQ9V+2lUXhn
+68j12y4EA1B1bstshzE/5pKPZ5TQcEx8xEkxeKVaUqe0b0yG3HBWZAfNC9/08iZb
+64lZFnKNIjzR/4S3O0KuioUadbQbsTWa1LJgLrcTUFK5C5JxbdSnTMSIvgh3TVsb
+4kY71VBMs1xFkJbVva1eDt8GlLcszPHkzRltGCMyQWNXk2slvwZKJLJUWnoMI97G
+sc0bgkNl/XsKJn1dswbfErYRkRUzqwk6rjNxqjS48LI22BPrB93u6Kx+13+RGNb2
+dJ21wGguMjF05hd6Or3lpxGJFKAJb0+oUoUr4SmmM61DsoJTj+FJCxfPrWmDpenj
+1MNsBPojz+DmeoSKsIbDPNQr0LYqWYrbdHOYQYmJx0dwL2beTddrBtfH8I5+YZC5
+ZSA41ur0f1Km6DlsiikBvkHcz1i6cFXVpn2OIrO9tLS3Jp+mwDyLULfldOfjcAea
+/XoNXNfAHlNgyQDWh47o8uFp4BuEFtALspIj7gnG44x0E1bG7VQ4h2t6ul7RQdUy
+3lrktvmKN4rbIjv/0/vNjiSq4CwGMiezOT3JfE4H+2+HrhemKyqg+bYe7UPJvSdn
+OQ9SdNJszct28WQb2Larh6Cz5LZ5z/hKUmU1D5+K5FGcmr20YOibnZnPbDFCJRu8
+6JALCsqrQVBVU5V+/yoTw/d2awPZLgpNbZR7XImmghJeUAXKCBCYP/C862j5eT0x
+fVDOWiQKKRmiaPU48FfswO5fw6rKvLFc0JSwJ3DUdeDCnR7u4ig1LP69zRcfmpgg
+hZ0VZQH164UBDYvwBRIJN2ZIO6Tga1nOXpVDpUm3T/n1PieP7SoAEZGRGa/X/coD
+ppGRs1qFWjsWIb18tfYQu0zJgq+1+3llKq707gbSW9FZ0TVsMQTVaqCRZEuObzL/
+KE24GB3FsAUVsMjmuBoIrz1SsYWo/SshWgqixaR0PHwRMGzPJHeT0t09VFBkkYHN
+nCilIjhgoZwv80GSB5quQ62RP1fRdspQ8H4SulTBlBql8EvCxZBvG0kHmkCArLlX
+puuxt8d7A2LVImZ4Vx00a2tgm0FIvXCgnqIacNgy1BDvKekOMIWBETgWF5pEV9BU
+hdlEjObq3FZAnuhFDj/IMtlq1NpsH3qa8eYAF+M5i+KBRfp4pwwb8s5lzoOXoXel
+FkGzQJ9tFUiNwz15ztNltChWcgpGztFVz8sX+Tm+wLIJ6JTvW7DTZeXiEllh0uub
+X3qG27J4ROVTYZA+aWkwh0HpDEtITFe727Q+bXSDaQOhxTQ60NCAD7pErFp4l4nv
+e/+c4C3Y8Wj9kG15rtnz+XsER14C4kqD2WF2YsNeUzcrEP7jUX8/vT7tub56Ax7w
+yyM9QJKNdNsBS8mzy/qoVoK57WOoTw0vZEV7G+jqvogvwxdo51cj4NzWUy4CF6Yc
+KEsFC5WzR8vB2TrET9sbU+4yh+3zP4op7axyRPXNyNsYa5KWEK2STYy5vxK31+qi
+nIX0CMLQUK7Ku12GUfPr3rWDVhYsaXECQSNMQdpvo0gJZTW+6VspBmNBSUoeqRe6
+WzFZYxsiIZrI8PizrnUEkDXksJhdsbfo2JAG6q2fmzRN6JbZj2xgFDe+qwu2laW2
+fAatLpoX1wAZPmD7G1I4tm0ukjFap8xRWgs5n+o+6n+bsKGJ1X7Mvs/eD0i8eRax
+st+Yli8aFWdaisMeG6GBvVxkvWIDhPegJ6J1kNl7sEO3ceYK5zJvt5DSF5hJ6Awu
+jUGuV6v06nWQjfV2bMG8avDms15O5E1CxlKAuC43Ig3HJ/3vJBM0uVdJzWlIJh22
+zoPrCsHeAQpZENUwVfGjKeHTVo3aJU3bMZMrL56zQvaXPzWZsX+dIvJgEdjsJJJV
+mk7M3Xl7HtYWRY1m6v5syxrL5uoC5QXdVYtYqCbiXUyJGDih3TVTTPDh6LWzqn3W
+zxw/3P7/ZBJTkmlOqTQAzUwfnSFKQeZmRt8l1PFHAC1F1Qem8fF+oJGucVf6a3/Z
+D3PH52t4g/s1bHrzHYIFAmTghtK+vIo5XawcMY72bu+WlH0yMZE7a+FRta3lK9wa
+0qjppwv1gfg6DwGYzg/IzjFYLi3wMBvK8uap90seKtsYpK7C5VzVT8ctXyHhKxIo
+OsLEcfhGHtAEawB19nd5pe99QRXztUNbju/ZrZ8H0j++EYv2+f/eirbSfoiUQcDO
+oTzTlEdUZyAq3eu68uLaSniIT48Uepi8BPwkIH009Rq6ZqeenwB6FerLJ5Di/OP/
+QKlDFiXa4h4momwDwN2U2NSs0RJoMN97FGU4hK/vhX0V+Y6sRIjOntY/11Pc6mTw
+eMnRTWu0VidUKKf97BCmeg4P2GuytqMhDucUj+NBd1RUGnMN6C4ZSG+/T30C46uc
+IhjSK04VFM0skzhGRbZyoIH0nU+S+53By22NcWolWBciLR5VXq90MWtevbFIasmH
+idMfdmbW32koHDH2vctLgCUX0b/5Wgt4V2UCf7x7TK2s5j7eF4aZHhRSvk+ly91a
+q/XroRV8zyUVF+w9amRooAFkIYzQs3vxYMD2BhnWwU0sCcS7WYopWgnoEHkenRmo
+Wx05Rn3Aihie+FPgSW+CQHAexBuc1hI9UZyy+OIJSiUPFhT4BnQ1gTX5WmhLjqWX
+S4KsRFDXQLHw7uFEjOk5zgveUywLEymZQzPEdOFLkHuMvKJK/WDWdG0PPP81fIzA
+Ax/lB4lyDb8a+gu+cXtqLrOLEUfGvYnhDQALVyK0uEqtchiyZStqwYNjM2D2Epel
+cKp7y+GbGaZC1tF6SMuzyOsupHSk6UWxXfJ3cCDU+MT2OZaLYffMPVxpPC5Bo/bG
+8/p3hc4aEiWCRUG3pxLcEsK9XrZ+FKo8qqOHtBM1A4PIwbCLR463ZWezRnpQHF6n
+VZqddZwMItJ+yf1zuewBfejkI1QLFt+1A+kW8rL9h8m6KNhpP9lK2RWXRf+SNPvY
+z7YioYLhVfGnA7Gnv6QRC5v2B0MP5CgAXqRwAN89MI4F/Wb5CBZETrb0MSCDgCMe
+lv0dMdlih6xDQiqlrC6dHRMgr2FHgBEpQbM9Kz7lWwrfi1Yxic7E7xaXaCVJ9d6j
+E7AskHIRBwu8owABNx2W4+HtgLYw6z6rv8jdZlPGsv/yMdxPIyUL5az5vhdSaRKp
+IJ05NxbBaM0zM9yx+aw8sMXyTdy6HkWfo2DjEBItrTg7sWHj9hXzh491tq6cEWze
+Lu17Eu02OE+6CmJ0IfRe1oRbAW/HSw+GKoybHLRTCyAzKo5QEjwE1W59RIMtxOMs
+g7biTbIrcFuEJuAV36m+DEbGTuuXwmv/wWdJPypL6v7q4jr1QPS0r0l/ZZYZMGI/
+uHrDGkv03BFU0tJ/rjCakn9hSrfA7qYbNAbp30IT4rhPyFifuqgtbYNAFTO9Db3s
+08W8/h5W0TwRtcqK92sGveSZzRj3CE5B1bDgA1oqRdRu991JwAG8HvRN4Q4vc/aB
+OcxzZfunj5Jo8farEdcFqcE6/vVA6itJ2FO0/Uu+5oW0VCvhGj/0I539r1sWyvl5
+iQQkVj2BxxJdtkAMeaOxaxrpU4TWW1wW+uvZi1KABcyItUMYaPfkzUxvm2D4FV46
+zc9KZXEbqJ0GjeJdp6XvgNHFGkW4TQffkEnW0V2aq7RG8PiH8e3q6PkCn30c+SB9
+5SlJr/N+Ff3qnpcJEtqzyyjjZDhIXzUf4HC0q0IHT8Mk0Bix9Hlwe8p2GZP0rhqE
+54HJyimY0py36zyzBMNnAIoSSFASUY+ll7el4cu3RoYjgo9NZK43Z22UJneLPube
+oqK46c1MbEOUbf4+sEjTAsnLgZu26ENAmBtbflkLfab86HjEsKDH2cS6P9hMcE54
++OCbQVSAMX+n/ZWcJZFaO4luobouiWRG8VjAhrX3eM+VsHSWBLAfeAROlNtGPJ8L
+gcL7hWPhsIhHKvgNO/5wrC9Y04cx0oXm59dI5IGHoIYfZ2o7YnYYglThIMJJbjdC
+c+inOfgQjDBOSlWICuNEWhK7GQpop/bKMc+IjA5VgFafFuFZT/Rd0zuBEPRaVWuZ
+BumZyGkxSZOtohtG41JUBt2E6V4Ar4jU86sDlhqrc40vZD2XBjWIMR555yJG8uXG
+p69+qy/Xnmx+Kw7NSfQfldrdE/b4DFqx3+XfReHuBGKKLmNbOVtFuY297Pqv1W1k
+R1FWOglIyx/hvm/Jxo6IsClDY0itKmWyk2BAZP9Rpxs1RdrK5KlgYGpLrhQi1PTj
+Xyy2xZsxledRLOidlxTNZdoaxOJDPhd001rtSWgTmC4ENU2omgZTn5li1E7d9qVo
+Rh5iT0h1Gsnqda7ETrTgm2iOoTr6eADkmrlXayogkyjUHUzr7nMRjb8Nn8vyc6Co
+H7fKtSC3yUVaVC0oUjpU4Yxoi6N/oQbPCQR7cDjmS9nq/M9Wx7/Fs7/oXKkKuRsm
+eD5GMSqTYBHC9MH2v18kNyw9Y8Jdqp9mdD1GNyP7GU7SFgKMFGyJcsAOp2X8RcPv
+aUbb46zhkTYt2niSUyNiwP6288xcQ+7GkQvU8PKVKwJGZj6Xv+T6OyIOMRToPfVG
+V658vFMq1TFenf40fUsZP/Q+225dGHdPlbn186L9+E5MOXNLk+KFxsj11yxrtZ02
+9zdBeAwJ9OBBliA5yV8x3rTEuXhTBOzGHK7Jz7EkE28lj2NJEjaFo5r6n9RFSTDl
+EUFVxdab+wRge/KIyUTcs0iLLQD8XPRmpFjZ0sHXqzLKKzUa/HfYReh0oWZnH394
+9/Ue6UXeeATyjpsEudecaie/ura/8jlKe/ctR19wh8IBP+FG8LE1MBvQewqsAEX3
+B1VIpdMej/WtvjvI8KW2ooYBklhcJyc0vw+X7GNwNLZJ2rw/vO2EFKiHHHuIEvju
+HhTJE8DWAV2lfWzeeS0J3kqhem13VXhbxkdNayPKstFD/Ac6vMffMNZEG28XI/Lk
+Z7+qRn97sAdD7MhHySZFB7kPnHjUTWf5QjLs4g2vVwQZbFgwIySNo9wZHElirZ+6
+bAjMGP8Q4POKK9gwgpRi77D4FatF0nIUXDHMBC9X/pmP/GjDVC43RycwhOUnqfgb
+Y6ytBCQ8Xbbn6JUXzJI7edGSH3avi9LbFZ7nI75kp/p7MOqFeVOFra3LINNlvumz
+Y6IlG214AkKFBiyKqcekH0oMk+0vYQN/4PEkRZru5NB6gfxSum4ypp2vw5hqrT6e
+CpQr+7TNJ1XR8Iv0Ny4QS1UDpcNq8yW6jTfCfZctFT6LdoHTk18XZz4Oyr0WALxa
+d6+5UB38gHakuGhC7xyiAEADBFy96cHqtE3N2K3DWyt5p92AgNnkEmlHJLp5MO5Q
+7s749maf5RwdMV7ur7GZHWyl9wijgpGPbHizRb6yTvOFzzW24+9EQ3I6gqfFtPJJ
+wU/Ua2i3Dxcx9ni89jGQYH7wLipCMHpeTtjjbCeIyGdToA4no4Db96T6rtIWfv7N
+zsjSv8X+PSPMrwUeF9e791qNDKdp+Eds39ZMvJdsbUbXoMz0aaMofPpa+uko0hwX
+zVd2PqqfVHbwLxMZt/bF+NJ0SRlN+jQZ76RBRkGBHT5aqJRVC+AmtOL6tRD9GT0r
+IqiCw9Y3A2SvWp+QeXyx91EoJ+1huVZuQTFlujULMoahEdsK+bemtFtWYT5oVIWQ
+B/svABWqK+Q3OccSnD3H63eDAsmLag2K54b6C4JyjdKK12SDkWobCqrgK1UvdXLl
+vxlkmr+7sJhwaKzl9qW8usgJeLK1M+0jlJb9qn7bn2jU6oZWdPeErf+csvR5c+Cl
+3Lsss8XJSHlXiNrh8T/MXSm3GdHdrXDIHJpqmF2Jihr9AlYdnNG898w3ZCmGDQJ4
+61WRv2IdoeFKo3uUKHuqB4fqnSl1xAqNyJxfUmZZG0OpX/TyGWhCkuRsKEzAuivo
+qka39zgoA0dcHoh9vGMRcN/bDMOY/K+gxREWqbTFYyv5mCFpCzWi3hVDgtk5lcyA
++auOMf2wE27liEdMjsez8OszzdhR158IcenRhtpRGI7mNXkRWOr55SvQfVaZBn7+
+8WrZ1ZMjIgHtBxtCYowV8exQ67jPG1+nwnhete+RpUD4rqKYNsItPFWAvCPDTGr0
+U87CZYzt76dCM+vGlC7wFYXctBzJQMjaZypG3zjShq6o7vV6VQ3+uuNtK69FdM/u
+edJkaSNL8Ewu2jGQ5p7br3rPufiJzYk4I+PD2/s/ixi6e+uIo4a5WtoDYYDEBJET
+ICKP4b3ED07/ry4dI0k597DghHIHDWZ7+/eVOQHNqhbTZmOrnq67uOXmeS/pVv9q
+nEf4+vokTkTuwohe61E02xPsIHIe1BtZQ0GTx/hkyueJhlIGYomeznN6j+qWQvHp
+92yuSbWx7SIjQQBXwSw+947PoLdG+OXqb2vAQJurOXVu70DG1JJFDJsmwRok5Vwd
+M2icyqbjHCepXtHGjnnZklOX6hoDnlBnRgVlEFl9zSmTI55GPtwpTUkDDYEmGFCA
+gzhkaN8Y80+qyhB13Gp5yjhcPjH7RWVzIyd7Y5rF+1zNJ70g+TonPCf1jxZYvaRA
+2A8DwvITnPqNoOACCYkBSuKsVMPNsSbhmp+Ij4QPWmjoFkTuTX/usCgQHwPYPmj2
+NIZgF+4vc43zQ5mIGjXONym5y/QXDBDFo0a5dQRuHe08WTOxzCfgS4KMHZiFILFA
+YTpOlULzgZ867BoT/Gr0NMnd2G62R9J47g97ZIe0D5TiY0ryWRsDVyRy3KXZdli7
+OcuHNbDfYjkwWwrgSE7Hba6u5iBmNt6lckimyq/7uSZ0h9Infw4DqdGDBHUnWVSI
+sJgY8r4VUG3DPSxkLfBJltHuVs0ee24CSNvWe+rUTP47cLX/Q485G0NmgUXc7jxd
+JuYYPOfY/ZoMV6RIZNjSIFR2vuw1hxK00m/8f9z+w3IBHa5Zk32NfsW4HPgEO9zE
+nDBWyRQakMp4C09LX6ukEmV/wHVuS9pOnCgNt2McTxLnZV/SgW2gEG6uCKddiD/2
+LBBbawxfH+rlqgQGtkZQA20xAFRVX7yoapxaAWH6OLmEoLKb9k40K882LrDw7UpU
+7v21Exi+nFxOuJDM13PL6jXvAf+OKOEL9W6wKZC1D1VlGBR2AIdfhh8QJ+anjQxy
+sfLTC0gmU7xXSahWn7rqscHgOIVRjXJ+wrJniUIcf4q/Lbn1Kxvnh9Y4MMPUjhJV
+KRAfQ0nb+7+IdJBUFK/ydc5fQXQ08jZRgmbkwL/xwgaXQ3cm/lKERwTTKamBhtE3
+sdfHcpbLw0cwLC8PZeoMZpfBgxckbYokK6XUP2NdlsYBYjqB1TY/jpzzNI4U0gea
+0Ueg7hIwVMR+UqXFjGKD5tZrQ9NdsLo40ImE1GmIF+k5vr6udWOsl+RIHVKC9mv7
+X7IW8IHUGQ8B2mtZKqjE6qXINaprLpfluFj/TFu3mTtb5o5eVOIx6AYIId4BoIY0
+DxWNTXlTIG6LbpGCM/tIskZGabpiiBFqNYfZBf+yJWsS3lRsp7kOCzeTyENScAyu
+mWzXCuXY7c1CUvHygdycAOZ7SYsgR048hJFSbJb86jzmHttXTnEHkMD/CvlZ06gx
+yQNGAXDwz9VoX+/NOWSlwtxWZPb4DMeHxFFYXGFTcSwEDd2/2ErISuRjyPiDVCwc
+7pGO839e5ou+a+YadsBdRIYAJBaM2Hrj2leHXvHdlC7zgrgyHNPujnH9af6qgfO3
+sfazDN20J+YPvSkQI3WuJYwqN4y0f9ET+oYOs8mls2q9/NQYKTslg1qCfaFxz5sD
++JmhzwS5KwSA/nLIi0PGji/1kFNXGvUJQasMsk5LWAnA328uupalqs+H3MZlixyj
+cIKI7KdmX66WwMjvCMDLH/c2S/J0rhn1Wo5bhqUKqSKUTLRwB2hEByXHgxh6KWjU
+10+2eIP6GGhRpU1iCmbtcf9hoZryJxEGpkqIqwISiKyvYKs5XMegWI9TedZZja0D
+9Onc1w0RSMtXZM8w0MVl7mZaSKo97Y6R9RCpPpNjnlm0XjfSS/D6DuPt6xlP5egj
+Oro/yC2VShmGom9mxUEfC4en4euZyCajcncc0rkIWw28IbNcb3iKlpdeKVzYn3uD
+XEoNKEIEGuq+y+w/86Xje6SLzc6litUQeo7IMMt8Ud2LSEYJtJDucCkZ2Xy8HtQQ
+iHn2zB8Y3K9d13n6/baceDwn7oIyNAKefAjjnQfxMP23Wt4iukFKgzpc2blwABVN
+uyKIeD9n5yGKGRntCLgqX9w29m8iDA6tbJfhkIkeO90Jhw4T179BqX8UDO1ATJXS
+Z0RAX9gU+z7EH4aEVqDJOTh47O9QCSFZWInUnoLKuDcaMK0aj7+8JS7U8G9qFxW9
+MTmoIHd+kBYn9Jjsg/DlQfA4CCI2ciJN5dVCVCthf3YJgaTKQYSi47DUgXh/37y5
+A1StllDhJqqcsd0darcIsU5tBrWGTBXljSBSOmCkMSFgf0vtASDouxeS2vV9RvWt
+s3YzogN0qXotFDTJoh8jXVikGyESU/of4JaFfKau/aHbS98ZEAWR/f3x7ry7M7Eh
+/04MTzXJJVYU9TWTHymq6tEUUfC+OkObUD3VUHsTaVWKACUaY2ts+vV/JFMC/vsF
+OdSCMtEOauEuSTlcIXrHZvfM2VtOf4r+jAAuPdcw8QDyskIgr+U/+n24TApOxQSd
+E8kniEh43xiQYkxj+WuuxN++o7qJHS2fCqVubDJZYnvNP5Iq4HB9yziKuO4NMwNe
+LLZtvbM8aqcVLw+hKi0SGvEycTnbcbIIibAjngWkNWZp5aXoneUQs6yWEtz464d1
+/ggR+qEiZLkOrDEp1X9ToDoukq/SlTgbKvsrZIdC7dXW6L6hd5v100eFdH1H+pNh
+OP+tadP/sGywvv96sLbs15UNk5vj75IQdjSIjqoGTsemIXvR9qHBjdop2fQnQE53
+ieBGN1CRK44TYXpS6QG2TFnUSHaBS139dmJ0dYviMJOYr9oP8qhuR7qZlfFeNJHm
+YDHdN7HnsZOmZp9Nle6CRB4XkqkYGRUjs7i2GA+TKXRmQOCO1qhZMnHmlyatYSz4
+kI9CNOR9p6H1Gq0399A9rcCZQNDPOQYAx9MtMtfRwBJsV3JaYriasxTyjYS2tL1K
+jY4ze788+DIZTZNPjXas2dpv+lbk6/qCUiz/CNTbZElG3as5rfzwUVKpulFNy1sS
+NJEiBdRAAEFxDVZtRFyvp/bjvYFyah4hYM3S3Bkoc8OFjwyALu8BaAAL+I1iqM3F
+H3BuCgW/grgls79ZHBA6BSn/MpuJvhxKuTWOrYBv3Q0SyvBJEp/uxvL/o/zDDnfM
+c/Y4B3R2sHE6eiQQx5H4FIRDfq0eDIE/CF29lYezBblhe+Gnqk/BrPkj+AoweM1g
+AXg5i990DD/mD5dQpaCY6nLpuqeisiIGNiU9zn5Qi9AgAOFHg9UT13Y61k/SPwla
+D+WbHZ6GB1cPOdO2B29lgZPxHyJLl0FiQB9i6O3sHkLCcHOiBjHqeYmliGWIAeUv
+i/46hSc21cOsB9jBjVyXHMN3pP8jVGZaJyip9aD4s7pH6srTo3gap2hl3A08AJX6
+LCk4+JWnoDIzeCvJQolHsMHmc/p5aFPWcXPFR14Y7K81GHwS0u+Pg2nJ94tGAXSl
+x/DE8L7Xqp+6LH8jorkzYhqoFt4OeSZTRz2pZ/x+u5lagx/v53q3pA+qWG8BFcUg
+fOzWu+7O3JOgLRFS4KZsj3YZVxCa4sPOJshDMHUdW4EYEiDNvj5oZDX9X4NtriSp
+1H0VAiWkNZPFGe5ZpFIY0fv+e4w0zX6CXE3Dw0laN835ieH7qxqGMz5FN293WnVR
+AuilL1bah5uWLfsR54iPCFGc8TnkSHnihGnJWd9Rka7MmYir+piF1X/+I5DbJWZd
+G9Y5rm5bhdrjFmOs7viUxP3JyHdEstAy5nim/5r7aDO4y71GDE81toiZMcLQSfFZ
+3PyWl0zEKXoSt+2YgUSoZ9ahl8j0OQx7y8yDOwlgif4Au3LjB5V2nGmBgAt9UP4Z
+mgCsbdRJIei9+7VhRTENBQlqZLvJMndR024buuNDgnc7JVfA0+jlKyDeBspSd15M
+DwXkTmuT6xwbU82v2okOkelJCzvmD4dRP8KhQMa2t6oszBKajDIFy5PS9t65sOl7
+URNLX53AWSNM0TWn9981HHBJVPgYtFRCWUdopTFWnT9qdUW+eTURm20xliK4ifKp
+NmEZviFEv86mAOHKtHse16b6RYlS8SE28W9nr9D4qELYrw5D53nGaRwRkGTlqYki
+YwxDX584Eni0Ht9RvwrQ67ahMtnE2nWtq5A3EPDqw2J4n+EEZvv+wHDwbzejeqv9
+VejdY5F+VIIKQdqPz7SAZYu6NEw8HKF3OCzzvC9vZacrPquioga4NPGyiV23G9fL
+xqz8RgR48gbpVyA0/hMgb6IDiSKgD5/mTCVbvgpnsWkDQi9ppAajqJmZSVf0fIkJ
+Hz3m1U8dWYvhdOC1NxM7GgCZcGoE7N15PXauUlo/45M+anSs677/cV6JaphE8kCR
+U9gcmfV6PfHXstHqKK1N5p/t3tVWODYVKQ43Afvs3Of8QZ8UdmPyNYCgy/yxUo+K
+6/wW6lp9BWFDBdP7o1UKTDIpXJcBQdfKWfjk2cGNWfXkI6LqQBqLQXDc8JsHSk4m
+bVmQjJgFDRR/NcXFT88NQH2rbAja0aYGPjgjUprkJOMRr33pr92RlacrPCSBST7z
+LnWJJytfxgwBpzjjGeJazsI/RV8eigjNPqAl4JKOcr2xY5Pbkspj0+kU+7cgpidz
+w4dLtXQsWwWuwkcgFrn9WMXrL6hTHOF5Ta5XRZ/yW9zlNV/zMO50AnHRNRHXCNY4
+vdmag7GEGA2+XzBfXZ5IjGkcYJ72SxHABCER0WP2QzXHAu6G4v7Ezloy7Y3Htz4w
+qAI+QnQpULdLMpnuFWKUepPFL9hkeFdIb2F4mHst1Vv31co8SxUEJsGbDNqHrTmK
+RFXh4ogltqxIIPBGrnYhJDEK9Iev28trSXhpELdQuArDSUb42i9s0AHj0Oh47hJh
+OON0n4EFldqs8sAI/NZhGXfZzpFwomaD1KPyl+Unlm8ioRmlm9G7uH7a1MIq4/3l
+s9RAAW6hOPkhu4OIXIe7Oep/Nc1FhRuXxdXeBuZbWSKS62f38szjIQS6hrgYkWLk
+cAoUrj3t2wOh1ZtvkiW8zA6UJlrP4MJ62kARCeR8CIkkScejREz8O2qHLrmOsqsK
+hDjDEoX67QigBtnmfpNGQgb2mwJcIiYr5LkjHsvB7r/atxYndiGZ071f2CX9ghag
+jpRpq0zjNOCjonzMmaY7yi2Ova9seFOEKowr+mII/fE3ZB3TADpAlnAXUv/0waD9
+DB3ExmMK1I/jcLYbOt7kR/Rbs1l4u+QHXocqgSVCtritQUE8DsHa3diJXSM+HSTz
+ZRV7PNBIHMc+g6k44GC1eIGDmgOhp/xuouwyEhjrEXWDgpq8FuzhWtj8VHE17Upj
+16+KQlC4Z9yJ6AUmKjYnbdLtOU9RdYAvXroohLRH5HhMzBgNpYDFSVSGoR6dCtrO
+V71dh/6JWZuGS8g4g/rFDcWCovzFaVkvayKks7aDWK+ZSGIsq1dLsQ3QP7+/eCw/
+aDlgxJx9Bx3bSWo49OTHyTTLwldFaO72INTl6rXNFigulyEM+zQonQgwOD5HZyE4
+L7+f6ULxmIOuYQLAxPcunGLsXAz0sMxayhlm01VM5qLYRp2Z5H+2uR5S05UrqPSC
+2k615o9ZTFG+/rdI4jkUUZrX22n3bkXZo2Nir25bCTIej7L1UYHys0Qvs0mFroeQ
+/nrVDZHcyys2dNFBzxW2YWRRLdO7wMz3RdK3S1nMoBTSA09WyQD3M8tZvutxjpUP
+CiI+1OrJpKs7kPCQ4VdWT85dvLVc21HQEprgWjyPN3GODwmwRPM9zXXQgg7x5WYl
+MQ4yQr4wwSF1RmkDPV7WMD/+4rwXO8F6Ax/3rFvJLBoO2Ez2UTaMyHC+HFa7L0tu
+Ei5J+GouQiw5jg82DvqgdwMpIuU2IjAS6Wen0q1MYTg/HTS6Xe2oaEyd3OT3LqMe
+81N6AeXddL1JMHZECrdovl8QlZH/Uww+2Yk/aYa01sRx4a01UD/whPxEMDtXGE1T
+qXPSre4H4tJ52RnKWXbTlczC01J5JLLrW/8L8q6s9ULDXchExA8BAxCOJ4eTJjdU
+YuzSC0gps2qkIK9NCoTv4Pmzjk48WewWOM768c7GajxUKfzZIVnRCzezyIXTHVi+
+Vf6xvsCrk0yoOdtbW0rdIn22jzbzQT9q/dJvNw/PXcDD5LuU6UwLGPM1akvRmzUG
+2VnT0Qd+GpeFw5/NARFs0dN2pfB04Vt2ZR0ytsRA1JDpFtI3QNJtf/GczebhiMQP
++81uuG80sljhz2t4sQ9SWkLglFGRsUJw6OVNWLq4u3ewLqtbA8DXRcS8hixX1Kd8
+l60xZDi2DzgUpTwsTRrPCqqHhYBZ78z6GCtrZ2BIjNlZ3/mzNMh7V7LHKjIENMHi
+FgtSitvA1U+EXQyTI/i43Ix4oVdTdS6JAYMWaTqX7jrXgmoJK2DdrFtYob1sQdMl
+eWcwK8oXWQ1IUyM77hpnvpQu9WJ6k9p8LB4p8wl2jlmOVJh2kbZTG4dVYK9LvUNh
+rixIIH9duDFRAmp6rDDGl509JVpgaHGo33Tx7ji8H/4=
+`pragma protect end_protected
Index: atari_chips/gtia/osc_in_sim/cadence/cds.lib
===================================================================
--- atari_chips/gtia/osc_in_sim/cadence/cds.lib	(nonexistent)
+++ atari_chips/gtia/osc_in_sim/cadence/cds.lib	(revision 1318)
@@ -0,0 +1,23 @@
+
+DEFINE std             $CDS_ROOT/tools/inca/files/STD/           
+DEFINE synopsys        $CDS_ROOT/tools/inca/files/SYNOPSYS/      
+DEFINE ieee            $CDS_ROOT/tools/inca/files/IEEE/          
+DEFINE ambit           $CDS_ROOT/tools/inca/files/AMBIT/         
+DEFINE vital_memory    $CDS_ROOT/tools/inca/files/VITAL_MEMORY/  
+DEFINE ncutils         $CDS_ROOT/tools/inca/files/NCUTILS/       
+DEFINE ncinternal      $CDS_ROOT/tools/inca/files/NCINTERNAL/    
+DEFINE ncmodels        $CDS_ROOT/tools/inca/files/NCMODELS/      
+DEFINE cds_assertions  $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work            ./libraries/work/                         
+DEFINE osc_in          ./libraries/osc_in/                       
+DEFINE altera_ver      ./libraries/altera_ver/                   
+DEFINE lpm_ver         ./libraries/lpm_ver/                      
+DEFINE sgate_ver       ./libraries/sgate_ver/                    
+DEFINE altera_mf_ver   ./libraries/altera_mf_ver/                
+DEFINE fiftyfivenm_ver ./libraries/fiftyfivenm_ver/              
+DEFINE altera          ./libraries/altera/                       
+DEFINE lpm             ./libraries/lpm/                          
+DEFINE sgate           ./libraries/sgate/                        
+DEFINE altera_mf       ./libraries/altera_mf/                    
+DEFINE altera_lnsim    ./libraries/altera_lnsim/                 
+DEFINE fiftyfivenm     ./libraries/fiftyfivenm/                  
Index: atari_chips/gtia/osc_in_sim/cadence/cds_libs/osc_in.cds.lib
===================================================================
--- atari_chips/gtia/osc_in_sim/cadence/cds_libs/osc_in.cds.lib	(nonexistent)
+++ atari_chips/gtia/osc_in_sim/cadence/cds_libs/osc_in.cds.lib	(revision 1318)
@@ -0,0 +1,23 @@
+
+DEFINE std             $CDS_ROOT/tools/inca/files/STD/           
+DEFINE synopsys        $CDS_ROOT/tools/inca/files/SYNOPSYS/      
+DEFINE ieee            $CDS_ROOT/tools/inca/files/IEEE/          
+DEFINE ambit           $CDS_ROOT/tools/inca/files/AMBIT/         
+DEFINE vital_memory    $CDS_ROOT/tools/inca/files/VITAL_MEMORY/  
+DEFINE ncutils         $CDS_ROOT/tools/inca/files/NCUTILS/       
+DEFINE ncinternal      $CDS_ROOT/tools/inca/files/NCINTERNAL/    
+DEFINE ncmodels        $CDS_ROOT/tools/inca/files/NCMODELS/      
+DEFINE cds_assertions  $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work            ./../libraries/work/                      
+DEFINE altera_ver      ./../libraries/altera_ver/                
+DEFINE lpm_ver         ./../libraries/lpm_ver/                   
+DEFINE sgate_ver       ./../libraries/sgate_ver/                 
+DEFINE altera_mf_ver   ./../libraries/altera_mf_ver/             
+DEFINE fiftyfivenm_ver ./../libraries/fiftyfivenm_ver/           
+DEFINE altera          ./../libraries/altera/                    
+DEFINE lpm             ./../libraries/lpm/                       
+DEFINE sgate           ./../libraries/sgate/                     
+DEFINE altera_mf       ./../libraries/altera_mf/                 
+DEFINE altera_lnsim    ./../libraries/altera_lnsim/              
+DEFINE fiftyfivenm     ./../libraries/fiftyfivenm/               
+DEFINE osc_in          ./../libraries/osc_in/                    
Index: atari_chips/gtia/osc_in_sim/cadence/hdl.var
===================================================================
--- atari_chips/gtia/osc_in_sim/cadence/hdl.var	(nonexistent)
+++ atari_chips/gtia/osc_in_sim/cadence/hdl.var	(revision 1318)
@@ -0,0 +1,2 @@
+
+DEFINE WORK work
Index: atari_chips/gtia/osc_in_sim/cadence/ncsim_setup.sh
===================================================================
--- atari_chips/gtia/osc_in_sim/cadence/ncsim_setup.sh	(nonexistent)
+++ atari_chips/gtia/osc_in_sim/cadence/ncsim_setup.sh	(revision 1318)
@@ -0,0 +1,210 @@
+
+# (C) 2001-2018 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 18.0 614 linux 2018.10.28.22:11:01
+
+# ----------------------------------------
+# ncsim - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     osc_in
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level shell script that compiles Altera simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "ncsim.sh", and modify text as directed.
+# 
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated files
+# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated - 
+# # into the location from which you launch the simulator, or incorporate
+# # into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# # - If necessary, specify any compilation options:
+# #   USER_DEFINED_COMPILE_OPTIONS
+# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# ncvlog <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME=<simulation top> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If osc_in is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 18.0 614 linux 2018.10.28.22:11:01
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="osc_in"
+QSYS_SIMDIR="./../"
+QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/18.0/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for 
+# overwriting variables. An example usage:
+#   sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+  eval $expression
+  if [ $? -ne 0 ]; then
+    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+    exit $?
+  fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
+  :
+else
+  :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/osc_in/
+mkdir -p ./libraries/altera_ver/
+mkdir -p ./libraries/lpm_ver/
+mkdir -p ./libraries/sgate_ver/
+mkdir -p ./libraries/altera_mf_ver/
+mkdir -p ./libraries/fiftyfivenm_ver/
+mkdir -p ./libraries/altera/
+mkdir -p ./libraries/lpm/
+mkdir -p ./libraries/sgate/
+mkdir -p ./libraries/altera_mf/
+mkdir -p ./libraries/altera_lnsim/
+mkdir -p ./libraries/fiftyfivenm/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"                -work altera_ver     
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                         -work lpm_ver        
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                            -work sgate_ver      
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                        -work altera_mf_ver  
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v"                -work fiftyfivenm_ver
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"          -work altera         
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"      -work altera         
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"         -work altera         
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"      -work altera         
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd"   -work altera         
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"              -work altera         
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                        -work lpm            
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                       -work lpm            
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                     -work sgate          
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                          -work sgate          
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"           -work altera_mf      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                      -work altera_mf      
+  ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                    -work altera_lnsim   
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"        -work altera_lnsim   
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm    
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.vhd"              -work fiftyfivenm    
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_components.vhd"         -work fiftyfivenm    
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+  ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_gpio_lite/altera_gpio_lite.sv" -work osc_in -cdslib ./cds_libs/osc_in.cds.lib
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QSYS_SIMDIR/osc_in.vhd"                                                                         
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+  export GENERIC_PARAM_COMPAT_CHECK=1
+  ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+  eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
+fi

Property changes on: atari_chips/gtia/osc_in_sim/cadence/ncsim_setup.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: atari_chips/gtia/osc_in_sim/mentor/msim_setup.tcl
===================================================================
--- atari_chips/gtia/osc_in_sim/mentor/msim_setup.tcl	(nonexistent)
+++ atari_chips/gtia/osc_in_sim/mentor/msim_setup.tcl	(revision 1318)
@@ -0,0 +1,295 @@
+
+# (C) 2001-2018 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ----------------------------------------
+# Auto-generated simulation script msim_setup.tcl
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     osc_in
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level script that compiles Altera simulation libraries and
+# the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "mentor.do", and modify the text as directed.
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator.
+# #
+# set QSYS_SIMDIR <script generation output directory>
+# #
+# # Source the generated IP simulation script.
+# source $QSYS_SIMDIR/mentor/msim_setup.tcl
+# #
+# # Set any compilation options you require (this is unusual).
+# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
+# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
+# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
+# #
+# # Call command to compile the Quartus EDA simulation library.
+# dev_com
+# #
+# # Call command to compile the Quartus-generated IP simulation files.
+# com
+# #
+# # Add commands to compile all design files and testbench files, including
+# # the top level. (These are all the files required for simulation other
+# # than the files compiled by the Quartus-generated IP simulation script)
+# #
+# vlog <compilation options> <design and testbench files>
+# #
+# # Set the top-level simulation or testbench module/entity name, which is
+# # used by the elab command to elaborate the top level.
+# #
+# set TOP_LEVEL_NAME <simulation top>
+# #
+# # Set any elaboration options you require.
+# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
+# #
+# # Call command to elaborate your design and testbench.
+# elab
+# #
+# # Run the simulation.
+# run -a
+# #
+# # Report success to the shell.
+# exit -code 0
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If osc_in is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 18.0 614 linux 2018.10.28.22:11:01
+
+# ----------------------------------------
+# Initialize variables
+if ![info exists SYSTEM_INSTANCE_NAME] { 
+  set SYSTEM_INSTANCE_NAME ""
+} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
+  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
+}
+
+if ![info exists TOP_LEVEL_NAME] { 
+  set TOP_LEVEL_NAME "osc_in"
+}
+
+if ![info exists QSYS_SIMDIR] { 
+  set QSYS_SIMDIR "./../"
+}
+
+if ![info exists QUARTUS_INSTALL_DIR] { 
+  set QUARTUS_INSTALL_DIR "/home/markw/intelFPGA_lite/18.0/quartus/"
+}
+
+if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
+  set USER_DEFINED_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
+  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
+}
+if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
+  set USER_DEFINED_ELAB_OPTIONS ""
+}
+
+# ----------------------------------------
+# Initialize simulation properties - DO NOT MODIFY!
+set ELAB_OPTIONS ""
+set SIM_OPTIONS ""
+if ![ string match "*-64 vsim*" [ vsim -version ] ] {
+} else {
+}
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+alias file_copy {
+  echo "\[exec\] file_copy"
+}
+
+# ----------------------------------------
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+ensure_lib          ./libraries/     
+ensure_lib          ./libraries/work/
+vmap       work     ./libraries/work/
+vmap       work_lib ./libraries/work/
+if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+  ensure_lib                  ./libraries/altera_ver/      
+  vmap       altera_ver       ./libraries/altera_ver/      
+  ensure_lib                  ./libraries/lpm_ver/         
+  vmap       lpm_ver          ./libraries/lpm_ver/         
+  ensure_lib                  ./libraries/sgate_ver/       
+  vmap       sgate_ver        ./libraries/sgate_ver/       
+  ensure_lib                  ./libraries/altera_mf_ver/   
+  vmap       altera_mf_ver    ./libraries/altera_mf_ver/   
+  ensure_lib                  ./libraries/altera_lnsim_ver/
+  vmap       altera_lnsim_ver ./libraries/altera_lnsim_ver/
+  ensure_lib                  ./libraries/fiftyfivenm_ver/ 
+  vmap       fiftyfivenm_ver  ./libraries/fiftyfivenm_ver/ 
+  ensure_lib                  ./libraries/altera/          
+  vmap       altera           ./libraries/altera/          
+  ensure_lib                  ./libraries/lpm/             
+  vmap       lpm              ./libraries/lpm/             
+  ensure_lib                  ./libraries/sgate/           
+  vmap       sgate            ./libraries/sgate/           
+  ensure_lib                  ./libraries/altera_mf/       
+  vmap       altera_mf        ./libraries/altera_mf/       
+  ensure_lib                  ./libraries/altera_lnsim/    
+  vmap       altera_lnsim     ./libraries/altera_lnsim/    
+  ensure_lib                  ./libraries/fiftyfivenm/     
+  vmap       fiftyfivenm      ./libraries/fiftyfivenm/     
+}
+ensure_lib        ./libraries/osc_in/
+vmap       osc_in ./libraries/osc_in/
+
+# ----------------------------------------
+# Compile device library files
+alias dev_com {
+  echo "\[exec\] dev_com"
+  if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"               -work altera_ver      
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                        -work lpm_ver         
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                           -work sgate_ver       
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                       -work altera_mf_ver   
+    eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                   -work altera_lnsim_ver
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v"               -work fiftyfivenm_ver 
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm_ver 
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"         -work altera          
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"     -work altera          
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"        -work altera          
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"     -work altera          
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd"  -work altera          
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"             -work altera          
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                       -work lpm             
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                      -work lpm             
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                    -work sgate           
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                         -work sgate           
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"          -work altera_mf       
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                     -work altera_mf       
+    eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/altera_lnsim_for_vhdl.sv"   -work altera_lnsim    
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"       -work altera_lnsim    
+    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm     
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.vhd"             -work fiftyfivenm     
+    eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_components.vhd"        -work fiftyfivenm     
+  }
+}
+
+# ----------------------------------------
+# Compile the design files in correct order
+alias com {
+  echo "\[exec\] com"
+  eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_gpio_lite/altera_gpio_lite.sv"        -work osc_in
+  eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_gpio_lite/mentor/altera_gpio_lite.sv" -work osc_in
+  eval  vcom $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS        "$QSYS_SIMDIR/osc_in.vhd"                                              
+}
+
+# ----------------------------------------
+# Elaborate top level design
+alias elab {
+  echo "\[exec\] elab"
+  eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L osc_in -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Elaborate the top level design with novopt option
+alias elab_debug {
+  echo "\[exec\] elab_debug"
+  eval vsim -novopt -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L osc_in -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L fiftyfivenm_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm $TOP_LEVEL_NAME
+}
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design
+alias ld "
+  dev_com
+  com
+  elab
+"
+
+# ----------------------------------------
+# Compile all the design files and elaborate the top level design with -novopt
+alias ld_debug "
+  dev_com
+  com
+  elab_debug
+"
+
+# ----------------------------------------
+# Print out user commmand line aliases
+alias h {
+  echo "List Of Command Line Aliases"
+  echo
+  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
+  echo
+  echo "dev_com                                           -- Compile device library files"
+  echo
+  echo "com                                               -- Compile the design files in correct order"
+  echo
+  echo "elab                                              -- Elaborate top level design"
+  echo
+  echo "elab_debug                                        -- Elaborate the top level design with novopt option"
+  echo
+  echo "ld                                                -- Compile all the design files and elaborate the top level design"
+  echo
+  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -novopt"
+  echo
+  echo 
+  echo
+  echo "List Of Variables"
+  echo
+  echo "TOP_LEVEL_NAME                                    -- Top level module name."
+  echo "                                                     For most designs, this should be overridden"
+  echo "                                                     to enable the elab/elab_debug aliases."
+  echo
+  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
+  echo
+  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
+  echo
+  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
+  echo
+  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
+  echo
+  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
+  echo
+  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
+}
+file_copy
+h
Index: atari_chips/gtia/osc_in_sim/osc_in.vhd
===================================================================
--- atari_chips/gtia/osc_in_sim/osc_in.vhd	(nonexistent)
+++ atari_chips/gtia/osc_in_sim/osc_in.vhd	(revision 1318)
@@ -0,0 +1,127 @@
+-- osc_in.vhd
+
+-- Generated using ACDS version 18.0 614
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity osc_in is
+	port (
+		inclock : in  std_logic                    := '0';             -- inclock.export
+		dout    : out std_logic_vector(1 downto 0);                    --    dout.export
+		pad_in  : in  std_logic_vector(0 downto 0) := (others => '0')  --  pad_in.export
+	);
+end entity osc_in;
+
+architecture rtl of osc_in is
+	component altera_gpio_lite is
+		generic (
+			PIN_TYPE                                 : string  := "output";
+			SIZE                                     : integer := 4;
+			REGISTER_MODE                            : string  := "bypass";
+			BUFFER_TYPE                              : string  := "single-ended";
+			ASYNC_MODE                               : string  := "none";
+			SYNC_MODE                                : string  := "none";
+			BUS_HOLD                                 : string  := "false";
+			OPEN_DRAIN_OUTPUT                        : string  := "false";
+			ENABLE_OE_PORT                           : string  := "false";
+			ENABLE_NSLEEP_PORT                       : string  := "false";
+			ENABLE_CLOCK_ENA_PORT                    : string  := "false";
+			SET_REGISTER_OUTPUTS_HIGH                : string  := "false";
+			INVERT_OUTPUT                            : string  := "false";
+			INVERT_INPUT_CLOCK                       : string  := "false";
+			USE_ONE_REG_TO_DRIVE_OE                  : string  := "false";
+			USE_DDIO_REG_TO_DRIVE_OE                 : string  := "false";
+			USE_ADVANCED_DDR_FEATURES                : string  := "false";
+			USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY : string  := "false";
+			ENABLE_OE_HALF_CYCLE_DELAY               : string  := "true";
+			INVERT_CLKDIV_INPUT_CLOCK                : string  := "false";
+			ENABLE_PHASE_INVERT_CTRL_PORT            : string  := "false";
+			ENABLE_HR_CLOCK                          : string  := "false";
+			INVERT_OUTPUT_CLOCK                      : string  := "false";
+			INVERT_OE_INCLOCK                        : string  := "false";
+			ENABLE_PHASE_DETECTOR_FOR_CK             : string  := "false"
+		);
+		port (
+			inclock         : in    std_logic                    := 'X';             -- export
+			dout            : out   std_logic_vector(1 downto 0);                    -- export
+			pad_in          : in    std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			inclocken       : in    std_logic                    := 'X';             -- export
+			fr_clock        : out   std_logic_vector(0 downto 0);                    -- export
+			hr_clock        : out   std_logic;                                       -- export
+			invert_hr_clock : in    std_logic                    := 'X';             -- export
+			outclock        : in    std_logic                    := 'X';             -- export
+			outclocken      : in    std_logic                    := 'X';             -- export
+			phy_mem_clock   : in    std_logic                    := 'X';             -- export
+			mimic_clock     : out   std_logic_vector(0 downto 0);                    -- export
+			din             : in    std_logic_vector(1 downto 0) := (others => 'X'); -- export
+			pad_io          : inout std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			pad_io_b        : inout std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			pad_in_b        : in    std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			pad_out         : out   std_logic_vector(0 downto 0);                    -- export
+			pad_out_b       : out   std_logic_vector(0 downto 0);                    -- export
+			aset            : in    std_logic                    := 'X';             -- export
+			aclr            : in    std_logic                    := 'X';             -- export
+			sclr            : in    std_logic                    := 'X';             -- export
+			nsleep          : in    std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			oe              : in    std_logic_vector(0 downto 0) := (others => 'X')  -- export
+		);
+	end component altera_gpio_lite;
+
+begin
+
+	osc_in_inst : component altera_gpio_lite
+		generic map (
+			PIN_TYPE                                 => "input",
+			SIZE                                     => 1,
+			REGISTER_MODE                            => "ddr",
+			BUFFER_TYPE                              => "single-ended",
+			ASYNC_MODE                               => "none",
+			SYNC_MODE                                => "none",
+			BUS_HOLD                                 => "false",
+			OPEN_DRAIN_OUTPUT                        => "false",
+			ENABLE_OE_PORT                           => "false",
+			ENABLE_NSLEEP_PORT                       => "false",
+			ENABLE_CLOCK_ENA_PORT                    => "false",
+			SET_REGISTER_OUTPUTS_HIGH                => "false",
+			INVERT_OUTPUT                            => "false",
+			INVERT_INPUT_CLOCK                       => "false",
+			USE_ONE_REG_TO_DRIVE_OE                  => "false",
+			USE_DDIO_REG_TO_DRIVE_OE                 => "false",
+			USE_ADVANCED_DDR_FEATURES                => "false",
+			USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY => "false",
+			ENABLE_OE_HALF_CYCLE_DELAY               => "true",
+			INVERT_CLKDIV_INPUT_CLOCK                => "false",
+			ENABLE_PHASE_INVERT_CTRL_PORT            => "false",
+			ENABLE_HR_CLOCK                          => "false",
+			INVERT_OUTPUT_CLOCK                      => "false",
+			INVERT_OE_INCLOCK                        => "false",
+			ENABLE_PHASE_DETECTOR_FOR_CK             => "false"
+		)
+		port map (
+			inclock         => inclock, -- inclock.export
+			dout            => dout,    --    dout.export
+			pad_in          => pad_in,  --  pad_in.export
+			inclocken       => '1',     -- (terminated)
+			fr_clock        => open,    -- (terminated)
+			hr_clock        => open,    -- (terminated)
+			invert_hr_clock => '0',     -- (terminated)
+			outclock        => '0',     -- (terminated)
+			outclocken      => '0',     -- (terminated)
+			phy_mem_clock   => '0',     -- (terminated)
+			mimic_clock     => open,    -- (terminated)
+			din             => "00",    -- (terminated)
+			pad_io          => open,    -- (terminated)
+			pad_io_b        => open,    -- (terminated)
+			pad_in_b        => "0",     -- (terminated)
+			pad_out         => open,    -- (terminated)
+			pad_out_b       => open,    -- (terminated)
+			aset            => '0',     -- (terminated)
+			aclr            => '0',     -- (terminated)
+			sclr            => '0',     -- (terminated)
+			nsleep          => "0",     -- (terminated)
+			oe              => "0"      -- (terminated)
+		);
+
+end architecture rtl; -- of osc_in
Index: atari_chips/gtia/osc_in_sim/synopsys/vcsmx/synopsys_sim.setup
===================================================================
--- atari_chips/gtia/osc_in_sim/synopsys/vcsmx/synopsys_sim.setup	(nonexistent)
+++ atari_chips/gtia/osc_in_sim/synopsys/vcsmx/synopsys_sim.setup	(revision 1318)
@@ -0,0 +1,18 @@
+
+WORK > DEFAULT
+DEFAULT:          ./libraries/work/            
+work:             ./libraries/work/            
+osc_in:           ./libraries/osc_in/          
+altera_ver:       ./libraries/altera_ver/      
+lpm_ver:          ./libraries/lpm_ver/         
+sgate_ver:        ./libraries/sgate_ver/       
+altera_mf_ver:    ./libraries/altera_mf_ver/   
+altera_lnsim_ver: ./libraries/altera_lnsim_ver/
+fiftyfivenm_ver:  ./libraries/fiftyfivenm_ver/ 
+altera:           ./libraries/altera/          
+lpm:              ./libraries/lpm/             
+sgate:            ./libraries/sgate/           
+altera_mf:        ./libraries/altera_mf/       
+altera_lnsim:     ./libraries/altera_lnsim/    
+fiftyfivenm:      ./libraries/fiftyfivenm/     
+LIBRARY_SCAN = TRUE
Index: atari_chips/gtia/osc_in_sim/synopsys/vcsmx/vcsmx_setup.sh
===================================================================
--- atari_chips/gtia/osc_in_sim/synopsys/vcsmx/vcsmx_setup.sh	(nonexistent)
+++ atari_chips/gtia/osc_in_sim/synopsys/vcsmx/vcsmx_setup.sh	(revision 1318)
@@ -0,0 +1,213 @@
+
+# (C) 2001-2018 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 18.0 614 linux 2018.10.28.22:11:01
+
+# ----------------------------------------
+# vcsmx - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     osc_in
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level shell script that compiles Altera simulation libraries 
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
+# 
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated library
+# # setup "synopsys_sim.setup" into the location from which you launch the
+# # simulator, or incorporate into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# #
+# # - If necessary, specify any compilation options:
+# #   USER_DEFINED_COMPILE_OPTIONS
+# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# vlogan <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME="'-top <simulation top>'" \
+# QSYS_SIMDIR=<script generation output directory> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If osc_in is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 18.0 614 linux 2018.10.28.22:11:01
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="osc_in"
+QSYS_SIMDIR="./../../"
+QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/18.0/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for 
+# overwriting variables. An example usage:
+#   sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+  eval $expression
+  if [ $? -ne 0 ]; then
+    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+    exit $?
+  fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `vcs -platform` != *"amd64"* ]]; then
+  :
+else
+  :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/osc_in/
+mkdir -p ./libraries/altera_ver/
+mkdir -p ./libraries/lpm_ver/
+mkdir -p ./libraries/sgate_ver/
+mkdir -p ./libraries/altera_mf_ver/
+mkdir -p ./libraries/altera_lnsim_ver/
+mkdir -p ./libraries/fiftyfivenm_ver/
+mkdir -p ./libraries/altera/
+mkdir -p ./libraries/lpm/
+mkdir -p ./libraries/sgate/
+mkdir -p ./libraries/altera_mf/
+mkdir -p ./libraries/altera_lnsim/
+mkdir -p ./libraries/fiftyfivenm/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"                 -work altera_ver      
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                          -work lpm_ver         
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                             -work sgate_ver       
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                         -work altera_mf_ver   
+  vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                     -work altera_lnsim_ver
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v"                 -work fiftyfivenm_ver 
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm_ver 
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"           -work altera          
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"       -work altera          
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"          -work altera          
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"       -work altera          
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd"    -work altera          
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"               -work altera          
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                         -work lpm             
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                        -work lpm             
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                      -work sgate           
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                           -work sgate           
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"            -work altera_mf       
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                       -work altera_mf       
+  vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                     -work altera_lnsim    
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"         -work altera_lnsim    
+  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm     
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.vhd"               -work fiftyfivenm     
+  vhdlan $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS                   "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_components.vhd"          -work fiftyfivenm     
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+  vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_gpio_lite/altera_gpio_lite.sv" -work osc_in
+  vhdlan -xlrm $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS             "$QSYS_SIMDIR/osc_in.vhd"                                       
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+  vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+  ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
+fi

Property changes on: atari_chips/gtia/osc_in_sim/synopsys/vcsmx/vcsmx_setup.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: atari_chips/gtia/osc_in_sim.f
===================================================================
--- atari_chips/gtia/osc_in_sim.f	(nonexistent)
+++ atari_chips/gtia/osc_in_sim.f	(revision 1318)
@@ -0,0 +1,3 @@
+osc_in_sim/osc_in.vhd
+osc_in_sim/altera_gpio_lite/altera_gpio_lite.sv
+osc_in_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv
Index: atari_chips/gtia/osc_out/altera_gpio_lite.sv
===================================================================
--- atari_chips/gtia/osc_out/altera_gpio_lite.sv	(nonexistent)
+++ atari_chips/gtia/osc_out/altera_gpio_lite.sv	(revision 1318)
@@ -0,0 +1,1200 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module altgpio_one_bit(
+	inclock,
+	outclock,
+	phy_mem_clock,
+	inclocken,
+	outclocken,
+	oe,
+	din,
+	dout,
+	pad,
+	pad_b,
+	aset,
+	sclr,
+	hr_clock,
+	fr_clock,
+	mimic_clock,
+	nsleep
+);
+
+	parameter PIN_TYPE = "output"; 
+	parameter BUFFER_TYPE = "single-ended"; 
+	parameter REGISTER_MODE = "bypass"; 
+	parameter ASYNC_MODE = "none"; 
+	parameter SYNC_MODE = "none"; 
+	parameter BUS_HOLD = "false"; 
+	parameter SET_REGISTER_OUTPUTS_HIGH = "false";  
+	parameter USE_ENHANCED_DDR_HIO_REGISTER = "false"; 
+	parameter BYPASS_THREE_QUARTER_REGISTER = "true"; 
+	parameter INVERT_OUTPUT = "false"; 
+	parameter INVERT_INPUT_CLOCK = "false"; 
+	parameter INVERT_OUTPUT_CLOCK = "false"; 
+	parameter INVERT_OE_INCLOCK = "false"; 
+	parameter USE_ONE_REG_TO_DRIVE_OE = "false"; 
+	parameter USE_DDIO_REG_TO_DRIVE_OE = "false"; 
+	parameter OPEN_DRAIN_OUTPUT = "false"; 
+	parameter ENABLE_OE_HALF_CYCLE_DELAY = "true"; 
+	parameter USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY = "false"; 
+	parameter ENABLE_CLOCK_ENA_PORT = "false"; 
+	parameter ENABLE_HR_CLOCK = "false"; 
+	parameter ENABLE_PHASE_DETECTOR_FOR_CK = "false"; 
+	parameter ENABLE_NSLEEP_PORT = "false"; 
+
+	localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? 2:1;
+	localparam DDIO_REG_POWER_UP = (ASYNC_MODE == "preset" || SET_REGISTER_OUTPUTS_HIGH == "true") ? "high" : "low";
+
+	input inclock;
+	input outclock;
+	input inclocken;
+	input outclocken;
+	input oe;
+	input nsleep;
+	input [DATA_SIZE - 1:0] din;
+	output [DATA_SIZE - 1:0] dout;
+	inout pad;
+	inout pad_b;
+	input aset;
+	input sclr;
+	input phy_mem_clock;
+	input hr_clock;
+	(* altera_attribute = "-name GLOBAL_SIGNAL\"OFF\"" *) output fr_clock;
+	output mimic_clock;
+
+	wire din_ddr;
+	wire buf_in;
+
+	wire oe_out;
+	wire nsleep_in;
+
+    generate
+        if (PIN_TYPE == "output" || PIN_TYPE == "bidir")
+        begin
+			wire [1:0] din_fr;
+            if (INVERT_OUTPUT == "false")
+			begin
+				assign din_fr = din;
+			end
+			else
+			begin
+				assign din_fr = ~din;
+			end
+
+			wire outclock_wire;
+			if (REGISTER_MODE != "bypass")
+			begin
+				if (INVERT_OUTPUT_CLOCK == "false")
+				begin: normal_input_clock
+					assign outclock_wire = outclock;
+				end
+				else
+				begin: inverted_output_clock
+					assign outclock_wire = ~outclock;
+				end
+			end
+
+			wire outclocken_wire;
+			assign  outclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? outclocken : 1'b1;
+
+			if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "true")
+			begin
+				if (ASYNC_MODE != "none")
+					begin: async_mode_out_path_enhanced_ddr
+								fiftyfivenm_ddio_out
+								#(
+									.async_mode(ASYNC_MODE),
+									.sync_mode(SYNC_MODE),
+									.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+									.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+									.power_up(DDIO_REG_POWER_UP),
+									.use_new_clocking_model("true")
+								) fr_out_data_ddio (
+									.datainhi(din_fr[0]),
+									.datainlo(din_fr[1]),
+									.dataout(din_ddr),
+									.clkhi(outclock_wire),
+									.clklo(outclock_wire),
+									.muxsel(outclock_wire),
+									.areset(aset),
+									.ena(outclocken_wire),
+									.phymemclock(phy_mem_clock)
+									`ifndef ALTERA_RESERVED_QIS
+									,
+									.clk (outclock_wire),
+									.sreset(1'b0),
+									.dfflo(),
+									.dffhi(),
+									.devpor(1'b1),
+									.devclrn(1'b1)
+									`endif
+								);
+					end
+				else if (SYNC_MODE != "none")
+					begin: sync_mode_out_path_enhanced_ddr
+								fiftyfivenm_ddio_out
+								#(
+									.async_mode(ASYNC_MODE),
+									.sync_mode(SYNC_MODE),
+									.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+									.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+									.power_up(DDIO_REG_POWER_UP),
+									.use_new_clocking_model("true")
+								) fr_out_data_ddio (
+									.datainhi(din_fr[0]),
+									.datainlo(din_fr[1]),
+									.dataout(din_ddr),
+									.clkhi(outclock_wire),
+									.clklo(outclock_wire),
+									.muxsel(outclock_wire),
+									.sreset(sclr),
+									.ena(outclocken_wire),
+									.phymemclock(phy_mem_clock)
+									`ifndef ALTERA_RESERVED_QIS
+									,
+									.clk (outclock_wire),
+									.areset(1'b0),
+									.dfflo(),
+									.dffhi(),
+									.devpor(1'b1),
+									.devclrn(1'b1)
+									`endif
+								);
+					end
+				else
+					begin: out_path_enhanced_ddr
+								fiftyfivenm_ddio_out
+								#(
+									.async_mode(ASYNC_MODE),
+									.sync_mode(SYNC_MODE),
+									.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+									.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+									.power_up(DDIO_REG_POWER_UP),
+									.use_new_clocking_model("true")
+								) fr_out_data_ddio (
+									.datainhi(din_fr[0]),
+									.datainlo(din_fr[1]),
+									.dataout(din_ddr),
+									.clkhi(outclock_wire),
+									.clklo(outclock_wire),
+									.muxsel(outclock_wire),
+									.ena(outclocken_wire),
+									.phymemclock(phy_mem_clock)
+									`ifndef ALTERA_RESERVED_QIS
+									,
+									.areset(1'b0),
+									.clk(1'b0),
+									.sreset(1'b0),
+									.dfflo(),
+									.dffhi(),
+									.devpor(1'b1),
+									.devclrn(1'b1)
+									`endif
+								);
+					end
+			end
+			else if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "false")
+			begin
+				if (ASYNC_MODE != "none")
+						begin: async_mode_out_path_ddr
+							fiftyfivenm_ddio_out
+							#(
+								.async_mode(ASYNC_MODE),
+								.sync_mode(SYNC_MODE),
+								.power_up(DDIO_REG_POWER_UP),
+								.use_new_clocking_model("true"),
+								.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+							) fr_out_data_ddio (
+								.datainhi(din_fr[0]),
+								.datainlo(din_fr[1]),
+								.dataout(din_ddr),
+								.clkhi(outclock_wire),
+								.clklo(outclock_wire),
+								.muxsel(outclock_wire),
+								.areset(aset),
+								.ena(outclocken_wire)
+								`ifndef ALTERA_RESERVED_QIS
+								,
+								.clk(1'b0),
+								.phymemclock(1'b0),
+								.sreset(1'b0),
+								.dfflo(),
+								.dffhi(),
+								.devpor(1'b1),
+								.devclrn(1'b1)
+								`endif
+							);
+						end
+				else if (SYNC_MODE != "none")
+						begin: sync_mode_out_path_ddr
+							fiftyfivenm_ddio_out
+							#(
+								.async_mode(ASYNC_MODE),
+								.sync_mode(SYNC_MODE),
+								.power_up(DDIO_REG_POWER_UP),
+								.use_new_clocking_model("true"),
+								.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+							) fr_out_data_ddio (
+								.datainhi(din_fr[0]),
+								.datainlo(din_fr[1]),
+								.dataout(din_ddr),
+								.clkhi(outclock_wire),
+								.clklo(outclock_wire),
+								.muxsel(outclock_wire),
+								.sreset(sclr),
+								.ena(outclocken_wire)
+								`ifndef ALTERA_RESERVED_QIS
+								,
+								.areset(1'b0),
+								.clk(1'b0),
+								.phymemclock(1'b0),
+								.dfflo(),
+								.dffhi(),
+								.devpor(1'b1),
+								.devclrn(1'b1)
+								`endif
+							);
+						end
+				else
+						begin: out_path_ddr
+							fiftyfivenm_ddio_out
+							#(
+								.async_mode(ASYNC_MODE),
+								.sync_mode(SYNC_MODE),
+								.power_up(DDIO_REG_POWER_UP),
+								.use_new_clocking_model("true"),
+								.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+							) fr_out_data_ddio (
+								.datainhi(din_fr[0]),
+								.datainlo(din_fr[1]),
+								.dataout(din_ddr),
+								.clkhi(outclock_wire),
+								.clklo(outclock_wire),
+								.muxsel(outclock_wire),
+								.ena(outclocken_wire)
+								`ifndef ALTERA_RESERVED_QIS
+								,
+								.areset(1'b0),
+								.clk(1'b0),
+								.phymemclock(1'b0),
+								.sreset(1'b0),
+								.dfflo(),
+								.dffhi(),
+								.devpor(1'b1),
+								.devclrn(1'b1)
+								`endif
+							);
+						end
+			end
+            else if (REGISTER_MODE == "single-register")
+            begin: out_path_sdr
+   			  reg reg_data_out /* synthesis altera_attribute="FAST_OUTPUT_REGISTER=on" */;
+                always @(posedge outclock_wire)
+                    reg_data_out <= din_fr[0];
+
+                assign din_ddr = reg_data_out;
+			end
+            else  
+            begin: out_path_reg_none
+                assign din_ddr = din_fr[0];
+            end
+        end
+    endgenerate
+
+    generate
+
+	    if (PIN_TYPE == "bidir" || PIN_TYPE == "output")
+        begin
+			wire oe_inclk_wire;
+			if (USE_ONE_REG_TO_DRIVE_OE == "true" || USE_DDIO_REG_TO_DRIVE_OE == "true")
+			begin
+				if (INVERT_OE_INCLOCK == "false")
+				begin: normal_oe_inclock
+					assign oe_inclk_wire = outclock;
+				end
+				else
+				begin: inverted_oe_inclock
+					assign oe_inclk_wire = ~outclock;
+				end
+			end
+
+			wire oe_outclocken_wire;
+			assign  oe_outclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? outclocken : 1'b1;
+
+			if (USE_DDIO_REG_TO_DRIVE_OE == "true")
+			begin
+				if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "true")
+				begin
+					if (ASYNC_MODE != "none")
+						begin: async_mode_oe_path_enhanced_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.areset(aset),
+											.ena(oe_outclocken_wire),
+											.phymemclock(phy_mem_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else if (SYNC_MODE != "none")
+						begin: sync_mode_oe_path_enhanced_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.sreset(sclr),
+											.ena(oe_outclocken_wire),
+											.phymemclock(phy_mem_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else
+						begin: oe_path_enhanced_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.ena(oe_outclocken_wire),
+											.phymemclock(phy_mem_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+				end
+				else if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "false")
+				begin
+					if (ASYNC_MODE != "none")
+						begin: async_mode_oe_path_ddr
+								fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.areset(aset),
+											.ena(oe_outclocken_wire)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.phymemclock(1'b0),
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else if (SYNC_MODE != "none")
+						begin: sync_mode_oe_path_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.sreset(sclr),
+											.ena(oe_outclocken_wire)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.phymemclock(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else
+						begin: oe_path_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.ena(oe_outclocken_wire)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.phymemclock(1'b0),
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+				end
+			end
+			else if (USE_ONE_REG_TO_DRIVE_OE == "true")
+			begin: oe_path_sdr
+					fiftyfivenm_ff oe_reg (
+							.clk(oe_inclk_wire),
+							.d(~oe),
+							.clrn(1'b1),
+							.ena(1'b1),
+							.q(oe_out)
+						);
+            end
+            else if (USE_ONE_REG_TO_DRIVE_OE == "false" && USE_DDIO_REG_TO_DRIVE_OE == "false")
+            begin: oe_path_reg_none
+				assign oe_out = ~oe;
+            end
+        end
+	endgenerate
+
+    generate
+        if (PIN_TYPE == "input" || PIN_TYPE == "bidir")
+        begin
+            wire [1:0] ddr_input;
+			wire inclock_wire;
+
+			if (REGISTER_MODE != "bypass")
+			begin
+				if (INVERT_INPUT_CLOCK == "false")
+				begin: normal_input_clock
+					assign inclock_wire = inclock;
+				end
+				else
+				begin: inverted_input_clock
+					assign inclock_wire = ~inclock;
+				end
+			end
+
+			wire inclocken_wire;
+			assign  inclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? inclocken : 1'b1;
+
+         	if (REGISTER_MODE == "ddr")
+         	begin
+		        if (USE_ENHANCED_DDR_HIO_REGISTER == "true" || USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY == "true")
+				begin
+						if (ENABLE_HR_CLOCK == "true")
+						begin
+								if (ASYNC_MODE != "none")
+									begin: async_mode_in_path_enhanced_ddr_with_halfrateresyncclk
+										fiftyfivenm_ddio_in
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.power_up(DDIO_REG_POWER_UP),
+											.invert_input_clock(INVERT_INPUT_CLOCK)
+										) fr_in_ddio (
+											.datain(buf_in),
+											.clk(inclock_wire),
+											.ena(inclocken_wire),
+											.halfrateresyncclk(hr_clock),
+											.regouthi(ddr_input[1]),
+											.regoutlo(ddr_input[0]),
+											.clkout(fr_clock),
+											.areset(aset)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.sreset(1'b0),
+											.dfflo(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+									end
+								else if (SYNC_MODE != "none")
+									begin:sync_mode_in_path_enhanced_ddr_with_halfrateresyncclk
+										fiftyfivenm_ddio_in
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.power_up(DDIO_REG_POWER_UP),
+											.invert_input_clock(INVERT_INPUT_CLOCK)
+										) fr_in_ddio (
+											.datain(buf_in),
+											.clk (inclock_wire),
+											.ena(inclocken_wire),
+											.sreset(sclr),
+											.halfrateresyncclk(hr_clock),
+											.regouthi(ddr_input[1]),
+											.regoutlo(ddr_input[0]),
+											.clkout(fr_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.dfflo(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+									end
+								else
+									begin:in_path_enhanced_ddr_with_halfrateresyncclk
+										fiftyfivenm_ddio_in
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.power_up(DDIO_REG_POWER_UP),
+											.invert_input_clock(INVERT_INPUT_CLOCK)
+										) fr_in_ddio (
+											.datain(buf_in),
+											.clk (inclock_wire),
+											.ena(inclocken_wire),
+											.halfrateresyncclk(hr_clock),
+											.regouthi(ddr_input[1]),
+											.regoutlo(ddr_input[0]),
+											.clkout(fr_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.sreset(1'b0),
+											.areset(1'b0),
+											.dfflo(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+									end
+						end
+						else
+						begin
+							if (ASYNC_MODE != "none")
+								begin: async_mode_in_path_enhanced_ddr
+									fiftyfivenm_ddio_in
+									#(
+										.async_mode(ASYNC_MODE),
+										.sync_mode(SYNC_MODE),
+										.power_up(DDIO_REG_POWER_UP),
+										.invert_input_clock(INVERT_INPUT_CLOCK)
+									) fr_in_ddio (
+										.datain(buf_in),
+										.clk(inclock_wire),
+										.ena(inclocken_wire),
+										.regouthi(ddr_input[1]),
+										.regoutlo(ddr_input[0]),
+										.clkout(fr_clock),
+										.areset(aset)
+										`ifndef ALTERA_RESERVED_QIS
+										,
+										.sreset(1'b0),
+										.dfflo(),
+										.devpor(1'b1),
+										.devclrn(1'b1),
+										.halfrateresyncclk(1'b0)
+										`endif
+									);
+								end
+							else if (SYNC_MODE != "none")
+								begin:sync_mode_in_path_enhanced_ddr
+									fiftyfivenm_ddio_in
+									#(
+										.async_mode(ASYNC_MODE),
+										.sync_mode(SYNC_MODE),
+										.power_up(DDIO_REG_POWER_UP),
+										.invert_input_clock(INVERT_INPUT_CLOCK)
+									) fr_in_ddio (
+										.datain(buf_in),
+										.clk (inclock_wire),
+										.ena(inclocken_wire),
+										.sreset(sclr),
+										.regouthi(ddr_input[1]),
+										.regoutlo(ddr_input[0]),
+										.clkout(fr_clock)
+										`ifndef ALTERA_RESERVED_QIS
+										,
+										.areset(1'b0),
+										.dfflo(),
+										.devpor(1'b1),
+										.devclrn(1'b1),
+										.halfrateresyncclk(1'b0)
+										`endif
+									);
+								end
+							else
+								begin:in_path_enhanced_ddr
+									fiftyfivenm_ddio_in
+									#(
+										.async_mode(ASYNC_MODE),
+										.sync_mode(SYNC_MODE),
+										.power_up(DDIO_REG_POWER_UP),
+										.invert_input_clock(INVERT_INPUT_CLOCK)
+									) fr_in_ddio (
+										.datain(buf_in),
+										.clk (inclock_wire),
+										.ena(inclocken_wire),
+										.regouthi(ddr_input[1]),
+										.regoutlo(ddr_input[0]),
+										.clkout(fr_clock)
+										`ifndef ALTERA_RESERVED_QIS
+										,
+										.sreset(1'b0),
+										.areset(1'b0),
+										.dfflo(),
+										.devpor(1'b1),
+										.devclrn(1'b1),
+										.halfrateresyncclk(1'b0)
+										`endif
+									);
+								end
+						end
+				end
+				else if (ENABLE_PHASE_DETECTOR_FOR_CK == "true")
+					begin
+						assign mimic_clock = buf_in;
+					end
+				else
+				begin: in_path_ddr
+					wire input_cell_l_q;
+					wire input_aset;
+
+					assign input_aset = ( ASYNC_MODE == "clear") ? !aset : aset;
+
+					fiftyfivenm_ff input_cell_l (
+						.clk(inclock_wire),
+						.d(buf_in),
+						.clrn(input_aset),
+						.ena(inclocken_wire),
+						.q(input_cell_l_q)
+					);
+
+					fiftyfivenm_ff input_latch_l (
+						.clk(~inclock_wire),
+						.d(input_cell_l_q),
+						.clrn(input_aset),
+						.ena(inclocken_wire),
+						.q(ddr_input[0])
+					);
+
+					fiftyfivenm_ff input_cell_h (
+						.clk(~inclock_wire),
+						.d(buf_in),
+						.clrn(input_aset),
+						.ena(inclocken_wire),
+						.q(ddr_input[1])
+					);
+
+				end
+			end
+			else if (REGISTER_MODE == "single-register")
+            begin: in_path_sdr
+                reg reg_data_in /* synthesis altera_attribute="FAST_INPUT_REGISTER=on" */;
+                always @(posedge inclock_wire) begin
+                    reg_data_in <= buf_in;
+                end
+                assign ddr_input[0] = reg_data_in;
+            end
+            else
+            begin: in_path_reg_none
+                assign ddr_input[0] = buf_in;
+            end
+
+            assign dout[DATA_SIZE - 1:0] = ddr_input[DATA_SIZE - 1:0];
+
+        end
+    endgenerate
+
+	generate
+		if (PIN_TYPE == "output" || PIN_TYPE == "bidir")
+		begin
+			if(BUFFER_TYPE == "pseudo_differential")
+			begin: pseudo_diff_output_buf
+
+				wire wire_pseudo_diff_o;
+				wire wire_pseudo_diff_o_bar;
+
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf_a (
+					.i(wire_pseudo_diff_o),
+					.oe(~oe_out),
+					.o(pad),
+					.obar()
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf_a_bar (
+					.i(wire_pseudo_diff_o_bar),
+					.oe(~oe_out),
+					.o(pad_b),
+					.obar()
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+
+				fiftyfivenm_pseudo_diff_out pseudo_diff_a
+				(
+					.i(din_ddr),
+					.o(wire_pseudo_diff_o),
+					.obar(wire_pseudo_diff_o_bar)
+				);
+
+
+
+			end
+			else if (BUFFER_TYPE == "true_differential")
+			begin: true_diff_output_buf
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf (
+					.i(din_ddr),
+					.oe(~oe_out),
+					.o(pad),
+					.obar(pad_b)
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+			end
+			else
+			begin: output_buf
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf (
+					.i(din_ddr),
+					.oe(~oe_out),
+					.o(pad),
+					.obar()
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+			end
+		end
+	endgenerate
+
+	assign nsleep_in = (ENABLE_NSLEEP_PORT == "true") ? nsleep : 1'b1;
+
+	generate
+		if (PIN_TYPE == "input" || PIN_TYPE == "bidir")
+		begin
+			if(BUFFER_TYPE == "true_differential" || BUFFER_TYPE == "pseudo_differential")
+			begin: diff_input_buf
+				if (ENABLE_NSLEEP_PORT == "true")
+				begin: diff_input_buf_with_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.ibar(pad_b),
+						.o(buf_in),
+						.nsleep(nsleep_in)
+					);
+				end
+				else
+				begin: diff_input_buf_without_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.ibar(pad_b),
+						.o(buf_in)
+					);
+				end
+			end
+			else
+			begin:input_buf
+				if (ENABLE_NSLEEP_PORT == "true")
+				begin: input_buf_with_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.o(buf_in),
+						.nsleep(nsleep_in)
+						`ifndef ALTERA_RESERVED_QIS
+						,
+						.ibar(1'b0)
+						`endif
+					);
+				end
+				else
+				begin: input_buf_without_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.o(buf_in)
+						`ifndef ALTERA_RESERVED_QIS
+						,
+						.ibar(1'b0)
+						`endif
+					);
+				end
+			end
+		end
+	endgenerate
+
+	generate
+		if (PIN_TYPE == "output")
+		begin
+			assign dout = {DATA_SIZE{1'b0}};
+		end
+
+		if (PIN_TYPE == "output" || REGISTER_MODE != "ddr" || USE_ENHANCED_DDR_HIO_REGISTER == "false")
+		begin
+			assign fr_clock = 1'b0;
+		end
+
+		if (PIN_TYPE == "input" || PIN_TYPE == "output" || REGISTER_MODE != "ddr" || ENABLE_PHASE_DETECTOR_FOR_CK == "false")
+		begin
+			assign mimic_clock = 1'b0;
+		end
+	endgenerate
+
+endmodule
+
+module altera_gpio_lite(
+	inclock,
+	outclock,
+	inclocken,
+	outclocken,
+	oe,
+	din,
+	dout,
+	pad_io,
+	pad_io_b,
+	pad_in,
+	pad_in_b,
+	pad_out,
+	pad_out_b,
+	aset,
+	aclr,
+	phy_mem_clock,
+	sclr,
+	hr_clock,
+	fr_clock,
+	invert_hr_clock,
+	mimic_clock,
+	nsleep
+);
+
+	parameter PIN_TYPE = "output"; 
+	parameter BUFFER_TYPE = "single-ended"; 
+	parameter REGISTER_MODE = "bypass"; 
+	parameter SIZE = 4;
+	parameter ASYNC_MODE = "none"; 
+	parameter SYNC_MODE = "none"; 
+	parameter BUS_HOLD = "false"; 
+	parameter SET_REGISTER_OUTPUTS_HIGH = "false"; 
+	parameter INVERT_OUTPUT = "false"; 
+	parameter INVERT_INPUT_CLOCK = "false"; 
+	parameter INVERT_OUTPUT_CLOCK = "false"; 
+	parameter INVERT_OE_INCLOCK = "false"; 
+	parameter USE_ONE_REG_TO_DRIVE_OE = "false"; 
+	parameter USE_DDIO_REG_TO_DRIVE_OE = "false"; 
+	parameter OPEN_DRAIN_OUTPUT = "false"; 
+	parameter USE_ADVANCED_DDR_FEATURES = "false"; 
+	parameter USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY = "false"; 
+	parameter INVERT_CLKDIV_INPUT_CLOCK = "false"; 
+	parameter ENABLE_HR_CLOCK = "false"; 
+	parameter ENABLE_OE_HALF_CYCLE_DELAY = "true"; 
+	parameter ENABLE_OE_PORT = "false"; 
+	parameter ENABLE_CLOCK_ENA_PORT = "false"; 
+	parameter ENABLE_PHASE_INVERT_CTRL_PORT = "false"; 
+	parameter ENABLE_PHASE_DETECTOR_FOR_CK = "false"; 
+	parameter ENABLE_NSLEEP_PORT = "false"; 
+
+    localparam USE_ENHANCED_DDR_HIO_REGISTER = USE_ADVANCED_DDR_FEATURES;
+	localparam BYPASS_THREE_QUARTER_REGISTER = (USE_ADVANCED_DDR_FEATURES == "true") ? "false" : "true";
+	localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? 2 : 1;
+
+	input inclock;
+	input outclock;
+	input inclocken;
+	input outclocken;
+	input [SIZE - 1:0] oe;
+	input [SIZE - 1:0] nsleep;
+	input [SIZE * DATA_SIZE - 1:0] din;
+	output [SIZE * DATA_SIZE - 1:0] dout;
+	inout [SIZE - 1:0] pad_io;
+	inout [SIZE - 1:0] pad_io_b;
+	input [SIZE - 1:0] pad_in;
+	input [SIZE - 1:0] pad_in_b;
+	output [SIZE - 1:0] pad_out;
+	output [SIZE - 1:0] pad_out_b;
+	input aset;
+	input aclr;
+	input sclr;
+	input phy_mem_clock;
+	input invert_hr_clock;
+	output [SIZE - 1:0] fr_clock;
+	output wire hr_clock;
+	output [SIZE - 1:0] mimic_clock;
+
+	wire [SIZE * DATA_SIZE - 1:0] din_reordered;
+	wire [SIZE * DATA_SIZE - 1:0] dout_reordered;
+	wire aclr_aset_wire;
+	wire sclr_wire;
+	wire [SIZE - 1:0] pad_io;
+	wire [SIZE - 1:0] pad_io_b;
+
+
+	assign aclr_aset_wire = (ASYNC_MODE == "clear") ? aclr : (ASYNC_MODE == "preset") ? aset : 1'b1;
+	assign sclr_wire = (SYNC_MODE == "clear") ? sclr : 1'b0;
+
+	generate
+		if (PIN_TYPE == "input")
+		begin
+			assign pad_io = pad_in;
+			assign pad_io_b = pad_in_b;
+			assign pad_out = {SIZE{1'b0}};
+			assign pad_out_b = {SIZE{1'b0}};
+		end
+		else if (PIN_TYPE == "output")
+		begin
+			assign pad_out = pad_io;
+			assign pad_out_b = pad_io_b;
+		end
+		else begin
+			assign pad_out = {SIZE{1'b0}};
+			assign pad_out_b = {SIZE{1'b0}};
+		end
+	endgenerate
+
+	genvar j, k;
+	generate
+		begin : reorder
+			for(j = 0; j < SIZE ; j = j + 1) begin : j_loop
+				for(k = 0; k < DATA_SIZE; k = k + 1) begin : k_d_loop
+					assign din_reordered[j * DATA_SIZE + k] = din[j + k * SIZE];
+					assign dout[j + k * SIZE] = dout_reordered[j * DATA_SIZE + k];
+				end
+			end
+		end
+	endgenerate
+
+	genvar i;
+	generate
+		begin : gpio_one_bit
+			for(i = 0 ; i < SIZE ; i = i + 1) begin : i_loop
+				wire oe_wire;
+				wire nsleep_wire;
+
+
+				assign oe_wire = (PIN_TYPE == "output" && ENABLE_OE_PORT == "false") ? 1'b1 :
+				                  (PIN_TYPE == "input") ? 1'b0 : oe[i];
+
+
+				assign nsleep_wire = (PIN_TYPE == "input" && ENABLE_NSLEEP_PORT == "false") ? 1'b1 :
+														(PIN_TYPE == "output") ? 1'b0 : nsleep[i];
+
+				altgpio_one_bit #(
+					.PIN_TYPE(PIN_TYPE),
+					.BUFFER_TYPE(BUFFER_TYPE),
+					.REGISTER_MODE(REGISTER_MODE),
+					.ASYNC_MODE(ASYNC_MODE),
+					.SYNC_MODE(SYNC_MODE),
+					.BUS_HOLD(BUS_HOLD),
+					.SET_REGISTER_OUTPUTS_HIGH(SET_REGISTER_OUTPUTS_HIGH),
+					.USE_ENHANCED_DDR_HIO_REGISTER(USE_ENHANCED_DDR_HIO_REGISTER),
+					.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY(USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY),
+					.BYPASS_THREE_QUARTER_REGISTER(BYPASS_THREE_QUARTER_REGISTER),
+					.INVERT_OUTPUT(INVERT_OUTPUT),
+					.INVERT_INPUT_CLOCK(INVERT_INPUT_CLOCK),
+					.INVERT_OUTPUT_CLOCK(INVERT_OUTPUT_CLOCK),
+					.INVERT_OE_INCLOCK(INVERT_OE_INCLOCK),
+					.USE_ONE_REG_TO_DRIVE_OE(USE_ONE_REG_TO_DRIVE_OE),
+					.USE_DDIO_REG_TO_DRIVE_OE(USE_DDIO_REG_TO_DRIVE_OE),
+					.OPEN_DRAIN_OUTPUT(OPEN_DRAIN_OUTPUT),
+					.ENABLE_OE_HALF_CYCLE_DELAY(ENABLE_OE_HALF_CYCLE_DELAY),
+					.ENABLE_CLOCK_ENA_PORT(ENABLE_CLOCK_ENA_PORT),
+					.ENABLE_HR_CLOCK(ENABLE_HR_CLOCK),
+					.ENABLE_PHASE_DETECTOR_FOR_CK(ENABLE_PHASE_DETECTOR_FOR_CK),
+					.ENABLE_NSLEEP_PORT(ENABLE_NSLEEP_PORT)
+				) altgpio_bit_i (
+					.inclock(inclock),
+					.outclock(outclock),
+					.phy_mem_clock(phy_mem_clock),
+					.inclocken(inclocken),
+					.outclocken(outclocken),
+					.oe(oe_wire),
+					.din(din_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]),
+					.dout(dout_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]),
+					.pad(pad_io[i]),
+					.pad_b(pad_io_b[i]),
+					.aset(aclr_aset_wire),
+					.sclr(sclr_wire),
+					.fr_clock(fr_clock[i]),
+					.hr_clock(hr_clock),
+					.mimic_clock(mimic_clock[i]),
+					.nsleep(nsleep_wire)
+				);
+			end
+		end
+	endgenerate
+
+	generate
+		if ((PIN_TYPE == "input" || PIN_TYPE == "bidir") && (ENABLE_HR_CLOCK == "true"))
+		begin
+			if (ENABLE_PHASE_INVERT_CTRL_PORT == "true")
+			begin
+				if (SYNC_MODE == "clear")
+				begin : clock_divider_sync_mode_invert_hr_clock
+					fiftyfivenm_io_clock_divider
+					#(
+						.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+						.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+						.sync_mode(SYNC_MODE)
+					) io_clkdiv (
+						.clk(inclock),
+						.phaseinvertctrl(invert_hr_clock),
+						.sreset(sclr_wire),
+						.clkout(hr_clock)
+					);
+				end
+				else
+				begin : clock_divider_invert_hr_clock
+					fiftyfivenm_io_clock_divider
+						#(
+							.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+							.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+							.sync_mode(SYNC_MODE)
+						) io_clkdiv (
+							.clk(inclock),
+							.phaseinvertctrl(invert_hr_clock),
+							.clkout(hr_clock)
+							`ifndef ALTERA_RESERVED_QIS
+							,
+							.sreset(1'b0)
+							`endif
+						);
+				end
+			end
+			else
+			begin
+				if (SYNC_MODE == "clear")
+				begin : clock_divider_sync_mode
+					fiftyfivenm_io_clock_divider
+					#(
+						.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+						.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+						.sync_mode(SYNC_MODE)
+					) io_clkdiv (
+						.clk(inclock),
+						.sreset(sclr_wire),
+						.clkout(hr_clock)
+						`ifndef ALTERA_RESERVED_QIS
+						,
+						.phaseinvertctrl(1'b0)
+						`endif
+					);
+				end
+				else
+				begin : clock_divider
+					fiftyfivenm_io_clock_divider
+						#(
+							.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+							.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+							.sync_mode(SYNC_MODE)
+						) io_clkdiv (
+							.clk(inclock),
+							.clkout(hr_clock)
+							`ifndef ALTERA_RESERVED_QIS
+							,
+							.sreset(1'b0),
+							.phaseinvertctrl(1'b0)
+							`endif
+						);
+				end
+			end
+		end
+		else begin
+			assign hr_clock = 1'b0;
+		end
+	endgenerate
+
+endmodule
Index: atari_chips/gtia/osc_out.bsf
===================================================================
--- atari_chips/gtia/osc_out.bsf	(nonexistent)
+++ atari_chips/gtia/osc_out.bsf	(revision 1318)
@@ -0,0 +1,70 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2018  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 208 144)
+	(text "osc_out" (rect 81 -1 112 11)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 128 20 140)(font "Arial" ))
+	(port
+		(pt 0 72)
+		(input)
+		(text "outclock" (rect 0 0 31 12)(font "Arial" (font_size 8)))
+		(text "outclock" (rect 4 61 52 72)(font "Arial" (font_size 8)))
+		(line (pt 0 72)(pt 64 72)(line_width 1))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "din[1..0]" (rect 0 0 29 12)(font "Arial" (font_size 8)))
+		(text "din[1..0]" (rect 4 101 58 112)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 64 112)(line_width 3))
+	)
+	(port
+		(pt 208 72)
+		(output)
+		(text "pad_out" (rect 0 0 31 12)(font "Arial" (font_size 8)))
+		(text "pad_out" (rect 166 61 208 72)(font "Arial" (font_size 8)))
+		(line (pt 208 72)(pt 144 72)(line_width 1))
+	)
+	(drawing
+		(text "outclock" (rect 18 43 84 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 69 67 174 144)(font "Arial" (color 0 0 0)))
+		(text "din" (rect 48 83 114 179)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 69 107 174 224)(font "Arial" (color 0 0 0)))
+		(text "pad_out" (rect 145 43 332 99)(font "Arial" (color 128 0 0)(font_size 9)))
+		(text "export" (rect 114 67 264 144)(font "Arial" (color 0 0 0)))
+		(text " altera_gpio_lite " (rect 140 128 388 266)(font "Arial" ))
+		(line (pt 64 32)(pt 144 32)(line_width 1))
+		(line (pt 144 32)(pt 144 128)(line_width 1))
+		(line (pt 64 128)(pt 144 128)(line_width 1))
+		(line (pt 64 32)(pt 64 128)(line_width 1))
+		(line (pt 65 52)(pt 65 76)(line_width 1))
+		(line (pt 66 52)(pt 66 76)(line_width 1))
+		(line (pt 65 92)(pt 65 116)(line_width 1))
+		(line (pt 66 92)(pt 66 116)(line_width 1))
+		(line (pt 143 52)(pt 143 76)(line_width 1))
+		(line (pt 142 52)(pt 142 76)(line_width 1))
+		(line (pt 0 0)(pt 208 0)(line_width 1))
+		(line (pt 208 0)(pt 208 144)(line_width 1))
+		(line (pt 0 144)(pt 208 144)(line_width 1))
+		(line (pt 0 0)(pt 0 144)(line_width 1))
+	)
+)
Index: atari_chips/gtia/osc_out.cmp
===================================================================
--- atari_chips/gtia/osc_out.cmp	(nonexistent)
+++ atari_chips/gtia/osc_out.cmp	(revision 1318)
@@ -0,0 +1,8 @@
+	component osc_out is
+		port (
+			outclock : in  std_logic                    := 'X';             -- export
+			din      : in  std_logic_vector(1 downto 0) := (others => 'X'); -- export
+			pad_out  : out std_logic_vector(0 downto 0)                     -- export
+		);
+	end component osc_out;
+
Index: atari_chips/gtia/osc_out.sip
===================================================================
--- atari_chips/gtia/osc_out.sip	(nonexistent)
+++ atari_chips/gtia/osc_out.sip	(revision 1318)
@@ -0,0 +1,8 @@
+set_global_assignment -entity "osc_out" -library "lib_osc_out" -name IP_TOOL_NAME "altera_gpio_lite"
+set_global_assignment -entity "osc_out" -library "lib_osc_out" -name IP_TOOL_VERSION "18.0"
+set_global_assignment -entity "osc_out" -library "lib_osc_out" -name IP_TOOL_ENV "mwpim"
+set_global_assignment -library "lib_osc_out" -name SPD_FILE [file join $::quartus(sip_path) "osc_out.spd"]
+
+set_global_assignment -library "lib_osc_out" -name MISC_FILE [file join $::quartus(sip_path) "osc_out_sim/osc_out.vhd"]
+set_global_assignment -library "lib_osc_out" -name MISC_FILE [file join $::quartus(sip_path) "osc_out_sim/altera_gpio_lite/altera_gpio_lite.sv"]
+set_global_assignment -library "lib_osc_out" -name MISC_FILE [file join $::quartus(sip_path) "osc_out_sim/altera_gpio_lite/mentor/altera_gpio_lite.sv"]
Index: atari_chips/gtia/osc_out.vhd
===================================================================
--- atari_chips/gtia/osc_out.vhd	(nonexistent)
+++ atari_chips/gtia/osc_out.vhd	(revision 1318)
@@ -0,0 +1,187 @@
+-- megafunction wizard: %GPIO Lite Intel FPGA IP v18.0%
+-- GENERATION: XML
+-- osc_out.vhd
+
+-- Generated using ACDS version 18.0 614
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity osc_out is
+	port (
+		outclock : in  std_logic                    := '0';             -- outclock.export
+		din      : in  std_logic_vector(1 downto 0) := (others => '0'); --      din.export
+		pad_out  : out std_logic_vector(0 downto 0)                     --  pad_out.export
+	);
+end entity osc_out;
+
+architecture rtl of osc_out is
+	component altera_gpio_lite is
+		generic (
+			PIN_TYPE                                 : string  := "output";
+			SIZE                                     : integer := 4;
+			REGISTER_MODE                            : string  := "bypass";
+			BUFFER_TYPE                              : string  := "single-ended";
+			ASYNC_MODE                               : string  := "none";
+			SYNC_MODE                                : string  := "none";
+			BUS_HOLD                                 : string  := "false";
+			OPEN_DRAIN_OUTPUT                        : string  := "false";
+			ENABLE_OE_PORT                           : string  := "false";
+			ENABLE_NSLEEP_PORT                       : string  := "false";
+			ENABLE_CLOCK_ENA_PORT                    : string  := "false";
+			SET_REGISTER_OUTPUTS_HIGH                : string  := "false";
+			INVERT_OUTPUT                            : string  := "false";
+			INVERT_INPUT_CLOCK                       : string  := "false";
+			USE_ONE_REG_TO_DRIVE_OE                  : string  := "false";
+			USE_DDIO_REG_TO_DRIVE_OE                 : string  := "false";
+			USE_ADVANCED_DDR_FEATURES                : string  := "false";
+			USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY : string  := "false";
+			ENABLE_OE_HALF_CYCLE_DELAY               : string  := "true";
+			INVERT_CLKDIV_INPUT_CLOCK                : string  := "false";
+			ENABLE_PHASE_INVERT_CTRL_PORT            : string  := "false";
+			ENABLE_HR_CLOCK                          : string  := "false";
+			INVERT_OUTPUT_CLOCK                      : string  := "false";
+			INVERT_OE_INCLOCK                        : string  := "false";
+			ENABLE_PHASE_DETECTOR_FOR_CK             : string  := "false"
+		);
+		port (
+			outclock        : in    std_logic                    := 'X';             -- export
+			din             : in    std_logic_vector(1 downto 0) := (others => 'X'); -- export
+			pad_out         : out   std_logic_vector(0 downto 0);                    -- export
+			outclocken      : in    std_logic                    := 'X';             -- export
+			inclock         : in    std_logic                    := 'X';             -- export
+			inclocken       : in    std_logic                    := 'X';             -- export
+			fr_clock        : out   std_logic_vector(0 downto 0);                    -- export
+			hr_clock        : out   std_logic;                                       -- export
+			invert_hr_clock : in    std_logic                    := 'X';             -- export
+			phy_mem_clock   : in    std_logic                    := 'X';             -- export
+			mimic_clock     : out   std_logic_vector(0 downto 0);                    -- export
+			dout            : out   std_logic_vector(1 downto 0);                    -- export
+			pad_io          : inout std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			pad_io_b        : inout std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			pad_in          : in    std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			pad_in_b        : in    std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			pad_out_b       : out   std_logic_vector(0 downto 0);                    -- export
+			aset            : in    std_logic                    := 'X';             -- export
+			aclr            : in    std_logic                    := 'X';             -- export
+			sclr            : in    std_logic                    := 'X';             -- export
+			nsleep          : in    std_logic_vector(0 downto 0) := (others => 'X'); -- export
+			oe              : in    std_logic_vector(0 downto 0) := (others => 'X')  -- export
+		);
+	end component altera_gpio_lite;
+
+begin
+
+	osc_out_inst : component altera_gpio_lite
+		generic map (
+			PIN_TYPE                                 => "output",
+			SIZE                                     => 1,
+			REGISTER_MODE                            => "ddr",
+			BUFFER_TYPE                              => "single-ended",
+			ASYNC_MODE                               => "none",
+			SYNC_MODE                                => "none",
+			BUS_HOLD                                 => "false",
+			OPEN_DRAIN_OUTPUT                        => "false",
+			ENABLE_OE_PORT                           => "false",
+			ENABLE_NSLEEP_PORT                       => "false",
+			ENABLE_CLOCK_ENA_PORT                    => "false",
+			SET_REGISTER_OUTPUTS_HIGH                => "false",
+			INVERT_OUTPUT                            => "false",
+			INVERT_INPUT_CLOCK                       => "false",
+			USE_ONE_REG_TO_DRIVE_OE                  => "false",
+			USE_DDIO_REG_TO_DRIVE_OE                 => "false",
+			USE_ADVANCED_DDR_FEATURES                => "false",
+			USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY => "false",
+			ENABLE_OE_HALF_CYCLE_DELAY               => "true",
+			INVERT_CLKDIV_INPUT_CLOCK                => "false",
+			ENABLE_PHASE_INVERT_CTRL_PORT            => "false",
+			ENABLE_HR_CLOCK                          => "false",
+			INVERT_OUTPUT_CLOCK                      => "false",
+			INVERT_OE_INCLOCK                        => "false",
+			ENABLE_PHASE_DETECTOR_FOR_CK             => "false"
+		)
+		port map (
+			outclock        => outclock, -- outclock.export
+			din             => din,      --      din.export
+			pad_out         => pad_out,  --  pad_out.export
+			outclocken      => '1',      -- (terminated)
+			inclock         => '0',      -- (terminated)
+			inclocken       => '0',      -- (terminated)
+			fr_clock        => open,     -- (terminated)
+			hr_clock        => open,     -- (terminated)
+			invert_hr_clock => '0',      -- (terminated)
+			phy_mem_clock   => '0',      -- (terminated)
+			mimic_clock     => open,     -- (terminated)
+			dout            => open,     -- (terminated)
+			pad_io          => open,     -- (terminated)
+			pad_io_b        => open,     -- (terminated)
+			pad_in          => "0",      -- (terminated)
+			pad_in_b        => "0",      -- (terminated)
+			pad_out_b       => open,     -- (terminated)
+			aset            => '0',      -- (terminated)
+			aclr            => '0',      -- (terminated)
+			sclr            => '0',      -- (terminated)
+			nsleep          => "0",      -- (terminated)
+			oe              => "0"       -- (terminated)
+		);
+
+end architecture rtl; -- of osc_out
+-- Retrieval info: <?xml version="1.0"?>
+--<!--
+--	Generated by Altera MegaWizard Launcher Utility version 1.0
+--	************************************************************
+--	THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--	************************************************************
+--	Copyright (C) 1991-2018 Altera Corporation
+--	Any megafunction design, and related net list (encrypted or decrypted),
+--	support information, device programming or simulation file, and any other
+--	associated documentation or information provided by Altera or a partner
+--	under Altera's Megafunction Partnership Program may be used only to
+--	program PLD devices (but not masked PLD devices) from Altera.  Any other
+--	use of such megafunction design, net list, support information, device
+--	programming or simulation file, or any other related documentation or
+--	information is prohibited for any other purpose, including, but not
+--	limited to modification, reverse engineering, de-compiling, or use with
+--	any other silicon devices, unless such use is explicitly licensed under
+--	a separate agreement with Altera or a megafunction partner.  Title to
+--	the intellectual property, including patents, copyrights, trademarks,
+--	trade secrets, or maskworks, embodied in any such megafunction design,
+--	net list, support information, device programming or simulation file, or
+--	any other related documentation or information provided by Altera or a
+--	megafunction partner, remains with Altera, the megafunction partner, or
+--	their respective licensors.  No other licenses, including any licenses
+--	needed under any third party's intellectual property, are provided herein.
+---->
+-- Retrieval info: <instance entity-name="altera_gpio_lite" version="18.0" >
+-- Retrieval info: 	<generic name="DEVICE_FAMILY" value="MAX 10" />
+-- Retrieval info: 	<generic name="PIN_TYPE" value="output" />
+-- Retrieval info: 	<generic name="SIZE" value="1" />
+-- Retrieval info: 	<generic name="gui_true_diff_buf" value="false" />
+-- Retrieval info: 	<generic name="gui_pseudo_diff_buf" value="false" />
+-- Retrieval info: 	<generic name="gui_bus_hold" value="false" />
+-- Retrieval info: 	<generic name="gui_open_drain" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_oe_port" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_nsleep_port" value="false" />
+-- Retrieval info: 	<generic name="gui_io_reg_mode" value="ddr" />
+-- Retrieval info: 	<generic name="gui_enable_aclr_port" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_aset_port" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_sclr_port" value="false" />
+-- Retrieval info: 	<generic name="gui_set_registers_to_power_up_high" value="false" />
+-- Retrieval info: 	<generic name="gui_clock_enable" value="false" />
+-- Retrieval info: 	<generic name="gui_invert_output" value="false" />
+-- Retrieval info: 	<generic name="gui_invert_input_clock" value="false" />
+-- Retrieval info: 	<generic name="gui_use_register_to_drive_obuf_oe" value="false" />
+-- Retrieval info: 	<generic name="gui_use_ddio_reg_to_drive_oe" value="false" />
+-- Retrieval info: 	<generic name="gui_use_advanced_ddr_features" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_phase_detector_for_ck" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_oe_half_cycle_delay" value="true" />
+-- Retrieval info: 	<generic name="gui_enable_hr_clock" value="false" />
+-- Retrieval info: 	<generic name="gui_enable_invert_hr_clock_port" value="false" />
+-- Retrieval info: 	<generic name="gui_invert_clkdiv_input_clock" value="false" />
+-- Retrieval info: 	<generic name="gui_invert_output_clock" value="false" />
+-- Retrieval info: 	<generic name="gui_invert_oe_inclock" value="false" />
+-- Retrieval info: 	<generic name="gui_use_hardened_ddio_input_registers" value="false" />
+-- Retrieval info: </instance>
+-- IPFS_FILES : osc_out.vho
+-- RELATED_FILES: osc_out.vhd, altera_gpio_lite.sv
Index: atari_chips/gtia/osc_out_sim/altera_gpio_lite/altera_gpio_lite.sv
===================================================================
--- atari_chips/gtia/osc_out_sim/altera_gpio_lite/altera_gpio_lite.sv	(nonexistent)
+++ atari_chips/gtia/osc_out_sim/altera_gpio_lite/altera_gpio_lite.sv	(revision 1318)
@@ -0,0 +1,1200 @@
+// (C) 2001-2018 Intel Corporation. All rights reserved.
+// Your use of Intel Corporation's design tools, logic functions and other 
+// software and tools, and its AMPP partner logic functions, and any output 
+// files from any of the foregoing (including device programming or simulation 
+// files), and any associated documentation or information are expressly subject 
+// to the terms and conditions of the Intel Program License Subscription 
+// Agreement, Intel FPGA IP License Agreement, or other applicable 
+// license agreement, including, without limitation, that your use is for the 
+// sole purpose of programming logic devices manufactured by Intel and sold by 
+// Intel or its authorized distributors.  Please refer to the applicable 
+// agreement for further details.
+
+
+`timescale 1 ps / 1 ps
+
+module altgpio_one_bit(
+	inclock,
+	outclock,
+	phy_mem_clock,
+	inclocken,
+	outclocken,
+	oe,
+	din,
+	dout,
+	pad,
+	pad_b,
+	aset,
+	sclr,
+	hr_clock,
+	fr_clock,
+	mimic_clock,
+	nsleep
+);
+
+	parameter PIN_TYPE = "output"; 
+	parameter BUFFER_TYPE = "single-ended"; 
+	parameter REGISTER_MODE = "bypass"; 
+	parameter ASYNC_MODE = "none"; 
+	parameter SYNC_MODE = "none"; 
+	parameter BUS_HOLD = "false"; 
+	parameter SET_REGISTER_OUTPUTS_HIGH = "false";  
+	parameter USE_ENHANCED_DDR_HIO_REGISTER = "false"; 
+	parameter BYPASS_THREE_QUARTER_REGISTER = "true"; 
+	parameter INVERT_OUTPUT = "false"; 
+	parameter INVERT_INPUT_CLOCK = "false"; 
+	parameter INVERT_OUTPUT_CLOCK = "false"; 
+	parameter INVERT_OE_INCLOCK = "false"; 
+	parameter USE_ONE_REG_TO_DRIVE_OE = "false"; 
+	parameter USE_DDIO_REG_TO_DRIVE_OE = "false"; 
+	parameter OPEN_DRAIN_OUTPUT = "false"; 
+	parameter ENABLE_OE_HALF_CYCLE_DELAY = "true"; 
+	parameter USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY = "false"; 
+	parameter ENABLE_CLOCK_ENA_PORT = "false"; 
+	parameter ENABLE_HR_CLOCK = "false"; 
+	parameter ENABLE_PHASE_DETECTOR_FOR_CK = "false"; 
+	parameter ENABLE_NSLEEP_PORT = "false"; 
+
+	localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? 2:1;
+	localparam DDIO_REG_POWER_UP = (ASYNC_MODE == "preset" || SET_REGISTER_OUTPUTS_HIGH == "true") ? "high" : "low";
+
+	input inclock;
+	input outclock;
+	input inclocken;
+	input outclocken;
+	input oe;
+	input nsleep;
+	input [DATA_SIZE - 1:0] din;
+	output [DATA_SIZE - 1:0] dout;
+	inout pad;
+	inout pad_b;
+	input aset;
+	input sclr;
+	input phy_mem_clock;
+	input hr_clock;
+	(* altera_attribute = "-name GLOBAL_SIGNAL\"OFF\"" *) output fr_clock;
+	output mimic_clock;
+
+	wire din_ddr;
+	wire buf_in;
+
+	wire oe_out;
+	wire nsleep_in;
+
+    generate
+        if (PIN_TYPE == "output" || PIN_TYPE == "bidir")
+        begin
+			wire [1:0] din_fr;
+            if (INVERT_OUTPUT == "false")
+			begin
+				assign din_fr = din;
+			end
+			else
+			begin
+				assign din_fr = ~din;
+			end
+
+			wire outclock_wire;
+			if (REGISTER_MODE != "bypass")
+			begin
+				if (INVERT_OUTPUT_CLOCK == "false")
+				begin: normal_input_clock
+					assign outclock_wire = outclock;
+				end
+				else
+				begin: inverted_output_clock
+					assign outclock_wire = ~outclock;
+				end
+			end
+
+			wire outclocken_wire;
+			assign  outclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? outclocken : 1'b1;
+
+			if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "true")
+			begin
+				if (ASYNC_MODE != "none")
+					begin: async_mode_out_path_enhanced_ddr
+								fiftyfivenm_ddio_out
+								#(
+									.async_mode(ASYNC_MODE),
+									.sync_mode(SYNC_MODE),
+									.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+									.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+									.power_up(DDIO_REG_POWER_UP),
+									.use_new_clocking_model("true")
+								) fr_out_data_ddio (
+									.datainhi(din_fr[0]),
+									.datainlo(din_fr[1]),
+									.dataout(din_ddr),
+									.clkhi(outclock_wire),
+									.clklo(outclock_wire),
+									.muxsel(outclock_wire),
+									.areset(aset),
+									.ena(outclocken_wire),
+									.phymemclock(phy_mem_clock)
+									`ifndef ALTERA_RESERVED_QIS
+									,
+									.clk (outclock_wire),
+									.sreset(1'b0),
+									.dfflo(),
+									.dffhi(),
+									.devpor(1'b1),
+									.devclrn(1'b1)
+									`endif
+								);
+					end
+				else if (SYNC_MODE != "none")
+					begin: sync_mode_out_path_enhanced_ddr
+								fiftyfivenm_ddio_out
+								#(
+									.async_mode(ASYNC_MODE),
+									.sync_mode(SYNC_MODE),
+									.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+									.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+									.power_up(DDIO_REG_POWER_UP),
+									.use_new_clocking_model("true")
+								) fr_out_data_ddio (
+									.datainhi(din_fr[0]),
+									.datainlo(din_fr[1]),
+									.dataout(din_ddr),
+									.clkhi(outclock_wire),
+									.clklo(outclock_wire),
+									.muxsel(outclock_wire),
+									.sreset(sclr),
+									.ena(outclocken_wire),
+									.phymemclock(phy_mem_clock)
+									`ifndef ALTERA_RESERVED_QIS
+									,
+									.clk (outclock_wire),
+									.areset(1'b0),
+									.dfflo(),
+									.dffhi(),
+									.devpor(1'b1),
+									.devclrn(1'b1)
+									`endif
+								);
+					end
+				else
+					begin: out_path_enhanced_ddr
+								fiftyfivenm_ddio_out
+								#(
+									.async_mode(ASYNC_MODE),
+									.sync_mode(SYNC_MODE),
+									.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+									.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+									.power_up(DDIO_REG_POWER_UP),
+									.use_new_clocking_model("true")
+								) fr_out_data_ddio (
+									.datainhi(din_fr[0]),
+									.datainlo(din_fr[1]),
+									.dataout(din_ddr),
+									.clkhi(outclock_wire),
+									.clklo(outclock_wire),
+									.muxsel(outclock_wire),
+									.ena(outclocken_wire),
+									.phymemclock(phy_mem_clock)
+									`ifndef ALTERA_RESERVED_QIS
+									,
+									.areset(1'b0),
+									.clk(1'b0),
+									.sreset(1'b0),
+									.dfflo(),
+									.dffhi(),
+									.devpor(1'b1),
+									.devclrn(1'b1)
+									`endif
+								);
+					end
+			end
+			else if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "false")
+			begin
+				if (ASYNC_MODE != "none")
+						begin: async_mode_out_path_ddr
+							fiftyfivenm_ddio_out
+							#(
+								.async_mode(ASYNC_MODE),
+								.sync_mode(SYNC_MODE),
+								.power_up(DDIO_REG_POWER_UP),
+								.use_new_clocking_model("true"),
+								.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+							) fr_out_data_ddio (
+								.datainhi(din_fr[0]),
+								.datainlo(din_fr[1]),
+								.dataout(din_ddr),
+								.clkhi(outclock_wire),
+								.clklo(outclock_wire),
+								.muxsel(outclock_wire),
+								.areset(aset),
+								.ena(outclocken_wire)
+								`ifndef ALTERA_RESERVED_QIS
+								,
+								.clk(1'b0),
+								.phymemclock(1'b0),
+								.sreset(1'b0),
+								.dfflo(),
+								.dffhi(),
+								.devpor(1'b1),
+								.devclrn(1'b1)
+								`endif
+							);
+						end
+				else if (SYNC_MODE != "none")
+						begin: sync_mode_out_path_ddr
+							fiftyfivenm_ddio_out
+							#(
+								.async_mode(ASYNC_MODE),
+								.sync_mode(SYNC_MODE),
+								.power_up(DDIO_REG_POWER_UP),
+								.use_new_clocking_model("true"),
+								.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+							) fr_out_data_ddio (
+								.datainhi(din_fr[0]),
+								.datainlo(din_fr[1]),
+								.dataout(din_ddr),
+								.clkhi(outclock_wire),
+								.clklo(outclock_wire),
+								.muxsel(outclock_wire),
+								.sreset(sclr),
+								.ena(outclocken_wire)
+								`ifndef ALTERA_RESERVED_QIS
+								,
+								.areset(1'b0),
+								.clk(1'b0),
+								.phymemclock(1'b0),
+								.dfflo(),
+								.dffhi(),
+								.devpor(1'b1),
+								.devclrn(1'b1)
+								`endif
+							);
+						end
+				else
+						begin: out_path_ddr
+							fiftyfivenm_ddio_out
+							#(
+								.async_mode(ASYNC_MODE),
+								.sync_mode(SYNC_MODE),
+								.power_up(DDIO_REG_POWER_UP),
+								.use_new_clocking_model("true"),
+								.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+							) fr_out_data_ddio (
+								.datainhi(din_fr[0]),
+								.datainlo(din_fr[1]),
+								.dataout(din_ddr),
+								.clkhi(outclock_wire),
+								.clklo(outclock_wire),
+								.muxsel(outclock_wire),
+								.ena(outclocken_wire)
+								`ifndef ALTERA_RESERVED_QIS
+								,
+								.areset(1'b0),
+								.clk(1'b0),
+								.phymemclock(1'b0),
+								.sreset(1'b0),
+								.dfflo(),
+								.dffhi(),
+								.devpor(1'b1),
+								.devclrn(1'b1)
+								`endif
+							);
+						end
+			end
+            else if (REGISTER_MODE == "single-register")
+            begin: out_path_sdr
+   			  reg reg_data_out /* synthesis altera_attribute="FAST_OUTPUT_REGISTER=on" */;
+                always @(posedge outclock_wire)
+                    reg_data_out <= din_fr[0];
+
+                assign din_ddr = reg_data_out;
+			end
+            else  
+            begin: out_path_reg_none
+                assign din_ddr = din_fr[0];
+            end
+        end
+    endgenerate
+
+    generate
+
+	    if (PIN_TYPE == "bidir" || PIN_TYPE == "output")
+        begin
+			wire oe_inclk_wire;
+			if (USE_ONE_REG_TO_DRIVE_OE == "true" || USE_DDIO_REG_TO_DRIVE_OE == "true")
+			begin
+				if (INVERT_OE_INCLOCK == "false")
+				begin: normal_oe_inclock
+					assign oe_inclk_wire = outclock;
+				end
+				else
+				begin: inverted_oe_inclock
+					assign oe_inclk_wire = ~outclock;
+				end
+			end
+
+			wire oe_outclocken_wire;
+			assign  oe_outclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? outclocken : 1'b1;
+
+			if (USE_DDIO_REG_TO_DRIVE_OE == "true")
+			begin
+				if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "true")
+				begin
+					if (ASYNC_MODE != "none")
+						begin: async_mode_oe_path_enhanced_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.areset(aset),
+											.ena(oe_outclocken_wire),
+											.phymemclock(phy_mem_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else if (SYNC_MODE != "none")
+						begin: sync_mode_oe_path_enhanced_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.sreset(sclr),
+											.ena(oe_outclocken_wire),
+											.phymemclock(phy_mem_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else
+						begin: oe_path_enhanced_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.use_enhanced_ddr_hio(USE_ENHANCED_DDR_HIO_REGISTER),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.ena(oe_outclocken_wire),
+											.phymemclock(phy_mem_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+				end
+				else if (REGISTER_MODE == "ddr" && USE_ENHANCED_DDR_HIO_REGISTER == "false")
+				begin
+					if (ASYNC_MODE != "none")
+						begin: async_mode_oe_path_ddr
+								fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.areset(aset),
+											.ena(oe_outclocken_wire)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.phymemclock(1'b0),
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else if (SYNC_MODE != "none")
+						begin: sync_mode_oe_path_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.sreset(sclr),
+											.ena(oe_outclocken_wire)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.phymemclock(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+					else
+						begin: oe_path_ddr
+									fiftyfivenm_ddio_oe
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.enable_half_cycle_delay(ENABLE_OE_HALF_CYCLE_DELAY),
+											.power_up(DDIO_REG_POWER_UP),
+											.bypass_three_quarter_register(BYPASS_THREE_QUARTER_REGISTER)
+										) fr_oe_data_ddio (
+											.oe(~oe),
+											.dataout(oe_out),
+											.clk(oe_inclk_wire),
+											.ena(oe_outclocken_wire)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.phymemclock(1'b0),
+											.sreset(1'b0),
+											.dfflo(),
+											.dffhi(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+						end
+				end
+			end
+			else if (USE_ONE_REG_TO_DRIVE_OE == "true")
+			begin: oe_path_sdr
+					fiftyfivenm_ff oe_reg (
+							.clk(oe_inclk_wire),
+							.d(~oe),
+							.clrn(1'b1),
+							.ena(1'b1),
+							.q(oe_out)
+						);
+            end
+            else if (USE_ONE_REG_TO_DRIVE_OE == "false" && USE_DDIO_REG_TO_DRIVE_OE == "false")
+            begin: oe_path_reg_none
+				assign oe_out = ~oe;
+            end
+        end
+	endgenerate
+
+    generate
+        if (PIN_TYPE == "input" || PIN_TYPE == "bidir")
+        begin
+            wire [1:0] ddr_input;
+			wire inclock_wire;
+
+			if (REGISTER_MODE != "bypass")
+			begin
+				if (INVERT_INPUT_CLOCK == "false")
+				begin: normal_input_clock
+					assign inclock_wire = inclock;
+				end
+				else
+				begin: inverted_input_clock
+					assign inclock_wire = ~inclock;
+				end
+			end
+
+			wire inclocken_wire;
+			assign  inclocken_wire = (ENABLE_CLOCK_ENA_PORT == "true") ? inclocken : 1'b1;
+
+         	if (REGISTER_MODE == "ddr")
+         	begin
+		        if (USE_ENHANCED_DDR_HIO_REGISTER == "true" || USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY == "true")
+				begin
+						if (ENABLE_HR_CLOCK == "true")
+						begin
+								if (ASYNC_MODE != "none")
+									begin: async_mode_in_path_enhanced_ddr_with_halfrateresyncclk
+										fiftyfivenm_ddio_in
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.power_up(DDIO_REG_POWER_UP),
+											.invert_input_clock(INVERT_INPUT_CLOCK)
+										) fr_in_ddio (
+											.datain(buf_in),
+											.clk(inclock_wire),
+											.ena(inclocken_wire),
+											.halfrateresyncclk(hr_clock),
+											.regouthi(ddr_input[1]),
+											.regoutlo(ddr_input[0]),
+											.clkout(fr_clock),
+											.areset(aset)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.sreset(1'b0),
+											.dfflo(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+									end
+								else if (SYNC_MODE != "none")
+									begin:sync_mode_in_path_enhanced_ddr_with_halfrateresyncclk
+										fiftyfivenm_ddio_in
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.power_up(DDIO_REG_POWER_UP),
+											.invert_input_clock(INVERT_INPUT_CLOCK)
+										) fr_in_ddio (
+											.datain(buf_in),
+											.clk (inclock_wire),
+											.ena(inclocken_wire),
+											.sreset(sclr),
+											.halfrateresyncclk(hr_clock),
+											.regouthi(ddr_input[1]),
+											.regoutlo(ddr_input[0]),
+											.clkout(fr_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.areset(1'b0),
+											.dfflo(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+									end
+								else
+									begin:in_path_enhanced_ddr_with_halfrateresyncclk
+										fiftyfivenm_ddio_in
+										#(
+											.async_mode(ASYNC_MODE),
+											.sync_mode(SYNC_MODE),
+											.power_up(DDIO_REG_POWER_UP),
+											.invert_input_clock(INVERT_INPUT_CLOCK)
+										) fr_in_ddio (
+											.datain(buf_in),
+											.clk (inclock_wire),
+											.ena(inclocken_wire),
+											.halfrateresyncclk(hr_clock),
+											.regouthi(ddr_input[1]),
+											.regoutlo(ddr_input[0]),
+											.clkout(fr_clock)
+											`ifndef ALTERA_RESERVED_QIS
+											,
+											.sreset(1'b0),
+											.areset(1'b0),
+											.dfflo(),
+											.devpor(1'b1),
+											.devclrn(1'b1)
+											`endif
+										);
+									end
+						end
+						else
+						begin
+							if (ASYNC_MODE != "none")
+								begin: async_mode_in_path_enhanced_ddr
+									fiftyfivenm_ddio_in
+									#(
+										.async_mode(ASYNC_MODE),
+										.sync_mode(SYNC_MODE),
+										.power_up(DDIO_REG_POWER_UP),
+										.invert_input_clock(INVERT_INPUT_CLOCK)
+									) fr_in_ddio (
+										.datain(buf_in),
+										.clk(inclock_wire),
+										.ena(inclocken_wire),
+										.regouthi(ddr_input[1]),
+										.regoutlo(ddr_input[0]),
+										.clkout(fr_clock),
+										.areset(aset)
+										`ifndef ALTERA_RESERVED_QIS
+										,
+										.sreset(1'b0),
+										.dfflo(),
+										.devpor(1'b1),
+										.devclrn(1'b1),
+										.halfrateresyncclk(1'b0)
+										`endif
+									);
+								end
+							else if (SYNC_MODE != "none")
+								begin:sync_mode_in_path_enhanced_ddr
+									fiftyfivenm_ddio_in
+									#(
+										.async_mode(ASYNC_MODE),
+										.sync_mode(SYNC_MODE),
+										.power_up(DDIO_REG_POWER_UP),
+										.invert_input_clock(INVERT_INPUT_CLOCK)
+									) fr_in_ddio (
+										.datain(buf_in),
+										.clk (inclock_wire),
+										.ena(inclocken_wire),
+										.sreset(sclr),
+										.regouthi(ddr_input[1]),
+										.regoutlo(ddr_input[0]),
+										.clkout(fr_clock)
+										`ifndef ALTERA_RESERVED_QIS
+										,
+										.areset(1'b0),
+										.dfflo(),
+										.devpor(1'b1),
+										.devclrn(1'b1),
+										.halfrateresyncclk(1'b0)
+										`endif
+									);
+								end
+							else
+								begin:in_path_enhanced_ddr
+									fiftyfivenm_ddio_in
+									#(
+										.async_mode(ASYNC_MODE),
+										.sync_mode(SYNC_MODE),
+										.power_up(DDIO_REG_POWER_UP),
+										.invert_input_clock(INVERT_INPUT_CLOCK)
+									) fr_in_ddio (
+										.datain(buf_in),
+										.clk (inclock_wire),
+										.ena(inclocken_wire),
+										.regouthi(ddr_input[1]),
+										.regoutlo(ddr_input[0]),
+										.clkout(fr_clock)
+										`ifndef ALTERA_RESERVED_QIS
+										,
+										.sreset(1'b0),
+										.areset(1'b0),
+										.dfflo(),
+										.devpor(1'b1),
+										.devclrn(1'b1),
+										.halfrateresyncclk(1'b0)
+										`endif
+									);
+								end
+						end
+				end
+				else if (ENABLE_PHASE_DETECTOR_FOR_CK == "true")
+					begin
+						assign mimic_clock = buf_in;
+					end
+				else
+				begin: in_path_ddr
+					wire input_cell_l_q;
+					wire input_aset;
+
+					assign input_aset = ( ASYNC_MODE == "clear") ? !aset : aset;
+
+					fiftyfivenm_ff input_cell_l (
+						.clk(inclock_wire),
+						.d(buf_in),
+						.clrn(input_aset),
+						.ena(inclocken_wire),
+						.q(input_cell_l_q)
+					);
+
+					fiftyfivenm_ff input_latch_l (
+						.clk(~inclock_wire),
+						.d(input_cell_l_q),
+						.clrn(input_aset),
+						.ena(inclocken_wire),
+						.q(ddr_input[0])
+					);
+
+					fiftyfivenm_ff input_cell_h (
+						.clk(~inclock_wire),
+						.d(buf_in),
+						.clrn(input_aset),
+						.ena(inclocken_wire),
+						.q(ddr_input[1])
+					);
+
+				end
+			end
+			else if (REGISTER_MODE == "single-register")
+            begin: in_path_sdr
+                reg reg_data_in /* synthesis altera_attribute="FAST_INPUT_REGISTER=on" */;
+                always @(posedge inclock_wire) begin
+                    reg_data_in <= buf_in;
+                end
+                assign ddr_input[0] = reg_data_in;
+            end
+            else
+            begin: in_path_reg_none
+                assign ddr_input[0] = buf_in;
+            end
+
+            assign dout[DATA_SIZE - 1:0] = ddr_input[DATA_SIZE - 1:0];
+
+        end
+    endgenerate
+
+	generate
+		if (PIN_TYPE == "output" || PIN_TYPE == "bidir")
+		begin
+			if(BUFFER_TYPE == "pseudo_differential")
+			begin: pseudo_diff_output_buf
+
+				wire wire_pseudo_diff_o;
+				wire wire_pseudo_diff_o_bar;
+
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf_a (
+					.i(wire_pseudo_diff_o),
+					.oe(~oe_out),
+					.o(pad),
+					.obar()
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf_a_bar (
+					.i(wire_pseudo_diff_o_bar),
+					.oe(~oe_out),
+					.o(pad_b),
+					.obar()
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+
+				fiftyfivenm_pseudo_diff_out pseudo_diff_a
+				(
+					.i(din_ddr),
+					.o(wire_pseudo_diff_o),
+					.obar(wire_pseudo_diff_o_bar)
+				);
+
+
+
+			end
+			else if (BUFFER_TYPE == "true_differential")
+			begin: true_diff_output_buf
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf (
+					.i(din_ddr),
+					.oe(~oe_out),
+					.o(pad),
+					.obar(pad_b)
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+			end
+			else
+			begin: output_buf
+				fiftyfivenm_io_obuf
+				#(
+					.bus_hold(BUS_HOLD),
+					.open_drain_output(OPEN_DRAIN_OUTPUT)
+				) obuf (
+					.i(din_ddr),
+					.oe(~oe_out),
+					.o(pad),
+					.obar()
+					`ifndef ALTERA_RESERVED_QIS
+					,
+					.seriesterminationcontrol(16'b0),
+					.devoe(1'b1)
+					`endif
+				);
+			end
+		end
+	endgenerate
+
+	assign nsleep_in = (ENABLE_NSLEEP_PORT == "true") ? nsleep : 1'b1;
+
+	generate
+		if (PIN_TYPE == "input" || PIN_TYPE == "bidir")
+		begin
+			if(BUFFER_TYPE == "true_differential" || BUFFER_TYPE == "pseudo_differential")
+			begin: diff_input_buf
+				if (ENABLE_NSLEEP_PORT == "true")
+				begin: diff_input_buf_with_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.ibar(pad_b),
+						.o(buf_in),
+						.nsleep(nsleep_in)
+					);
+				end
+				else
+				begin: diff_input_buf_without_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.ibar(pad_b),
+						.o(buf_in)
+					);
+				end
+			end
+			else
+			begin:input_buf
+				if (ENABLE_NSLEEP_PORT == "true")
+				begin: input_buf_with_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.o(buf_in),
+						.nsleep(nsleep_in)
+						`ifndef ALTERA_RESERVED_QIS
+						,
+						.ibar(1'b0)
+						`endif
+					);
+				end
+				else
+				begin: input_buf_without_nsleep
+					fiftyfivenm_io_ibuf
+					#(
+						.bus_hold(BUS_HOLD)
+					) ibuf (
+						.i(pad),
+						.o(buf_in)
+						`ifndef ALTERA_RESERVED_QIS
+						,
+						.ibar(1'b0)
+						`endif
+					);
+				end
+			end
+		end
+	endgenerate
+
+	generate
+		if (PIN_TYPE == "output")
+		begin
+			assign dout = {DATA_SIZE{1'b0}};
+		end
+
+		if (PIN_TYPE == "output" || REGISTER_MODE != "ddr" || USE_ENHANCED_DDR_HIO_REGISTER == "false")
+		begin
+			assign fr_clock = 1'b0;
+		end
+
+		if (PIN_TYPE == "input" || PIN_TYPE == "output" || REGISTER_MODE != "ddr" || ENABLE_PHASE_DETECTOR_FOR_CK == "false")
+		begin
+			assign mimic_clock = 1'b0;
+		end
+	endgenerate
+
+endmodule
+
+module altera_gpio_lite(
+	inclock,
+	outclock,
+	inclocken,
+	outclocken,
+	oe,
+	din,
+	dout,
+	pad_io,
+	pad_io_b,
+	pad_in,
+	pad_in_b,
+	pad_out,
+	pad_out_b,
+	aset,
+	aclr,
+	phy_mem_clock,
+	sclr,
+	hr_clock,
+	fr_clock,
+	invert_hr_clock,
+	mimic_clock,
+	nsleep
+);
+
+	parameter PIN_TYPE = "output"; 
+	parameter BUFFER_TYPE = "single-ended"; 
+	parameter REGISTER_MODE = "bypass"; 
+	parameter SIZE = 4;
+	parameter ASYNC_MODE = "none"; 
+	parameter SYNC_MODE = "none"; 
+	parameter BUS_HOLD = "false"; 
+	parameter SET_REGISTER_OUTPUTS_HIGH = "false"; 
+	parameter INVERT_OUTPUT = "false"; 
+	parameter INVERT_INPUT_CLOCK = "false"; 
+	parameter INVERT_OUTPUT_CLOCK = "false"; 
+	parameter INVERT_OE_INCLOCK = "false"; 
+	parameter USE_ONE_REG_TO_DRIVE_OE = "false"; 
+	parameter USE_DDIO_REG_TO_DRIVE_OE = "false"; 
+	parameter OPEN_DRAIN_OUTPUT = "false"; 
+	parameter USE_ADVANCED_DDR_FEATURES = "false"; 
+	parameter USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY = "false"; 
+	parameter INVERT_CLKDIV_INPUT_CLOCK = "false"; 
+	parameter ENABLE_HR_CLOCK = "false"; 
+	parameter ENABLE_OE_HALF_CYCLE_DELAY = "true"; 
+	parameter ENABLE_OE_PORT = "false"; 
+	parameter ENABLE_CLOCK_ENA_PORT = "false"; 
+	parameter ENABLE_PHASE_INVERT_CTRL_PORT = "false"; 
+	parameter ENABLE_PHASE_DETECTOR_FOR_CK = "false"; 
+	parameter ENABLE_NSLEEP_PORT = "false"; 
+
+    localparam USE_ENHANCED_DDR_HIO_REGISTER = USE_ADVANCED_DDR_FEATURES;
+	localparam BYPASS_THREE_QUARTER_REGISTER = (USE_ADVANCED_DDR_FEATURES == "true") ? "false" : "true";
+	localparam DATA_SIZE = (REGISTER_MODE == "ddr") ? 2 : 1;
+
+	input inclock;
+	input outclock;
+	input inclocken;
+	input outclocken;
+	input [SIZE - 1:0] oe;
+	input [SIZE - 1:0] nsleep;
+	input [SIZE * DATA_SIZE - 1:0] din;
+	output [SIZE * DATA_SIZE - 1:0] dout;
+	inout [SIZE - 1:0] pad_io;
+	inout [SIZE - 1:0] pad_io_b;
+	input [SIZE - 1:0] pad_in;
+	input [SIZE - 1:0] pad_in_b;
+	output [SIZE - 1:0] pad_out;
+	output [SIZE - 1:0] pad_out_b;
+	input aset;
+	input aclr;
+	input sclr;
+	input phy_mem_clock;
+	input invert_hr_clock;
+	output [SIZE - 1:0] fr_clock;
+	output wire hr_clock;
+	output [SIZE - 1:0] mimic_clock;
+
+	wire [SIZE * DATA_SIZE - 1:0] din_reordered;
+	wire [SIZE * DATA_SIZE - 1:0] dout_reordered;
+	wire aclr_aset_wire;
+	wire sclr_wire;
+	wire [SIZE - 1:0] pad_io;
+	wire [SIZE - 1:0] pad_io_b;
+
+
+	assign aclr_aset_wire = (ASYNC_MODE == "clear") ? aclr : (ASYNC_MODE == "preset") ? aset : 1'b1;
+	assign sclr_wire = (SYNC_MODE == "clear") ? sclr : 1'b0;
+
+	generate
+		if (PIN_TYPE == "input")
+		begin
+			assign pad_io = pad_in;
+			assign pad_io_b = pad_in_b;
+			assign pad_out = {SIZE{1'b0}};
+			assign pad_out_b = {SIZE{1'b0}};
+		end
+		else if (PIN_TYPE == "output")
+		begin
+			assign pad_out = pad_io;
+			assign pad_out_b = pad_io_b;
+		end
+		else begin
+			assign pad_out = {SIZE{1'b0}};
+			assign pad_out_b = {SIZE{1'b0}};
+		end
+	endgenerate
+
+	genvar j, k;
+	generate
+		begin : reorder
+			for(j = 0; j < SIZE ; j = j + 1) begin : j_loop
+				for(k = 0; k < DATA_SIZE; k = k + 1) begin : k_d_loop
+					assign din_reordered[j * DATA_SIZE + k] = din[j + k * SIZE];
+					assign dout[j + k * SIZE] = dout_reordered[j * DATA_SIZE + k];
+				end
+			end
+		end
+	endgenerate
+
+	genvar i;
+	generate
+		begin : gpio_one_bit
+			for(i = 0 ; i < SIZE ; i = i + 1) begin : i_loop
+				wire oe_wire;
+				wire nsleep_wire;
+
+
+				assign oe_wire = (PIN_TYPE == "output" && ENABLE_OE_PORT == "false") ? 1'b1 :
+				                  (PIN_TYPE == "input") ? 1'b0 : oe[i];
+
+
+				assign nsleep_wire = (PIN_TYPE == "input" && ENABLE_NSLEEP_PORT == "false") ? 1'b1 :
+														(PIN_TYPE == "output") ? 1'b0 : nsleep[i];
+
+				altgpio_one_bit #(
+					.PIN_TYPE(PIN_TYPE),
+					.BUFFER_TYPE(BUFFER_TYPE),
+					.REGISTER_MODE(REGISTER_MODE),
+					.ASYNC_MODE(ASYNC_MODE),
+					.SYNC_MODE(SYNC_MODE),
+					.BUS_HOLD(BUS_HOLD),
+					.SET_REGISTER_OUTPUTS_HIGH(SET_REGISTER_OUTPUTS_HIGH),
+					.USE_ENHANCED_DDR_HIO_REGISTER(USE_ENHANCED_DDR_HIO_REGISTER),
+					.USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY(USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY),
+					.BYPASS_THREE_QUARTER_REGISTER(BYPASS_THREE_QUARTER_REGISTER),
+					.INVERT_OUTPUT(INVERT_OUTPUT),
+					.INVERT_INPUT_CLOCK(INVERT_INPUT_CLOCK),
+					.INVERT_OUTPUT_CLOCK(INVERT_OUTPUT_CLOCK),
+					.INVERT_OE_INCLOCK(INVERT_OE_INCLOCK),
+					.USE_ONE_REG_TO_DRIVE_OE(USE_ONE_REG_TO_DRIVE_OE),
+					.USE_DDIO_REG_TO_DRIVE_OE(USE_DDIO_REG_TO_DRIVE_OE),
+					.OPEN_DRAIN_OUTPUT(OPEN_DRAIN_OUTPUT),
+					.ENABLE_OE_HALF_CYCLE_DELAY(ENABLE_OE_HALF_CYCLE_DELAY),
+					.ENABLE_CLOCK_ENA_PORT(ENABLE_CLOCK_ENA_PORT),
+					.ENABLE_HR_CLOCK(ENABLE_HR_CLOCK),
+					.ENABLE_PHASE_DETECTOR_FOR_CK(ENABLE_PHASE_DETECTOR_FOR_CK),
+					.ENABLE_NSLEEP_PORT(ENABLE_NSLEEP_PORT)
+				) altgpio_bit_i (
+					.inclock(inclock),
+					.outclock(outclock),
+					.phy_mem_clock(phy_mem_clock),
+					.inclocken(inclocken),
+					.outclocken(outclocken),
+					.oe(oe_wire),
+					.din(din_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]),
+					.dout(dout_reordered[(i + 1) * DATA_SIZE - 1 : i * DATA_SIZE]),
+					.pad(pad_io[i]),
+					.pad_b(pad_io_b[i]),
+					.aset(aclr_aset_wire),
+					.sclr(sclr_wire),
+					.fr_clock(fr_clock[i]),
+					.hr_clock(hr_clock),
+					.mimic_clock(mimic_clock[i]),
+					.nsleep(nsleep_wire)
+				);
+			end
+		end
+	endgenerate
+
+	generate
+		if ((PIN_TYPE == "input" || PIN_TYPE == "bidir") && (ENABLE_HR_CLOCK == "true"))
+		begin
+			if (ENABLE_PHASE_INVERT_CTRL_PORT == "true")
+			begin
+				if (SYNC_MODE == "clear")
+				begin : clock_divider_sync_mode_invert_hr_clock
+					fiftyfivenm_io_clock_divider
+					#(
+						.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+						.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+						.sync_mode(SYNC_MODE)
+					) io_clkdiv (
+						.clk(inclock),
+						.phaseinvertctrl(invert_hr_clock),
+						.sreset(sclr_wire),
+						.clkout(hr_clock)
+					);
+				end
+				else
+				begin : clock_divider_invert_hr_clock
+					fiftyfivenm_io_clock_divider
+						#(
+							.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+							.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+							.sync_mode(SYNC_MODE)
+						) io_clkdiv (
+							.clk(inclock),
+							.phaseinvertctrl(invert_hr_clock),
+							.clkout(hr_clock)
+							`ifndef ALTERA_RESERVED_QIS
+							,
+							.sreset(1'b0)
+							`endif
+						);
+				end
+			end
+			else
+			begin
+				if (SYNC_MODE == "clear")
+				begin : clock_divider_sync_mode
+					fiftyfivenm_io_clock_divider
+					#(
+						.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+						.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+						.sync_mode(SYNC_MODE)
+					) io_clkdiv (
+						.clk(inclock),
+						.sreset(sclr_wire),
+						.clkout(hr_clock)
+						`ifndef ALTERA_RESERVED_QIS
+						,
+						.phaseinvertctrl(1'b0)
+						`endif
+					);
+				end
+				else
+				begin : clock_divider
+					fiftyfivenm_io_clock_divider
+						#(
+							.invert_input_clock_phase(INVERT_CLKDIV_INPUT_CLOCK),
+							.use_phasectrlin(ENABLE_PHASE_INVERT_CTRL_PORT),
+							.sync_mode(SYNC_MODE)
+						) io_clkdiv (
+							.clk(inclock),
+							.clkout(hr_clock)
+							`ifndef ALTERA_RESERVED_QIS
+							,
+							.sreset(1'b0),
+							.phaseinvertctrl(1'b0)
+							`endif
+						);
+				end
+			end
+		end
+		else begin
+			assign hr_clock = 1'b0;
+		end
+	endgenerate
+
+endmodule
Index: atari_chips/gtia/osc_out_sim/cadence/cds.lib
===================================================================
--- atari_chips/gtia/osc_out_sim/cadence/cds.lib	(nonexistent)
+++ atari_chips/gtia/osc_out_sim/cadence/cds.lib	(revision 1318)
@@ -0,0 +1,23 @@
+
+DEFINE std             $CDS_ROOT/tools/inca/files/STD/           
+DEFINE synopsys        $CDS_ROOT/tools/inca/files/SYNOPSYS/      
+DEFINE ieee            $CDS_ROOT/tools/inca/files/IEEE/          
+DEFINE ambit           $CDS_ROOT/tools/inca/files/AMBIT/         
+DEFINE vital_memory    $CDS_ROOT/tools/inca/files/VITAL_MEMORY/  
+DEFINE ncutils         $CDS_ROOT/tools/inca/files/NCUTILS/       
+DEFINE ncinternal      $CDS_ROOT/tools/inca/files/NCINTERNAL/    
+DEFINE ncmodels        $CDS_ROOT/tools/inca/files/NCMODELS/      
+DEFINE cds_assertions  $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
+DEFINE work            ./libraries/work/                         
+DEFINE osc_out         ./libraries/osc_out/                      
+DEFINE altera_ver      ./libraries/altera_ver/                   
+DEFINE lpm_ver         ./libraries/lpm_ver/                      
+DEFINE sgate_ver       ./libraries/sgate_ver/                    
+DEFINE altera_mf_ver   ./libraries/altera_mf_ver/                
+DEFINE fiftyfivenm_ver ./libraries/fiftyfivenm_ver/              
+DEFINE altera          ./libraries/altera/                       
+DEFINE lpm             ./libraries/lpm/                          
+DEFINE sgate           ./libraries/sgate/                        
+DEFINE altera_mf       ./libraries/altera_mf/                    
+DEFINE altera_lnsim    ./libraries/altera_lnsim/                 
+DEFINE fiftyfivenm     ./libraries/fiftyfivenm/                  
Index: atari_chips/gtia/osc_out_sim/cadence/ncsim_setup.sh
===================================================================
--- atari_chips/gtia/osc_out_sim/cadence/ncsim_setup.sh	(nonexistent)
+++ atari_chips/gtia/osc_out_sim/cadence/ncsim_setup.sh	(revision 1318)
@@ -0,0 +1,210 @@
+
+# (C) 2001-2018 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and 
+# other software and tools, and its AMPP partner logic functions, and 
+# any output files any of the foregoing (including device programming 
+# or simulation files), and any associated documentation or information 
+# are expressly subject to the terms and conditions of the Altera 
+# Program License Subscription Agreement, Altera MegaCore Function 
+# License Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by Altera 
+# or its authorized distributors. Please refer to the applicable 
+# agreement for further details.
+
+# ACDS 18.0 614 linux 2018.10.28.22:04:02
+
+# ----------------------------------------
+# ncsim - auto-generated simulation script
+
+# ----------------------------------------
+# This script provides commands to simulate the following IP detected in
+# your Quartus project:
+#     osc_out
+# 
+# Altera recommends that you source this Quartus-generated IP simulation
+# script from your own customized top-level script, and avoid editing this
+# generated script.
+# 
+# To write a top-level shell script that compiles Altera simulation libraries
+# and the Quartus-generated IP in your project, along with your design and
+# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
+# into a new file, e.g. named "ncsim.sh", and modify text as directed.
+# 
+# You can also modify the simulation flow to suit your needs. Set the
+# following variables to 1 to disable their corresponding processes:
+# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
+# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
+# - SKIP_COM: skip compiling Quartus-generated IP simulation files
+# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
+# 
+# ----------------------------------------
+# # TOP-LEVEL TEMPLATE - BEGIN
+# #
+# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
+# # construct paths to the files required to simulate the IP in your Quartus
+# # project. By default, the IP script assumes that you are launching the
+# # simulator from the IP script location. If launching from another
+# # location, set QSYS_SIMDIR to the output directory you specified when you
+# # generated the IP script, relative to the directory from which you launch
+# # the simulator. In this case, you must also copy the generated files
+# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated - 
+# # into the location from which you launch the simulator, or incorporate
+# # into any existing library setup.
+# #
+# # Run Quartus-generated IP simulation script once to compile Quartus EDA
+# # simulation libraries and Quartus-generated IP simulation files, and copy
+# # any ROM/RAM initialization files to the simulation directory.
+# # - If necessary, specify any compilation options:
+# #   USER_DEFINED_COMPILE_OPTIONS
+# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
+# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_ELAB=1 \
+# SKIP_SIM=1 \
+# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
+# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
+# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
+# QSYS_SIMDIR=<script generation output directory>
+# #
+# # Compile all design files and testbench files, including the top level.
+# # (These are all the files required for simulation other than the files
+# # compiled by the IP script)
+# #
+# ncvlog <compilation options> <design and testbench files>
+# #
+# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
+# # testbench module/entity name.
+# #
+# # Run the IP script again to elaborate and simulate the top level:
+# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
+# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
+# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
+# #
+# source <script generation output directory>/cadence/ncsim_setup.sh \
+# SKIP_FILE_COPY=1 \
+# SKIP_DEV_COM=1 \
+# SKIP_COM=1 \
+# TOP_LEVEL_NAME=<simulation top> \
+# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
+# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
+# #
+# # TOP-LEVEL TEMPLATE - END
+# ----------------------------------------
+# 
+# IP SIMULATION SCRIPT
+# ----------------------------------------
+# If osc_out is one of several IP cores in your
+# Quartus project, you can generate a simulation script
+# suitable for inclusion in your top-level simulation
+# script by running the following command line:
+# 
+# ip-setup-simulation --quartus-project=<quartus project>
+# 
+# ip-setup-simulation will discover the Altera IP
+# within the Quartus project, and generate a unified
+# script which supports all the Altera IP within the design.
+# ----------------------------------------
+# ACDS 18.0 614 linux 2018.10.28.22:04:02
+# ----------------------------------------
+# initialize variables
+TOP_LEVEL_NAME="osc_out"
+QSYS_SIMDIR="./../"
+QUARTUS_INSTALL_DIR="/home/markw/intelFPGA_lite/18.0/quartus/"
+SKIP_FILE_COPY=0
+SKIP_DEV_COM=0
+SKIP_COM=0
+SKIP_ELAB=0
+SKIP_SIM=0
+USER_DEFINED_ELAB_OPTIONS=""
+USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
+
+# ----------------------------------------
+# overwrite variables - DO NOT MODIFY!
+# This block evaluates each command line argument, typically used for 
+# overwriting variables. An example usage:
+#   sh <simulator>_setup.sh SKIP_SIM=1
+for expression in "$@"; do
+  eval $expression
+  if [ $? -ne 0 ]; then
+    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
+    exit $?
+  fi
+done
+
+# ----------------------------------------
+# initialize simulation properties - DO NOT MODIFY!
+ELAB_OPTIONS=""
+SIM_OPTIONS=""
+if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
+  :
+else
+  :
+fi
+
+# ----------------------------------------
+# create compilation libraries
+mkdir -p ./libraries/work/
+mkdir -p ./libraries/osc_out/
+mkdir -p ./libraries/altera_ver/
+mkdir -p ./libraries/lpm_ver/
+mkdir -p ./libraries/sgate_ver/
+mkdir -p ./libraries/altera_mf_ver/
+mkdir -p ./libraries/fiftyfivenm_ver/
+mkdir -p ./libraries/altera/
+mkdir -p ./libraries/lpm/
+mkdir -p ./libraries/sgate/
+mkdir -p ./libraries/altera_mf/
+mkdir -p ./libraries/altera_lnsim/
+mkdir -p ./libraries/fiftyfivenm/
+
+# ----------------------------------------
+# copy RAM/ROM files to simulation directory
+
+# ----------------------------------------
+# compile device library files
+if [ $SKIP_DEV_COM -eq 0 ]; then
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"                -work altera_ver     
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                         -work lpm_ver        
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                            -work sgate_ver      
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                        -work altera_mf_ver  
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.v"                -work fiftyfivenm_ver
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_syn_attributes.vhd"          -work altera         
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_standard_functions.vhd"      -work altera         
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/alt_dspbuilder_package.vhd"         -work altera         
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_europa_support_lib.vhd"      -work altera         
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives_components.vhd"   -work altera         
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.vhd"              -work altera         
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220pack.vhd"                        -work lpm            
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.vhd"                       -work lpm            
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate_pack.vhd"                     -work sgate          
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.vhd"                          -work sgate          
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf_components.vhd"           -work altera_mf      
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.vhd"                      -work altera_mf      
+  ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                    -work altera_lnsim   
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim_components.vhd"        -work altera_lnsim   
+  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/fiftyfivenm_atoms_ncrypt.v" -work fiftyfivenm    
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_atoms.vhd"              -work fiftyfivenm    
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QUARTUS_INSTALL_DIR/eda/sim_lib/fiftyfivenm_components.vhd"         -work fiftyfivenm    
+fi
+
+# ----------------------------------------
+# compile design files in correct order
+if [ $SKIP_COM -eq 0 ]; then
+  ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/altera_gpio_lite/altera_gpio_lite.sv" -work osc_out -cdslib ./cds_libs/osc_out.cds.lib
+  ncvhdl -v93 $USER_DEFINED_VHDL_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS   "$QSYS_SIMDIR/osc_out.vhd"                                                                          
+fi
+
+# ----------------------------------------
+# elaborate top level design
+if [ $SKIP_ELAB -eq 0 ]; then
+  export GENERIC_PARAM_COMPAT_CHECK=1
+  ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
+fi
+
+# ----------------------------------------
+# simulate
+if [ $SKIP_SIM -eq 0 ]; then
+  eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
+fi

Property changes on: atari_chips/gtia/osc_out_sim/cadence/ncsim_setup.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: atari_chips/gtia/osc_out_sim/synopsys/vcsmx/synopsys_sim.setup
===================================================================
--- atari_chips/gtia/osc_out_sim/synopsys/vcsmx/synopsys_sim.setup	(nonexistent)
+++ atari_chips/gtia/osc_out_sim/synopsys/vcsmx/synopsys_sim.setup	(revision 1318)
@@ -0,0 +1,18 @@
+
+WORK > DEFAULT
+DEFAULT:          ./libraries/work/            
+work:             ./libraries/work/            
+osc_out:          ./libraries/osc_out/         
+altera_ver:       ./libraries/altera_ver/      
+lpm_ver:          ./libraries/lpm_ver/         
+sgate_ver:        ./libraries/sgate_ver/       
+altera_mf_ver:    ./libraries/altera_mf_ver/   
+altera_lnsim_ver: ./libraries/altera_lnsim_ver/
+fiftyfivenm_ver:  ./libraries/fiftyfivenm_ver/ 
+altera:           ./libraries/altera/          
+lpm:              ./libraries/lpm/             
+sgate:            ./libraries/sgate/           
+altera_mf:        ./libraries/altera_mf/       
+altera_lnsim:     ./libraries/altera_lnsim/    
+fiftyfivenm:      ./libraries/fiftyfivenm/     
+LIBRARY_SCAN = TRUE
